A method for processing signal delay differences at the MIPI D-PHY receiver

Abstract

The present invention discloses a method for processing signal delay differences at the receiving end of MIPI D-PHY, belonging to the field of high-speed serial buses. A FIFO is placed after the PPI at the receiving end of each data channel in MIPI D-PHY; it is reset separately using the RxSyncHs signal, and the RxValidHs signal is used as the condition for writing data into the FIFO respectively. This application can effectively solve the delay problem existing in data transmission of the MIPI D-PHY interface, improve its reliability and stability, and has great market potential and application value.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed serial bus, and particularly to a method for processing signal delay differences at the receiving end of MIPI D-PHY. Background Art

[0002] The MIPI D-PHY interface is a digital serial interface technology used to connect displays and cameras in mobile devices. D-PHY supports distributing data to multiple data channels for simultaneous transmission, such as Figure 1 and Figure 2 shown, but this will result in differences in the delay of each data channel, and there will also be differences in the time when the receiving end of each data channel in DPHY receives the data. If not processed, it may lead to misalignment of the parsed data. Therefore, a structure for processing delay differences needs to be designed at the data receiving end. Summary of the Invention

[0003] The purpose of the present invention is to provide a method for processing signal delay differences at the receiving end of MIPI D-PHY to solve the problems in the background art.

[0004] To solve the above technical problems, the present invention provides a method for processing signal delay differences at the receiving end of MIPI D-PHY, including:

[0005] Placing a FIFO after the PPI at the receiving end of each data channel in MIPI D-PHY;

[0006] Resetting them respectively with the RxSyncHs signal, and using the RxValidHs signal as the condition for writing data into the FIFO respectively.

[0007] In one embodiment, after all used data channels receive the RxSyncHs signal, all FIFOs start reading data simultaneously, ensuring that the first data received by each data channel is processed simultaneously. The channels that receive data earlier need to wait until the channels that receive data latest also receive data before starting to process.

[0008] In one embodiment, the depth of the FIFO is determined by measuring the maximum delay of the data in each data channel.

[0009] In one embodiment, when there is no difference in the time when each data channel receives data, the transmission delay of the entire link will not increase; the greater the difference in the time when data is received, the greater the increased link delay.

[0010] In one embodiment, the method is applicable to the receiving end where there are delay differences between any other data streams except the receiving end of MIPI D-PHY.

[0011] The present invention provides a method for processing the signal delay difference of the MIPI D-PHY receiving end, which can solve the problem that the time when each D-PHY data channel receives data is different. The circuit is simple, easy to use, and easy to promote and apply. The present application can effectively solve the delay problem existing in the data transmission of the MIPI D-PHY interface, improve its reliability and stability, and has great market potential and application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of data being distributed to multiple data channels for simultaneous transmission.

[0013] Figure 2 This is a timing diagram of the PPI RX signal.

[0014] Figure 3 It is a schematic diagram of placing a FIFO after the PPI of each data channel receiving end provided by the present invention. DETAILED DESCRIPTION

[0015] The following is a further detailed description of a method for processing MIPI D-PHY receiving end signal delay differences proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0016] In order to solve the problem of signal delay difference at the MIPID-PHY receiving end, the present invention provides a method of placing a FIFO after the PPI at the receiving end of each data channel, such as Figure 3 As shown in the figure, the RxSyncHs signal is used to reset, and the RxValidHs signal is used as the condition for writing data into the FIFO. Each RxSyncHs signal is latched at the same time. When all the used data channels receive the RxSyncHs signal, all FIFOs start reading data at the same time. This ensures that the first data received by each data channel is processed at the same time. This means that the data channel that receives the data first needs to wait until the data channel that receives the data last also receives the data before starting to process. Figure 3 shown.

[0017] Add a delay line at the receiving end (rx) of the MIPI D-PHY interface, store the data received by each data channel into the FIFO respectively, and start reading the data from the FIFO simultaneously until the first data is received by all the data channels to be used, and then perform assembly processing on the data. In this way, the order of the assembled data is consistent with the order of the transmitted data. The depth of the FIFO needs to be determined by measuring the maximum delay of the data in each data channel.

[0018] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for processing the signal delay difference of the MIPI D-PHY receiver, characterized in that Including: Placing a FIFO after the PPI at the receiving end of each data channel in the MIPI D-PHY; Resetting the FIFO with the RxSyncHs signal respectively, and using the RxValidHs signal as the condition for writing data into the FIFO respectively; After all used data channels receive the RxSyncHs signal, all FIFOs start reading data simultaneously, ensuring that the first data received by each data channel is processed simultaneously. The channels that receive data earlier need to wait until the channels that receive data latest also receive data before starting to process.

2. The method for processing the signal delay difference of the MIPI D-PHY receiver according to claim 1, wherein The depth of the FIFO is determined by measuring the maximum latency of the data in each data channel.

3. The method for processing the signal delay difference of the MIPI D-PHY receiver according to claim 1, wherein When there is no difference in the time when each data channel receives data, the transmission delay of the entire link will not increase; the greater the difference in the time of receiving data, the greater the increased link delay.

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