Remote access method and device based on UCIe mailbox mechanism and storage medium

Abstract

The invention relates to the technical field of EDA, in particular to a remote access method and device based on a UCIe mailbox mechanism and a storage medium. The method comprises the steps that a destination address is obtained by analyzing a sideband register access request packet; when the destination address is located in a register address space of a high layer, the adapter layer sends the sideband register access request packet to the high layer through a sideband interface cfg in an FDI and obtains an access result; the adapter layer writes the access result into a mailbox register, and packages the access result and related data in the mailbox register to form a sideband access completion transaction; and the sideband access completion transaction is fed back to the sending end chip in an original way. Efficient and flexible access without CPU intervention to a high layer through a sideband is achieved, and the UCIe protocol specification is met.

Description

Technical Field

[0001] The present invention relates to the field of EDA technology, and in particular to a remote access method, device and storage medium based on a UCIe mailbox mechanism. Background Art

[0002] With the continuous advancement of chip design technology, chiplet technology has gradually become the focus of industry attention because it can effectively solve the problems of size, cost and yield faced by single-chip design. However, in the process of interconnecting small chips, how to achieve efficient, flexible and low-power communication has become a technical problem that needs to be solved urgently. Although traditional interconnection methods, such as PCIe (Peripheral Component Interconnect Express), are widely used, they cannot fully meet the requirements of Die-to-Die applications commonly used in chiplets, and it is difficult to perfectly adapt to the new challenges brought by cutting-edge packaging technologies such as 2.5D and 3D. As an emerging in-package interconnection standard, UCIe (Universal Chiplet Interconnect Express) is an in-package interconnection standard designed specifically for chiplet technology. It shows unprecedented compatibility and flexibility. It not only supports multiple standard protocols such as PCIe and CXL (Compute Express Link), but also allows users to customize protocols, thereby realizing the coexistence and time-sharing multiplexing of multiple protocols in the same package. UCIe introduces a sideband link, which is dedicated to the interaction of sideband information (Message) such as register access, parameter exchange, and state machine coordination. It also introduces a mailbox mechanism based on the sideband to achieve indirect access to the sending chip (Die), significantly improving the efficiency of data transmission and the flexibility of the system.

[0003] However, the UCIe mailbox mechanism can only access the adapter layer (Die-to-Die Adapter Layer) and physical layer (Physical Layer) of the sending chip, and cannot access the protocol layer (Protocol Layer) or higher layers. Currently, access to the remote protocol layer (Protocol Layer) or higher layers is through the main band. Access through the main band not only adds complex training and calibration logic to the processing of the main band access request, but also occupies the bandwidth of the main band. Therefore, there is an urgent need for a method that can access the remote protocol layer or higher layers without occupying the main band resources. Summary of the invention

[0004] In view of the above technical problems, the technical solution adopted by the present invention is: a high-level access method based on the UCIe mailbox mechanism, the method comprising the following steps:

[0005] The adapter layer of the receiving chip receives and parses the sideband register access request packet sent by the sending chip to obtain the destination address.

[0006] When the destination address is located in the register address space of a high-level layer, the adapter layer sends the sideband register access request packet to the high-level layer through the sideband interface cfg in the flow-aware chip-to-chip interface FDI; the high-level layer is the protocol layer or its upper layer; the sideband register access request packet is used to trigger the high-level layer to feedback the access result to the adapter layer through the cfg in the FDI.

[0007] After receiving the access result, the adapter layer writes the access result into a mailbox register; the adapter layer packages the access result and related data in the mailbox register to form a sideband access completion transaction; and feeds back the sideband access completion transaction to the sending end chip.

[0008] In addition, the present invention also provides a non-transitory computer-readable storage medium, in which at least one instruction or at least one program is stored, and the at least one instruction or the at least one program is loaded and executed by a processor to implement the above method.

[0009] In addition, the present invention also provides an electronic device, including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0010] The present invention has at least the following beneficial effects:

[0011] The present invention provides a remote access method, device and storage medium based on the UCIe mailbox mechanism, which determines whether it is a high-level register address space according to the destination address obtained by parsing the sideband register access request packet. If so, the high-level layer is accessed by utilizing the sideband interface cfg specified in the UCIe protocol, thereby realizing efficient and flexible access to the high-level layer through the sideband without CPU intervention, and conforming to the UCIe protocol specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A flow chart of a high-level access method based on the UCIe mailbox mechanism provided by an embodiment of the present invention;

[0014] Figure 2A schematic diagram of a structure of a sending end accessing a receiving end provided by an embodiment of the present invention;

[0015] Figure 3 A schematic diagram of a mailbox register in the UCIe protocol is provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0017] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meanings as commonly understood by those skilled in the art.

[0018] See also Figure 1 , which shows a high-level access method based on the UCIe mailbox mechanism, the method comprising the following steps:

[0019] S100, the adapter layer of the receiving end chip receives and parses the sideband register access request packet sent by the sending end chip to obtain a destination address.

[0020] Among them, the UCIe (Universal Chiplet Interconnect Express) protocol is an open industry interconnection standard designed to achieve package-level interconnection between chiplets (or Dies for short). The UCIe protocol includes a protocol layer, an adapter layer, and a physical layer. The protocol layer reuses existing protocols such as PCIe and CXL; the adapter layer is responsible for reliable data transmission, arbitration and multiplexing, link state management, and parameter negotiation; the physical layer is responsible for link initialization, training, and power management status.

[0021] Among them, see Figure 2 The adapter layer (Adapter) of UCIe is located between the protocol layer and the physical layer. It is connected to the upper layer through the sideband interface cfg of the flow-aware die-to-die interface (FDI), and is connected to the physical layer through the RDI (Raw Die-to-Die Interface) interface.

[0022] In one embodiment, the transmitting chip and / or the receiving chip is a processor chip (CPU), a graphics processing unit (GPU) or an accelerator chip (Accelerators), and other types of chips also fall within the protection scope of the present invention.

[0023] The UCIe adapter layer includes a mailbox module, which includes a plurality of mailbox registers, which are used to store and forward access requests and response data to the remote chip (receiving chip) according to the mailbox mechanism. Figure 2 , the mailbox mechanism is explained by taking the high-level of the sending chip needing to remotely access the registers or data of the receiving chip as an example: the high-level of the sending chip sends the sideband request transaction to the adapter layer through the sideband interface cfg of the FDI interface; the adapter layer parses the header information of the sideband request transaction. If it is parsed as a remote access to the receiving chip, the relevant information of the sideband request transaction, such as the address, operation type, data load, etc., is written into one or more mailbox registers; and a sideband register access request packet for accessing the remote end is generated based on the mailbox register; the sideband register access request packet is sent to the physical layer through RDI, and the physical layer sends it to the receiving chip through the UCIe sideband link (Sideband). After the receiving chip processes the request, it returns the response data to the mailbox module of the sending chip and stores it in the mailbox register of the sending chip. Finally, the high-level of the sending chip can check the status of the mailbox register through periodic polling or interrupt mechanism. Once new response data is found, the response data can be read from the mailbox register to complete the entire access process. Indirect access of the high-level of the sending chip to the receiving chip is realized.

[0024] It should be noted that the mailbox mechanism is mainly used to indirectly access the physical layer and adapter layer related registers of the remote receiving chip or the related registers between the two, and cannot directly access the protocol layer or higher-level logic of the receiving end. This is determined by the design of the UCIe protocol itself.

[0025] Among them, a sideband request transaction is a communication unit on a sideband channel, which is used to transmit requests and responses between interconnected components. A sideband request transaction includes a set of defined symbols or data packets used to perform specific operations, such as reading or writing sideband registers, managing connection status, etc. It should be noted that when a sideband request transaction includes a data packet, the data packet will include necessary address information and access type, such as the destination address of read or write, so that the recipient can perform the corresponding register access operation.

[0026] S200, when the destination address is located in the register address space of the high-level layer, the adapter layer sends the sideband register access request packet to the high-level layer through the sideband interface cfg in the flow-aware chip-to-chip interface FDI; the high-level layer is the protocol layer or its upper layer; the sideband register access request packet is used to trigger the high-level layer to feedback the access result to the adapter layer through the cfg in the FDI.

[0027] In order to solve the problem that the sideband signal cannot interact with the high-level layer, the embodiment of the present invention uses the sideband interface cfg specified in the UCIe protocol as the access interface for the adapter layer to access the high-level layer, and determines whether the destination address in the sideband request transaction is located in the register address space of the high-level layer. If so, it is accessed through cfg. That is, the solution provided by the embodiment of the present invention follows the sideband signal-related conventions defined by the UCIe protocol, and all operations meet the UCIe protocol specifications. It accesses the high-level layer through the destination address combined with the original sideband interface of the UCIe protocol, and realizes efficient and flexible access to the high-level layer of the receiving chip without CPU intervention. This mechanism is compatible with the UCIe protocol specification, realizes significant expansion and enhancement of the existing mailbox mechanism function, and reduces the implementation complexity by minimizing the system transformation requirements.

[0028] Among them, the protocol layer is responsible for supporting one or more protocol implementations supported by UCIe, such as PCIe, CXL, etc. The UCIe protocol standard stipulates that the adapter layer can only access the protocol layer through the main band, and cannot access the protocol layer through the side band.

[0029] Among them, the upper layer is the logic at a higher level than the adapter layer, such as the system side, application program, etc., and usually does not directly interact with the sideband signal of the UCIe protocol.

[0030] In one implementation, the sideband register access request packet complies with the UCIe protocol standard.

[0031] Among them, the step of determining whether the destination address is located in a high-level register address space is also included before S200. There are two solutions to this determination step.

[0032] The first solution is based on the address judgment of the sideband register access request packet (Sideband Register Access Request Packets). The UCIe protocol specifies the address range of the registers located in the adapter layer and the physical layer, and there is an unused address space, hereinafter referred to as the reserved address bit. The embodiment of the present invention uses the reserved address bit as the address space of the register of the protocol layer or its upper layer, so that when the adapter layer of the receiving chip determines the routing target, it parses the received sideband register access request packet and determines the object to be accessed according to the address obtained after the parsing. If the reserved address bit obtained by the parsing is not empty, the adapter layer initiates access to the higher layer based on the address of the reserved address bit.

[0033] In one embodiment, before S100, the step of configuring the address in the sideband register access request packet at the transmitting end is also included: when the transmitting end chip accesses the upper layer of the receiving end chip, the reserved address bit in the sideband register access request packet is configured as the address of the upper layer of the receiving end chip.

[0034] In one embodiment, after the adapter layer at the receiving end parses and obtains the destination address, the method also includes a step of determining whether the destination address is located in a high-level register address space: obtaining a reserved address bit in the destination address, and when the address of the reserved address bit is located in a high-level register address space, determining that the destination address is located in a high-level register address space.

[0035] The second solution is to use the unused reserved bits in the mailbox register as trigger signals for accessing the remote upper layer. Figure 3 As shown, Figure 3 The figure is a schematic diagram of the mailbox register in the UCIe protocol. The mailbox module includes the sideband mailbox index low register, the sideband mailbox index high register, the sideband mailbox data low register, the sideband mailbox data high register, the sideband mailbox control register, the sideband mailbox status register and the reserved bit.

[0036] In one embodiment, before S100, the sending end also includes a step of configuring the mailbox register: defining and allocating the reserved bits specified in the mailbox register as control signals for accessing the remote upper layer. These reserved bits are set outside the standard definition of the UCIe protocol through software or hardware configuration, and can be configured through local register access transactions, sideband transactions or other methods. After configuration, the sending end generates a sideband register access request packet based on the access transaction and its related data stored in the mailbox register, that is, the control signal including the reserved bit.

[0037] In one embodiment, after the adapter layer at the receiving end parses and obtains the destination address, the method also includes a step of determining whether the destination address is located in a high-level register address space: obtaining a reserved bit of a mailbox register in the destination address, and when the value of the reserved bit is a valid value, determining that the destination address is located in a high-level register address space.

[0038] Among them, at the adapter layer in the receiving end chip, after the adapter layer receives the sideband register access request packet, the adapter layer parses the sideband register access request packet and decides to access the registers of the adapter layer, physical layer or protocol layer. If the result of the parsing is to access the adapter layer, the adapter layer completes the register access operation, packages the register access result and its related data in the sideband access completion transaction, and replies to the sending end. If the result of the parsing is to access the physical layer, the adapter layer initiates a sideband access request to the physical layer based on the result of the parsing, and sends the sideband access completion transaction to the adapter layer after the physical layer processing is completed. The adapter layer packages the register access result and its related data in the sideband access completion transaction and replies to the sending end. If the result of the parsing is to access the high layer, the adapter layer accesses the high layer through the sideband transaction, and after the access is completed, the access result and its related data are packaged in the sideband access completion transaction, and replies to the sending end.

[0039] The present invention mainly improves the adapter layer of UCIe to achieve access to the remote protocol layer and upper layers. Compared with the original UCIe protocol, the changes are relatively small. The advantages lie in its simplicity and convenience. By directly utilizing the resources in the existing protocol, the extended functions can be achieved without large-scale modifications to the UCIe protocol.

[0040] S300, after receiving the access result, the adapter layer writes the access result into a mailbox register; the adapter layer packages the access result and related data in the mailbox register to form a sideband access completion transaction; and feeds back the sideband access completion transaction to the sending end chip in the original path.

[0041] In one implementation, the step of feeding back the sideband access completion transaction to the transmitting end chip includes: feeding back the sideband access completion transaction to the physical layer through the original data interface RDI, and the physical layer feeding back the sideband access completion transaction to the transmitting end chip through the UCIe sideband link. The transmitting end chip then returns through the physical layer and the adapter layer in sequence.

[0042] In summary, the present invention provides a high-level access method based on the UCIe mailbox mechanism, which receives and parses the sideband register access request packet sent by the sending chip through the adapter layer of the receiving chip, and determines whether it is a high-level space according to the parsing result. If so, the high level is accessed by using the sideband interface cfg specified in the UCIe protocol, thereby realizing efficient and flexible access to the high level of the receiving chip without CPU intervention. It follows the sideband signal related conventions defined by the UCIe protocol, and all operations must meet the UCIe protocol specifications, which reduces the implementation complexity by minimizing the system modification requirements.

[0043] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0044] An embodiment of the present invention further provides an electronic device, comprising a processor and the aforementioned non-transitory computer-readable storage medium.

[0045] An embodiment of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0046] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0047] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A high-level access method based on the UCIe mailbox mechanism, characterized in that: The method comprises the following steps: The adapter layer of the receiving chip receives and parses the sideband register access request packet sent by the sending chip to obtain the destination address; When the destination address is located in the register address space of the higher layer, the adapter layer sends the sideband register access request packet to the higher layer through the sideband interface cfg in the flow-aware chip-to-chip interface FDI; The high layer is a protocol layer or an upper layer thereof; The sideband register access request packet is used to trigger the high layer to feed back the access result to the adapter layer through the cfg in the FDI; After receiving the access result, the adapter layer writes the access result into a mailbox register; The adapter layer packages the access result and related data in the mailbox register to form a sideband access completion transaction; The sideband access completion transaction is fed back to the sending end chip in the original path.

2. The method according to claim 1, characterized in that The sideband register access request packet complies with the UCIe protocol standard.

3. The method according to claim 1, characterized in that The step of feeding back the sideband access completion transaction to the transmitting end chip includes: feeding back the sideband access completion transaction to the physical layer through the original data interface RDI, and the physical layer feeding back the sideband access completion transaction to the transmitting end chip through the UCIe sideband link.

4. The method according to claim 1, characterized in that: After obtaining the destination address, the method further comprises the step of determining whether the destination address is located in a high-level register address space: A reserved address bit in the destination address is obtained, and when the address of the reserved address bit is located in a high-level register address space, it is determined that the destination address is located in the high-level register address space.

5. The method according to claim 4, characterized in that The method also includes the step of configuring the address in the sideband register access request packet at the transmitting end: when the transmitting end chip accesses the upper layer of the receiving end chip, the reserved address bit in the sideband register access request packet is configured as the address of the upper layer of the receiving end chip.

6. The method according to claim 1, characterized in that After obtaining the destination address, the method further comprises the step of determining whether the destination address is located in a high-level register address space: After the adapter layer of the receiving chip receives and parses the sideband register access request packet sent by the sending chip, it also includes: writing the parsed destination address and other relevant data into the mailbox register; obtaining the reserved bit of the mailbox register, and when the value of the reserved bit is a valid value, it is determined that the destination address is located in the high-level register address space.

7. The method according to claim 6, characterized in that The method further comprises the step of configuring a mailbox register at the transmitting end: defining and allocating a designated reserved bit in the mailbox register as a control signal for accessing a remote high layer.

8. The method according to claim 1, characterized in that The receiving end chip is a processor chip, a graphics processing unit or an accelerator chip.

9. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by the processor to implement the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 9.

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