Storage and calculation fusion type arithmetic unit

Abstract

The invention relates to storage and calculation fusion, in particular to a storage and calculation fusion type arithmetic unit which is characterized in that a multiplier MUL is used for completing multiplication, and a source operand comes from a local cache MO or a register REG; the adder ADD is used for completing additive operation, and source operands come from the local cache MO, the accumulation register ACC or the register REG; the truncator CUT is used for completing truncating operation, and source operands come from the local cache MO, the accumulation register ACC or the register REG; the ACC is used for caching an intermediate result of the operation of the PE; the local cache MO is used for caching an intermediate result of the operation of the operation unit PE, can be used as a source operand of the operation of the operation unit PE, and can broadcast the stored content to other operation units PE to jointly participate in the operation; according to the technical scheme provided by the invention, the defects of relatively poor computing power expansibility and relatively low memory access efficiency in the prior art can be effectively overcome.

Description

Technical Field

[0001] The present invention relates to storage and computing fusion, and in particular to a storage and computing fusion computing unit. Background Art

[0002] The arithmetic unit is the source of computing power for high-computing-power processors. The number of multiplication and addition operations completed per second is usually used as the main indicator to measure the computing power of the processor. This indicator involves the number of arithmetic units and the operating frequency of the arithmetic units. That is, a large number of arithmetic units need to be integrated inside the high-computing-power processor. At the same time, the arithmetic units need to meet the physical design constraints and achieve a higher operating frequency. The arithmetic unit design mainly includes two types of design schemes, one is a vector processor based on vector registers, and the other is a data stream processor based on coarse-grained reconfigurable arithmetic units. These two types of design schemes face the problems of computing power scalability and memory access efficiency respectively.

[0003] For vector processors, vector instructions have high execution efficiency, and continuous and regular vector memory access addresses are very friendly to the storage system. The data bandwidth and computing power match, which is very suitable for streaming processing scenarios in the field of digital signals. However, the performance scalability of the computing architecture based on LOAD / STORE is poor, and the communication between the operation units needs to be completed through a centralized register file. When the application scale increases, whether it is to improve the processor performance by increasing the transmission width or expanding the number of registers, the cost in area and power consumption is very high. On the other hand, the vector processor centrally controls the computing resources ALU (Arithmetic Logic Units) and storage resources based on the instruction stream. Each computing resource ALU obtains the operation data from the centralized storage system and writes the operation results back to it. The frequent data exchange in the storage and computing separation architecture causes a lot of power consumption to be wasted on the bus.

[0004] Different from the centralized control and storage design of vector processors, each operation unit in the data flow processor has independent control logic and can carry local storage, such as local cache or register files. The entire structure adopts data flow control, that is, all operation units form a processing chain relationship, and data is directly transferred between operation units. The data flow processor is based on configuration or data-driven execution, which can avoid excessive serialization of operation unit execution. The communication link of the underlying computing architecture is exposed through the software and hardware interface to realize distributed instruction issuance, which can avoid data communication of active instructions based on register files. Data flow graph configuration instructions can reduce the hardware overhead related to instruction issuance. However, compared with the continuous and regular memory access characteristics of vector processors, the memory access efficiency of data flow processors is low. The spatially distributed memory access addresses are difficult to merge into the vector-style continuous memory access addresses, which will generate a large number of redundant addresses, resulting in low memory access efficiency. Summary of the invention

[0005] 1. Technical issues to be solved

[0006] In view of the above-mentioned shortcomings of the prior art, the present invention provides a storage-computing fusion computing unit, which can effectively overcome the defects of poor computing power scalability and low memory access efficiency in the prior art.

[0007] (II) Technical solution

[0008] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0009] A storage-computation fusion operation unit comprises a multiplier MUL, an adder ADD, a bit cutter CUT, an accumulation register ACC and a local cache MO;

[0010] Multiplier MUL, performs multiplication operation, and the source operand comes from the local cache MO or register REG;

[0011] Adder ADD, completes the addition operation, the source operand comes from the local cache MO, the accumulator register ACC or the register REG;

[0012] The bit cutter CUT performs the bit cut operation, and the source operand comes from the local cache MO, the accumulator register ACC or the register REG;

[0013] Accumulator register ACC is used to cache the intermediate results of the calculation unit PE;

[0014] The local cache MO is used to cache the intermediate results of the operation of the operation unit PE, can be used as the source operand of the operation of the operation unit PE, and can broadcast the storage content to other operation units PE to participate in the operation together.

[0015] Preferably, the operation unit PE also includes selectors MUX1, MUX2, MUX3, MUX4, and MUX5, the input ends of the selectors MUX1 and MUX2 are both connected to the register REG and the local cache MO, the input end of the multiplier MUL is connected to the selectors MUX1 and MUX2, the input end of the adder ADD is connected to the multiplier MUL and the selector MUX5, the input end of the selector MUX3 is connected to the multiplier MUL and the adder ADD, the input end of the accumulator register ACC is connected to the selector MUX3, the input end of the selector MUX5 is connected to the accumulator register ACC and the accumulator register ACC, the input end of the truncation device CUT is connected to the accumulator register ACC, the input end of the selector MUX4 is connected to the multiplier MUL and the truncation device CUT, and the input end of the truncation device CUT is connected to the selector MUX4.

[0016] Preferably, the input end of the register REG is connected to the selector MUX6, and the input end of the selector MUX6 is connected to the multiplier MUL, the accumulator register ACC and the local cache MO.

[0017] Preferably, when the operation unit PE supports 16-bit operation precision, it includes 4 16-bit multipliers MUL, 4 32-bit adders ADD, 2 16-bit truncation registers CUT and 2 40-bit accumulation registers ACC, and can complete 4 16-bit multiplication and accumulation and truncation operations inside the operation unit PE;

[0018] When the operation unit PE supports 32-bit operation precision, it includes a 32-bit multiplier MUL, a 64-bit adder ADD, a 32-bit truncation register CUT and a 72-bit accumulation register ACC, and can complete a 32-bit multiplication-accumulation and truncation operation inside the operation unit PE.

[0019] Preferably, the arithmetic unit PE supports different arithmetic precisions through hardware multiplexing, that is, 32-bit arithmetic precision is realized based on 16-bit arithmetic precision;

[0020] Among them, a 32-bit multiplication operation is implemented by four 16-bit multipliers MUL, three 32-bit adders ADD, two 16-bit truncation devices CUT and one 32-bit truncation device CUT.

[0021] Preferably, the local cache MO is composed of two or more static random access memory units SRAM, with staggered addressing;

[0022] Among them, the two static random access memory cells SRAM are MO_0 and MO_1 respectively, all storage addresses inside MO_0 are even addresses, and all storage addresses inside MO_1 are odd addresses.

[0023] Preferably, the operation unit PE further includes a base address register MB, and the local cache MO is addressed by using the base address register MB+immediate number. For accessing the local cache MO, only the immediate number needs to be specified, and the base address register MB+immediate number will be used as the access address.

[0024] Among them, the bit width of the base address register MB is log2 (the depth of the local cache MO).

[0025] Preferably, the execution pipeline structure of the computing unit PE is divided into 6 levels, namely:

[0026] S0: Generate the memory access address of the local cache MO. The local cache MO addressing adopts the base address register MB + immediate value mode;

[0027] S1: local cache MO outputs data storage, register REG outputs stored data;

[0028] S2: Multiplier MUL input source operand selection, the source operand comes from the local cache MO or register REG;

[0029] S3: perform multiplication operation;

[0030] S4: read the accumulator register ACC to perform an addition operation, and write the result back to the accumulator register ACC; read the accumulator register ACC to perform a truncation operation, and write the result back to the local cache MO or register REG;

[0031] S5: Output the operation result of the operation unit PE and write it back to the local cache MO or register REG.

[0032] (III) Beneficial effects

[0033] Compared with the prior art, the storage-computation fusion computing unit provided by the present invention has the following beneficial effects:

[0034] 1) The proposed storage-computation fusion architecture can effectively save memory access bandwidth. The data required by each computing unit PE to perform operations no longer passes through the centralized register REG. The data can be stored in the local cache MO to perform operations. The intermediate results of the operation do not need to be written back to the centralized register REG, but can be cached in the accumulator register ACC, or written to the local cache MO after truncation. In a well-designed algorithm, this architecture does not need to repeatedly read and write external data memory, and all operations can be completed based on the on-chip local cache MO;

[0035] 2) The proposed storage-computing fusion architecture has good computing power scalability. The computing unit PE is not only an independent computing unit, but also can be interconnected through a bus to form an array structure. The array structure can be expanded according to the computing power requirements. For example, an 8*8 PE array consisting of 64 computing units PE in total. Multiple PE arrays can also be expanded through spatial dimensions to form a processor computing core with higher computing power.

[0036] 3) In response to different computing precision requirements, the computing unit PE adopts a hardware reuse solution. Hardware reuse can reduce the hardware implementation cost. A high-precision operation can be obtained by combining the intermediate results of multiple low-precision operations, and more computing resources can be provided when performing low-precision operations.

[0037] 4) The local cache MO inside the proposed storage-computing fusion architecture is composed of two or more static random access memory cells SRAM, with interleaved addressing and the addressing method of base address register MB + immediate value. This storage-computing fusion architecture has the characteristics of software programmability. At the same time, since the base address register MB is the private register of each computing unit PE, it has the advantage of low fan-out in physical implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 It is a schematic diagram of the data path of the computing unit PE in the present invention;

[0040] Figure 2 It is a schematic diagram of the structure of the operation unit PE in the present invention supporting 16-bit operation precision;

[0041] Figure 3 It is a schematic diagram of the structure of the operation unit PE in the present invention supporting 32-bit operation precision;

[0042] Figure 4 It is a schematic diagram of the structure of the operation unit PE in the present invention multiplexing 16-bit multiplication operation when executing 32-bit multiplication operation;

[0043] Figure 5 Schematic diagram of the address of the local cache MO inside the computing unit PE in the present invention;

[0044] Figure 6 It is a schematic diagram of the local cache MO inside the computing unit PE in the present invention using the base address register MB + immediate number for addressing;

[0045] Figure 7 It is a timing diagram of the execution pipeline structure of the computing unit PE in the present invention. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] A storage-computation fusion computing unit, such as Figure 1 As shown, it includes a multiplier MUL, an adder ADD, a bit truncation CUT, an accumulator register ACC and a local cache MO;

[0048] Multiplier MUL, performs multiplication operation, and the source operand comes from the local cache MO or register REG;

[0049] Adder ADD, completes the addition operation, the source operand comes from the local cache MO, the accumulator register ACC or the register REG;

[0050] The bit cutter CUT performs the bit cut operation, and the source operand comes from the local cache MO, the accumulator register ACC or the register REG;

[0051] Accumulator register ACC is used to cache the intermediate results of the calculation unit PE;

[0052] The local cache MO is used to cache the intermediate results of the operation of the operation unit PE, can be used as the source operand of the operation of the operation unit PE, and can broadcast the storage content to other operation units PE to participate in the operation together.

[0053] In the technical solution of the present application, the operations that the operation unit PE can perform include multiplication, addition, multiplication-accumulation and truncation operations. The storage-computation fusion architecture means that the multiplier MUL, adder ADD, truncation CUT, accumulator register ACC and local cache MO are all integrated in the same module, that is, Figure 1 The design of integrating the operation unit and the memory can reduce the memory access overhead during operation. Each operation unit PE has an independent workspace and only needs to access the local cache MO during the operation, without accessing the centralized register REG, which meets the data locality characteristics and can maximize the use of limited memory access bandwidth.

[0054] like Figure 1 As shown, the operation unit PE also includes selectors MUX1, MUX2, MUX3, MUX4, and MUX5. The input ends of the selectors MUX1 and MUX2 are connected to the register REG and the local cache MO. The input end of the multiplier MUL is connected to the selectors MUX1 and MUX2. The input end of the adder ADD is connected to the multiplier MUL and the selector MUX5. The input end of the selector MUX3 is connected to the multiplier MUL and the adder ADD. The input end of the accumulator register ACC is connected to the selector MUX3. The input end of the selector MUX5 is connected to the accumulator register ACC and the accumulator register ACC. The input end of the truncation device CUT is connected to the accumulator register ACC. The input end of the selector MUX4 is connected to the multiplier MUL and the truncation device CUT. The input end of the truncation device CUT is connected to the selector MUX4.

[0055] An input end of the register REG is connected to the selector MUX6, and an input end of the selector MUX6 is connected to the multiplier MUL, the accumulator register ACC and the local cache MO.

[0056] Figure 1The data path of the operation unit PE shown can implement multiplication, addition, multiplication-accumulation and truncation operations based on the multiplier MUL, adder ADD, truncation device CUT, accumulator register ACC and local cache MO, and the operation results can be written back to the local cache MO or register REG.

[0057] The following is a multiplication and accumulation operation to illustrate the workflow of the calculation unit PE. Figure 1 The corresponding data path is indicated by a black line in the figure. The corresponding instruction form is ACC+=MO[0]*MO[1]. This instruction means to perform multiplication on the values ​​of two static random access memory cells SRAM and accumulate the multiplication result to the accumulator register ACC. The two operands of the multiplier MUL come from MO[0] and MO[1] (corresponding to Figure 1 2.1, 2.2), the multiplication result is used as a source operand of the adder ADD (corresponding to Figure 1 3.2), the other operand of the adder ADD comes from the accumulator register ACC (corresponding to Figure 1 6), the operation result of adder ADD (corresponding to Figure 1 7) is output to the accumulator register ACC after being passed through the selector MUX3, and the above process is repeated to complete the entire multiplication and accumulation operation. In addition, the data stored in the accumulator register ACC can also be truncated and output to the local cache MO (corresponding to Figure 1 4.3→9 data path).

[0058] This storage-computation fusion operation unit design allows each operation unit PE to directly access the local cache MO, and the operation results can also be directly written back to the local cache MO. When designing a high-computing power processor, multiple operation units PE can be used to form a PE array. The source operands and destination operands of these operation units PE are all from local storage, thereby reducing the read and write pressure of the register REG. It is an effective operation unit design scheme that can expand the computing power of the processor.

[0059] like Figure 2 As shown, when the operation unit PE supports 16-bit operation precision, it includes 4 16-bit multipliers MUL, 4 32-bit adders ADD, 2 16-bit truncation registers CUT and 2 40-bit accumulation registers ACC, and can complete 4 16-bit multiplication and accumulation and truncation operations inside the operation unit PE;

[0060] like Figure 3 As shown, when the operation unit PE supports 32-bit operation precision, it includes a 32-bit multiplier MUL, a 64-bit adder ADD, a 32-bit truncation register CUT and a 72-bit accumulation register ACC, and can complete a 32-bit multiplication and accumulation and truncation operation inside the operation unit PE.

[0061] like Figure 4 As shown, the operation unit PE supports different operation precisions through hardware multiplexing, that is, 32-bit operation precision is realized based on 16-bit operation precision;

[0062] Among them, a 32-bit multiplication operation is implemented by four 16-bit multipliers MUL, three 32-bit adders ADD, two 16-bit truncation devices CUT and one 32-bit truncation device CUT.

[0063] like Figure 2 and Figure 3 As shown in the figure, comparing the structures of 16-bit operation precision and 32-bit operation precision, the ratio of the number of multipliers MUL and adders ADD is 4:1. Therefore, the operation unit PE supports different operation precisions through hardware multiplexing, that is, 32-bit operation precision is implemented based on 16-bit operation precision. This design can save area overhead.

[0064] like Figure 4 As shown, one 32-bit multiplication operation (AB*CD) can be implemented by four 16-bit multipliers MUL, three 32-bit adders ADD, two 16-bit truncation devices CUT and one 32-bit truncation device CUT. Figure 4 In the figure, AB and CD represent 32-bit data respectively, where A and C correspond to the upper 16-bit data of AB and CD respectively, and B and D correspond to the lower 16-bit data of AB and CD respectively. Using the multiplication crossover operation rule, the intermediate result of two 32-bit operations is the result of four 16-bit multiplication plus shift operations. Figure 4 In the figure, labels ①, ②, ③ and ④ are used to represent the intermediate results respectively, and finally these four intermediate results are accumulated through the addition tree to obtain the final 32-bit multiplication result.

[0065] like Figure 5 As shown, the local cache MO is composed of two or more static random access memory cells SRAM, which are interleavedly addressed;

[0066] Among them, the two static random access memory cells SRAM are MO_0 and MO_1 respectively, all storage addresses inside MO_0 are even addresses, and all storage addresses inside MO_1 are odd addresses.

[0067] like Figure 6 As shown, the operation unit PE also includes a base address register MB, and the local cache MO addressing adopts the base address register MB + immediate number mode. For the access to the local cache MO, only the immediate number needs to be specified, and the base address register MB + immediate number will be used as the access address;

[0068] Among them, the bit width of the base address register MB is log2 (local cache MO depth). If the local cache MO depth is 256, the bit width of the base address register MB is 8 bits.

[0069] like Figure 6 As shown, the immediate value IMM encoded by the software instruction is 4, and the base address register MB is A, then the hardware directly uses MO[A+4] as the access address.

[0070] The local cache MO designed above has the following advantages:

[0071] 1) The base address register MB is a private register of each computing unit PE. Access to the local cache MO does not need to go through a centralized address register or a general register, so there will be no problem of high register fan-out;

[0072] 2) In the instruction form, only the immediate value offset needs to be encoded. The base address register MB, as an implicit value, does not need to be encoded. The bit width of the immediate value offset is significantly smaller than the absolute value of the immediate value, thereby saving instruction encoding resources;

[0073] 3) When designing a loop program, assign a value to the base address register MB at the beginning of the loop, and directly operate the immediate index inside the loop body. If you need to loop through another local cache MO, directly modify the base address register MB at the beginning of the loop without modifying the internal code of the loop body.

[0074] The computing unit designed by the present invention has a storage unit that directly participates in the computing, so it is necessary to reasonably design the pipeline to meet the physical design timing requirements, such as Figure 7 As shown in the figure (the registers shown in the dotted line position are pipeline registers), the execution pipeline structure of the operation unit PE is divided into 6 levels, namely:

[0075] S0: Generate the memory access address of the local cache MO. The local cache MO addressing adopts the base address register MB + immediate value mode;

[0076] S1: local cache MO outputs data storage, register REG outputs stored data;

[0077] S2: Multiplier MUL input source operand selection, the source operand comes from the local cache MO or register REG;

[0078] S3: perform multiplication operation;

[0079] S4: read the accumulator register ACC to perform an addition operation, and write the result back to the accumulator register ACC; read the accumulator register ACC to perform a truncation operation, and write the result back to the local cache MO or register REG;

[0080] S5: Output the operation result of the operation unit PE and write it back to the local cache MO or register REG.

[0081] In the above technical solution, the S1 pipeline stage directly stores the output data of the local cache MO, which is to meet the timing requirements of memory access; the S2 pipeline stage selects the source operand and then performs a partial multiplication operation, and stores the intermediate result. This is because the multiplication operation usually takes a long time, so a separate pipeline is designed to complete the multiplication pre-operation; the S4 pipeline stage implements the accumulation of the accumulator register ACC and the truncation of the accumulator register ACC. These two types of operations are located in the same pipeline stage. Placing the reading and writing of the accumulator register ACC in the same pipeline stage can realize the reading and writing of ACC without data dependency.

[0082] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A storage-computation fusion computing unit, characterized in that: It includes a multiplier MUL, an adder ADD, a bit truncation CUT, an accumulator register ACC and a local cache MO; Multiplier MUL, performs multiplication operation, and the source operand comes from the local cache MO or register REG; Adder ADD, completes the addition operation, the source operand comes from the local cache MO, the accumulator register ACC or the register REG; The bit cutter CUT performs the bit cut operation, and the source operand comes from the local cache MO, the accumulator register ACC or the register REG; Accumulator register ACC is used to cache the intermediate results of the calculation unit PE; The local cache MO is used to cache the intermediate results of the operation of the operation unit PE, can be used as the source operand of the operation of the operation unit PE, and can broadcast the storage content to other operation units PE to participate in the operation together.

2. The storage-computation fusion computing unit according to claim 1, characterized in that: The operation unit PE also includes selectors MUX1, MUX2, MUX3, MUX4, and MUX5. The input ends of the selectors MUX1 and MUX2 are both connected to the register REG and the local cache MO. The input end of the multiplier MUL is connected to the selectors MUX1 and MUX2. The input end of the adder ADD is connected to the multiplier MUL and the selector MUX5. The input end of the selector MUX3 is connected to the multiplier MUL and the adder ADD. The input end of the accumulator register ACC is connected to the selector MUX3. The input end of the selector MUX5 is connected to the accumulator register ACC and the accumulator register ACC. The input end of the truncation device CUT is connected to the accumulator register ACC. The input end of the selector MUX4 is connected to the multiplier MUL and the truncation device CUT. The input end of the truncation device CUT is connected to the selector MUX4.

3. The storage-computation fusion computing unit according to claim 2, characterized in that: The input end of the register REG is connected to the selector MUX6, and the input end of the selector MUX6 is connected to the multiplier MUL, the accumulator register ACC and the local cache MO.

4. The storage-computation fusion computing unit according to claim 1, characterized in that: When the operation unit PE supports 16-bit operation precision, it includes 4 16-bit multipliers MUL, 4 32-bit adders ADD, 2 16-bit truncation registers CUT and 2 40-bit accumulation registers ACC, and can complete 4 16-bit multiplication and accumulation and truncation operations inside the operation unit PE; When the operation unit PE supports 32-bit operation precision, it includes a 32-bit multiplier MUL, a 64-bit adder ADD, a 32-bit truncation register CUT and a 72-bit accumulation register ACC, and can complete a 32-bit multiplication-accumulation and truncation operation inside the operation unit PE.

5. The storage-computation fusion computing unit according to claim 4, characterized in that: The arithmetic unit PE supports different arithmetic precisions through hardware multiplexing, that is, 32-bit arithmetic precision is realized based on 16-bit arithmetic precision; Among them, a 32-bit multiplication operation is implemented by four 16-bit multipliers MUL, three 32-bit adders ADD, two 16-bit truncation devices CUT and one 32-bit truncation device CUT.

6. The storage-computation fusion computing unit according to claim 1, characterized in that: The local cache MO is composed of two or more static random access memory units SRAM, with staggered addressing; Among them, the two static random access memory cells SRAM are MO_0 and MO_1 respectively, all storage addresses inside MO_0 are even addresses, and all storage addresses inside MO_1 are odd addresses.

7. The storage-computation fusion computing unit according to claim 6, characterized in that: The operation unit PE also includes a base address register MB. The local cache MO is addressed by the base address register MB + immediate number. For access to the local cache MO, only the immediate number needs to be specified, and the base address register MB + immediate number will be used as the access address. Among them, the bit width of the base address register MB is log2 (the depth of the local cache MO).

8. The storage-computation fusion computing unit according to claim 7, characterized in that: The execution pipeline structure of the computing unit PE is divided into 6 levels, namely: S0: Generate the memory access address of the local cache MO. The local cache MO addressing adopts the base address register MB + immediate value mode; S1: local cache MO outputs data storage, register REG outputs stored data; S2: Multiplier MUL input source operand selection, the source operand comes from the local cache MO or register REG; S3: perform multiplication operation; S4: read the accumulator register ACC to perform an addition operation, and write the result back to the accumulator register ACC; read the accumulator register ACC to perform a truncation operation, and write the result back to the local cache MO or register REG; S5: Output the operation result of the operation unit PE and write it back to the local cache MO or register REG.

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