Storage devices

Abstract

This disclosure provides a storage device. The storage device includes: a storage cell array including a plurality of storage cells and a plurality of redundant storage cells; the plurality of redundant storage cells are configured to repair a faulty storage cell among the plurality of storage cells; a fault address storage circuit storing at least one first fault address corresponding to a first faulty storage cell; a repair logic storage circuit including a plurality of first storage structures and a plurality of second storage structures; the plurality of first storage structures store redundant addresses corresponding to the plurality of redundant storage cells, and the second storage structures store the first faulty addresses; the repair logic storage circuit is configured to: receive a first operation mode command, the first operation mode command including at least one second faulty address corresponding to a second faulty storage cell; the second faulty storage cell is different from the first faulty storage cell; and, in response to the first operation mode command, write the second faulty address to the second storage structure.

Description

Technical Field

[0001] This disclosure relates to the field of memory, and more particularly to a memory device. Background Technology

[0002] With the development of high-performance computing, big data analytics, and in-memory databases, the demand for memory capacity and bandwidth is increasing.

[0003] Driven by the ever-increasing demands for memory capacity density and bandwidth performance, memory manufacturing processes are constantly shrinking and interface speeds are continuously improving. However, at the same time, with process upgrades, the probability of memory errors and the memory failure rate are gradually increasing, posing a significant risk to memory reliability. To repair faults in memory, PostPackage Repair (PPR) is proposed as a memory repair method. This method uses redundant addresses in memory to replace faulty addresses, thereby enabling computer devices to read and write data normally. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a storage device.

[0005] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0006] This disclosure provides a storage device, including: a storage cell array comprising a plurality of storage cells and a plurality of redundant storage cells; the plurality of redundant storage cells being configured to repair a faulty storage cell among the plurality of storage cells; a fault address storage circuit configured to store at least one first fault address corresponding to a first faulty storage cell; and a repair logic storage circuit comprising a plurality of first storage structures and a plurality of second storage structures, wherein the first storage structures and the second storage structures correspond one-to-one and their internal stored data are mutually mapped; the plurality of first storage structures storing redundant addresses corresponding to the plurality of redundant storage cells, and one redundant address corresponding to one first storage structure; the second storage structures storing the first faulty address, and one first faulty address corresponding to one second storage structure; the repair logic storage circuit being configured to: receive a first operation mode command, the first operation mode command including at least one second faulty address corresponding to a second faulty storage cell; the second faulty storage cell being different from the first faulty storage cell; and, in response to the first operation mode command, write the second faulty address to the second storage structure.

[0007] In some embodiments, the first storage structure has a corresponding first storage address, and the second storage structure has a corresponding second storage address; the first operation mode command further includes a third storage address corresponding to the second fault address, and each of the third storage addresses is the same as a second storage address; the repair logic storage circuit is specifically configured to: in response to the first operation mode command, write the second fault address into the corresponding second storage structure according to the third storage address.

[0008] In some embodiments, at least one of the third storage addresses corresponds to a second storage structure storing the first fault address; the repair logic storage circuit is configured to: in response to the first operation mode command, overwrite the first fault address stored in the second storage structure with the second fault address corresponding to at least one of the third storage addresses.

[0009] In some embodiments, at least one of the third storage addresses corresponds to a second storage structure that does not store the first fault address; the repair logic storage circuit is configured to directly write the second fault address into the second storage structure in response to the first operation mode command.

[0010] In some embodiments, the repair logic storage circuit is configured to: in response to power-on of the storage device, obtain the first fault address from the fault address storage circuit; and write the first fault address into the second storage structure in a first preset order; and in response to power-on of the storage device, write the obtained redundant address into the first storage structure in a second preset order.

[0011] In some embodiments, the repair logic storage circuit is further configured to: receive a second operation mode command, the second operation mode command including at least one fourth storage address; each of the fourth storage addresses being identical to a second storage address; and in response to the second operation mode command, read and output the fault address stored in the second storage structure corresponding to the fourth storage address.

[0012] In some embodiments, the repair logic storage circuit is further configured to: receive a third operation mode command, the third operation mode command including at least an access address of the storage cell to be accessed; and in response to the third operation mode command, match the access address with a fault address in the second storage structure; output a first signal if the match is successful, the first signal indicating access to a redundant address corresponding to the successfully matched fault address; and output a second signal if the match fails, the second signal indicating access to the access address.

[0013] In some embodiments, the repair logic storage circuitry includes a content-addressable memory.

[0014] In some embodiments, the fault address storage circuit includes a fuse array or an antifuse array.

[0015] In some embodiments, the storage device further includes a mode register and an interface; the interface is configured to receive bus commands; the mode register is coupled to the interface and the repair logic storage circuit, and is configured to generate a corresponding operation mode command based on the bus command.

[0016] In some embodiments, the interface is coupled to a memory controller, which is configured to: obtain the fault severity of the first faulty memory cell and the fault severity of the second faulty memory cell in the memory device; compare the fault severity of the first faulty memory cell and the fault severity of the second faulty memory cell; determine a third memory address in the repair logic memory circuit for the second faulty address based on the comparison result; and send the bus command containing the third memory address.

[0017] In some embodiments, the memory controller is further configured to: determine a third storage address in the repair logic storage circuit for the second fault address based on the comparison result and in conjunction with the utilization rate of the redundant storage cells.

[0018] In some embodiments, the memory controller is further configured to: determine the third storage address as the second storage address corresponding to the second storage structure storing the first fault address based on the fact that the fault degree of the second fault storage unit is higher than that of the first fault storage unit and the utilization rate of the redundant storage unit is greater than a preset utilization rate; and determine the third storage address as the second storage address corresponding to the second storage structure that does not store the first fault address based on the fact that the fault degree of the second fault storage unit is lower than or equal to that of the first fault storage unit, or the utilization rate of the redundant storage unit is less than or equal to a preset utilization rate.

[0019] In this embodiment, the repair logic storage circuit, in response to a first operation mode command, writes a second fault address to a second storage structure. Here, since the first and second storage structures are in one-to-one correspondence and their internal stored data are mutually mapped, when the second fault address is written to the second storage structure storing the first fault address, the mapping between the first fault address and the redundant address is eliminated, and a new mapping is formed between the second fault address and the redundant address. When the second fault address is written to a second storage structure that does not store the first fault address, a mapping is formed between the second fault address and a redundant address that does not correspond to the first fault address. Thus, the mapping relationship between redundant addresses and fault addresses is updated, improving the accuracy of fault addresses, increasing the utilization rate of redundant addresses, and extending the product's lifespan. Attached Figure Description

[0020] Figure 1 A schematic diagram of the memory structure provided in the embodiments of this disclosure;

[0021] Figure 2 This is a schematic structural block diagram of a storage device provided in an embodiment of the present disclosure;

[0022] Figure 3 A schematic diagram of the storage status of different storage locations in the repair logic storage circuit provided in the embodiments of this disclosure. Figure 1 ;

[0023] Figure 4 A schematic diagram of the storage status of different storage locations in the repair logic storage circuit provided in the embodiments of this disclosure. Figure 2 ;

[0024] Figure 5 A schematic diagram of the storage status of different storage locations in the repair logic storage circuit provided in the embodiments of this disclosure. Figure 3 ;

[0025] Figure 6 A schematic diagram of the storage status of different storage locations in the repair logic storage circuit provided in the embodiments of this disclosure. Figure 4 ;

[0026] Figure 7 A schematic diagram of the storage status of different storage locations in the repair logic storage circuit provided in the embodiments of this disclosure. Figure 5 ;

[0027] Figure 8 This is a schematic structural block diagram of another storage device provided in an embodiment of the present disclosure. Detailed Implementation

[0028] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0029] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0030] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0031] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0032] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0034] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0035] Figure 1 This is a schematic diagram of the memory structure provided in an embodiment of this disclosure. For example... Figure 1 As shown, memory 100 can be a Dual In-line Memory Module (DIMM). A DIMM can be loaded into the host computer through memory slots provided by the motherboard. A DIMM can consist of one or more memory rows 101, and a memory row 101 can include multiple memory chips (memory chips) 102. For example, a memory row 101 includes eight memory chips 102. A memory chip 102 can include multiple memory banks, and a memory bank is an array of multiple storage cells, including multiple rows and multiple columns of storage cells.

[0036] The memory chip 102 in memory 100 may be damaged at the time of manufacture; specifically, the storage cell within memory chip 102 may be damaged. This damaged storage cell cannot be written to or read from. Furthermore, the storage cell may also become damaged during subsequent use of the memory.

[0037] In some embodiments, the host supports checking memory 100 and correcting detected errors, i.e., repairing faults in memory 100. For example, each time memory 100 performs a read / write task, an error checking and correcting (ECC) method is used to identify faults in memory 100. The ECC method is used to identify errors when a small number of bits in memory 100 are faulty. Errors that can be corrected are called corrected errors (CE), or correctable faults. However, if the error correction algorithm is beyond its capabilities, for example, if there are large-scale multi-bit faults in memory 100, error correction will fail, resulting in an uncorrected error (UCE), or uncorrectable fault. When a UCE occurs, it can cause serious malfunctions in the computing device, such as a system crash, resulting in data loss in memory 100.

[0038] To avoid UCE (Underlying Memory Errors), when memory 100 fails, a redundant storage unit can be used to replace the faulty storage unit. That is, when the host sends a command to memory 100, it checks the address information carried in the command. If the address in the command points to the faulty storage unit, the redundant storage unit is accessed instead. Both the redundant storage unit and the faulty storage unit can be located in memory chip 102.

[0039] In this embodiment, PPR (Physical Repair Process) can be used to repair memory 100 faults. Current DDR4 and DDR5 protocols use PPR to manage fault addresses. PPR can be further divided into hardware repair (hard PPR, hPPR) and software repair (soft PPR, sPPR). Both hPPR and sPPR send repair instructions and fault addresses to memory chip 102 through a mode register. hPPR can permanently write the fault address using an electronic fuse array (EFUSE), thus the redundant addresses corresponding to the redundant memory cells mapped to the fault addresses in hPPR are not reclaimable. sPPR, on the other hand, temporarily stores the fault addresses in latches or flip-flops (DFFs), thus the redundant addresses corresponding to the redundant memory cells mapped to the fault addresses in sPPR are reclaimable. Here, both the fault address and the redundant address are physical addresses associated with specific word lines, not logical addresses.

[0040] Here, PPR technology has some drawbacks, specifically: 1. hPPR cannot modify fault addresses stored in EFUSE. It's important to note that these fault addresses include both those written to EFUSE at the memory chip's factory and those written to EFUSE by the user during subsequent use. 2. When using hPPR, once all redundant addresses are mapped to fault addresses, the absence of unused redundant addresses will cause subsequent sPPR to fail.

[0041] However, in actual use of memory 100, there is indeed a need to modify the fault addresses permanently written in EFUSE. For example, when an address is identified as faulty, the faulty storage unit pointed to by that address cannot read or write data normally. However, the host can use ECC to identify the faulty address and correct it. In this case, the faulty storage unit pointed to by the faulty address can actually work normally. However, since the manufacturer has already written the faulty address into EFUSE at the factory, the faulty address cannot be modified, and subsequent users cannot reuse the redundant address used to replace the faulty address through sPPR technology. Furthermore, in subsequent use of memory 100, the faulty storage unit 2 that is generated later may have a more severe fault than the faulty storage unit 1 that was generated earlier. Given a limited number of redundant addresses, the faulty address of faulty storage unit 2 needs to be replaced by a redundant address more than that of faulty storage unit 1; however, the PPR technology involved in the aforementioned embodiments cannot solve this problem.

[0042] Based on this, embodiments of the present disclosure provide a storage device.

[0043] This disclosure provides a storage device comprising: a storage cell array including multiple storage cells and multiple redundant storage cells; the multiple redundant storage cells being configured to repair faulty storage cells among the multiple storage cells; a fault address storage circuit configured to store at least one first fault address corresponding to a first faulty storage cell; and a repair logic storage circuit including multiple first storage structures and multiple second storage structures, wherein the first storage structures and the second storage structures correspond one-to-one and their internal stored data are mutually mapped; the multiple first storage structures store redundant addresses corresponding to multiple redundant storage cells, and one redundant address corresponds to one first storage structure; the second storage structures store first fault addresses, and one first fault address corresponds to one second storage structure; the repair logic storage circuit is configured to: receive a first operation mode command, the first operation mode command including at least one second fault address corresponding to a second faulty storage cell; the second faulty storage cell is different from the first faulty storage cell; and, in response to the first operation mode command, write the second fault address to the second storage structure.

[0044] In some embodiments, the storage device may include a memory chip, such as Figure 1 The memory chip 102 is shown in the figure. In some specific embodiments, the storage device may include random access memory (DRAM), but is not limited thereto. For example, the storage device may be double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), etc.

[0045] In this embodiment of the disclosure, the storage device may also be a storage system including a storage chip, such as... Figure 1 The memory 100 shown is a dual in-line memory module. In this embodiment of the disclosure, the storage device can be coupled to a host, receive bus commands sent from the host, and perform corresponding operations in response to the bus commands.

[0046] In some embodiments, the storage device may be included in various types of electronic devices. The electronic device may include a host computer. Here, the electronic device may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein.

[0047] Figure 2 This is a schematic diagram of the structure of a storage device provided in an embodiment of this disclosure. Figure 2As shown, the storage device 200 includes a memory cell array 201, a fault address storage circuit 202, and a repair logic storage circuit 203. The memory cell array 201 may include multiple memory cells 204 located at the intersections of multiple word lines and multiple bit lines. The memory cell array 201 may also include multiple redundant memory cells 205 located at the intersections of multiple redundant word lines and multiple redundant bit lines. When a fault occurs in a memory cell 204, that is, when a faulty memory cell exists in memory cell 204... Figure 2 When (not shown in the image), the faulty storage unit can be repaired by replacing the faulty address of the faulty storage unit with the redundant address corresponding to the redundant storage unit 205 in the storage unit array 201.

[0048] It should be noted that the storage cells 204 and redundant storage cells 205 included in the storage cell array 201 can be structures or cells with similar structural features obtained according to the same manufacturing process and possessing storage functions. The difference between storage cells 204 and redundant storage cells 205 lies in their different positions in the storage device 200 and their different initial functional positioning. Specifically, storage cells 204 are used to store user data, and redundant storage cells 205 are used to repair faulty storage cells 204, that is, to replace faulty storage cells 204 to perform normal data reading or writing.

[0049] Fault address storage circuit 202 is coupled to memory cell array 201 and configured to store at least one first fault address corresponding to a first fault memory cell in memory cell array 201. The first fault memory cell may include one or more fault memory cells, each corresponding to a first fault address. In other words, fault address storage circuit 202 is configured to store the first fault address corresponding to at least one of the first fault memory cells comprising one or more fault memory cells. Here, the first fault memory cell may be a fault memory cell identified by the manufacturer at the time of manufacture of memory device 200, or it may be a fault memory cell identified by the memory controller during subsequent use. In one example, the memory controller is coupled to memory device 200, and the memory controller and memory device 200 together constitute a memory system.

[0050] In this embodiment of the disclosure, the fault address storage circuit 202 includes a non-volatile storage device, which may be a one-time programmable memory. In some embodiments, the fault address storage circuit 202 includes a fuse array or an antifuse array.

[0051] Here, both the fuse array and the antifuse array are programmable fuse arrays containing fuses. When a fuse in either the fuse array or the antifuse array blows, its resistance changes. At this point, the internal circuitry of the fuse array and antifuse array can convert the fuse resistance value into a corresponding logic value. In other words, depending on the fuse resistance value, the fuse array and antifuse array will generate different voltage levels. These voltage levels can be identified and output by an external reading circuit, thereby enabling programming functionality.

[0052] In one example, after the storage device 200 leaves the factory, post-packaging repair technology can be used to repair faults in the storage device 200, specifically repairing the first faulty storage cell in the storage device 200. Specifically, a hardware repair method can be used, where the fuses in the fuse array are blown to permanently encode the first fault address corresponding to the first faulty storage cell into the fuse array. In this way, the first fault address of the first faulty storage cell stored in the fault address storage circuit 202 cannot be modified.

[0053] In some embodiments, the first storage structure has a corresponding first storage address, and the second storage structure has a corresponding second storage address.

[0054] like Figure 2 As shown, the repair logic storage circuit 203 is coupled to the fault address storage circuit 202. The repair logic storage circuit 203 includes a first storage structure 206 and a second storage structure 207. The first storage structure 206 has a corresponding first storage address, and the second storage structure 207 has a corresponding second storage address. In other words, the first storage address is the address of the first storage structure 206, and the second storage address is the address of the second storage structure 207.

[0055] It should be noted that the storage structure here can be understood in comparison to the storage cell 204 in the aforementioned storage cell array 201. The storage structure here and the aforementioned storage cell 204 can be the smallest storage modules in different memories. The number of first storage structures 206 can be designed according to the number of redundant addresses, and the number of first storage structures 206 can include multiple structures. For example, the number of first storage structures 206 can be greater than or equal to the number of redundant addresses. In some embodiments, the number of second storage structures 207 can be equal to the number of first storage structures 206, thus ensuring a one-to-one correspondence between the first storage structures 206 and the second storage structures 207.

[0056] In some embodiments, the repair logic storage circuit is configured to: obtain a first fault address from the fault address storage circuit in response to power-on of the storage device; and write the first fault address into a second storage structure in a first preset order.

[0057] like Figure 2 As shown, the repair logic storage circuit 203 can, in response to the power-on of the storage device 200, obtain the first fault address of the first fault storage cell from the fault address storage circuit 202. Furthermore, the repair logic storage circuit 203 can write the obtained first fault address into the second storage structure according to a first preset order.

[0058] In some embodiments, the first preset order can be a specific arrangement order determined according to a preset mapping algorithm. Specifically, the first preset order may include the writing order of each first fault address and the position of the second storage structure corresponding to the first fault address in the repair logic storage circuit 203. Since the first storage structure and the second storage structure are in one-to-one correspondence and their internal stored data are mutually mapped, after the first fault address is written to the second storage structure according to this specific arrangement order, a mapping relationship can be formed between the first fault address and the redundant address corresponding to its storage location.

[0059] In other embodiments, writing the first fault address into the second storage structure 207 in a first preset order includes: sequentially writing the first fault address into the second storage structure 207.

[0060] In some embodiments, the repair logic storage circuit is configured to: in response to power-on of the storage device, write the acquired redundant addresses into the first storage structure in a second preset order.

[0061] In this embodiment, the repair logic storage circuit 203 can, in response to the power-on of the storage device 200, obtain the redundant addresses of all redundant storage cells 205 from the initial storage location of the redundant addresses, and write the obtained redundant addresses to the first storage structure in a second preset order. In some embodiments, the initial storage location of the redundant addresses may be located inside the repair logic storage circuit 203. For example, the initial storage location may be located in a non-volatile storage structure inside the repair logic storage circuit 203. This non-volatile storage structure may be a read-only memory (ROM), which can retain data even when the memory is powered off, but the non-volatile storage structure here is not limited to this. In other embodiments, the initial storage location of the redundant addresses may be located outside the repair logic storage circuit 203. For example, the initial storage location may be located in a non-volatile storage structure outside the repair logic storage circuit 203.

[0062] In some embodiments of this disclosure, the second preset order can be a specific arrangement order determined according to a preset mapping algorithm. For details, please refer to the description of the first preset order, which will not be repeated here.

[0063] In other embodiments of this disclosure, writing the acquired redundant addresses into the first storage structure 206 in a second preset order may include: sequentially writing the acquired redundant addresses into the first storage structure 206.

[0064] In this embodiment, the relationship between the storage location of the redundant address in the first storage structure 206 and the storage location of the fault address in the second storage structure 207 determines the mapping relationship between the redundant address and the fault address. In other words, the repair logic storage circuit 203 includes multiple first storage structures 206 and multiple second storage structures 207, and the positions of the multiple first storage structures 206 and the multiple second storage structures 207 correspond one-to-one. The first storage address is the address of the first storage structure 206, and the redundant address of a redundant storage cell is stored in one first storage structure 206. The second storage address is the address of the second storage structure 207, and the fault address of a faulty storage cell is stored in one second storage structure 207. Since the positions of the multiple first storage structures 206 and the multiple second storage structures 207 correspond one-to-one, a mapping relationship between the redundant address and the fault address can be formed.

[0065] In some embodiments, the number of redundant addresses is greater than the number of first fault addresses. That is, the redundant storage units corresponding to the redundant addresses still have some space that can be used to repair faulty storage units other than the first faulty storage units.

[0066] Figure 3 A schematic diagram of the storage status of different storage locations in the repair logic storage circuit provided in the embodiments of this disclosure. Figure 1 For example, such as Figure 3 As shown, the repair logic storage circuit 203 includes multiple first storage structures 206 and multiple second storage structures 207. The repair logic storage circuit 203 can sequentially write multiple redundant addresses into the sequentially arranged first storage structures 206-1, 206-2, 206-3, 206-4, 206-5, and 206-6… The repair logic storage circuit 203 can also obtain the first fault addresses of multiple first fault storage units from the fault address storage circuit 202, and sequentially write these multiple first fault addresses into the sequentially arranged second storage structures 207-1, 207-2, and 207-3…

[0067] It is understandable that the first fault address stored in the second storage structure 207-1 is mapped to the redundant address in the first storage structure 206-1, the first fault address stored in the second storage structure 207-2 is mapped to the redundant address in the first storage structure 206-2, the first fault address stored in the second storage structure 207-3 is mapped to the redundant address in the first storage structure 206-3, and other mapping relationships can be deduced in the same way.

[0068] In some implementations, the number of redundant addresses is equal to the number of first fault addresses. That is, all redundant storage units corresponding to the redundant addresses have been used to repair the first fault storage unit corresponding to the first fault address, and there are no extra redundant storage units available to repair faulty storage units other than the first fault storage unit.

[0069] Figure 4 A schematic diagram of the storage status of different storage locations in the repair logic storage circuit provided in the embodiments of this disclosure. Figure 2 .like Figure 4 As shown, in some other embodiments, the repair logic storage circuit 203 can obtain multiple first fault addresses corresponding to the first fault storage unit from the fault address storage circuit 202, and the number of first fault addresses obtained from the fault address storage circuit 202 can be equal to the number of second storage structures 207 in the repair logic storage circuit 203. In this case, all redundant addresses are mapped to the first fault addresses.

[0070] In this embodiment of the disclosure, the repair logic storage circuit 203 may include volatile memory.

[0071] In this embodiment, the repair logic storage circuit 203 can be configured to receive a first operation mode command. The first operation mode command includes at least one second fault address corresponding to the second fault storage unit. Here, the second fault storage unit is different from the first fault storage unit. The second fault storage unit can be a storage unit that fails during subsequent use of the storage device, and the faulty storage unit and its corresponding second fault address can be obtained through appropriate testing methods.

[0072] In some embodiments, the second fault storage unit may include one or more fault storage units, each corresponding to a second fault address. In other words, the first operating mode command may include one or more second fault addresses.

[0073] In some embodiments, the first operating mode command further includes a third storage address corresponding to the second fault address, each third storage address being identical to a second storage address; the repair logic storage circuit is specifically configured to: in response to the first operating mode command, write the second fault address into the corresponding second storage structure according to the third storage address.

[0074] Figure 5 A schematic diagram of the storage status of different storage locations in the repair logic storage circuit provided in the embodiments of this disclosure. Figure 3 In this embodiment of the disclosure, the first operation mode command further includes a third storage address, which is the storage address corresponding to the second fault address. Each third storage address is identical to a second storage address; in other words, the third storage address belongs to the second storage address, meaning that each third storage address is equivalent to one of a plurality of second storage addresses. Combined with... Figure 3 and Figure 5 The repair logic storage circuit 203 responds to the first operation mode command and writes the second fault address into the second storage structure 207 according to the third storage address.

[0075] In some embodiments, at least one third storage address corresponds to a second storage structure storing a first fault address; the repair logic storage circuit is configured to: in response to a first operating mode command, overwrite the first fault address stored in the second storage structure with a second fault address corresponding to at least one third storage address.

[0076] The following explanation uses the example of a first operating mode command that includes two second fault addresses.

[0077] Combination Figure 3 and Figure 5 As shown, the third storage address corresponding to the first second fault address received by the repair logic storage circuit 203 corresponds to the second storage structure 207-2 that stores the first fault address. Thus, the repair logic storage circuit 203 stores the first second fault address in the second storage structure 207-2. At this time, a mapping is formed between the second fault address stored in the second storage structure 207-2 and the redundant address stored in the first storage structure 206-2. That is, the first fault address originally stored in the second storage structure 207-2 is overwritten by a newly received second fault address by the repair logic storage circuit 203, thereby eliminating the mapping between the first fault address and the redundant address stored in the first storage structure 206-2. In other words, the first fault address originally stored in the second storage structure 207-2 is modified to a non-faulty address, and the storage unit corresponding to this non-faulty address becomes a non-faulty storage unit, which can be used normally.

[0078] The repair logic storage circuit 203 receives a second fault address, and the corresponding third storage address corresponds to the second storage structure 207-3 that stores the first fault address. Thus, the repair logic storage circuit 203 stores the second fault address in the second storage structure 207-3. At this point, a mapping is formed between the second fault address stored in the second storage structure 207-3 and the redundant address stored in the first storage structure 206-3. In other words, the first fault address originally stored in the second storage structure 207-3 is overwritten by another newly received second fault address by the repair logic storage circuit 203. Therefore, the mapping between the first fault address and the redundant address stored in the first storage structure 206-3 is eliminated. That is, the first fault address originally stored in the second storage structure 207-3 is modified to a non-faulty address, and the storage unit corresponding to this non-faulty address is a non-faulty storage unit, which can be used normally. Based on this, all second fault addresses corresponding to the third storage addresses overwrite the first fault addresses stored in the second storage structure. In other words, the mapping relationship between some of the first fault addresses and redundant addresses is replaced by the mapping relationship between the second fault addresses and redundant addresses.

[0079] Figure 6 A schematic diagram of the storage status of different storage locations in the repair logic storage circuit provided in the embodiments of this disclosure. Figure 4 Combining Figure 3 and Figure 6 In response to the first operation mode command, the repair logic storage circuit 203 writes the second fault address into the second storage structure 207 according to the third storage address. The following explanation uses an example where the first operation mode command includes N (e.g., N is greater than 2) second fault addresses.

[0080] Combination Figure 3 and Figure 6 As shown, the third storage address corresponding to the first second fault address received by the repair logic storage circuit 203 corresponds to the second storage structure 207-2 that stores the first fault address. Thus, the repair logic storage circuit 203 stores the first second fault address in the second storage structure 207-2. At this time, a mapping is formed between the second fault address stored in the second storage structure 207-2 and the redundant address stored in the first storage structure 206-2. That is, the first fault address originally stored in the second storage structure 207-2 is overwritten by a newly received second fault address by the repair logic storage circuit 203, thereby eliminating the mapping between the first fault address and the redundant address stored in the first storage structure 206-2.

[0081] The third storage address corresponding to the second second fault address received by the repair logic storage circuit 203 corresponds to the second storage structure 207-3 that stores the first fault address. Thus, the repair logic storage circuit 203 stores the second second fault address in the second storage structure 207-3, forming a mapping between the second fault address stored in the second storage structure 207-3 and the redundant address stored in the first storage structure 206-3. In other words, the first fault address originally stored in the second storage structure 207-3 is overwritten by the newly received second fault address by the repair logic storage circuit 203, thereby eliminating the mapping between the first fault address and the redundant address stored in the first storage structure 206-3.

[0082] The repair logic storage circuit 203 receives the third to Nth (for example, N equals 4) second fault addresses, and the corresponding third storage addresses are respectively associated with the second storage structures 207-4 to 207-N+1 that do not store the first fault addresses. The repair logic storage circuit 203 then stores the received third to Nth second fault addresses sequentially into the second storage structures 207-4 to 207-N+1. At this time, a new mapping is formed between the second fault addresses stored in the second storage structures 207-4 to 207-N+1 and the redundant addresses stored in the first storage structures 206-4 to 206-5.

[0083] Understandable Figure 6 In this context, some of the multiple third storage addresses correspond to a second storage structure that stores the first fault address, while some of the multiple third storage addresses correspond to a second storage structure that does not store the first fault address. Based on this, the second fault addresses corresponding to some of the third storage addresses overwrite some of the first fault addresses stored in the second storage structure. In other words, the mapping relationship between some of the second fault addresses and redundant addresses replaces the mapping relationship between some of the first fault addresses and redundant addresses, and a new mapping is formed between some of the second fault addresses and redundant addresses.

[0084] In some embodiments, at least one third storage address corresponds to a second storage structure that does not store the first fault address; the repair logic storage circuit is configured to directly write the second fault address into the second storage structure in response to a first operating mode command.

[0085] Figure 7 A schematic diagram of the storage status of different storage locations in the repair logic storage circuit provided in the embodiments of this disclosure. Figure 5 Combining Figure 3 and Figure 7In response to the first operation mode command, the repair logic storage circuit 203 writes the second fault address into the second storage structure 207 according to the third storage address. The following explanation uses an example where the first operation mode command includes two second fault addresses.

[0086] Combination Figure 3 and Figure 7 The repair logic storage circuit 203 receives two second fault addresses, and the corresponding third storage addresses correspond to the second storage structures 207-5 and 207-6, respectively, which do not store the first fault addresses. The repair logic storage circuit 203 stores the two second fault addresses in the second storage structures 207-5 and 207-6, respectively. At this time, a mapping is formed between the second fault address stored in the second storage structure 207-5 and the redundant address stored in the first storage structure 206-5, and a mapping is formed between the second fault address stored in the second storage structure 207-6 and the redundant address stored in the first storage structure 206-6. It can be understood that... Figure 7 In this context, all third storage addresses correspond to the second storage structure that does not store the first fault address. Based on this, a new mapping is formed between the second fault address and the redundant address.

[0087] It is understood that, in this embodiment of the present disclosure, the first operation mode command may further include a write flag and an enable signal. The write flag is used to instruct the repair logic storage circuit 203 to write the second fault address to the second storage structure 207, and the enable signal is used to instruct the repair logic storage circuit 203 to be enabled.

[0088] In this embodiment, the repair logic storage circuit 203 can respond to a first operation mode command by writing the second fault address to the second storage structure 207, thereby solving the problem that the first fault address cannot be modified because the fuse array is permanently written to the first fault address. This updates the mapping relationship between redundant addresses and fault addresses, improving the utilization rate of the redundant storage unit 205.

[0089] It should be noted that the repair logic storage circuit 203 can be a volatile memory, which will lose data when power is off. Therefore, after the mapping relationship between redundant addresses and fault addresses is updated, in order to prevent data loss, all current fault addresses can be saved to the fault address storage circuit 202 according to preset rules before power failure, and all previously saved fault addresses can be retrieved from the fault address storage circuit 202 when the storage device is powered on again.

[0090] In some embodiments, the repair logic storage circuit is further configured to: receive a second operation mode command, the second operation mode command including at least one fourth storage address; each fourth storage address being identical to a second storage address; and in response to the second operation mode command, read and output the fault address stored in the second storage structure corresponding to the fourth storage address.

[0091] In this embodiment of the disclosure, the repair logic storage circuit 203 can receive a second operation mode command. The second operation mode command includes one or more fourth storage addresses. Here, the fourth storage address can be the address of the storage structure currently used to store the fault address, and the fourth storage address belongs to the second storage address; that is, each fourth storage address is equivalent to one of the multiple second storage addresses.

[0092] The repair logic storage circuit 203 can, in response to a second operation mode command, read and output the fault address stored in the second storage structure corresponding to the fourth storage address. For example, the repair logic storage circuit 203 can, in response to a second operation mode command, read and output the first fault address stored in the second storage structure 207. Alternatively, the repair logic storage circuit 203 can, in response to a second operation mode command, read and output the second fault address stored in the second storage structure 207.

[0093] It is understood that, in this embodiment of the present disclosure, the second operation mode command may further include a read flag and an enable signal. The read flag is used to instruct the repair logic storage circuit 203 to read and output the fault address stored in the second storage structure 207 corresponding to the fourth storage address, and the enable signal is used to instruct the repair logic storage circuit 203 to be turned on.

[0094] It should be noted that in this embodiment, the fault address storage circuit 202 (e.g., a fuse array) does not have a user-facing interface, while the repair logic storage circuit 203 has a user-facing external interface. Therefore, by using the repair logic storage circuit 203 to obtain the fault address in the fault address storage circuit 202, the user can read the fault address stored in the fault address storage circuit 202.

[0095] It is understood that, in the embodiments of this disclosure, the fault addresses corresponding to all faulty storage units can be easily and conveniently obtained when needed through the above-described method.

[0096] In some embodiments, the repair logic storage circuit is further configured to: receive a third operation mode command, the third operation mode command including at least the access address of the storage cell to be accessed; and in response to the third operation mode command, match the access address with a fault address in the second storage structure; output a first signal if the match is successful, the first signal indicating access to a redundant address corresponding to the successfully matched fault address; and output a second signal if the match fails, the second signal indicating access to the access address.

[0097] In this embodiment, the repair logic storage circuit 203 receives a third operation mode command. The third operation mode command includes the access address of the storage cell to be accessed. Here, access includes reading and writing. In response to the third operation mode command, the repair logic storage circuit 203 matches the received access address with a fault address stored in the second storage structure 207. If the access address and fault address match successfully, the repair logic storage circuit 203 outputs a first signal. In other words, when the second storage structure 207 of the repair logic storage circuit 203 stores a fault address identical to the access address, the repair logic storage circuit 203 outputs a first signal.

[0098] For example, such as Figure 7 As shown, when the access address successfully matches either the first fault address or the second fault address stored in the second storage structure 207, the repair logic storage circuit 203 outputs a first signal. At this time, the first signal is used to indicate access to the redundant address mapped to the successfully matched first or second fault address. Specifically, in the case of a successful match, the first signal can be used to instruct data to be written to the redundant storage unit 205 pointed to by the redundant address mapped to the successfully matched first or second fault address, or the first signal can be used to instruct data to be read from the redundant storage unit 205 pointed to by the redundant address mapped to the successfully matched first or second fault address.

[0099] If the access address and fault address fail to match, the repair logic storage circuit 203 outputs a second signal. In other words, when the second storage structure 207 of the repair logic storage circuit 203 does not store a fault address that matches the access address, the repair logic storage circuit 203 outputs a second signal. The second signal is used to indicate access to the access address. Here, in the case of a match failure, this access address is the address corresponding to storage cell 204. At this time, the second signal can be used to indicate writing data to storage cell 204, or the second signal can be used to indicate reading data from storage cell 204.

[0100] It is understood that, in this embodiment of the present disclosure, the third operation mode command may further include a matching flag and an enable signal. The matching flag is used to instruct the repair logic storage circuit 203 to match the access address with the stored fault address, and the enable signal is used to instruct the repair logic storage circuit 203 to be activated.

[0101] In this embodiment, no limitation is made on the order or number of times the first, second, and third operation mode commands are sent to the repair logic storage circuit 203. Users can adaptively adjust the sending order and number of times the above three operation mode commands are sent according to their needs.

[0102] As can be seen from the foregoing embodiments, the repair logic storage circuit 203 needs to have both storage and matching functions. In some embodiments, the repair logic storage circuit 203 includes a content-addressable memory (CAM).

[0103] Content-addressable memory (CAM) is a type of memory that combines storage and comparison functions. Each storage unit of CAM contains an embedded comparison logic. Data written to CAM is compared with the data stored inside it, and different information is output based on the comparison result.

[0104] In this embodiment of the disclosure, the repair logic storage circuit 203 is not limited to content-addressable memory. Any memory or circuit that can realize the function of "finding the corresponding redundant address according to the input access address and being able to access the redundant address" falls within the protection scope of this embodiment of the disclosure.

[0105] Figure 8 This is a schematic structural block diagram of another storage device provided in an embodiment of this disclosure. Figure 8 As shown in this embodiment, the storage device 800 includes a storage cell array 201, a fault address storage circuit 202, and a repair logic storage circuit 203. In some embodiments, the storage device 800 further includes a mode register 801 and an interface 802; the interface 802 is configured to receive bus commands; the mode register 801 is coupled to the interface 802 and the repair logic storage circuit 203, and is configured to generate corresponding operation mode commands according to the bus commands.

[0106] Here, the descriptions of the memory cell array 201, the fault address storage circuit 202, and the repair logic storage circuit 203 can be found in [reference]. Figure 2The details are omitted here. Interface 802 can be an I / O port. Mode register 801 is coupled to interface 802 and also to repair logic storage circuit 203. Interface 802 is used to receive bus commands from bus 803 and transmit them to mode register 801. Interface 802 is also used to output data in mode register 801 through bus 803. Mode register 801 can output corresponding first operation mode command, second operation mode command, or third operation mode command according to the received bus command. In other words, bus commands sent by bus 803 can be parsed by mode register 801 into first operation mode command, second operation mode command, or third operation mode command. And the first operation mode command, second operation mode command, and third operation mode command can be sent to repair logic storage circuit 203.

[0107] In some embodiments, interface 802 is coupled to memory controller 804.

[0108] In this embodiment of the disclosure, bus commands can be output by the memory controller 804 and transmitted to the interface 802 via the bus 803. In some embodiments, the memory controller 804 can be integrated into an external device coupled to the memory device 800. In other embodiments, the memory controller 804 can be integrated into a storage system for controlling the memory chip.

[0109] In this embodiment of the disclosure, bus 803 may include at least one bus. Specifically, the bus may include a clock bus for transmitting clock signal CK, a command / address bus for transmitting command and / or address CA, and a data bus for transmitting data DQ.

[0110] In some embodiments, the memory controller is configured to: acquire the fault severity of a first faulty memory cell and a second faulty memory cell in the memory device; compare the fault severity of the first faulty memory cell and the fault severity of the second faulty memory cell; determine a third memory address in the repair logic memory circuit based on the comparison result; and send a bus command containing the third memory address.

[0111] In this embodiment of the disclosure, the third storage address can be determined by comparing the fault severity of the first faulty storage unit with the fault severity of the second faulty storage unit. Specifically, as shown... Figure 7 As shown, when the fault severity of the first faulty memory cell is higher than that of the second faulty memory cell, the memory controller determines that the third memory address corresponds to the second memory structure 207, which does not store the first faulty address. Figure 5As shown, when the fault level of the first faulty memory cell is lower than that of the second faulty memory cell, the memory controller determines that the third memory address corresponds to the second memory structure that stores the first faulty address.

[0112] refer to Figure 8 After determining the third memory address, the memory controller 804 can send a bus command containing the third memory address to the interface 802 via the bus 803.

[0113] In some embodiments, the memory controller is further configured to: determine a third storage address in the repair logic storage circuit of the second fault address based on the comparison result and in combination with the utilization rate of the redundant storage cells.

[0114] In this embodiment of the disclosure, the third storage address of the second fault address in the repair logic storage circuit can be determined based on the comparison result of the fault degree of the first fault storage unit and the fault degree of the second fault storage unit, and in combination with the utilization rate of the redundant storage units.

[0115] In some embodiments, the memory controller is further configured to: determine a third storage address as a second storage address corresponding to a second storage structure that stores the first fault address, based on the fact that the fault degree of the second fault storage unit is higher than that of the first fault storage unit and the utilization rate of the redundant storage unit is greater than a preset utilization rate; and determine a third storage address as a second storage address corresponding to a second storage structure that does not store the first fault address, based on the fact that the fault degree of the second fault storage unit is lower than or equal to that of the first fault storage unit, or the utilization rate of the redundant storage unit is less than or equal to a preset utilization rate.

[0116] In this embodiment, the preset utilization rate can be close to or equal to 100%. The preset utilization rate can also be adjusted according to actual conditions. Specifically, when the failure severity of the first faulty storage unit is lower than that of the second faulty storage unit, and the utilization rate of the redundant storage unit is greater than or equal to the preset utilization rate, the third storage address is determined to be the second storage address corresponding to the second storage structure storing the first faulty address. Here, you can refer to... Figure 4 ,like Figure 4 As shown, the utilization rate of the redundant storage units is 100%. In this case, if the failure severity of the first faulty storage unit is lower than that of the second faulty storage unit, then the second faulty address corresponding to the third storage address overwrites the first faulty address stored in the second storage structure. In other words, at least part of the mapping relationship between the first faulty address and its corresponding redundant address is eliminated, while a mapping relationship between the second faulty address and the redundant address is established.

[0117] When the failure severity of the first faulty storage unit is lower than that of the second faulty storage unit, and the utilization rate of the redundant storage units is less than a preset utilization rate, the third storage address is determined to be the second storage address corresponding to the second storage structure that does not store the first faulty address. For example... Figure 7 As shown, when the utilization rate of the redundant storage unit is less than the preset utilization rate, and the failure level of the first faulty storage unit is lower than the failure level of the second faulty storage unit, the third storage address is determined to be the second storage address corresponding to the second storage structure that does not store the first faulty address, and a new mapping is formed between the second faulty address and the redundant address.

[0118] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0119] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A storage device, characterized in that, include: A storage cell array, comprising multiple storage cells and multiple redundant storage cells; The plurality of redundant storage units are configured to repair faulty storage units among the plurality of storage units; The fault address storage circuit is configured to store at least one first fault address corresponding to the first fault storage unit; The repair logic storage circuit includes multiple first storage structures each having a first storage address and multiple second storage structures each having a second storage address. The first storage structures and the second storage structures correspond one-to-one and their internal stored data are mutually mapped. The multiple first storage structures store redundant addresses corresponding to the multiple redundant storage units, and one redundant address corresponds to one first storage structure. The second storage structure stores the first fault address, and one first fault address corresponds to one second storage structure; The repair logic storage circuit is configured as follows: Receive a first operation mode command, the first operation mode command including at least one second fault address corresponding to the second fault storage unit; the second fault storage unit is different from the first fault storage unit; and In response to the first operation mode command, the first fault address stored in the second storage structure is overwritten with the second fault address; or, in response to the first operation mode command, the second fault address is written into the second storage structure.

2. The storage device according to claim 1, characterized in that, The first storage structure has a corresponding first storage address, and the second storage structure has a corresponding second storage address; the first operation mode command also includes a third storage address corresponding to the second fault address, and each of the third storage addresses is the same as a second storage address; The repair logic storage circuit is specifically configured as follows: In response to the first operation mode command, the second fault address is written into the corresponding second storage structure according to the third storage address.

3. The storage device according to claim 2, characterized in that, At least one of the third storage addresses corresponds to a second storage structure that stores the first fault address; The repair logic storage circuit is configured as follows: In response to the first operation mode command, the first fault address stored in the second storage structure is overwritten with the second fault address corresponding to at least one of the third storage addresses.

4. The storage device according to claim 2, characterized in that, At least one of the third storage addresses corresponds to a second storage structure that does not store the first fault address; The repair logic storage circuit is configured as follows: In response to the first operation mode command, the second fault address is directly written into the second storage structure.

5. The storage device according to claim 1, characterized in that, The repair logic storage circuit is configured as follows: In response to the power-on of the storage device, the first fault address is obtained from the fault address storage circuit; and the first fault address is written into the second storage structure in a first preset order. In response to the power-on of the storage device, the acquired redundant addresses are written into the first storage structure in a second preset order.

6. The storage device according to claim 1, characterized in that, The repair logic storage circuit is also configured to: Receive a second operation mode command, the second operation mode command including at least one fourth storage address; each of the fourth storage addresses is the same as one of the second storage addresses; In response to the second operation mode command, the fault address stored in the second storage structure corresponding to the fourth storage address is read and output.

7. The storage device according to claim 1, characterized in that, The repair logic storage circuit is also configured to: Receive a third operation mode command, the third operation mode command including at least the access address of the memory unit to be accessed; and In response to the third operation mode command, the access address is matched with the fault address in the second storage structure; if the match is successful, a first signal is output, which indicates access to the redundant address corresponding to the successfully matched fault address; if the match fails, a second signal is output, which indicates access to the access address.

8. The storage device according to any one of claims 1 to 7, characterized in that, The repair logic storage circuit includes a content-addressable memory.

9. The storage device according to any one of claims 1 to 7, characterized in that, The fault address storage circuit includes a fuse array or an antifuse array.

10. The storage device according to any one of claims 1 to 7, characterized in that, The storage device also includes a mode register and an interface; The interface is configured to receive bus commands; The mode register is coupled to the interface and the repair logic storage circuit, and is configured to generate a corresponding operation mode command according to the bus command.

11. The storage device according to claim 10, characterized in that, The interface is coupled to a memory controller, which is configured to: Obtain the fault severity of the first faulty storage unit and the fault severity of the second faulty storage unit in the storage device; The degree of failure of the first faulty storage unit is compared with the degree of failure of the second faulty storage unit; Based on the comparison results, the third storage address in the repair logic storage circuit is determined to be the second fault address; Send the bus command containing the third storage address.

12. The storage device according to claim 11, characterized in that, The memory controller is also configured to: Based on the comparison results and the utilization rate of redundant storage units, the third storage address of the second fault address in the repair logic storage circuit is determined.

13. The storage device according to claim 12, characterized in that, The memory controller is also configured to: Based on the fact that the failure level of the second faulty storage unit is higher than that of the first faulty storage unit, and the utilization rate of the redundant storage unit is greater than the preset utilization rate, the third storage address is determined to be the second storage address corresponding to the second storage structure storing the first faulty address. Based on the fact that the failure level of the second faulty storage unit is lower than or equal to the failure level of the first faulty storage unit, or the utilization rate of the redundant storage unit is less than or equal to the preset utilization rate, the third storage address is determined to be the second storage address corresponding to the second storage structure that does not store the first faulty address.

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