Memory system, operating method thereof, and readable storage medium

Abstract

Embodiments of the present disclosure disclose a memory system, an operating method thereof, and a readable storage medium, the memory system including: a memory device including a plurality of memory blocks, each of the memory blocks including a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines; the memory controller is coupled with the storage device and is configured to utilize the first type of reread meters and the second type of reread meters to jointly obtain reread voltage; the first type of rereading table comprises first voltage deviation values corresponding to different conditions when one storage block in the plurality of storage blocks is fully written; the second type of rereading table comprises a second voltage deviation value corresponding to the state of each word line based on the first type of rereading table when one storage block in the plurality of storage blocks is not fully written; the memory device is controlled to perform a reread operation using the reread voltage.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory system and an operating method thereof, and a readable storage medium. Background Art

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become a mainstream product in the storage market due to its high storage density, controllable production cost, suitable editing and erasing speed and retention characteristics.

[0003] However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and systems thereof. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a memory system, including:

[0005] A memory device, the memory device comprising a plurality of memory blocks, each of the memory blocks comprising a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines;

[0006] A memory controller is coupled to the memory device and is configured to:

[0007] A reread voltage is obtained by using a first type of reread table and a second type of reread table; the first type of reread table includes first voltage offset values ​​corresponding to different situations when one of the multiple storage blocks is full; the second type of reread table includes a second voltage offset value corresponding to the state of each word line of one of the multiple storage blocks when it is not full based on the first type of reread table;

[0008] The memory device is controlled to perform a reread operation using the reread voltage.

[0009] In some embodiments, the storage block includes a first storage block, the first storage block is an unfilled storage block, and the memory controller is configured to:

[0010] Using the first type of reread table, obtaining a first voltage offset value corresponding to the first storage block;

[0011] Using the second type of reread table, and combining the group to which the word line coupled to the memory cell to be read in the first memory block belongs and the relationship between the word line coupled to the memory cell to be read and the first blank word line, a corresponding second voltage offset value is obtained;

[0012] A reread voltage when a read operation is performed on the storage unit to be read in the first storage block is obtained according to the first voltage offset value and the second voltage offset value.

[0013] In some embodiments, the memory controller is configured to:

[0014] Add the first voltage offset value and the second voltage offset value to obtain a total offset voltage value;

[0015] The re-read voltage is obtained by summing the default read voltage and the total offset voltage value.

[0016] In some embodiments,

[0017] The storage block includes word lines 0 to N which are sequentially numbered according to physical positions; the storage block is programmed in the order from the 0 to N word lines; N is an integer greater than 2;

[0018] All word lines of the storage block are divided into a plurality of groups, each group comprising a plurality of adjacent word lines;

[0019] All word lines in the first storage block include: the first blank word line, edge word lines adjacent to the first blank word line, and middle word lines spaced apart from the first blank word line;

[0020] The edge word lines falling into different groups have different second voltage offset values, and the middle word lines falling into different groups have different second voltage offset values.

[0021] In some embodiments, the edge word lines and the middle word lines falling into the same group have different second voltage offset values.

[0022] In some embodiments, each group includes the same or similar number of word lines.

[0023] In some embodiments, the closer the middle word line is to the 0th word line, the greater the absolute value of the offset of the second voltage offset value corresponding to the corresponding group into which the middle word line falls is compared with the first voltage offset value;

[0024] The closer the edge word line is to the 0th word line, the greater the absolute value of the offset of the second voltage offset value in the second type reread table corresponding to the corresponding group into which the edge word line falls is compared with the first voltage offset value;

[0025] When the edge word line and the middle word line fall into the same group, the absolute value of the offset of the second voltage offset value corresponding to the edge word line relative to the first voltage offset value is greater than the absolute value of the offset of the second voltage offset value corresponding to the middle word line relative to the first voltage offset value.

[0026] In some embodiments, the memory cell comprises a multi-bit memory cell, and the multi-bit memory cell reads multi-bit storage data by a multi-level read voltage;

[0027] The second voltage offset value corresponding to each level of the multi-level read voltage is the same;

[0028] or,

[0029] The second voltage offset values ​​corresponding to some level read voltages in the multi-level read voltages are different.

[0030] In some embodiments, at least two levels of read voltages in the multi-level read voltages correspond to different second voltage offset values;

[0031] The multi-level read voltage is divided into a plurality of intervals, each interval including a first-level read voltage or adjacent multi-level read voltages;

[0032] The second voltage offset values ​​corresponding to each level of read voltage in one of the intervals are the same, and the second voltage offset values ​​corresponding to multiple levels of read voltage in different intervals are different.

[0033] In some embodiments, each of the groups corresponds to the multiple intervals; for different multiple intervals corresponding to the same group, the smaller the average order of the read voltage contained in the corresponding interval, the greater the absolute value of the offset of the second voltage offset value corresponding to the corresponding interval compared to the first voltage offset value.

[0034] In some embodiments, the memory device includes multiple types of memory pages; the different situations include at least one of the following:

[0035] The storage unit includes different storage bit numbers;

[0036] The storage pages include different types;

[0037] Different usage scenarios of the memory device.

[0038] In some embodiments, the memory controller is configured to:

[0039] After executing the reread operation, performing a hard decoding operation on the reread data;

[0040] In response to the hard decoding operation failing, performing a soft decoding operation;

[0041] In response to the soft decoding operation failing, a redundant array data recovery operation is performed.

[0042] According to a second aspect of an embodiment of the present disclosure, there is provided a method for operating a memory system, including:

[0043] A reread voltage is obtained by using a first type of reread table and a second type of reread table; the first type of reread table includes first voltage offset values ​​corresponding to different situations when one of the multiple storage blocks of the memory device is full; the second type of reread table includes a second voltage offset value corresponding to the state of each word line of one of the multiple storage blocks when it is not full based on the first type of reread table;

[0044] A re-read operation is performed using the re-read voltage.

[0045] In some embodiments, the storage block includes a first storage block, and the first storage block is an unfilled storage block; the step of obtaining the reread voltage by using the first type reread table and the second type reread table includes:

[0046] Using the first type of reread table, obtaining a first voltage offset value corresponding to the first storage block;

[0047] Using the second type of reread table, and combining the group to which the word line coupled to the memory cell to be read in the first memory block belongs and the relationship between the word line coupled to the memory cell to be read and the first blank word line, a corresponding second voltage offset value is obtained;

[0048] A re-read voltage corresponding to the storage unit to be read in the first storage block is obtained according to the first voltage offset value and the second voltage offset value.

[0049] In some embodiments, obtaining the reread voltage of the storage unit to be read in the first storage block when performing a read operation according to the first voltage offset value and the second voltage offset value includes:

[0050] Add the first voltage offset value and the second voltage offset value to obtain a total offset voltage value;

[0051] The re-read voltage is obtained by summing the default read voltage and the total offset voltage value.

[0052] In some embodiments,

[0053] The storage block includes word lines 0 to N which are sequentially numbered according to physical positions; the storage block is programmed in the order from the 0 to N word lines; N is an integer greater than 2;

[0054] All word lines included in the storage block are divided into a plurality of groups, each group including a plurality of adjacent word lines;

[0055] All word lines in the first storage block include: the first word line, an edge word line adjacent to the first blank word line, and an intermediate word line spaced apart from the first blank word line; wherein the edge word lines falling into different groups have different second voltage offset values, and the intermediate word lines falling into different groups have different second voltage offset values.

[0056] In some embodiments, the edge word lines and the middle word lines falling into the same group have different second voltage offset values.

[0057] In some embodiments, each group includes the same or similar number of word lines.

[0058] In some embodiments, the closer the middle word line is to the 0th word line, the greater the absolute value of the offset of the second voltage offset value corresponding to the corresponding group into which the middle word line falls is compared with the first voltage offset value;

[0059] The closer the edge word line is to the 0th word line, the greater the absolute value of the offset of the second voltage offset value in the second type reread table corresponding to the corresponding group into which the edge word line falls is compared with the first voltage offset value;

[0060] When the edge word line and the middle word line fall into the same group, the absolute value of the offset of the second voltage offset value corresponding to the edge word line relative to the first voltage offset value is greater than the absolute value of the offset of the second voltage offset value corresponding to the middle word line relative to the first voltage offset value.

[0061] In some embodiments, the memory cell comprises a multi-bit memory cell, and the multi-bit memory cell reads multi-bit storage data by a multi-level read voltage;

[0062] The second voltage offset value corresponding to each level of the multi-level read voltage is the same;

[0063] or,

[0064] The second voltage offset values ​​corresponding to some level read voltages in the multi-level read voltages are different.

[0065] In some embodiments, at least two levels of read voltages in the multi-level read voltages correspond to different second voltage offset values;

[0066] The multi-level read voltage is divided into a plurality of intervals, each interval including a first-level read voltage or adjacent multi-level read voltages;

[0067] The second voltage offset values ​​corresponding to each level of read voltage in one of the intervals are the same, and the second voltage offset values ​​corresponding to multiple levels of read voltage in different intervals are different.

[0068] In some embodiments, each of the groups corresponds to the multiple intervals; for different multiple intervals corresponding to the same group, the smaller the average order of the read voltage contained in the corresponding interval, the greater the absolute value of the offset of the second voltage offset value corresponding to the corresponding interval compared to the first voltage offset value.

[0069] In some embodiments, the memory device includes multiple types of memory pages; the different situations include at least one of the following:

[0070] The storage unit includes different storage bit numbers;

[0071] The storage pages include different types;

[0072] Different usage scenarios of the memory device.

[0073] In some embodiments, the operating method further includes:

[0074] After executing the reread operation, performing a hard decoding operation on the reread data;

[0075] In response to the hard decoding operation failing, performing a soft decoding operation;

[0076] In response to the soft decoding operation failing, a redundant array data recovery operation is performed.

[0077] According to a third aspect of the embodiments of the present disclosure, a readable storage medium is provided, wherein the readable storage medium stores a computer program, and when the computer program is executed, the operating method described in any one of the embodiments is implemented.

[0078] In the disclosed embodiment, a first type of reread table and a second type of reread table are used to jointly obtain a reread voltage; the first type of reread table includes first voltage offset values ​​corresponding to different situations when one of the multiple storage blocks is full; the second type of reread table includes the state of each word line when one of the multiple storage blocks is not full. The reread operation is performed based on different second voltage offset values ​​corresponding to the first type of reread table, the first voltage offset value, the second voltage offset value and the default read voltage to obtain the reread voltage, thereby reducing the amount of data in the reread table, facilitating fast search of the reread table and the polling rate of the reread operation, thereby increasing the read rate of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0080] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0081] Figure 2b A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0082] Figure 3a A schematic diagram of the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0083] Figure 3b A schematic diagram of an exemplary memory device including a peripheral circuit according to an embodiment of the present disclosure;

[0084] Figure 4 A cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present disclosure;

[0085] Figure 5 A schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present disclosure;

[0086] Figure 6 A schematic diagram of a read operation flow including a reread operation according to an embodiment of the present disclosure;

[0087] Figure 7 A block diagram of a memory controller including an error correction module according to an embodiment of the present disclosure is applied in a memory system;

[0088] Figure 8 is a schematic diagram of a rereading table according to an embodiment of the present disclosure;

[0089] Fig. 9 A schematic diagram of a threshold voltage shift of a fully written memory block, a middle word line of an incompletely written memory block, and an edge word line of an incompletely written memory block according to an embodiment of the present disclosure;

[0090] Fig.10 A first type of reread representation corresponding to a full storage block in an embodiment of the present disclosure;

[0091] Fig.11 A schematic diagram of a threshold voltage after Gray code programming according to an embodiment of the present disclosure;

[0092] Fig.12a A schematic diagram of the second type of rereading table according to an embodiment of the present disclosure;

[0093] Figure 12b Another schematic diagram of the second type of rereading table according to an embodiment of the present disclosure;

[0094] Fig.12c A schematic diagram of a second type of re-read table with storage state division intervals according to an embodiment of the present disclosure;

[0095] Fig.13The present invention is a flowchart of an operation method of a memory system according to an embodiment of the present disclosure.

[0096] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0097] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0098] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0099] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0100] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0101] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0102] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0103] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0104] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0105] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0106] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, a three-dimensional NAND memory is taken as an example for description.

[0107] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0108] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0109] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0110] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2a In one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0111] Figure 3a A schematic diagram of the structure of a storage cell array of a three-dimensional NAND memory is given as an example. Figure 3a As shown, the memory cell array of the three-dimensional NAND memory is composed of several parallel and staggered rows of memory cell rows parallel to the gate isolation structure, every two rows of memory cell rows are separated by the gate isolation structure and the upper selection gate isolation structure, and each memory cell row includes a plurality of memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure, the first gate isolation structure divides the memory cell array into a plurality of memory blocks (expressed in English as Blocks), the plurality of second gate isolation structures may divide the memory blocks into a plurality of finger storage areas (expressed in English as Finger), and the upper selection gate isolation structure provided in the middle of each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. Figure 3a The memory block shown in FIG. 1 includes 6 memory cells. In practical applications, the number of memory cells in a memory block is not limited thereto. The memory cells in a memory block coupled to a certain word line can be called a memory page (expressed in English as Page).

[0112] It should be noted that Figure 3a The number of memory cell rows between the gate isolation structure and the upper selection gate isolation structure given in the disclosure is only an exemplary demonstration and is not used to limit the number of memory cell rows contained in a finger storage area of ​​the three-dimensional NAND memory in the present disclosure. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0113] Figure 3b 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Figure 1 300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is taken as a three-dimensional NAND-type memory cell array for illustration, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0114] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed by writing one of three possible nominal storage values ​​to the cell, and a fourth nominal storage value in addition to the three nominal storage values ​​can be used to represent an erased state.

[0115] like Figure 3b As shown in , each NAND memory string 308 may include a lower select gate (BSG) 310 at its source terminal and an upper select gate (TSG) 312 at its drain terminal. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0 V) ​​to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0 V) ​​to a corresponding BSG 310 via one or more BSG lines 315.

[0116] like Figure 3bAs shown in , the NAND memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in the selected memory block 304a, the source lines 314 coupled to the selected memory block 304a and the unselected memory blocks 304b in the same plane as the selected memory block 304a can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at the half-memory block level, at the quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, in combination with the above Figure 3a , a plurality of memory cells are isolated by an upper selection gate isolation structure and a gate isolation structure, and a plurality of memory cells between the upper selection gate isolation structure and the gate isolation structure are arranged into a plurality of memory cell rows, and each memory cell row is parallel to the gate isolation structure and the upper selection gate isolation structure. The memory cells in the memory slices sharing the same word line form a physical page 320. Each physical page 320 can be mapped to at least one logical page according to the storage mode of the corresponding memory cell 306 (for example, SLC or MLC as mentioned above), and the logical page can constitute the basic data unit of the programming operation and the reading operation.

[0117] Figure 4 1 shows a cross-sectional schematic diagram of an exemplary memory cell array 301 including NAND memory strings 308 according to some aspects of the present disclosure. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a memory string 308 that vertically penetrates the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 may determine the number of memory cells included in the memory cell array 301.

[0118] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0119] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0120] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0121] Return to reference Figure 3b, the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0122] The page buffer / sense amplifier 504 may be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 may store a page of programming data (write data) to be programmed into one memory page 320 of the memory cell array 301. In another example, the page buffer / sense amplifier 504 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 may also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 may be configured to be controlled by the control logic 512, and select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0123] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory block 304 of the memory cell array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word lines 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

[0124] In some specific embodiments, the programming operation may include multiple stages. For example, the programming operation may include a channel precharge stage, a channel boosting stage, a programming pulse stage, and a recovery stage. In the channel precharge stage, the voltage generator may generate the voltage required for the next stage, such as the voltage applied to each gate, the channel boosting voltage, etc.; in the channel boosting stage, the channel boosting voltage may be applied to the selected word line; in the programming pulse stage, the target voltage for each programming may be applied to the selected word line. In the recovery stage, the voltage of both the unselected word line and the selected word line may be reduced to the corresponding voltage, such as Vcc, Vdd. In the recovery stage, the voltage may be reduced to the corresponding voltage by one or more step-by-step steps, such as first reducing the voltage to an intermediate voltage, and maintaining the intermediate voltage for a period of time, and then reducing the voltage to the corresponding voltage.

[0125] The control logic 512 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic 512 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via a data bus 518 and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0126] In some embodiments, the memory cells of the NAND memory can be divided into single-layer memory cells (one-bit memory cells), double-layer memory cells (two-bit memory cells), three-layer memory cells (three-bit memory cells), four-layer memory cells (four-bit memory cells), and five-layer memory cells (five-bit memory cells) according to the storage density. However, regardless of the single-layer memory cells or multi-layer memory cells, the read operation can be performed in units of pages. Specifically, when performing a read operation, a read voltage is applied to the word line (i.e., the selected word line) coupled to the selected page in the memory device 104. When the read voltage reaches the threshold voltage of multiple memory cells coupled to the selected word line, or the number of memory cells that have not reached the threshold voltage is within the allowable range, the read operation of the entire page ends. The memory cell can be an M-bit memory cell, and the memory cell has 2 including an erased state. M storage states, through 2 M -1 level read voltage reads M bits of stored data. Exemplarily, for example, the first level read voltage is between the threshold voltages of the erased state and the first storage state, and when the first level read voltage is applied to the word line, the storage cell in the erased state is turned on, and the storage cell in the first storage state is not turned on, and the erased state and the first storage state are distinguished and read out.

[0127] It should be noted that in the process of executing the read operation, the storage unit that has not reached the target threshold voltage is marked as an error bit. In order to prevent read errors, an error correction code (ECC) is introduced. When the number of error bits is less than or equal to the maximum number of failed bits that the error correction code can correct, the error bits in the read operation can be corrected. In this way, the correct reading of data can be achieved.

[0128] In some embodiments, the host 108 sends a read command (or a read instruction, a read request) to the memory controller 106 according to the current user command requirements; the memory controller 106 transmits the read control command including information such as the logical address-physical address mapping table to the memory device 104 through the interface 516, controls the memory device 104 to perform a read operation on the storage unit corresponding to the corresponding physical address, and the memory device 104 sends the read data to the memory controller 106 through the interface 516, and the memory controller 106 feeds the data back to the host 108 through the interface such as PCIe or SATA. Specifically, the memory controller 106 sends the read control command to the control logic of the memory device through the interface 516, and the control logic applies the relevant operating voltage to the selected word line or bit line according to the relevant physical address, thereby performing a read operation on the corresponding storage unit. The operating voltage can be generated by the control logic according to the relevant read voltage mapping table to control the voltage generator to generate the relevant operating voltage, and then applied to the word line of the corresponding address through the row decoder, or applied to the bit line of the corresponding address through the column decoder.

[0129] In some other embodiments, when the memory device 104 reads the corresponding storage unit under the control of the memory controller 106, a read error occurs. At this time, the memory controller 106 responds to the failure of the read operation and controls the memory (or the error correction module in the memory controller 106). The error correction mode may include ECC error correction. According to some aspects of the embodiments of the present disclosure, Figure 6 FIG. 1 is a schematic diagram showing an exemplary read operation flow of a memory system 102. Figure 6 As shown, when the memory controller 106 controls the memory device 104 to perform a read operation, a default read operation (FW default read) is first performed on the storage unit of the corresponding physical address. After the default read fails, a reread operation (Read retry) is performed after the default read operation fails. After the reread operation fails, a soft decoding operation (Soft decode) is performed. After the soft decoding fails, a redundant array data recovery (RAID) operation is performed. After the RAID operation fails, the read operation stops and the read fails because the error cannot be corrected. The memory controller 106 sends a read fail signal to the host 108. The reread operation and the default read operation can be applied to hard decoding.

[0130] Error correction operations such as reread operation, soft decoding and RAID can be performed by the memory device 104 under the control of the error correction module 1064 (e.g., ECC module) in the memory controller 106. The control command is sent by the memory controller 106 to the memory device 104 via the interface 516, and the memory device 104 feeds back the read information to the memory controller 106 via the interface 516. It should be noted that after any one of the reread operation, soft decoding and RAID operation is read successfully, the subsequent operation can be stopped.

[0131] In some specific embodiments, the soft decoding operation can be understood as re-decoding the data through the decoding unit 1066 (e.g., soft decoder) in the memory controller 106, and performing a re-reading operation based on the re-decoded data. The RAID operation can be understood as implementing data mirroring through secondary encoding, and reconstructing the stored data and its parity check data, wherein the re-encoding of the redundant array of the stored data is usually performed in the data buffer 1067 of the memory controller 106.

[0132] According to some aspects of the embodiments of the present disclosure, Figure 7 A block diagram of a memory system 102 including a memory controller 106 including an error correction module 1064 is provided. Figure 7 As shown, the memory system 102 includes: a memory controller 106 and a memory, and the memory controller 106 and the memory device 104 can be coupled in any suitable manner. In the embodiment of the present disclosure, the memory controller 106 includes a host I / F 1061, a memory I / F 1062, a control unit 1063, an error correction (ECC) module 1064, a data buffer 1067, and an internal bus 1060, wherein the error correction module 1064 includes an encoding unit 1065 and a decoding unit 1066. The host I / F 1061 outputs the command, user data (write data), etc. received from the host 108 to the internal bus 1060, and sends the user data (read data) read from the memory device 104, the response from the control unit 1063, etc. to the host 108.

[0133] The memory I / F controls the process of writing user data and the like to the memory device 104 and the process of reading from the memory device 104 based on the instruction of the control unit 1063. The control unit 1063 controls the memory system 102 as a whole, and the control unit 1063 is, for example, a central processing unit (CPU), a microprocessor (MPU), etc. When the control unit 1063 receives a command from the host 108 via the host I / F 1061, it performs control according to the command. For example, the control unit 1063 instructs the memory I / F to write user data and parity check to the memory device 104 according to the command from the host 108. In addition, the control unit 1063 instructs the memory I / F to read user data and parity check from the memory device 104 according to the command from the host 108.

[0134] The error correction module 1064 includes an encoding unit 1065 and a decoding unit 1066. The encoding unit 1065 encodes the user data of a predetermined size written in the same page to generate parity data. The parity data is written in the page where the user data that is the basis of the encoding has been written, and the decoding unit 1066 decodes using the parity data. The data buffer 1067 temporarily stores the user data received from the host 108 before storing it in the memory device 104, and temporarily stores the data read from the memory device 104 before sending it to the host 108.

[0135] In some embodiments, Figure 6 The process of determining the reread voltage in the reread operation may include: the error correction module 1064 in the memory controller 106 obtains the corresponding voltage offset value by querying the corresponding reread table, and the voltage offset value can be a positive offset value or a negative offset value, and obtains the reread voltage by summing it with the default read voltage. The memory controller 106 controls the memory device 104 to perform a reread operation on the storage unit of the corresponding physical address using the reread voltage. It should be noted that the memory controller 106 may adopt a polling method when querying the reread table. A reread table may include multiple sub-tables, such as m sub-tables (or Figure 8 In the example, the sub-table may include a voltage offset value for a corresponding storage state of a corresponding storage cell, and the sub-tables are queried sequentially from the first sub-table to the mth sub-table. A voltage offset value is obtained by querying once, and then a re-read voltage is obtained by summing. The memory device 104 uses the re-read voltage for reading. Therefore, a re-read operation may have a maximum of m sub-read operations, and the embodiment of the present disclosure does not limit this.

[0136] In some embodiments, the memory cell array includes a plurality of memory blocks, and each memory block includes multiple layers of word lines. In each memory block, a plurality of memory cells coupled to a certain layer of word lines can be used as one or more physical pages. In some embodiments, as the storage capacity demand of the memory device 104 increases, the more memory blocks are divided, the higher the integration density of the total memory string is, and the more word line layers (corresponding to the number of memory cell stacking layers) are. On the same layer of word lines, there may be a threshold voltage shift between the memory cells on a full memory block (close block) and the memory cells on an incomplete memory block (open block) due to the difference in the total amount of stored charge, due to the influence of factors such as parasitic capacitance and charge coupling. The threshold voltage shift here is exemplified for memory cells in the same storage state, and the incomplete memory block mainly reads the memory cells that have been written to it. Therefore, in the reread table of some specific embodiments, separate reread tables are set for full memory blocks and incomplete memory blocks. Specifically, in combination with Figure 6 As shown, when a default read operation fails for a logical page in a full storage block, the memory controller 106 queries the reread table corresponding to the full storage block. When a default read operation fails for a logical page in an incomplete storage block, the memory controller 106 queries the reread table corresponding to the incomplete storage block. Even for storage cells in the same word line and the same storage state, the voltage offset values ​​corresponding to the two reread tables may be different.

[0137] It should be noted that for an incompletely written memory block, there are blank word lines and write word lines; wherein, a blank word line may indicate a word line in which the states of the memory cells coupled to the corresponding word line are all in an erased state, i.e., the states of the memory cells coupled to the blank word line are all in an erased state, and a write word line may indicate that the states of the memory cells coupled to the corresponding word line are not all in an erased state (at least partially in a programmed state), i.e., the states of the memory cells coupled to the write word line are not all in an erased state. Further, based on sequential programming, the first blank word line is the blank word line that appears first in the programming order among all blank word lines.

[0138] In some embodiments, for a full memory block, there is no blank word line, and a reread table can be used for different memory pages in the memory block without considering the word line position to reduce the size of the reread table. For an incomplete memory block, there are blank word lines and write word lines, because there is a charge difference between the physical page corresponding to the write word line and the physical page corresponding to the adjacent blank word line, resulting in a more complex threshold voltage offset of the threshold voltage of the memory cell in the incomplete memory block compared to the full memory block, and the positional relationship between the write word line and the blank word line in the memory block will also make the threshold voltage offset more complex.

[0139] Exemplarily, during programming operation, the top word line or the bottom word line can be used as the starting programming word line; wherein, the top word line is respectively located at two opposite ends of the block (or, memory string), the top word line can be located at one end relatively close to the bit line, and the bottom word line can be located at one end relatively far from the bit line. The starting word line can be word line 0, and the word lines are numbered in sequence according to the programming sequence of the word lines (the sequence of applying programming voltage), such as word lines 0 to 63, word lines 0 to 95, word lines 0 to 127, word lines 0 to 230, word lines 0 to 400 or more. When programming and writing, it can be written from word line 0 in sequence so that a single storage block can be filled to reduce the addressing pressure, but this is only for physical addresses, and logical addresses do not limit their continuity. For the written word lines of the unfilled storage blocks, continuous physical addresses can be corresponded. A word line adjacent to the first blank word line in the written word lines can be recorded as an edge word line (edge ​​WL), and the remaining word lines are recorded as inner word lines (inner WL). Specifically, taking word lines 0 to 230 as an example, when the word lines to be written are word lines 0 to 55, the middle word lines are word lines 0 to 54, and the edge word line is word line 55; when the word lines to be written are word lines 0 to 115, the middle word lines are word lines 0 to 114, and the edge word line is word line 115. The edge word line is closest to the first blank word line and is most affected by the blank word line. The offset value of the threshold voltage corresponding to the edge word line is greater than the offset value of the threshold voltage corresponding to the middle word line. For an incomplete storage block, the reread table needs to include at least the content for the edge word line and the middle word line, or include sub-tables for the edge word line and the middle word line, to meet the offset conditions of different threshold voltages.

[0140] In some embodiments, for an incomplete storage block, when the word line number is larger (the more word line layers), the offset values ​​of the threshold voltages corresponding to the edge word lines and the middle word lines at different positions are also different. The word lines can be grouped, and each group corresponds to different reread table contents or different reread sub-tables. The management of the reread table for full storage blocks and incomplete storage blocks in the disclosed embodiment may include a variety of situations: the various storage tables corresponding to full storage blocks and incomplete storage blocks are merged into a reread total table for unified management; or, for different types of storage blocks, or even for the reread tables corresponding to the word lines in different storage blocks after grouping, they can be presented in the form of reread sub-tables. The disclosed embodiment does not limit the unified management and separate management of the reread table, and the subsequent firmware or program will query according to the grouping information and word line position attached to the reread table.

[0141] For example, refer to Figure 8 An exemplary reread summary table including an associated reread table for a full memory block is shown. Figure 8In , taking a TLC storage cell storing 3-bit data and having 7-level read voltage as an example, the table header shows the reread voltage offset values ​​corresponding to the reread voltages of the 7 storage states. The offset values ​​include positive, negative or 0. The offset value is summed with the corresponding default read voltage to obtain a new reread voltage. The offset position includes word line address information, storage block type information, etc. The firmware can determine which row of the storage table to start polling for the current reread operation or which row of the reread table needs to be executed based on this information. The seven-level read voltages are: Rd1LP, Rd2MP, Rd3UP, Rd4MP, Rd5LP, Rd6MP, and Rd7UP. When the reread storage cell is located in a full storage block, the polled reread table may include RR-1, RR-9 to RR-33, and a maximum of 26 queries and 26 voltage offset value operations may be performed to determine whether the reread operation passes. Any reread operation that passes can stop polling; if it fails after 26 times, the reread operation is determined to have failed and the soft decoding operation is entered. Figure 8 The reread table part of RR-34 to RR-188 not shown is also included, which corresponds to the reread table part corresponding to the different word line groups of the unfilled storage block. Exemplarily, taking RR-1 as an example, the voltage offset value obtained by a query of the first storage state is a1 (the unit can be mV), and a1 is summed with the default read voltage of the first storage state to obtain the reread voltage, and the storage cell is reread to determine whether the read is passed.

[0142] Taking the TLC storage cells of word lines 0 to 231 as an example, the first group includes word lines 0 to 56, the second group includes word lines 57 to 116, the third group includes word lines 117 to 172, and the fourth group includes word lines 173 to 230. The grouping here includes the write word lines including the middle word lines and the edge word lines. Exemplarily, when the write word lines 0 to 57 fall into the second group, word lines 0 to 56 still belong to the second group, and their voltage offset values ​​are looked up in the table according to the corresponding mode of the second group. When performing a reread operation query Figure 8When the reread table shown in the figure is used, when the written word line falls into the first group, all the middle word lines poll the RR-34 to RR-59 parts in the reread table, and query the voltage offset value at most 26 times, and the 26 times can be the preset value written in the firmware; the edge word line polls the RR-112 to RR-137 parts in the reread table, and query the voltage offset value at most 26 times. When the written word line falls into the second group, all the middle word lines poll the RR-60 to RR-85 parts in the reread table, and query the voltage offset value at most 26 times; the edge word line polls the RR-138 to RR-163 parts in the reread table, and query the voltage offset value at most 26 times. When the written word line falls into the third group, all the middle word lines poll the RR-86 to RR-111 parts in the reread table, and query the voltage offset value at most 26 times; the edge word line polls the RR-164 to RR-189 parts in the reread table, and query the voltage offset value at most 26 times. When the write word line falls into the fourth group, the middle word lines therein all poll the portion of the corresponding fully written storage block in the reread table, and query the voltage offset value at most 26 times; the edge word lines poll the portion from RR-34 to RR-59, and query the voltage offset value at most 26 times. It should be pointed out that here, when the write word line falls into the fourth group, the middle word lines and the edge word lines are the same as the reread tables corresponding to other groups, which is only a special case and may be different in other embodiments.

[0143] In some actual reread operations, several specific reread operations are exemplified to explain the corresponding relationship between the word line groups and the reread table in the embodiments of the present disclosure. When the written word lines are 0 to 10 and fall into the first group, the middle word lines are 0 to 9, and the RR-34 to RR-59 parts are polled; the edge word line is 10 and the RR-112 to RR-137 parts are polled. When the written word lines are 0 to 56 and fall into the first group, the middle word lines are 0 to 55, and the RR-34 to RR-59 parts in the reread table are polled; the edge word line is 56, and the RR-112 to RR-137 parts are polled. When the written word lines are 0 to 57 and fall into the second group, the written word lines 0 to 56 are middle word lines, and they are not polled according to RR-34 to RR-59, but polled according to RR-60 to RR-85; the edge word lines are polled according to RR-138 to RR-163. When the written word lines are 0 to 117 and fall into the third group, the middle word lines are 0 to 116 and are polled according to RR-86 to RR-111; the edge word lines are polled according to RR-164 to RR-189. In particular, when the written word line is word line 0, the middle word line and the edge word line are both word line 0, and there are many cases of initial programming threshold voltage shift. It can be partially polled according to RR-34 to RR-59, RR-112 to RR-137, and the query can be made up to 52 times, reducing the number of failed bits (Fail Bit Count, FBC) to improve the re-reading accuracy. When word lines 0 to 231 are all full, the storage block is full, and the full storage block is polled according to the table lookup.

[0144] Figure 8 The re-read table also includes special cases such as RR-2, RR-3 to RR-7 and RR-8, which may include some other test items, such as early life detection and end-of-life detection of storage cells, which can be completed before the first polling. RR-2 corresponds to the full storage block, RR-3 to RR-7 correspond to the middle word line of the unfull storage block, and RR-8 corresponds to the edge word line of the unfull storage block. Figure 8 The number of rows included in the reread table (or reread sub-table) and the preset maximum number of table lookups (for example, 26 times) in a polling process of a reread operation are only examples and are not limited. The more preset number of table lookups in a reread operation, the less FBC caused by the determined reread voltage and the higher the reread accuracy.

[0145] Combination Figure 8 As shown, in order to better overcome the influence of the intermediate word lines and edge word lines at different positions in the storage block that are not fully written on the threshold voltage offset, the write word lines are grouped and independent polling reread table parts are set respectively, and polling items from RR-1 to RR-189 are set, and the amount of data in the reread table is relatively large.

[0146] In addition, in some other usage scenarios, there are other corresponding re-read tables, including but not limited to read interference; data retention; working life; temperature and other test items. Different test items can also be set separately. Figure 8 The reread table shown, or adding corresponding RR polling items, further increases the size of the reread table, and further increases the occupation of storage space, especially when the reread operation is started, the occupied space of the relevant registers or data buffer 1067 in the memory controller 106 is further increased, which will increase the data transmission pressure to a certain extent, and will also occupy the space occupied by other data, reducing data processing performance.

[0147] In view of this, according to a first aspect of an embodiment of the present disclosure, a memory system 102 is provided, including:

[0148] A memory device 104, the memory device comprising a plurality of memory blocks, each memory block comprising a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines;

[0149] The memory controller 106 is coupled to the memory device and is configured to:

[0150] The reread voltage is obtained by using the first type of reread table and the second type of reread table; the first type of reread table includes first voltage offset values ​​corresponding to different situations when one of the multiple storage blocks is full; the second type of reread table includes a second voltage offset value corresponding to the state of each word line of one of the multiple storage blocks when it is not full based on the first type of reread table;

[0151] The memory device 104 is controlled to perform a reread operation using the reread voltage.

[0152] In the embodiment of the present disclosure, Figure 8 The part of the reread table corresponding to the full storage block in is used as the reference reread table, and the Fig.10 The first type of rereading table shown, the first type of rereading table can be Figure 8 In the reread table, a part of the subtable is based on Fig.10 The first type of reread table in the voltage offset is used to construct the reread table corresponding to the unfilled storage block. The first type of reread table retains the RR-1, RR-9 to RR-33 parts of the filled storage block, deletes the reread table of the original unfilled storage block, and RR-2, RR-3 to RR-7 and RR-8 that do not meet the requirements. Fig. 9 Additional test cases for medium offset regularity. Fig.10 The offset voltage shown in is recorded as the first voltage offset value. In some embodiments, the present disclosure performs threshold voltage tests on a plurality of fully written memory blocks, middle word lines of memory blocks that are not fully written in a plurality of situations, and edge word lines.

[0153] Reference Fig. 9As shown, under the premise of coupling the word lines with the same number or the word lines at the same layer, the threshold voltage of the fully written storage block with less influence of the word line position on the voltage offset can be used as a reference, the threshold voltage of the middle word line in the unfilled storage block has a first offset value relative to the threshold voltage of the fully written storage block, and the threshold voltage of the edge word line in the unfilled storage block has a second offset value relative to the threshold voltage of the fully written storage block, and the second offset value is greater than the first offset value. For storage cells with a smaller number of storage bits, such as TLC, the middle word lines corresponding to all storage states thereof are subjected to the same threshold voltage offset of the first offset value, and the edge word lines corresponding to all storage states are subjected to the same threshold voltage offset of the second offset value. For storage cells with a larger storage position, such as QLC or some TLC, the middle word lines corresponding to different storage states are subjected to different threshold voltage offsets of the first offset value, and the edge word lines corresponding to different storage states are subjected to different threshold voltage offsets of the second offset value. In view of this, a corresponding voltage offset can be made on the basis of the reread table corresponding to the fully written storage block to construct a reread table corresponding to the unfilled storage block. The second voltage offset value in the second type of reread table is based on Fig. 9 The threshold voltage offset relationship between the middle word line of the unfilled storage block and the filled storage block, and the threshold voltage offset relationship between the edge word line of the unfilled storage block and the filled storage block are set to reduce the total amount of the reread table. For the filled storage block, the first voltage offset value is summed with the default read voltage to obtain the reread voltage; for the unfilled storage block, the first voltage offset value, the second voltage offset value and the default read voltage are summed to obtain the reread voltage.

[0154] In some embodiments, the memory device 104 includes multiple types of memory pages; the different situations include at least one of the following:

[0155] The storage unit includes different storage bit numbers;

[0156] The storage pages include different types;

[0157] Different usage scenarios of the memory device 104 .

[0158] In the embodiment of the present disclosure, a memory cell can store M bits of data, and the memory device 104 can include M pages. The M-bit memory cell reads its M-bit stored data through an N-level read voltage; M and N are both integers greater than 1, and N=2 M -1.

[0159] When M=2, the storage data in the storage unit includes two bits. At this time, the memory includes two types of pages, namely, upper page and lower page. The two-bit storage unit needs to pass through three stages (3=2 2-1) read voltage to read its two-bit storage data; illustratively, the two-bit data stored in the storage cell corresponds to four states (one erased state and three storage states), that is, four voltage ranges are assigned to four data values. When reading, the two-bit storage data stored in the storage cell is read by applying a three-level read voltage for distinguishing the four voltage ranges. Among them, the upper page corresponds to the first-level read voltage, and the lower page corresponds to the second-level read voltage.

[0160] When M=3, the storage data in the storage unit includes three bits. At this time, the memory includes three types of pages, namely, upper page, middle page and lower page. The three-bit storage unit needs to pass through seven stages (7=2 3 -1) read voltage to read its three-bit storage data; illustratively, the three-bit data stored in the storage cell corresponds to eight states (one erased state and seven storage states), that is, eight voltage ranges are assigned to eight data values. When reading, the three-bit storage data stored in the storage cell is read by applying seven-level read voltages for distinguishing the eight voltage ranges. Among them, the upper page corresponds to the second-level read voltage, the middle page corresponds to the third-level read voltage, and the lower page corresponds to the second-level read voltage. For example Fig. 9 as well as Fig.10 In the reread table, the seven levels of read voltage (Vrd1-7) of the seven storage states except the erase state are respectively: Rd1LP, Rd2MP, Rd3UP, Rd2MP, Rd5LP, Rd6MP, Rd7UP. The upper page can correspond to Rd3UP and Rd7UP, the middle page corresponds to Rd2MP, Rd2MP and Rd6MP, and the lower page corresponds to Rd1LP and Rd5LP. The corresponding relationship between the corresponding level read voltage offset voltage and different types of storage pages in the reread table is the same as the corresponding relationship between the read voltage and the storage page, and will not be repeated.

[0161] When M=4, the storage data in the storage unit includes four bits. At this time, the memory includes four types of pages, namely, upper page, middle upper page, middle lower page, and lower page. The four-bit storage unit corresponds to fifteen levels (15=2 4 -1) read voltage to read its four-bit data; illustratively, the four-bit data stored in the storage cell corresponds to sixteen states (one erased state and fifteen storage states), that is, sixteen voltage ranges are allocated to sixteen data values, and when reading, by applying fifteen levels of read voltages for distinguishing the sixteen voltage ranges, the three-bit storage data stored in the storage cell is read. Among them, the upper page corresponds to the fourth level of read voltage, the middle upper page corresponds to the third level of read voltage, the middle lower page corresponds to the fourth level of read voltage, and the lower page corresponds to the fourth level of read voltage.

[0162] In some embodiments, the corresponding order reading voltage corresponding to each type of page to distinguish the corresponding bit storage data is determined according to a coding rule. Exemplarily, the coding rule includes but is not limited to Gray code coding rules. It should be noted that the typical binary Gray code (Binary Gray Code) is usually referred to as Gray code. In the encoding of a set of numbers, if any two adjacent codes have only one binary digit different, then this encoding is called Gray code. In addition, since the maximum number and the minimum number are only one digit different, that is, "connected end to end", it is also called a cyclic code or reflection code; Gray code also has many other encoding forms, such as decimal number encoding, four-bit natural binary encoding, etc.; Among them, Gray code is to produce a code table by recursion, for example, two-bit Gray code, three-bit Gray code, four-bit Gray code, etc. Reference Fig.11 As shown, taking the three-dimensional Gray code as an example, such as 111, 110, 100, 000, 101, 011, 001, 101, which correspond to the erased state (ER) and seven storage states (P1-P7), respectively, as mentioned above, reading the eight voltage ranges corresponding to the eight storage states (one erased state and seven storage states) requires seven levels of read voltage. In the embodiment of the present disclosure, the three types of pages corresponding to the three-bit storage unit are respectively corresponded to the seven-level read voltage through the encoding rule of the three-bit Gray code, wherein the lower page corresponds to the first-level read voltage and the fifth-level read voltage; the middle page corresponds to the second-level read voltage, the fourth-level read voltage, and the sixth-level read voltage; the upper page corresponds to the third-level read voltage and the seventh-level read voltage. It should be noted that after the encoding rule is changed, the corresponding order is also adjusted accordingly. Different usage scenarios include but are not limited to: read interference; data retention; working life; temperature and other test items, and different test items correspond to the reread table corresponding to multiple full storage blocks, and also correspond to the reread table of multiple unfull storage blocks.

[0163] In some embodiments, the storage block includes a first storage block, the first storage block is an unfilled storage block, and the memory controller 106 is configured to:

[0164] Using the first type of reread table, obtaining a first voltage offset value corresponding to the first storage block;

[0165] Using the second type of reread table, and combining the group to which the word line coupled to the memory cell to be read in the first memory block belongs and the relationship between the word line coupled to the memory cell to be read and the first blank word line, a corresponding second voltage offset value is obtained;

[0166] A reread voltage when a read operation is performed on the storage unit to be read in the first storage block is obtained according to the first voltage offset value and the second voltage offset value.

[0167] In some embodiments, the memory controller 106 is configured to:

[0168] Add the first voltage offset value and the second voltage offset value to obtain a total offset voltage value;

[0169] The default read voltage is summed with the total offset voltage value to obtain the re-read voltage. Figure 6 The read voltage for the default read operation is shown.

[0170] For a fully written memory block, the first voltage offset value is added to the default read voltage to obtain a reread voltage; for an incompletely written memory block, the first voltage offset value, the second voltage offset value and the default read voltage are added to obtain a reread voltage.

[0171] In some embodiments, the memory block includes word lines 0 to N that are sequentially numbered according to physical positions; the memory block is programmed in order from the 0 to N word lines; N is an integer greater than 2;

[0172] All word lines of the storage block are divided into a plurality of groups, each group comprising a plurality of adjacent word lines;

[0173] All word lines in the first storage block include: the first blank word line, edge word lines adjacent to the first blank word line, and middle word lines spaced apart from the first blank word line; wherein the edge word lines have different second voltage offset values ​​when they fall into different groups, and the middle word lines have different second voltage offset values ​​when they fall into different groups.

[0174] In some embodiments, each group includes the same or similar number of word lines.

[0175] In some embodiments, the edge word lines and the middle word lines falling into the same group have different second voltage offset values.

[0176] The first storage block is an unfilled storage block. When performing a reread operation, use Fig.10 The first type of reread table set in different situations corresponding to the full storage block shown obtains the first voltage offset value. As mentioned above, the word lines are numbered and grouped according to the programming order. The distance between the word line to be reread and the first blank word line can determine the middle word line and the edge word line of the written word line. The closest word line adjacent to the first blank word line in the written word line is the edge word line, and the rest are the middle word lines. In the same word line group, the second voltage offset value corresponding to the edge word line is greater than the second voltage offset value corresponding to the middle word line. The first voltage offset value, the second voltage offset value and the default read voltage corresponding to the corresponding word line are summed to obtain the reread voltage.

[0177] Reference Fig.12a As shown, an example form of the second type of rereading table is shown. Figure 12b shows the second type of rereading table with Figure 8 The corresponding relationship of the re-read table in the table. Among them, close blk is a full storage block, and the full storage block is closed for programming operations; open block is an unfull storage block, and the unfull storage block is activated or turned on for programming operations, openWL is the middle word line in the unfull storage block, inner WL is the middle word line in it, and edge WL is the edge word line in it. It should be pointed out that Fig.12a and Figure 12b The second voltage offset value in the embodiment may be applicable to an overall offset of the first voltage offset value for all storage states of the memory cells.

[0178] Exemplarily, taking the TLC storage cells of word lines 0 to 231 as an example, the first group includes 0 to 56, the second group includes 57 to 116, the third group includes 117 to 172, and the fourth group includes 173 to 230. The grouping here includes write word lines including middle word lines and edge word lines. When the number of word lines is further increased, more groups can be added, and the number of word lines contained in each group can be the same or different. Exemplarily, when the write word lines 0 to 57 fall into the second group, word lines 0 to 56 still belong to the second group, and the second voltage offset value in the second type of reread table is looked up in the table according to the corresponding mode of the second group. Fig.12a In the example, each group of write word lines corresponds to two different second voltage offset values, and the absolute value of the second voltage offset value corresponding to the edge word line is greater than the absolute value of the second voltage offset value corresponding to the middle word line. Here, each storage state of the memory cell corresponds to the same second voltage offset value, and four groups can correspond to 8 second voltage offset values.

[0179] Specific, combined Figure 12b As shown, the corresponding RR-1 and RR-9 to RR-33 in setting 1 are Figure 8 and Fig.10 The first type of reread table content corresponding to the full memory block shown in is the offset reference voltage of the second voltage offset value, with 26 RR settings. It should be noted that for the reference case corresponding to setting 1, the second voltage offset value relative to the first voltage offset value of the full memory block is 0.

[0180] Reference Fig.12a As shown, when the write word lines are 0 to 10 and fall into the first group, the middle word lines are 0 to 9, and the corresponding second voltage offset value can be -90mv, and the second voltage offset value corresponding to the edge word line is 10 is -190mv. The reread operation of the middle word line can refer to Figure 12bAs shown in setting 2 in FIG. 1 , a second voltage offset value of -90 mv is added to the first voltage offset value corresponding to all storage states in each RR setting to replace Figure 8 Reread the RR-34 to RR-59 settings in the table. The edge word line is word line 10 at this time, and the second voltage offset value is -190mv, corresponding to Figure 12b In setting 5, based on the first voltage offset value of the fully written memory block, all memory states are offset by a second voltage offset value.

[0181] When the write word lines are 0 to 57 and fall into the second group, and the middle word lines are 0 to 56, the second voltage offset value of the second group is not used, but the second voltage offset value of the second group is -60mv, corresponding to Figure 12b Setting 3 in the example shifts the first voltage offset value of the full memory block to -60mv; the edge word line is No. 57, and the second voltage offset value is -160mv, corresponding to Figure 12b Setting 6 in the example shifts all first voltage offset values ​​corresponding to fully written storage blocks by -160mv. Similarly, the second voltage offset value of the middle word line of the third group of written word lines is -30mv, and the second voltage offset value of the edge word line is -120mv; the second voltage offset value of the middle word line of the fourth group of written word lines is 0mv, and the second voltage offset value of the edge word line is -90mv.

[0182] Combination Figure 12b As shown, after the second reread table is set in the embodiment of the present disclosure, the total RR setting items of the reread table may include 26 full storage blocks as offset references, 8 second voltage offset value setting items, and 7 additional situations. Figure 8 The 189 RR setting items shown in the embodiment of the present disclosure reduce the amount of data in the reread table, facilitate fast lookup of the firmware and the polling rate of the reread operation, thereby increasing the reading rate of the memory system.

[0183] In some embodiments, the closer the middle word line is to the 0th word line, the greater the absolute value of the offset of the second voltage offset value corresponding to the corresponding group into which the middle word line falls is compared with the first voltage offset value;

[0184] The closer the edge word line is to the 0th word line, the greater the absolute value of the offset of the second voltage offset value in the second type reread table corresponding to the corresponding group into which the edge word line falls is compared with the first voltage offset value;

[0185] When the edge word line and the middle word line fall into the same group, the absolute value of the offset of the second voltage offset value corresponding to the edge word line relative to the first voltage offset value is greater than the absolute value of the offset of the second voltage offset value corresponding to the middle word line relative to the first voltage offset value.

[0186] Reference Fig.12a As shown, from the perspective of the middle word lines in different groups, the closer the middle word lines are to word line 0, the smaller the number, the earlier the programming order, and the greater the absolute value of the second voltage offset value corresponding to them. From the perspective of the edge word lines in different groups, the closer the edge word lines are to word line 0, the smaller the number, the earlier the programming order, and the greater the absolute value of the second voltage offset value corresponding to them. The absolute value of the second voltage offset value corresponding to the edge word lines of the same group may be greater than the absolute value of the second voltage offset value corresponding to the middle word lines.

[0187] In some embodiments, the memory cell comprises a multi-bit memory cell, and the multi-bit memory cell reads multi-bit storage data by a multi-level read voltage;

[0188] The second voltage offset value corresponding to each level of the multi-level read voltage is the same;

[0189] or,

[0190] The second voltage offset values ​​corresponding to some level read voltages in the multi-level read voltages are different.

[0191] Reference Fig.12a and Figure 12b As shown, for the storage on the same word line, all storage states are overall shifted by the same second voltage shift value.

[0192] In some embodiments, at least two levels of read voltages in the multi-level read voltages correspond to different second voltage offset values;

[0193] The multi-level read voltage is divided into a plurality of intervals, each interval including a first-level read voltage or adjacent multi-level read voltages;

[0194] The second voltage offset values ​​corresponding to each level of read voltage in one of the intervals are the same, and the second voltage offset values ​​corresponding to multiple levels of read voltage in different intervals are different.

[0195] Reference Fig.12c As shown, the storage state is divided into multiple intervals, and the second voltage offset values ​​corresponding to different storage states of the storage cells on the same word line are also different. Taking the P1 to P7 storage states of TLC as an example, only the first group of word lines and the second group of word lines are shown as examples for explanation. For example, the 7-level read voltage of the TLC storage cell is divided into 3 intervals, and the corresponding second voltage offset value applied to the reread operation setting is also divided into 3 intervals, wherein the first interval may only include the P1 state, the second interval may include the P2 to P6 states, and the third interval may include the P7 state.

[0196] Taking the write word lines falling into 0 to 56 as an example, the second voltage offset value corresponding to the P1 storage state of the storage cell corresponding to the intermediate word line is -100mv, the second voltage offset values ​​corresponding to the P2 to P6 states are all -90mv, and the second voltage offset value corresponding to the P7 state is -80mv; the second voltage offset value corresponding to the P1 storage state of the storage cell corresponding to the edge word line is -200mv, the second voltage offset values ​​corresponding to the P2 to P6 states are all -190mv, and the second voltage offset value corresponding to the P7 state is -180mv.

[0197] In some other embodiments, when the storage states of the memory cell are further increased, for example, a QLC having P1 to P15, the first interval includes the P1 state, the second interval includes the P2 to P14 states, and the third interval includes the P15 state. Alternatively, the first interval includes the P1 to P2 states, the second interval includes the P3 to P13 states, and the third interval includes the P14 to P15 states. More intervals may be further divided, each of which includes the same or different number of storage states, so as to increase the accuracy of the second voltage offset value and improve the pass rate of the reread operation.

[0198] In some embodiments, each of the groups corresponds to the multiple intervals; for different multiple intervals corresponding to the same group, the smaller the average order of the read voltage contained in the corresponding interval, the greater the absolute value of the offset of the second voltage offset value corresponding to the corresponding interval compared to the first voltage offset value.

[0199] Reference Fig.12c As shown, for the storage state division intervals of the storage cells corresponding to the first group of write word lines, the average order of the first interval is smaller than that of the second interval, and the average order of the second interval is smaller than that of the third interval. The absolute value of the second voltage offset value corresponding to the middle word line in the first interval is the largest, followed by the second interval, and the smallest in the third interval. The variation law of the second voltage value of the edge word line is the same and will not be repeated. In some actual embodiments, the variation law of the storage state corresponding to the second voltage offset value may be related to the amount of charge stored in the storage cell. When the storage amount is small, a larger threshold voltage offset will be generated, requiring more voltage offset values ​​to correct.

[0200] In some embodiments, the memory controller 106 is configured to:

[0201] After executing the reread operation, performing a hard decoding operation on the reread data;

[0202] In response to the hard decoding operation failing, performing a soft decoding operation;

[0203] In response to the soft decoding operation failing, a redundant array data recovery operation is performed.

[0204] Reference Figure 6As shown, when the memory controller 106 controls the memory device 104 to perform a read operation, a default read operation (FW default read) is first performed on the storage unit of the corresponding physical address. After the default read fails, a reread operation (Read retry) is performed after the default read operation fails. After the reread operation fails, a soft decoding operation (Softdecode) is performed. After the soft decoding fails, a redundant array data recovery (RAID) operation is performed. After the RAID operation fails, the read operation stops and the read fails due to the inability to correct the error. The memory controller 106 sends a read fail (Read fail) signal to the host 108.

[0205] According to some aspects of the embodiments of the present disclosure, a method for operating a memory system 102 is provided, referring to Fig.13 As shown, the operation method includes:

[0206] A reread voltage is obtained by using a first type of reread table and a second type of reread table; the first type of reread table includes first voltage offset values ​​corresponding to different situations when one of the multiple storage blocks of the memory device is full; the second type of reread table includes a second voltage offset value corresponding to the state of each word line of one of the multiple storage blocks when it is not full based on the first type of reread table;

[0207] A re-read operation is performed using the re-read voltage.

[0208] In some embodiments, the storage block includes a first storage block, and the first storage block is an unfilled storage block; the step of obtaining the reread voltage by using the first type reread table and the second type reread table includes:

[0209] Using the first type of reread table, obtaining a first voltage offset value corresponding to the first storage block;

[0210] Using the second type of reread table, and combining the group to which the word line coupled to the memory cell to be read in the first memory block belongs and the distance between the word line coupled to the memory cell to be read and the first blank word line, a corresponding second voltage offset value is obtained;

[0211] A reread voltage when a read operation is performed on the storage unit to be read in the first storage block is obtained according to the first voltage offset value and the second voltage offset value.

[0212] In some embodiments, obtaining the re-read voltage corresponding to the storage unit to be read in the first storage block according to the first voltage offset value and the second voltage offset value includes:

[0213] Add the first voltage offset value and the second voltage offset value to obtain a total offset voltage value;

[0214] The re-read voltage is obtained by summing the default read voltage and the total offset voltage value.

[0215] In some embodiments, the memory block includes word lines 0 to N that are sequentially numbered according to physical positions; the memory block is programmed in order from the 0 to N word lines; N is an integer greater than 2;

[0216] All word lines included in the storage block are divided into a plurality of groups, each group including a plurality of adjacent word lines;

[0217] All word lines in the first storage block include: the first word line, an edge word line adjacent to the first blank word line, and an intermediate word line spaced apart from the first blank word line; wherein the edge word lines falling into different groups have different second voltage offset values, and the intermediate word lines falling into different groups have different second voltage offset values.

[0218] In some embodiments, each group includes the same or similar number of word lines.

[0219] In some embodiments, the edge word lines and the middle word lines falling into the same group have different second voltage offset values.

[0220] In some embodiments, the closer the middle word line is to the 0th word line, the greater the absolute value of the offset of the second voltage offset value corresponding to the corresponding group into which the middle word line falls is compared with the first voltage offset value;

[0221] The closer the edge word line is to the 0th word line, the greater the absolute value of the offset of the second voltage offset value in the second type reread table corresponding to the corresponding group into which the edge word line falls is compared with the first voltage offset value;

[0222] When the edge word line and the middle word line fall into the same group, the absolute value of the offset of the second voltage offset value corresponding to the edge word line relative to the first voltage offset value is greater than the absolute value of the offset of the second voltage offset value corresponding to the middle word line relative to the first voltage offset value.

[0223] In some embodiments, the memory cell comprises a multi-bit memory cell, and the multi-bit memory cell reads multi-bit storage data by a multi-level read voltage;

[0224] The second voltage offset value corresponding to each level of the multi-level read voltage is the same;

[0225] or,

[0226] The second voltage offset values ​​corresponding to some level read voltages in the multi-level read voltages are different.

[0227] In some embodiments, at least two levels of read voltages in the multi-level read voltages correspond to different second voltage offset values;

[0228] The multi-level read voltage is divided into a plurality of intervals, each interval including a first-level read voltage or adjacent multi-level read voltages;

[0229] The second voltage offset values ​​corresponding to each level of read voltage in one of the intervals are the same, and the second voltage offset values ​​corresponding to multiple levels of read voltage in different intervals are different.

[0230] In some embodiments, each of the groups corresponds to the multiple intervals; for different multiple intervals corresponding to the same group, the smaller the average order of the read voltage contained in the corresponding interval, the greater the absolute value of the offset of the second voltage offset value corresponding to the corresponding interval compared to the first voltage offset value.

[0231] In some embodiments, the memory device 104 includes multiple types of memory pages; the different situations include at least one of the following:

[0232] The storage unit includes different storage bit numbers;

[0233] The storage pages include different types;

[0234] Different usage scenarios of the memory device 104 .

[0235] In some embodiments, the operating method further includes:

[0236] After executing the reread operation, performing a hard decoding operation on the reread data;

[0237] In response to the hard decoding operation failing, performing a soft decoding operation;

[0238] In response to the soft decoding operation failing, a redundant array data recovery operation is performed.

[0239] According to some aspects of the embodiments of the present disclosure, a readable storage medium is provided, wherein the readable storage medium stores a computer program, and when the computer program is executed, the operation method described in the above embodiments is implemented. The readable storage medium may include a NAND memory, and the storage unit of the NAND memory may include a floating gate type storage unit of a floating gate transistor, or a charge capture type storage unit including a charge capture transistor.

[0240] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory system, characterized in that: include: A memory device, the memory device comprising a plurality of memory blocks, each of the memory blocks comprising a plurality of word lines and a plurality of memory cells coupled to the plurality of word lines; A memory controller is coupled to the memory device and is configured to: A reread voltage is obtained by using a first type of reread table and a second type of reread table; the first type of reread table includes first voltage offset values ​​corresponding to different situations when one of the multiple storage blocks is full; the second type of reread table includes a second voltage offset value corresponding to the state of each word line of one of the multiple storage blocks when it is not full based on the first type of reread table; The memory device is controlled to perform a reread operation using the reread voltage.

2. The memory system according to claim 1, wherein: The storage block includes a first storage block, the first storage block is an incomplete storage block, and the memory controller is configured as follows: Using the first type of reread table, obtaining a first voltage offset value corresponding to the first storage block; Using the second type of reread table, and combining the group to which the word line coupled to the memory cell to be read in the first memory block belongs and the relationship between the word line coupled to the memory cell to be read and the first blank word line, a corresponding second voltage offset value is obtained; A reread voltage when a read operation is performed on the storage unit to be read in the first storage block is obtained according to the first voltage offset value and the second voltage offset value.

3. The memory system according to claim 2, wherein: The memory controller is configured to: Add the first voltage offset value and the second voltage offset value to obtain a total offset voltage value; The re-read voltage is obtained by summing the default read voltage and the total offset voltage value.

4. The memory system according to claim 2, wherein: The storage block includes word lines 0 to N which are sequentially numbered according to physical positions; Programming the memory blocks in order from the 0th word line to the Nth word line; Said N is an integer greater than 2; All word lines of the storage block are divided into a plurality of groups, each group comprising a plurality of adjacent word lines; All word lines in the first storage block include: the first blank word line, edge word lines adjacent to the first blank word line, and middle word lines spaced apart from the first blank word line; The edge word lines falling into different groups have different second voltage offset values, and the middle word lines falling into different groups have different second voltage offset values.

5. The memory system according to claim 4, characterized in that: The edge word lines and the middle word lines falling into the same group have different second voltage offset values.

6. The memory system according to claim 4, characterized in that: Each group includes the same or similar number of word lines.

7. The memory system according to claim 4, characterized in that: The closer the middle word line is to the 0th word line, the greater the absolute value of the offset of the second voltage offset value corresponding to the corresponding group into which the middle word line falls is compared with the first voltage offset value; The closer the edge word line is to the 0th word line, the greater the absolute value of the offset of the second voltage offset value in the second type reread table corresponding to the corresponding group into which the edge word line falls is compared with the first voltage offset value; When the edge word line and the middle word line fall into the same group, the absolute value of the offset of the second voltage offset value corresponding to the edge word line relative to the first voltage offset value is greater than the absolute value of the offset of the second voltage offset value corresponding to the middle word line relative to the first voltage offset value.

8. The memory system according to claim 4, characterized in that: The storage unit includes a multi-bit storage unit, and the multi-bit storage unit reads multi-bit storage data through a multi-level read voltage; The second voltage offset value corresponding to each level of the multi-level read voltage is the same; or, The second voltage offset values ​​corresponding to some levels of read voltages in the multi-level read voltages are different.

9. The memory system according to claim 8, characterized in that: The second voltage offset values ​​corresponding to at least two levels of read voltages in the multi-level read voltages are different; The multi-level read voltage is divided into a plurality of intervals, each interval including a first-level read voltage or adjacent multi-level read voltages; The second voltage offset values ​​corresponding to each level of read voltage in one of the intervals are the same, and the second voltage offset values ​​corresponding to multiple levels of read voltage in different intervals are different.

10. The memory system according to claim 9, characterized in that: Each of the groups corresponds to the multiple intervals; for different multiple intervals corresponding to the same group, the smaller the average order of the read voltage contained in the corresponding interval, the greater the absolute value of the offset of the second voltage offset value corresponding to the corresponding interval compared to the first voltage offset value.

11. The memory system according to claim 1, wherein: The memory device includes multiple types of memory pages; the different situations include at least one of the following: The storage unit includes different storage bit numbers; The storage pages include different types; Different usage scenarios of the memory device.

12. The memory system according to claim 1, wherein: The memory controller is configured to: After executing the reread operation, performing a hard decoding operation on the reread data; In response to the hard decoding operation failing, performing a soft decoding operation; In response to the soft decoding operation failing, a redundant array data recovery operation is performed.

13. A method for operating a memory system, characterized in that: include: A reread voltage is obtained by using a first type of reread table and a second type of reread table; the first type of reread table includes first voltage offset values ​​corresponding to different situations when one of the multiple storage blocks of the memory device is full; the second type of reread table includes a second voltage offset value corresponding to the state of each word line of one of the multiple storage blocks when it is not full based on the first type of reread table; A re-read operation is performed using the re-read voltage.

14. The operating method according to claim 13, characterized in that: The storage block includes a first storage block, and the first storage block is an unfilled storage block; the method of obtaining the reread voltage by using the first type reread table and the second type reread table includes: Using the first type of reread table, obtaining a first voltage offset value corresponding to the first storage block; Using the second type of reread table, and combining the group to which the word line coupled to the memory cell to be read in the first memory block belongs and the relationship between the word line coupled to the memory cell to be read and the first blank word line, a corresponding second voltage offset value is obtained; A reread voltage when a read operation is performed on the storage unit to be read in the first storage block is obtained according to the first voltage offset value and the second voltage offset value.

15. The operating method according to claim 14, characterized in that: The obtaining, according to the first voltage offset value and the second voltage offset value, a reread voltage corresponding to the storage unit to be read in the first storage block includes: Add the first voltage offset value and the second voltage offset value to obtain a total offset voltage value; The re-read voltage is obtained by summing the default read voltage and the total offset voltage value.

16. The operating method according to claim 14, characterized in that: The storage block includes word lines 0 to N which are sequentially numbered according to physical positions; the storage block is programmed in the order from the 0 to N word lines; Said N is an integer greater than 2; All word lines included in the storage block are divided into a plurality of groups, each group including a plurality of adjacent word lines; All word lines in the first storage block include: the first word line, an edge word line adjacent to the first blank word line, and an intermediate word line spaced apart from the first blank word line; wherein the edge word lines falling into different groups have different second voltage offset values, and the intermediate word lines falling into different groups have different second voltage offset values.

17. The operating method according to claim 16, characterized in that: The edge word lines and the middle word lines falling into the same group have different second voltage offset values.

18. The operating method according to claim 16, characterized in that: Each group includes the same or similar number of word lines.

19. The operating method according to claim 16, characterized in that: The closer the middle word line is to the 0th word line, the greater the absolute value of the offset of the second voltage offset value corresponding to the corresponding group into which the middle word line falls is compared with the first voltage offset value; The closer the edge word line is to the 0th word line, the greater the absolute value of the offset of the second voltage offset value in the second type reread table corresponding to the corresponding group into which the edge word line falls is compared with the first voltage offset value; When the edge word line and the middle word line fall into the same group, the absolute value of the offset of the second voltage offset value corresponding to the edge word line relative to the first voltage offset value is greater than the absolute value of the offset of the second voltage offset value corresponding to the middle word line relative to the first voltage offset value.

20. The operating method according to claim 16, characterized in that: The storage unit includes a multi-bit storage unit, and the multi-bit storage unit reads multi-bit storage data through a multi-level read voltage; The second voltage offset value corresponding to each level of the multi-level read voltage is the same; or, The second voltage offset values ​​corresponding to some levels of read voltages in the multi-level read voltages are different.

21. The operating method according to claim 20, characterized in that: The second voltage offset values ​​corresponding to at least two levels of read voltages in the multi-level read voltages are different; The multi-level read voltage is divided into a plurality of intervals, each interval including a first-level read voltage or adjacent multi-level read voltages; The second voltage offset values ​​corresponding to each level of read voltage in one of the intervals are the same, and the second voltage offset values ​​corresponding to multiple levels of read voltage in different intervals are different.

22. The operating method according to claim 21, characterized in that: Each of the groups corresponds to the multiple intervals; for different multiple intervals corresponding to the same group, the smaller the average order of the read voltage contained in the corresponding interval, the greater the absolute value of the offset of the second voltage offset value corresponding to the corresponding interval compared to the first voltage offset value.

23. The operating method according to claim 13, characterized in that: The memory device includes multiple types of memory pages; the different situations include at least one of the following: The storage unit includes different storage bit numbers; The storage pages include different types; Different usage scenarios of the memory device.

24. The operating method according to claim 13, characterized in that: The operation method also includes: After executing the reread operation, performing a hard decoding operation on the reread data; In response to the hard decoding operation failing, performing a soft decoding operation; In response to the soft decoding operation failing, a redundant array data recovery operation is performed.

25. A readable storage medium, characterized in that: The readable storage medium stores a computer program, and when the computer program is executed, the operating method according to any one of claims 13 to 24 is implemented.

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