Digital eye pattern test method and device, electronic equipment and storage medium

Abstract

The invention provides a digital eye pattern testing method and device, electronic equipment and a storage medium. The method comprises the following steps: acquiring a training value of an optimal position of a read-write time sequence; wherein the training value comprises a phase and a voltage; determining a phase and voltage test range for testing according to the training value; based on each group of phases and voltages in the test range, using the configured test cases to perform testing; a test result is recorded; wherein the test results are passing and non-passing; and in response to the condition that the current test meets a preset ending condition, ending the digital eye diagram test, and outputting a digital eye diagram based on all recorded test results. According to the method, the test of the digital eye diagram can be realized under the conditions of low cost and no hardware limitation.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of computer technology, and in particular to a digital eye diagram testing method, device, electronic device, and storage medium. Background Art

[0002] With the continuous iteration of DDR (Double date rate) / HBM (High Bandwidth Memory), the data read and write speed and density are getting higher and higher, which greatly improves the read and write efficiency and places more stringent requirements on the signal quality of I / O (data bus). In the parameter tuning and signal integrity verification of silicon (post-silicon) system-level Memory (memory) IP (the design of circuit modules with independent functions in the chip), the digital eye diagram is an intuitive way to measure signal quality.

[0003] Currently, the most commonly used method is to obtain a digital eye diagram through an oscilloscope, but the equipment cost is high. For example, a high-bandwidth oscilloscope often costs millions. The test is limited by hardware and has high requirements for solder joints and probe types. Different DDRs in embedded designs require a special interposer (adapter board), and the design is more difficult for HBM packaged in the chip. Therefore, there is an urgent need for a digital eye diagram test method that is not limited by hardware and has a low cost. Summary of the invention

[0004] In view of this, the present application provides a digital eye diagram testing method, device, electronic device and storage medium, which can realize the testing of digital eye diagram at low cost and without hardware restrictions.

[0005] To solve the above technical problems, the technical solution of this application is implemented as follows: In one embodiment, a digital eye diagram testing method is provided, the method comprising: Obtaining a training value of an optimal position of a read / write timing sequence; wherein the training value includes a phase and a voltage; Determining a test range of phase and voltage for testing according to the training values; Based on each set of phases and voltages within the test range, use the configured test cases to perform tests respectively; and record the test results; wherein the test results are pass or fail; In response to the current test satisfying a preset end condition, the digital eye diagram test is ended, and a digital eye diagram is output based on all recorded test results.

[0006] Wherein, determining the test range of the phase and voltage for testing according to the training value includes: Taking the training value as the center point, determining the test range and the test starting point of the phase and voltage used for the test according to the training value, the preset voltage height and the preset phase width; The testing is performed separately using configured test cases based on each set of phases and voltages within the test range, including: Starting from the test starting point, determining a set of phases and voltages used for each test according to a preset first phase step and a first voltage step, and performing the test using a configured test case based on the determined set of phases and voltages; The preset end condition is that the current test is the test corresponding to the last set of phases and voltages within the test range.

[0007] Wherein, starting from the test starting point, when determining a set of phases and voltages used for each test according to a preset first phase step and a first voltage step, the phases and voltages used for each test are determined by relative values.

[0008] Wherein, determining the test range of the phase and voltage for testing according to the training value includes: The range corresponding to the scanning in all directions with the training value as the center point is used as the test range of the phase and voltage for the test; The testing is performed separately using configured test cases based on each set of phases and voltages within the test range, including: Taking the training value as the test starting point, determining a set of phases and voltages used for each test in different test directions according to the preset second phase step and second voltage step, and performing the test using the configured test case based on the determined set of phases and voltages; when performing the test in each test direction, terminating the test in the test direction when the test result is a failure; The preset end condition is that the current test is the test in the last test direction among all test directions, and the test result of the current test is failure.

[0009] If the test fails, or if the test succeeds and ECC occurs, the test result is recorded as failed. If the test runs successfully and no ECC occurs, the test result is recorded as passed.

[0010] After obtaining the training value of the optimal position of the read / write timing, determining the test range of the phase and voltage for testing according to the training value; the method further comprises: Determine whether to turn on periodic training. If so, turn off the periodic training, and then determine the test range of the phase and voltage used for testing according to the training value; otherwise, directly determine the test range of the phase and voltage used for testing according to the training value.

[0011] In another embodiment, a digital eye diagram testing device is provided, the device comprising: An acquisition unit, used to acquire a training value of an optimal position of a read / write timing sequence; wherein the training value includes a phase and a voltage; A determination unit, configured to determine a test range of a phase and a voltage for testing according to the training value; A test unit, for performing tests respectively based on each set of phases and voltages within the test range using configured test cases; A recording unit, used to record the test results; wherein the test results are pass or fail; The output unit is used to terminate the digital eye diagram test in response to the current test meeting a preset termination condition, and output the digital eye diagram based on all recorded test results.

[0012] Wherein, the device further comprises: A processing unit is used to determine whether to turn on periodic training after the acquisition unit acquires the training value of the optimal position of the read and write timing. If so, turn off the periodic training and then trigger the determination unit to determine the test range of the phase and voltage used for testing according to the training value; otherwise, directly trigger the determination unit to determine the test range of the phase and voltage used for testing according to the training value.

[0013] In another embodiment, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a digital eye diagram testing method when executing the program.

[0014] In another embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the program is executed by a processor, a digital eye diagram testing method is implemented.

[0015] As can be seen from the above technical solution, in the above embodiment, the test range of the phase and voltage used for testing is determined by the training value of the optimal position of the read-write timing; based on each set of phase and voltage within the test range, the configured test case is used for testing; and the test results are recorded; wherein the test results are pass and fail; in response to the current test meeting the preset end condition, the digital eye diagram test is ended, and the digital eye diagram is output based on all the recorded test results. This method can greatly improve the test efficiency. Therefore, this method can realize the test of the digital eye diagram at a low cost and without hardware restrictions. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 This is a schematic diagram of the digital eye diagram test process in an embodiment of the present application; Figure 2 This is a flow chart of performing an eye diagram test based on a test starting point in an embodiment of the present application; FIG3 (a) is a schematic diagram of a digital eye diagram when the test is started from the test starting point and the PHYODT is set to 40 ohms; FIG3( b ) is a schematic diagram of a digital eye diagram when the test is started from the test starting point and the PHYODT is set to 60 ohms; Figure 4 This is a flow chart of starting an eye diagram test based on training values ​​in an embodiment of the present application; FIG5 (a) is a diagram of a digital eye diagram when the test is started based on the training value and the PHYODT is set to 40 ohms; FIG5( b ) is a diagram of a digital eye diagram when the test is started based on the training value and the PHYODT is set to 60 ohms; Figure 6 This is a structural schematic diagram of a digital eye diagram testing device in an embodiment of the present application; Figure 7 A schematic diagram of the physical structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the test scope protected by this application.

[0019] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe the order or precedence of the objects. It should be understood that the data used in this way can be interchanged where appropriate, so that the implementation of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0020] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0021] In silicon system-level Memory IP parameter tuning and signal integrity verification, with the continuous iteration of DDR / HBM, the data read and write rate and density are getting higher and higher. The current maximum data rate of LPDDR (Low Power Double Date Rate, low-power double-rate synchronous dynamic random access memory) 5 is 6.4Gbps, the maximum data rate of HBM2e is 3.6Gbps, and the rate of HBM3 reaches 6.4Gbps. The burst length of LPDDR5 is BL16, HBM2e is BL4, and HBM3 is BL8. These changes have greatly improved the read and write efficiency and have more stringent requirements on the signal quality of I / O. In memory testing, a fast and intuitive way to measure signal quality is the eye diagram.

[0022] The most commonly used method at present is to measure the digital eye diagram through an oscilloscope. For standardized DIMM (dual in-line memory module), probe tips can be used for direct detection. In embedded design, DRAM is soldered on the PCB board and can be measured through the BGA interposer. For example, LPDDR5 can be equipped with a customized interposer to lead out the required signal and connect it to the oscilloscope through the probe. Since HBM is encapsulated in the chip, it is difficult to install the interposer.

[0023] It can be seen that there are the following disadvantages when measuring digital eye diagrams through the hardware method of oscilloscope: High equipment cost: For example, a high-bandwidth oscilloscope often costs several million; The test is limited by hardware: the requirements for solder joints and probe types are relatively high; different DDRs in embedded design require dedicated interposers, and the design is more difficult for HBM packaged in the chip.

[0024] Low test efficiency: The existing mainstream accelerator cards have at least 6 or 8 DDR chips and two HBM chips. The total bit width of DDR reaches 192bit / 256bit. A single HBM chip has 1024bit. It is difficult to cover all lanes (channels) in the test, which takes a lot of time.

[0025] Based on the above problems, a digital eye diagram test method is provided in an embodiment of the present application, which is applied to the digital eye diagram test of DDR or HBM memory. No changes or additions are required to the hardware, and the digital eye diagram test is implemented by software without being restricted by hardware. The software function module for performing the digital eye diagram test can be stored on the device where the board under test is located, or it can be stored on any device that can communicate with the device where the board under test is located, such as a server, a PC, etc.

[0026] The implementation scheme provided in the embodiment of the present application is to determine the test range of the phase and voltage used for testing through the training value of the optimal position of the read and write timing; based on each set of phase and voltage within the test range, use the configured test case for testing; and record the test results; wherein the test results are pass and fail; in response to the current test meeting the preset end condition, end the digital eye diagram test, and output the digital eye diagram based on all the recorded test results. This method does not require the use of an oscilloscope, which can greatly reduce the test cost, does not require hardware such as solder joints and probes, and does not require different processing for DDR and HBM, that is, it is not limited by hardware; and is not limited by the number of test channels, and multiple channels can be tested simultaneously, which can greatly improve the test efficiency. Therefore, this method can implement the test of the digital eye diagram under the condition of low cost and without hardware restrictions.

[0027] The following is a detailed description of the process of implementing the digital eye diagram test in the embodiment of the present application in conjunction with the accompanying drawings.

[0028] See also Figure 1 , Figure 1 This is a schematic diagram of the digital eye diagram test process in the embodiment of this application. The specific steps are: Step 101, obtaining a training value of an optimal position of a read / write sequence; wherein the training value includes a phase and a voltage.

[0029] Step 102: Determine the test range of the phase and voltage for testing according to the training value.

[0030] Step 103, based on each set of phases and voltages within the test range, use the configured test cases to perform testing; and record the test results; wherein the test results are pass or fail.

[0031] When this step is implemented, each set of determined voltages and phases is tested separately, and the test results are recorded.

[0032] If the test fails, or if the test succeeds and ECC (Error Checking and Correcting) occurs, the test result is recorded as failed. If the test runs successfully and no ECC occurs, the test result is recorded as passed.

[0033] Step 104 , in response to the current test satisfying a preset end condition, the digital eye diagram test is ended, and a digital eye diagram is output based on all recorded test results.

[0034] When outputting the digital eye diagram based on all the recorded test results, if it is a single-channel test, it can be directly output according to the test results. If multiple channels are tested together, the test results at the same phase voltage position will be superimposed and output.

[0035] In order to show the test situation more clearly, when the test result is failed, it can also be divided into first failure and second failure; If the test fails, the test result is recorded as the first failure; If the test runs successfully and ECC occurs, the test result is recorded as the second failure; If the test runs successfully and no ECC occurs, the test result is recorded as passed.

[0036] That is, when the test fails, or although the test runs successfully but ECC occurs, the test is also determined to be failed; whether to distinguish between these two types of failed results is set according to actual needs; if you only need to output an eye diagram that distinguishes between failed and passed test results, you can use different identifiers to distinguish between passed and failed when recording the test results. If you want to reflect the reason for failure in the eye diagram at the same time, you can record the test results through three identifiers, such as the first failure is recorded as "99", the second failure is recorded as "1", and the pass is recorded as "0". This is only one way of representation and is not limited to this representation.

[0037] For testing multiple channels together, the principle of superimposing the test results at the same phase voltage position can be: as long as the test result of a channel is "99", the test result corresponding to the position is output as 99. If the test results of a position for all channels are not 99, they are output by superimposing the values. This is only an example of eye diagram output, and there is no limitation on this in specific implementation.

[0038] In this embodiment, the test range of the phase and voltage used for testing is determined by the training value of the optimal position of the read-write timing; based on the phase and voltage within the test range, the configured test case is used for testing; and the test results are recorded; in response to the current test meeting the preset end condition, the digital eye diagram test is ended, and the digital eye diagram is output based on all the recorded test results. This method does not require the use of an oscilloscope, which can greatly reduce the test cost, does not require hardware such as solder joints and probes, and does not require different processing of DDR and HBM, that is, it is not limited by hardware; and is not limited by the number of test channels, and multiple channels can be tested simultaneously, which can greatly improve the test efficiency. Therefore, this method can realize the test of digital eye diagrams at low cost and without hardware restrictions.

[0039] In another example, between step 101 and step 102 , it is also necessary to determine whether retraining is turned on. If so, retraining is turned off and step 102 is executed; otherwise, step 102 is directly executed.

[0040] After obtaining the training value of the optimal position of the read and write timing, and before determining the test range of the phase and voltage used for testing based on the training value, the purpose of turning off the periodic training is to prevent the automatic adjustment of the phase and voltage due to temperature changes during the execution of the test case after the memory enters the normal operating mode, thereby ensuring the accuracy of the voltage and phase set for testing in the embodiment of the present application.

[0041] In the embodiment of the present application, the method for determining the test range of the phase and voltage for testing based on the training value and the condition for ending the test are provided in two implementations, but are not limited to the following two implementations: The first method: Determine a test range and a test start point, and start a full scan test from the test start point within the test range: Determine the test range of phases and voltages used for testing based on the trained values, including: Taking the training value as the center point, determining the test range and the test starting point of the phase and voltage used for the test according to the training value, the preset voltage height and the preset phase width; Based on each phase and voltage group within the test range, the test is performed separately using the configured test cases, including: Starting from the test start point, a set of phases and voltages used in each test is determined according to a preset first phase step and a first voltage step, and a configured test case is used to perform the test based on the determined set of phases and voltages; The preset end condition is that the current test is the last test corresponding to a set of phases and voltages within the test range.

[0042] Among them, starting from the test starting point, when a set of phases and voltages used in each test is determined according to the preset first phase step and first voltage step, the phases and voltages used in each test are determined by relative values.

[0043] The second method is to use the training value as the center point and spread the scanning test in all directions: Determine the test range of phases and voltages used for testing based on the trained values, including: The range corresponding to the scanning in all directions with the training value as the center point is used as the test range of the phase and voltage for the test; Based on each phase and voltage group within the test range, the test is performed separately using the configured test cases, including: Taking the training value as the test starting point, determining the phase and voltage used for each test in different test directions according to the preset second phase step and second voltage step, and performing the test using the configured test case based on the determined phase and voltage; when performing the test in each test direction, the test in the test direction is terminated when the test result is a failure; The preset end condition is that the current test is the last test in all test directions, and the test result of the current test is failure.

[0044] See also Figure 2 , Figure 2 This is a flow chart of the eye diagram test based on the test starting point in the embodiment of the present application. The specific steps are: Step 201, obtaining a training value of an optimal position of a read / write sequence; wherein the training value includes a phase and a voltage.

[0045] Step 202, taking the training value as the center point, and determining the test range and test start point of the phase and voltage used for the test according to the center point, the preset voltage height and the preset phase width.

[0046] The settings of the preset phase width and preset voltage height depend on the pressure of the test case on the channel. If the pressure is relatively small, the values ​​of the preset phase width and the preset voltage height can be set larger. If the pressure is large, the values ​​of the preset phase width and the preset voltage height can be set smaller.

[0047] The test starting point here is also a boundary point.

[0048] In the specific implementation, if the preset phase width is 64 first phase steps, a total of 1UI, and the preset voltage height is 60 first voltage steps, a total of 120mV, then the phase corresponding to the test starting point is the phase in the training value minus 32 first phase steps, and the voltage corresponding to the test starting point is the voltage in the training value minus 30 first voltage steps.

[0049] In the embodiment of the present application, a set of voltages and phases are determined by relative values. Therefore, in the specific implementation, the training value is used as the center point, and the test starting point can be determined according to the specific test requirements. For example, the position in the lower left corner of the example above is used as the test starting point, or the test point at other positions can be used as the test starting point. The specific implementation is not limited to this, and the step size of the phase and voltage can be moved to obtain the voltage and phase used for the test.

[0050] The advantage of the implementation method of determining a set of voltages and phases by taking relative values ​​is that when multiple channel eye diagrams are superimposed, the superimposed eyes will not be closed due to the difference in the eye diagrams of each channel. If the absolute values ​​of the phase and voltage are taken, it is easy to fail to obtain a true eye diagram when the eye diagram of each channel is relatively small and the sampled phase and voltage differences are too large.

[0051] If the absolute value is used, when the phase voltage ranges of the multiple channels are greatly different, the superimposed eye diagram will disappear. If the relative value is used, the center point is based on the training value. Even if the eye diagrams of each channel are different, they will always spread out from the center point. Finally, the superimposed eye diagram can reflect the worst situation of all channels.

[0052] Step 203, starting from the test starting point, determine a set of phases and voltages used for each test according to the preset first phase step and first voltage step, perform testing based on the determined set of phases and voltages using the configured test case, and record the test results.

[0053] The first phase step and the first voltage step are set according to the definition of the IP manufacturer.

[0054] Here, a set of phase and voltage refers to a set of data including a voltage and a phase.

[0055] In this step, a set of phases and voltages used for each test is determined according to the first phase step and the first voltage step. This does not mean that a first phase step and a first voltage step must be moved each time to determine a set of phases and voltages used for the test. Instead, if moved, the movement is made in units of the first phase step and the first voltage step. When moving to the next test point, it may only move one first phase step or one first voltage step.

[0056] After determining the starting point of the test, the test can be performed in sequence in a manner of keeping the voltage unchanged and increasing the phase. After all phases are traversed, a first step step voltage is added, and all phases corresponding to the latest voltage are traversed until all groups of phases and voltages determined according to the first phase step and the first voltage step within the test range are traversed.

[0057] This test method does not need to determine the test result of the current test, and the test is performed until all phase and voltage groups determined according to the first phase step and the first voltage step in the determined test range are tested.

[0058] After completing each set of voltage and phase tests, record the corresponding test results.

[0059] The test cases in the embodiments of the present application may be self-written test cases or specific test cases, such as BIST / DIAG case / model case, etc. BIST is PRBS23. DIAG is a test set for diagnosing hardware quality, such as board-level test, memory test, stress test, etc. Model test, such as Llama, etc., does not restrict the acquisition and implementation of specific test cases used for testing.

[0060] The test results recorded are pass and fail. The fail test results can be further divided into first fail and second fail; If the test fails, the test result is recorded as the first failure; If the test runs successfully and ECC occurs, the test result is recorded as the second failure; If the test runs successfully and no ECC occurs, the test result is recorded as passed.

[0061] That is, when the test fails, or although the test runs successfully but ECC occurs, the test is also determined to be failed; whether to distinguish between these two types of failed results is set according to actual needs; if you only need to output an eye diagram that distinguishes between failed and passed test results, you can use different identifiers to distinguish between passed and failed when recording the test results. If you want to reflect the reason for failure in the eye diagram at the same time, you can record the test results through three identifiers, such as the first failure is recorded as "99", the second failure is recorded as "1", and the pass is recorded as "0". This is only one way of representation and is not limited to this representation.

[0062] Step 204, in response to the current test satisfying a preset termination condition, terminate the digital eye diagram test, and output a digital eye diagram based on all recorded test results; wherein the preset termination condition is that the current test is the last set of phase and voltage corresponding tests within the test range of the phase and voltage determined for the test.

[0063] In this embodiment, the training value of the optimal position of the read-write timing, as well as the preset voltage height and the preset phase width are used to determine the test range and test starting point of the phase and voltage used for the test. Starting from the test starting point, all groups of phases and voltages within the test range are obtained in units of the preset first phase step and the first voltage step, and the configured test cases are used to perform tests based on all the determined groups of phases and voltages, and the test results are recorded; the digital eye diagram test is ended in response to the current test being the last group of voltage and phase, and the digital eye diagram is output based on all the recorded test results. This method does not require the use of an oscilloscope, can greatly reduce the test cost, does not require hardware such as solder joints and probes, and does not require different processing of DDR and HBM, that is, it is not limited by hardware; and is not limited by the number of test channels, multiple channels can be tested simultaneously, which can greatly improve the test efficiency. Therefore, this method can implement the test of the digital eye diagram at a low cost and without hardware restrictions.

[0064] In specific implementation, a single channel may be moved to obtain a digital eye diagram of a single channel, or multiple channels may be moved simultaneously to obtain a superimposed digital eye diagram; The following is a digital eye diagram obtained by using the digital eye diagram testing method provided by the embodiment of the present application in conjunction with the accompanying drawings.

[0065] Take the test of a GPU chip as an example. Under the RDQS frequency of 3200Mhz, all channels of 8 DDR chips simultaneously generate superimposed digital eye diagrams. The horizontal direction is delay, and one step is equal to 2.4ps (1 / 64UI). The vertical direction is voltage VREF, and one step is equal to 2mV (0.04%×VDDQ). The training value is the center point, and the corresponding value is 0x0.

[0066] See Figure 3 (a), which is a digital eye diagram based on the test start point and PHYODT is set to 40ohm. See Figure 3 (b), which is a digital eye diagram based on the test start point and PHYODT is set to 60ohm. In Figures 3 (a) and 3 (b), the digital eye diagram output is based on 2 step movement units for clarity.

[0067] In Figure 3 (a) and Figure 3 (b), 0 means that the test results of all channel pairs at the corresponding voltage and phase position are passed, and the superimposed result is still represented by 0. 99 means that the test results of all channels at the corresponding voltage and phase position are the first failure. The values ​​other than 0 and 99 represent the superimposed value of the test results of all channels at the voltage and phase position and the test results of all channels are not the first failure. The test results of some channels may be passed, recorded as 0, and the test results of some channels may be the second failure, recorded as 1. The superimposed test results are several, indicating how many channels have the second failure at the voltage and phase position.

[0068] It can be seen from FIG. 3 (a) and FIG. 3 (b) that when the PHYODT is increased from 40 ohm to 60 ohm, the eye width changes from 67.2 ps to 62.4 ps, and the eye height changes from 96 mV to 72 mV. It can be seen that the scheme of performing eye diagram testing based on the test starting point provided in the embodiment of the present application can test digital eye diagrams under different PHYODT conditions and obtain correct test results.

[0069] See also Figure 4 , Figure 4 This is a flow chart of starting an eye diagram test based on training values ​​in an embodiment of the present application. The specific steps are: Step 401, obtaining a training value of an optimal position of a read / write sequence; wherein the training value includes a phase and a voltage.

[0070] Step 402 : Scan the range corresponding to the training value as the center point in all directions as the test range of the phase and voltage for testing.

[0071] The test range preliminarily determined here is the allowable voltage and phase range, and the test range is narrowed by the end condition.

[0072] Step 403, using the training value as the test starting point, determining a set of phases and voltages used for each test in different test directions according to the preset second phase step and second voltage step, and performing tests based on the set of phases and voltages using the configured test cases, and recording the test results; when testing in each test direction, terminate the test in that test direction if the test result is a failure.

[0073] The second phase step and the second voltage step are set according to the definition of the IP manufacturer, where the second phase step and the second voltage are corresponding movement values ​​of the established coordinates.

[0074] Here, a set of phase and voltage refers to a set of data including a voltage and a phase.

[0075] In this step, a set of phases and voltages used for each test is determined according to the second phase step and the second voltage step. This does not mean that a second phase step and a second voltage step must be moved each time to determine a set of phases and voltages used for the test. A set of voltages and steps used for the test can be determined by moving one of the first phase step or the second voltage step in one direction.

[0076] This test method uses the training value as the center point, and based on the preset second phase step and second voltage step, the phase and voltage are moved in circles to achieve the test in each test direction. When the test result in any direction is not passed, the test in that direction is terminated, which can greatly save the number of tests and improve the test efficiency.

[0077] After completing each set of voltage and phase tests, record the corresponding test results.

[0078] The test cases in the embodiments of the present application may be self-written test cases or specific test cases, such as BIST / DIAG case / model case, etc. BIST is PRBS23. DIAG is a test set for diagnosing hardware quality, such as board-level test, memory test, stress test, etc. Model test, such as Llama, etc., does not restrict the acquisition and implementation of specific test cases used for testing.

[0079] The test results recorded are pass and fail. The fail test results can be further divided into first fail and second fail; If the test fails, the test result is recorded as the first failure; If the test runs successfully and ECC occurs, the test result is recorded as the second failure; If the test runs successfully and no ECC occurs, the test result is recorded as passed.

[0080] That is, when the test fails, or although the test runs successfully but ECC occurs, the test is also determined to be failed; whether to distinguish between these two types of failed results is set according to actual needs; if you only need to output an eye diagram that distinguishes between failed and passed test results, you can use different identifiers to distinguish between passed and failed when recording the test results. If you want to reflect the reason for failure in the eye diagram at the same time, you can record the test results through three identifiers, such as the first failure is recorded as "99", the second failure is recorded as "1", and the pass is recorded as "0". This is only one way of representation and is not limited to this representation.

[0081] Step 404, in response to the current test satisfying a preset termination condition, terminate the digital eye diagram test, and output a digital eye diagram based on all recorded test results; wherein the preset termination condition is that the current test is the last test in all test directions, and the test result of the current test is failure.

[0082] In this embodiment, the training value of the optimal position of the read and write timing is used as the center point, and the second phase step and the second voltage step are scanned in all directions to determine the phase and voltage used for the test. When the test result is not passed in any direction, the test in that direction is terminated; and when the test results in all directions are not passed, the test of the digital eye diagram is terminated, and the digital eye diagram is output based on all the recorded test results. This method does not require the use of an oscilloscope, which can greatly reduce the test cost, does not require hardware such as solder joints and probes, and does not require different processing for DDR and HBM, that is, it is not limited by hardware; and it is not limited by the number of test channels, and multiple channels can be tested simultaneously, which can greatly improve the test efficiency. Therefore, this method can realize the test of the digital eye diagram under the condition of low cost and without hardware restrictions.

[0083] In specific implementation, a single channel may be moved to obtain a digital eye diagram of a single channel, or multiple channels may be moved simultaneously to obtain a superimposed digital eye diagram; The following is a digital eye diagram obtained by using the digital eye diagram testing method provided by the embodiment of the present application in conjunction with the accompanying drawings.

[0084] Taking the test of another GPU chip as an example, at the RDQS frequency of 3200Mhz, all channels of 8 DDR chips simultaneously generate superimposed digital eye diagrams, with delay in the horizontal direction, and one step equal to 2.4ps (1 / 64UI). The vertical direction is voltage VREF, and one step equals 2mV (0.04%×VDDQ). The training value is the center point, and the corresponding value is 0x0.

[0085] See Figure 5 (a), which is a schematic diagram of a digital eye diagram based on the training value, with PHYODT set to 40ohm. See Figure 5 (b), which is a schematic diagram of a digital eye diagram based on the training value, with PHYODT set to 60ohm. In Figures 5 (a) and 5 (b), the digital eye diagrams are outputted using a 2-step moving unit as an example for clarity.

[0086] In FIG. 5( a ) and FIG. 5( b ), 0 indicates that the test results of all channel pairs at the corresponding voltage and phase position are passed, and the superimposed result is still represented by 0. 99 indicates that the test results of all channels at the corresponding voltage and phase position are the first failure. The values ​​other than 0 and 99 represent the superimposed values ​​of the test results of all channels at the voltage and phase position and the test results of all channels are not the first failure. The test results of some channels may be passed, which is recorded as 0, and the test results of some channels may be the second failure, which is recorded as 1. The superimposed test results are numerical values, indicating how many channels have the second failure at the voltage and phase position.

[0087] It can be seen from FIG. 5 (a) and FIG. 5 (b) that when the PHYODT is increased from 40 ohm to 60 ohm, the eye width changes from 72 ps to 62.4 ps, and the eye height changes from 84 mV to 64 mV. It can be seen that the scheme for starting the eye diagram test based on the training value provided in the embodiment of the present application can test the digital eye diagrams of different PHYODT conditions and obtain correct test results.

[0088] Based on the same inventive concept, the present application also provides a digital eye diagram testing device. Figure 6 , Figure 6 This is a schematic diagram of the structure of a digital eye diagram test device in an embodiment of the present application. The device includes: An acquisition unit 601 is used to acquire a training value of an optimal position of a read / write timing sequence; wherein the training value includes a phase and a voltage; A determination unit 602, configured to determine a test range of a phase and a voltage for testing according to a training value; The test unit 603 is used to perform tests respectively based on each set of phases and voltages within the test range using configured test cases; Storage unit 604, recording test results; wherein the test results are pass or fail; The output unit 605 is used to terminate the digital eye diagram test in response to the current test meeting a preset termination condition, and output the digital eye diagram based on all recorded test results.

[0089] In another embodiment, The determining unit 602 is specifically used to determine the test range of the phase and voltage for the test according to the training value, taking the training value as the center point, and determining the test range and test starting point of the phase and voltage for the test according to the training value, the preset voltage height and the preset phase width; The test unit 603 is specifically configured to determine a set of phases and voltages used for each test according to a preset first phase step and a first voltage step when performing tests respectively based on each set of phases and voltages within the test range using the configured test cases, starting from the test start point, and performing tests based on the determined set of phases and voltages using the configured test cases; The preset end condition is that the current test is the last test corresponding to a set of phases and voltages within the test range.

[0090] In another embodiment, starting from the test start point, when a set of phases and voltages used in each test is determined according to a preset first phase step and a first voltage step, the phases and voltages used in each test are determined by relative values.

[0091] In another embodiment, The determination unit 602 is specifically configured to determine the test range of the phase and voltage for the test according to the training value, and to scan the range corresponding to the training value as the test range of the phase and voltage for the test; The test unit 603 is specifically used to determine a group of phases and voltages used for each test in different test directions according to a preset second phase step and a second voltage step when testing each group of phases and voltages in the test range using the configured test cases, with the training value as the test starting point, and to perform the test using the configured test cases based on the determined group of phases and voltages; when testing in each test direction, the test in the test direction is terminated when the test result is a failure; The preset end condition is that the current test is the last test in all test directions, and the test result of the current test is failure.

[0092] In another embodiment, If the test fails, or if the test succeeds and ECC occurs, the test result is recorded as failed; If the test runs successfully and no ECC occurs, the test result is recorded as passed.

[0093] In another embodiment, the apparatus further comprises: Processing unit 606 is used to determine whether to turn on periodic training after the acquisition unit acquires the training value of the optimal position of the read and write timing. If so, turn off the periodic training and then trigger the determination unit to determine the test range of the phase and voltage used for testing according to the training value; otherwise, directly trigger the determination unit to determine the test range of the phase and voltage used for testing according to the training value.

[0094] In another embodiment, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the digital eye diagram testing method is implemented when the processor executes the program.

[0095] In another embodiment, a computer-readable storage medium is provided, on which computer instructions are stored. When the instructions are executed by a processor, a digital eye diagram testing method is implemented.

[0096] Figure 7 Schematic diagram of the physical structure of an electronic device provided by an embodiment of the present invention. Figure 7 As shown, the electronic device may include: a processor (Processor) 710, a communication interface (Communications Interface) 720, a memory (Memory) 730 and a communication bus 740, wherein the processor 710, the communication interface 720, and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call the logic instructions in the memory 730 to execute the following method: Obtaining training values ​​of the optimal position of the read and write timing; wherein the training values ​​include phase and voltage; Determine the test range of phase and voltage for testing according to the training values; Based on each set of phases and voltages within the test range, use the configured test cases to perform tests respectively; and record the test results; the test results are pass or fail; In response to the current test satisfying a preset end condition, the digital eye diagram test is ended, and a digital eye diagram is output based on all recorded test results.

[0097] In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0098] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0099] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0100] The flow chart and block diagram in the accompanying drawings of the present application show the possible architecture, function and operation of the system, method and computer program product according to the various embodiments disclosed in the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the above-mentioned module, program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the box can also occur in the order of the standards in different figures. For example, the boxes represented by two connections can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0101] Those skilled in the art will appreciate that the features described in the various embodiments and / or claims disclosed in this application may be combined and / or combined in a variety of ways, even if such combinations or combinations are not explicitly described in this application. In particular, without departing from the spirit and teachings of this application, the features described in the various embodiments and / or claims of this application may be combined and / or combined in a variety of ways, and all of these combinations and / or combinations fall within the test scope disclosed in this application.

[0102] Specific embodiments are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas, and is not used to limit the present application. For those skilled in the art, changes can be made in the specific implementation methods and application test scopes based on the ideas, spirits and principles of the present invention. Any modifications, equivalent substitutions, improvements, etc. made by them should be included in the test scope protected by this application.

Claims

1. A digital eye diagram testing method, characterized in that: The method comprises: Obtaining a training value of an optimal position of a read / write timing sequence; wherein the training value includes a phase and a voltage; Determining a test range of phase and voltage for testing according to the training values; Based on each set of phases and voltages within the test range, use the configured test cases to perform tests respectively; and record the test results; wherein the test results are pass or fail; In response to the current test satisfying a preset end condition, the digital eye diagram test is ended, and a digital eye diagram is output based on all recorded test results; Wherein, determining the test range of the phase and voltage for testing according to the training value includes: Taking the training value as the center point, determining the test range of the phase and voltage for testing according to the training value, the preset voltage height and the preset phase width; or, The range corresponding to the scanning in all directions with the training value as the center point is used as the test range of the phase and voltage for the test.

2. The method according to claim 1, characterized in that: When the training value is used as the center point, and the test range of the phase and voltage for the test is determined according to the training value, the preset voltage height and the preset phase width, the method further includes: determining a test start point; The testing is performed separately using configured test cases based on each set of phases and voltages within the test range, including: Starting from the test starting point, determining a set of phases and voltages used for each test according to a preset first phase step and a first voltage step, and performing the test using a configured test case based on the determined set of phases and voltages; The preset end condition is that the current test is the test corresponding to the last set of phases and voltages within the test range.

3. The method according to claim 2, characterized in that When determining a set of phases and voltages used for each test according to a preset first phase step and a first voltage step starting from the test starting point, the phases and voltages used for each test are determined by relative values.

4. The method according to claim 1, characterized in that: When the range corresponding to the scanning of the training value as the center point is used as the test range of the phase and voltage for testing, the testing is performed separately using the configured test cases based on each group of phases and voltages within the test range, including: Taking the training value as the test starting point, determining a set of phases and voltages used for each test in different test directions according to the preset second phase step and second voltage step, and performing the test using the configured test case based on the determined set of phases and voltages; when performing the test in each test direction, terminating the test in the test direction when the test result is a failure; The preset end condition is that the current test is the test in the last test direction among all test directions, and the test result of the current test is failure.

5. The method according to claim 1, characterized in that If the test fails, or if the test succeeds and ECC occurs, the test result is recorded as failed; If the test runs successfully and no ECC occurs, the test result is recorded as passed.

6. The method according to claim 1, characterized in that After obtaining the training value of the optimal position of the read / write timing, determining the test range of the phase and voltage for testing according to the training value; the method further comprises: Determine whether to turn on periodic training. If so, turn off the periodic training, and then determine the test range of the phase and voltage used for testing according to the training value; otherwise, directly determine the test range of the phase and voltage used for testing according to the training value.

7. A digital eye diagram testing device, characterized in that: The device comprises: An acquisition unit, used to acquire a training value of an optimal position of a read / write timing sequence; wherein the training value includes a phase and a voltage; A determination unit, configured to determine a test range of a phase and a voltage for testing according to the training value; A test unit, for performing tests respectively based on each set of phases and voltages within the test range using configured test cases; A recording unit, used to record the test results; wherein the test results are pass or fail; An output unit, configured to terminate the digital eye diagram test in response to the current test satisfying a preset termination condition, and output the digital eye diagram based on all recorded test results; Among them, the determination unit is specifically used to determine the test range of the phase and voltage for testing according to the training value, with the training value as the center point, and determine the test range of the phase and voltage for testing according to the training value, a preset voltage height and a preset phase width; or, scan the range corresponding to the training value as the center point in all directions as the test range of the phase and voltage for testing.

8. The device according to claim 7, characterized in that The device further comprises: A processing unit is used to determine whether to turn on periodic training after the acquisition unit acquires the training value of the optimal position of the read and write timing. If so, turn off the periodic training and then trigger the determination unit to determine the test range of the phase and voltage used for testing according to the training value; otherwise, directly trigger the determination unit to determine the test range of the phase and voltage used for testing according to the training value.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 6 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method described in any one of claims 1 to 6 is implemented.

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