Control circuit of voltage converter

Abstract

The embodiment of the invention provides a control circuit of a voltage converter. The control circuit comprises a detection module, a control module and a driving module, the detection module determines a load voltage detection signal according to an error adjustment voltage signal and a slope compensation current signal, and when the load voltage detection signal meets a first preset condition, a light load mode switching signal is generated; the control module determines an under-voltage signal according to a reference voltage and a feedback voltage of the voltage converter, determines a fixed-frequency pulse signal according to an input voltage and an output voltage of the voltage converter, and provides the under-voltage signal and the fixed-frequency pulse signal for the driving module under the action of the light-load mode switching signal. And generating a first upper tube control signal and a first lower tube control signal according to the under-voltage signal and the fixed-frequency pulse signal. The control circuit can ensure the stability of the voltage converter in high-frequency small duty ratio application in a light load mode, reduce the ripple of the output voltage, and reduce the area of the voltage converter.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a control circuit of a voltage converter. Background Art

[0002] The energy loss and efficiency of the switching power supply at light load are mainly affected by the quiescent current and switching loss. In order to improve the efficiency of light load, a separate variable frequency controlled light load mode is generally designed to reduce the switching frequency, so as to reduce the switching loss when the quiescent current is constant. In high frequency and small duty cycle applications, the minimum on time of the constant frequency peak current mode (PCM) architecture BUCK is affected by the upper tube turn-on blanking time and comparator delay and cannot be small enough, resulting in poor stability of the BUCK in light load mode. It is easy to have a phenomenon of continuous ripple for several times and then no ripple for a long time, resulting in large ripple in the output voltage, which in turn causes the output voltage of the error amplifier to fluctuate, leading to further deterioration of the stability and output ripple of the voltage converter.

[0003] In the prior art, the ripple interval can be increased by reducing the switching frequency and increasing the inductance, giving the internal control node signal sufficient time to establish, which can reduce the sensitivity of the energy delivered to the output end to the minimum on-time in light-load mode to maintain the balance between output ripple and efficiency. However, the above method cannot meet the needs of high-frequency and small duty cycle applications. Summary of the invention

[0004] The present disclosure provides a control circuit of a voltage converter, which can ensure the stability of the voltage converter in a light-load mode of high-frequency and small-duty-cycle applications, reduce the ripple of the output voltage, and also reduce the area of ​​the voltage converter.

[0005] In a first aspect, the present disclosure provides a control circuit of a voltage converter, comprising a detection module, a control module and a driving module.

[0006] The detection module is configured to determine a load voltage detection signal based on an error adjustment voltage signal and a slope compensation current signal, wherein the error adjustment voltage signal depends on the inductor sampling current signal and the slope compensation current signal, and different duty cycles of the voltage converter correspond to different slope compensation current signals; and generate a light load mode switching signal when the load voltage detection signal meets a first preset condition to enable the voltage converter to enter a light load mode.

[0007] The control module is configured to determine an undervoltage signal based on a reference voltage and a feedback voltage of a voltage converter, and to determine a constant-frequency pulse signal based on an input voltage and an output voltage of the voltage converter; and to provide the undervoltage signal and the constant-frequency pulse signal to the driving module under the action of the light-load mode switching signal.

[0008] The driving module is configured to generate a first upper tube control signal and a first lower tube control signal according to the undervoltage signal and the fixed-frequency pulse signal in the light-load mode.

[0009] In some embodiments of the present disclosure, the detection module is further configured to generate a normal mode switching signal when the load voltage detection signal satisfies a second preset condition, so that the voltage converter exits the light load mode and enters the normal mode.

[0010] The control module is also configured to determine an inductor sampling voltage signal according to the slope compensation current signal and the inductor sampling current signal, and to determine a pulse width modulation signal according to the error adjustment voltage signal and the inductor sampling voltage signal; and to provide the pulse width modulation signal to the driving module under the action of the normal mode switching signal.

[0011] The driving module is further configured to generate a second upper tube control signal and a second lower tube control signal according to the pulse width modulation signal and the clock signal in the normal mode.

[0012] In some embodiments of the present disclosure, the detection module includes a signal processing unit and a detection unit, the input end of the signal processing unit is connected to the error adjustment voltage signal, the output end of the signal processing unit is connected to the first input end of the detection unit, the second input end of the detection unit is connected to the first voltage threshold, the third input end of the detection unit is connected to the second voltage threshold, and the output end of the detection unit is connected to the enable end of the detection unit and the control end of the control module; wherein the second voltage threshold is greater than the first voltage threshold.

[0013] The signal processing unit is configured to convert the error adjustment voltage signal into an error amplified current signal, remove the slope compensation current signal from the error amplified current signal, and convert the error amplified current signal after removal into a voltage signal to obtain the load voltage detection signal.

[0014] The detection unit is configured to, in the normal mode, generate the light load mode switching signal when the voltage of the load voltage detection signal is less than the first voltage threshold; in the light load mode, generate the normal mode switching signal when the voltage of the load voltage detection signal is greater than the second voltage threshold.

[0015] In some embodiments of the present disclosure, the signal processing unit includes an operational amplifier, a transistor, a current mirror structure, a first resistor, a second resistor and a current source, the non-phase input terminal of the operational amplifier is connected to the error adjustment voltage signal, the inverting input terminal of the operational amplifier is connected to the first end of the first resistor and the first end of the transistor, the output terminal of the operational amplifier is connected to the control terminal of the transistor, and the second end of the first resistor is grounded.

[0016] The second end of the transistor is connected to the first output end of the current mirror structure, the second output end of the current mirror structure is connected to the first end of the second resistor, the input end of the current source and the first input end of the detection unit, the second end of the second resistor and the output end of the current source are grounded; wherein the resistance values ​​of the first resistor and the second resistor are equal.

[0017] The current source is configured to provide the slope compensation current signal.

[0018] In some embodiments of the present disclosure, the detection unit includes a hysteresis comparator, a delay device, a frequency detector and a first logic unit, the first input end of the hysteresis comparator is connected to the output end of the signal processing unit, the second input end of the hysteresis comparator is connected to the first voltage threshold, the third input end of the hysteresis comparator is connected to the second voltage threshold, the output end of the hysteresis comparator is connected to the input end of the delay device, the output end of the delay device is connected to the first input end of the first logic unit, the enable end of the frequency detector is connected to the output end of the first logic unit and the control end of the control module, and the output end of the frequency detector is connected to the second input end of the first logic unit.

[0019] The hysteresis comparator is configured to, in the normal mode, generate a first comparison signal when the voltage of the load voltage detection signal is less than the first voltage threshold; and in the light load mode, generate a second comparison signal when the voltage of the load voltage detection signal is greater than the second voltage threshold.

[0020] The delay device is configured to, in the normal mode, delay the first comparison signal to obtain a first comparison delay signal; and in the light load mode, delay the second comparison signal to obtain a second comparison delay signal.

[0021] The frequency detector is configured to determine a frequency detection signal according to whether the switching frequency of the voltage converter reaches the frequency of the clock signal under the action of the light-load mode switching signal.

[0022] The first logic unit is configured to, in the light load mode, generate the normal mode switching signal according to the frequency detection signal and the second comparison delay signal; in the normal mode, generate the light load mode switching signal according to the first comparison delay signal.

[0023] In some embodiments of the present disclosure, the signal processing unit also includes a low-pass filter, an input end of the low-pass filter is connected to the second output end of the current mirror structure, the first end of the second resistor and the input end of the current source, and the output end of the low-pass filter is connected to the first input end of the detection unit.

[0024] In some embodiments of the present disclosure, the control module includes a first comparator, a timer, a selector and an AND gate, the inverting input of the first comparator is connected to the feedback voltage, the non-inverting input of the first comparator is connected to the reference voltage, the output of the first comparator is connected to the first input of the AND gate, the second input of the AND gate is connected to the output of the detection module and the control end of the selector, the output of the AND gate is connected to the first input of the driving module, the first input of the timer is connected to the input voltage, the second input of the timer is connected to the output voltage, the output of the timer is connected to the first input of the selector, and the output of the selector is connected to the second input of the driving module.

[0025] The timer is configured to, when the upper tube is turned on, determine the upper tube on-time according to the input voltage and the output voltage, and generate the fixed-frequency pulse signal according to the upper tube on-time. The selector is configured to, under the action of the light-load mode switching signal, select and output the fixed-frequency pulse signal.

[0026] In some embodiments of the present disclosure, the control module also includes an error amplifier, a second comparator, a third resistor, a fourth resistor, a first capacitor, a second capacitor and an adder, the inverting input of the error amplifier is connected to the feedback voltage, the non-inverting input of the error amplifier is connected to the reference voltage, the output of the error amplifier is connected to the first plate of the first capacitor, the first plate of the second capacitor and the inverting input of the second comparator, the non-inverting input of the second comparator is connected to the first end of the third resistor and the output of the adder, the first input of the adder is connected to the slope compensation current signal, the second input of the adder is connected to the inductor sampling current signal, the output of the second comparator is connected to the second input of the selector, the second plate of the second capacitor is connected to the first end of the fourth resistor, the second end of the fourth resistor, the second end of the third resistor and the second plate of the first capacitor are grounded.

[0027] The second comparator is configured to compare the error adjustment voltage signal with the inductor sampling voltage signal to obtain the pulse width modulation signal. The selector is also configured to select and output the pulse width modulation signal under the action of the normal mode switching signal.

[0028] In some embodiments of the present disclosure, the control module also includes an OR gate and a maximum duration detection unit, the output end of the maximum duration detection unit is connected to the first input end of the OR gate, the output end of the timer is connected to the second input end of the OR gate, and the output end of the OR gate is connected to the first input end of the selector.

[0029] The maximum duration detection unit is configured to output a maximum duration detection signal to turn off the upper tube when the on-time of the upper tube reaches the maximum on-time in the light load mode.

[0030] In some embodiments of the present disclosure, the driving module includes a frequency limiting unit and a second logic unit, the first input end of the frequency limiting unit is connected to the clock signal, the second input end of the frequency limiting unit is connected to the first output end of the control module, the output end of the frequency limiting unit is connected to the first input end of the second logic unit, and the second input end of the second logic unit is connected to the second output end of the control module.

[0031] The second logic unit includes a first NOR gate, a second NOR gate, a first inverter and a second inverter, wherein the first input end of the first NOR gate is connected to the output end of the frequency limiting unit, the second input end of the first NOR gate is connected to the output end of the second NOR gate and the input end of the first inverter, the output end of the first NOR gate is connected to the first input end of the second NOR gate, the second input end of the second NOR gate is connected to the second output end of the control module, the output end of the first inverter is connected to the input end of the second inverter and the control end of the lower tube, and the output end of the second inverter is connected to the control end of the upper tube.

[0032] The frequency limiting unit is configured to, in the light load mode, output the undervoltage signal and limit the switching frequency of the voltage converter to be less than or equal to the frequency of the clock signal; and in the normal mode, output the clock signal.

[0033] In a second aspect, the present disclosure provides a switching power supply, comprising a voltage converter and a control circuit of any voltage converter provided in the first aspect.

[0034] In a third aspect, the present disclosure provides a chip, comprising a control circuit of any voltage converter provided in the first aspect.

[0035] The technical solution disclosed in the present invention provides a control circuit of a voltage converter, including a detection module, a control module and a driving module. The detection module can determine a load voltage detection signal based on an error adjustment voltage signal and a slope compensation current signal, wherein the error adjustment voltage signal depends on an inductor sampling current signal and a slope compensation current signal, different duty cycles of the voltage converter correspond to different slope compensation current signals, and when the load voltage detection signal meets a first preset condition, a light load mode switching signal is generated to enable the voltage converter to enter a light load mode. The control module can determine an undervoltage signal based on a reference voltage and a feedback voltage of the voltage converter, and determine a fixed-frequency pulse signal based on an input voltage and an output voltage of the voltage converter, and under the action of the light load mode switching signal, a fixed-frequency pulse signal is sent to the driver. The module provides an undervoltage signal and a fixed-frequency pulse signal. The driving module can generate a first upper tube control signal and a first lower tube control signal according to the undervoltage signal and the fixed-frequency pulse signal in the light-load mode. In this way, in the light-load mode, the undervoltage signal of the output voltage controls the opening of the upper tube. The opening time of the upper tube depends on the period of the fixed-frequency pulse signal, and the period of the fixed-frequency pulse signal is fixed and is not affected by other signals. Therefore, the minimum opening time of the upper tube can be small enough to ensure the stability of the voltage converter in different duty cycles and switching frequency applications in the light-load mode, thereby ensuring the stability of the voltage converter in the light-load mode in high-frequency and small duty cycle applications, reducing the ripple of the output voltage. In addition, since there is no need to use a large inductor, the area of ​​the voltage converter can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0037] Figure 1 A circuit diagram of a voltage converter provided by an embodiment of the present disclosure;

[0038] Figure 2 A schematic diagram of a control circuit of a voltage converter is provided in accordance with an embodiment of the present disclosure;

[0039] Figure 3 A circuit diagram of a detection module provided in an embodiment of the present disclosure;

[0040] Figure 4 A schematic diagram of waveforms of various signals in the detection module provided in an embodiment of the present disclosure;

[0041] Figure 5 A circuit diagram of a control module provided in an embodiment of the present disclosure;

[0042] Figure 6A timing diagram of a light load mode in steady state provided by an embodiment of the present disclosure;

[0043] Figure 7 A timing diagram of a normal mode steady state provided by an embodiment of the present disclosure;

[0044] Figure 8 A circuit diagram of another control module provided in an embodiment of the present disclosure;

[0045] Fig. 9 A circuit diagram of a driving module provided in an embodiment of the present disclosure;

[0046] Fig.10 A timing diagram before and after mode switching provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise clearly defined herein. As used herein, "electrically connected" can be directly connected or indirectly connected through at least one intermediate element, as long as the circuit is connected, and can also be internal communication between two elements.

[0049] Reference to "embodiments" in this disclosure means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0050] In addition, the terms "first", "second", etc. in the specification and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0051] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0052] Figure 1 A circuit diagram of a voltage converter provided by an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the voltage converter may be a BUCK converter, which includes an upper tube Hs, a lower tube Ls, an inductor L, a capacitor C and a load I Load .

[0053] The first end of the upper tube Hs is connected to the input end of the voltage converter, the second end of the upper tube Hs is connected to the first end of the lower tube Ls and the first end of the inductor L, the control end of the upper tube Hs is connected to the upper tube control signal Hsdr, the second end of the lower tube Ls is grounded, and the control end of the lower tube Ls is connected to the lower tube control signal Lsdr. The second end of the inductor L is connected to the first plate of the capacitor C and the load I Load The input terminal and the output terminal of the voltage converter, the second plate of the capacitor C and the load I Load The output terminal is grounded.

[0054] The input end of the voltage converter receives the input voltage Vin, and steps down the input voltage Vin to obtain the output voltage Vout, and outputs the output voltage Vout to the load I through the output end of the voltage converter. Load .

[0055] When the upper tube control signal Hsdr is a high level signal, the upper tube Hs is turned on; when the upper tube control signal Hsdr is a low level signal, the upper tube Hs is turned off; when the lower tube control signal Lsdr is a high level signal, the lower tube Ls is turned on; when the lower tube control signal Lsdr is a low level signal, the lower tube Ls is turned off.

[0056] In the BUCK converter, when the upper tube control signal Hsdr is a high level signal, the lower tube control signal Lsdr is a low level signal, and when the upper tube control signal Hsdr is a low level signal, the lower tube control signal Lsdr is a high level signal. That is to say, at the same time, only one of the upper tube Hs and the lower tube Ls can be turned on.

[0057] The energy loss and efficiency of the voltage converter at light load are mainly affected by the quiescent current and switching loss. In order to improve the efficiency at light load, a separate variable frequency controlled light load mode is generally designed to reduce the switching frequency to reduce the switching loss when the quiescent current is constant.

[0058] In high-frequency and low-duty-cycle applications, the minimum on-time T of the voltage converter of the PCM architecture is ON_MINAffected by the blanking time of the upper tube and the delay of the comparator, it cannot be small enough, resulting in poor stability of the voltage converter in light load mode. At this time, it is easy to have a phenomenon of continuous ripples for several times and then no ripples for a long time, resulting in large ripples in the output voltage Vout, causing the output voltage of the error amplifier to fluctuate, resulting in further deterioration of the stability and output ripple of the voltage converter.

[0059] In order to solve the above problems in the prior art, the switching frequency can be reduced and the inductance can be increased to increase the ripple interval, giving the internal control node signal sufficient establishment time, which can reduce the sensitivity of the energy delivered to the output end to the minimum on-time in light load mode to maintain the balance between output ripple and efficiency. However, this method cannot meet the needs of high-frequency and small duty cycle applications, and will also increase the area of ​​the voltage converter.

[0060] In view of the above technical problems, the present disclosure provides a control circuit of a voltage converter, including a detection module, a control module and a driving module. The detection module can determine a load voltage detection signal according to an error adjustment voltage signal and a slope compensation current signal, wherein the error adjustment voltage signal depends on the inductor sampling current signal and the slope compensation current signal, different duty cycles of the voltage converter correspond to different slope compensation current signals, and when the load voltage detection signal meets a first preset condition, a light load mode switching signal is generated to enable the voltage converter to enter a light load mode. The control module can determine an undervoltage signal according to a reference voltage and a feedback voltage of the voltage converter, and determine a fixed-frequency pulse signal according to the input voltage and the output voltage of the voltage converter. Under the action of the light load mode switching signal, a light load mode switching signal is generated. The driving module provides an undervoltage signal and a fixed-frequency pulse signal. The driving module can generate a first upper tube control signal and a first lower tube control signal according to the undervoltage signal and the fixed-frequency pulse signal in the light-load mode. In this way, in the light-load mode, the undervoltage signal of the output voltage controls the opening of the upper tube. The opening time of the upper tube depends on the period of the fixed-frequency pulse signal, and the period of the fixed-frequency pulse signal is fixed and is not affected by other signals. Therefore, the minimum opening time of the upper tube can be small enough to ensure the stability of the voltage converter in different duty cycles and switching frequency applications in the light-load mode, thereby ensuring the stability of the voltage converter in the light-load mode in high-frequency and small duty cycle applications, reducing the ripple of the output voltage. In addition, since there is no need to use a large inductor, the area of ​​the voltage converter can be reduced.

[0061] Figure 2 A schematic diagram of a control circuit of a voltage converter is provided in an embodiment of the present disclosure. Figure 2 As shown, the control circuit 100 includes: a detection module 110 , a control module 120 and a driving module 130 .

[0062] Combination Figure 1 and Figure 2As shown, the first output end of the driving module 130 is connected to the control end of the upper tube Hs to output the upper tube control signal Hsdr to the upper tube Hs, and the second output end of the driving module 130 is connected to the control end of the lower tube Ls to output the lower tube control signal Hsdr to the lower tube Ls.

[0063] like Figure 2 As shown, the input end of the detection module 110 is connected to the error adjustment voltage signal EAO, the output end of the detection module 110 is connected to the control end of the control module 120, the first input end of the control module 120 is connected to the reference voltage Vref, the second input end of the control module 120 is connected to the feedback voltage Vfb of the voltage converter, the third input end of the control module 120 is connected to the input end of the voltage converter to receive the input voltage Vin, the fourth input end of the control module 120 is connected to the output end of the voltage converter to receive the output voltage Vout, the first output end of the control module 120 is connected to the first input end of the driving module 130, the second output end of the control module 120 is connected to the second input end of the driving module 130, and the third input end of the driving module 130 is connected to the clock signal CLK.

[0064] The detection module 110 is configured to determine the load voltage detection signal VLoad according to the error adjustment voltage signal EAO and the slope compensation current signal Islope, wherein the error adjustment voltage signal EAO depends on the inductor sampling current signal Isense_L and the slope compensation current signal Islope, and different duty ratios of the voltage converter correspond to different slope compensation current signals Islope. When the load voltage detection signal VLoad meets the first preset condition, a light load mode switching signal is generated to enable the voltage converter to enter the light load mode.

[0065] The control module 120 is configured to determine the undervoltage signal FBUV according to the reference voltage Vref and the feedback voltage Vfb, determine the fixed-frequency pulse signal on_timer according to the input voltage Vin and the output voltage Vout of the voltage converter, and provide the undervoltage signal FBUV and the fixed-frequency pulse signal on_timer to the driving module 130 under the action of the light-load mode switching signal. The driving module 130 is configured to generate the first upper tube control signal Hsdr1 and the first lower tube control signal Lsdr1 according to the undervoltage signal FBUV and the fixed-frequency pulse signal on_timer in the light-load mode.

[0066] For example, Figure 3 A circuit diagram of a detection module provided in an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the detection module 110 includes a signal processing unit 111 and a detection unit 112. Figure 2 and Figure 3As shown, the input end of the signal processing unit 111 is connected to the error adjustment voltage signal EAO, the output end of the signal processing unit 111 is connected to the first input end of the detection unit 112, the second input end of the detection unit 112 is connected to the first voltage threshold VL, and the output end of the detection unit 112 is connected to the enable end of the detection unit 112 and the control end of the control module 120.

[0067] In the PCM architecture, the potential of the error adjustment voltage signal EAO in steady state is determined by the peak value of the inductor current and the slope component under different duty cycles of the voltage converter. It can be understood that the error adjustment voltage signal EAO depends on the inductor sampling current signal Isense_L and the slope compensation current signal Islope, and different duty cycles of the voltage converter correspond to different slope compensation current signals Islope. In addition to the slight influence of the inductor current ripple, the peak value of the inductor current can be used to directly characterize the current load size. Therefore, the slope compensation introduced under different duty cycles in the error adjustment voltage signal EAO is removed, that is, the voltage corresponding to the slope compensation current signal Islope introduced under different duty cycles in the error adjustment voltage signal EAO is removed, and a voltage signal that is almost only affected by the load can be obtained, that is, the load voltage detection signal Vload.

[0068] Continue to see Figure 3 The signal processing unit 111 includes an operational amplifier OP, a first transistor M1, a second transistor M2, a third transistor M3, a first resistor R1, a second resistor R2 and a current source IB, wherein the resistance values ​​of the first resistor R1 and the second resistor R2 are equal, and are equal to the resistance value of the resistor that affects the inductor current sampling coefficient.

[0069] The non-inverting input terminal of the operational amplifier OP is connected to the error adjustment voltage signal EAO, the inverting input terminal of the operational amplifier OP is connected to the first end of the first resistor R1 and the first end of the first transistor M1, the output terminal of the operational amplifier OP is connected to the control end of the first transistor M1, and the second end of the first resistor R1 is grounded.

[0070] The first end of the second transistor M2 and the first end of the third transistor M3 are connected to the power supply voltage Vcc, and the control end of the second transistor M2 is connected to the second end of the second transistor M2 and the control end of the third transistor M3, so the second transistor M2 and the third transistor M3 form a current mirror structure. Among them, the first output end of the current mirror structure, that is, the second end of the second transistor M2, is connected to the second end of the first transistor M1, the second output end of the current mirror structure, that is, the second end of the third transistor M3, is connected to the first end of the second resistor R2, the input end of the current source IB and the first input end of the detection unit 112, and the second end of the second resistor R2 and the output end of the current source IB are grounded.

[0071] Specifically, the first transistor M1 is an N-type metal oxide semiconductor field effect transistor (NMOS), and the second transistor M2 and the third transistor M3 are PMOS. The gate of the first transistor M1 is connected to the output end of the operational amplifier OP, the source of the first transistor M1 is connected to the first end of the first resistor R1, the drain of the first transistor M1 is connected to the drain of the second transistor M2, the gate of the second transistor M2 and the gate of the third transistor M3, the source of the second transistor M2 and the source of the third transistor M3 are connected to the power supply voltage Vcc, and the drain of the third transistor M3 is connected to the first end of the second resistor R2.

[0072] After the operational amplifier OP amplifies the error adjustment voltage signal EAO, it is output to the first transistor M1 as the gate voltage of the first transistor M1 to turn on the first transistor M1. The first transistor M1 can convert the error adjustment voltage signal EAO into a corresponding current signal, and the larger the error adjustment voltage signal EAO is, the larger the current flowing through the first transistor M1 is.

[0073] The first resistor R1 can adjust the magnitude of the current flowing through the first transistor M1. By setting the first resistor R1 to be equal to the resistance value of the resistor that affects the inductor current sampling coefficient, the error adjustment voltage signal EAO can be converted into an error amplified current signal in cooperation with the first transistor M1, that is, the current signal flowing through the first transistor M1 is an error amplified current signal. In other words, the current signal flowing through the second transistor M2 is an error amplified current signal. Since the second transistor M2 and the third transistor M3 form a current mirror structure, the third transistor M3 can mirror the error amplified current signal and output it.

[0074] Since the current source IB can provide the slope compensation current signal Islope, the current source IB and the second resistor R2 are connected in parallel between the drain of the third transistor M3 and the ground. Therefore, the current flowing through the second resistor R2 is the error amplified current signal minus the slope compensation current signal Islope, and the slope compensation current signal Islope can be eliminated from the error amplified current signal.

[0075] The resistance of the second resistor R2 is set to be equal to the resistance of the first resistor R1, and the voltage of the second resistor R2 is EAO-Vslope, wherein Vslope is the voltage of the slope compensation current signal Islope, that is, the load voltage detection signal VLoad=EAO-Vslope.

[0076] In this way, the signal processing unit 111 can convert the error adjustment voltage signal EAO into an error amplified current signal, remove the slope compensation current signal Islope from the error amplified current signal, and convert the removed error amplified current signal into a voltage signal to obtain a load voltage detection signal VLoad.

[0077] Continue to see Figure 3 The detection unit 112 includes a hysteresis comparator HCMP, a delay device Delay, a frequency detector 1121 and a first logic unit 1122. The first input end of the hysteresis comparator HCMP is connected to the output end of the signal processing unit 111, the second input end of the hysteresis comparator HCMP is connected to the first voltage threshold VL, the output end of the hysteresis comparator HCMP is connected to the input end of the delay device Delay, and the output end of the delay device Delay is connected to the first input end of the first logic unit 1122. The enable end of the frequency detector 1121 is connected to the output end of the first logic unit 1122 and the control end of the control module 120, and the output end of the frequency detector 1121 is connected to the second input end of the first logic unit 1122.

[0078] Exemplarily, the first voltage threshold VL is a light load threshold set according to the inductor current sampling coefficient and the voltage converter product definition. The hysteresis comparator HCMP can compare the voltage of the load voltage detection signal VLoad with the first voltage threshold VL, and output a corresponding comparison signal. The comparison signal includes a first comparison signal and a second comparison signal, for example, the first comparison signal is a high level signal, and the second comparison signal is a low level signal.

[0079] The delay device Delay can perform delay processing on the comparison signal to obtain a comparison delay signal Light_Load, wherein the comparison delay signal Light_Load includes a first comparison delay signal and a second comparison delay signal. For example, the first comparison delay signal is a high level signal, and the second comparison delay signal is a low level signal.

[0080] The first logic unit 1122 can generate a mode switching signal Mode_Detec according to the comparison delay signal Light_Load, wherein the mode switching signal Mode_Detec includes a light load mode switching signal and a normal mode switching signal, for example, the light load mode switching signal is a high level signal, and the normal mode switching signal is a low level signal.

[0081] Figure 4 A waveform diagram of each signal in the detection module provided in the embodiment of the present disclosure is shown in FIG. Figure 4 As shown, in normal mode, when the load I LoadWhen the load voltage detection signal VLoad decreases, the voltage of the load voltage detection signal VLoad decreases. The hysteresis comparator HCMP compares the voltage of the load voltage detection signal VLoad with the first voltage threshold VL. When the voltage of the load voltage detection signal VLoad is greater than or equal to the first voltage threshold VL, that is, the load voltage detection signal VLoad does not meet the first preset condition, the hysteresis comparator HCMP maintains the second comparison signal, that is, maintains a low level signal.

[0082] At this time, the comparison delay signal Light_Load maintains the second comparison delay signal, ie, maintains a low level signal, and the mode switching signal Mode_Detec maintains the normal mode switching signal, ie, maintains a low level signal.

[0083] With load I Load The voltage of the load voltage detection signal VLoad continues to decrease, and the hysteresis comparator HCMP continues to output the second comparison signal until the voltage of the load voltage detection signal VLoad is less than the first voltage threshold VL, the load voltage detection signal VLoad meets the first preset condition, and the hysteresis comparator HCMP generates a first comparison signal, then the comparison signal jumps from the second comparison signal to the first comparison signal, that is, from a low level signal to a high level signal.

[0084] At this time, the delay device Delay delays the first comparison signal to obtain a first comparison delay signal, and the comparison delay signal Light_Load jumps from the second comparison delay signal to the first comparison delay signal, that is, jumps from a low level signal to a high level signal. The first logic unit 1122 generates a light load mode switching signal according to the first comparison delay signal, and the mode switching signal Mode_Detec jumps from a normal mode switching signal to a light load mode switching signal, that is, jumps from a low level signal to a high level signal, and the voltage converter switches from the normal mode to the light load mode.

[0085] Thus, in the normal mode, when the voltage of the load voltage detection signal VLoad is less than the first voltage threshold VL, the detection unit 112 generates a light-load mode switching signal.

[0086] Figure 5 A circuit diagram of a control module provided by an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the control module 120 includes a first comparator CMP1 , a timer Timer, a selector MUX and a first AND gate AND1 .

[0087] Combination Figure 2 and Figure 5As shown, the inverting input terminal of the first comparator CMP1 is connected to the feedback voltage Vfb, the non-inverting input terminal of the first comparator CMP1 is connected to the reference voltage Vref, the output terminal of the first comparator CMP1 is connected to the first input terminal of the first AND gate AND1, the second input terminal of the first AND gate AND1 is connected to the output terminal of the detection module 110 and the control terminal of the selector MUX, and the output terminal of the first AND gate AND1 is connected to the first input terminal of the driving module 130. The first input terminal of the timer Timer is connected to the input voltage Vin, the second input terminal of the timer Timer is connected to the output voltage Vout, the output terminal of the timer Timer is connected to the first input terminal of the selector MUX, and the output terminal of the selector MUX is connected to the second input terminal of the driving module 130.

[0088] Exemplarily, the first comparator CMP1 can compare the feedback voltage Vfb and the reference voltage Vref to obtain the undervoltage signal FBUV, wherein the undervoltage signal FBUV includes a high level signal and a low level signal. For example, when the feedback voltage Vfb is less than the reference voltage Vref, the undervoltage signal FBUV is a high level signal, and when the feedback voltage Vfb is greater than or equal to the reference voltage Vref, the undervoltage signal FBUV is a low level signal.

[0089] The first AND gate AND1 can perform an AND operation on the undervoltage signal FBUV and the mode switching signal Mode_Detec. In the light load mode, the mode switching signal Mode_Detec is a light load mode switching signal, that is, a high level signal. At this time, the AND operation result of the undervoltage signal FBUV and the mode switching signal Mode_Detec is the undervoltage signal FBUV, and the first AND gate AND1 provides the undervoltage signal FBUV to the driving module 130.

[0090] When the upper tube Hs is turned on, the timer Timer can determine the upper tube turn-on time T according to the input voltage Vin and the output voltage Vout. ON , and according to the upper tube opening time T ON Generate a fixed frequency pulse signal on_timer.

[0091] Under the action of the light load mode switching signal, the selector MUX turns on the first input terminal and the output terminal of the selector MUX, and the selector MUX selects to output the fixed frequency pulse signal on_timer. Then, in the light load mode, the selector MUX can provide the fixed frequency pulse signal on_timer to the driving module 130.

[0092] Exemplarily, in the light load mode, the upper tube control signal Hsdr generated by the driving module 130 is the first upper tube control signal Hsdr1, and the lower tube control signal Lsdr generated by the driving module 130 is the first lower tube control signal Lsdr1. The first upper tube control signal Hsdr1 includes a first upper tube on signal and a first upper tube off signal, and the first lower tube control signal Lsdr1 includes a first lower tube on signal and a first lower tube off signal, for example, the first upper tube on signal and the first lower tube off signal are high level signals, and the first upper tube off signal and the first lower tube on signal are low level signals.

[0093] Figure 6 The timing diagram of the light load mode steady state provided by the embodiment of the present disclosure is as follows: Figure 6 As shown, in light load mode, after the output voltage Vout is lower than the set value, the feedback voltage Vfb is lower than the reference voltage Vref, the undervoltage signal FBUV is a high-level signal, and the driving module 130 generates a first upper tube start signal and a first lower tube shutdown signal at the rising edge of the undervoltage signal FBUV.

[0094] After the upper tube Hs is turned on, when the driving module 130 receives the first fixed-frequency pulse signal on_timer, it generates a first upper tube shutdown signal and a first lower tube start signal until the undervoltage signal FBUV jumps to a high level signal again, thereby generating a cycle of the first upper tube control signal Hsdr1 and the first lower tube control signal Lsdr1.

[0095] In summary, in light load mode, the undervoltage signal FBUV of the output voltage Vout controls the opening of the upper tube Hs, and the opening time of the upper tube depends on the period of the fixed-frequency pulse signal on_timer. Since the period of the fixed-frequency pulse signal on_timer is fixed and is not affected by other signals, the minimum opening time of the upper tube can be small enough to ensure the stability of the voltage converter in light load mode in applications with different duty cycles and switching frequencies, thereby ensuring the stability of the voltage converter in light load mode in high-frequency and small duty cycle applications, and reducing the ripple of the output voltage. In addition, since there is no need to use a large inductor, the area of ​​the voltage converter can be reduced.

[0096] In some embodiments, see Figure 3 The signal processing unit 121 also includes a low-pass filter LFP, an input end of the low-pass filter LFP is connected to the second output end of the current mirror structure, the first end of the second resistor R2 and the input end of the current source IB, and an output end of the low-pass filter LFP is connected to the first input end of the detection unit 122.

[0097] For example, Figure 3As shown, the input end of the low-pass filter LFP is connected to the drain of the third transistor M3, the first end of the second resistor R2 and the input end of the current source IB. The low-pass filter LFP can perform low-pass filtering on the voltage of the second resistor R2 to reduce the voltage ripple of the second resistor R2, thereby obtaining a load voltage detection signal VLoad that directly represents the load size.

[0098] In the embodiment of the present disclosure, by adding a low-pass filter LFP between the first end of the second resistor R2 and the first input end of the detection unit 122, the voltage ripple of the second resistor R2 can be reduced, thereby reducing the ripple of the load voltage detection signal VLoad, thereby improving the stability of the voltage converter in the light load mode of high-frequency and small duty cycle applications.

[0099] In some embodiments, the detection module 110 is further configured to generate a normal mode switching signal when the load voltage detection signal VLoad satisfies a second preset condition, so as to enable the voltage converter to exit the light load mode and enter the normal mode.

[0100] The control module 120 is also configured to determine the inductor sampling voltage signal according to the slope compensation current signal Islope and the inductor sampling current signal Isense_L, determine the pulse width modulation signal PWM according to the error adjustment voltage signal EAO and the inductor sampling voltage signal, and provide the pulse width modulation signal PWM to the driving module 130 under the action of the normal mode switching signal.

[0101] The driving module 130 is further configured to generate a second upper tube control signal Hsdr2 and a second lower tube control signal Lsdr2 according to the pulse width modulation signal PWM and the clock signal CLK in the normal mode.

[0102] Exemplarily, the second voltage threshold VH is another light-load threshold set according to the inductor current sampling coefficient and the voltage converter product definition, and the second voltage threshold VH is greater than the first voltage threshold VL.

[0103] Continue to see Figure 3 , the third input terminal of the detection unit 112 is connected to the second voltage threshold VH, that is, the third input terminal of the hysteresis comparator HCMP is connected to the second voltage threshold VH, and the hysteresis comparator HCMP can also compare the voltage of the load voltage detection signal VLoad with the second voltage threshold VH, and output a comparison signal based on the comparison result of the voltage of the load voltage detection signal VLoad with the first voltage threshold VL and the comparison result of the voltage of the load voltage detection signal VLoad with the second voltage threshold VH.

[0104] like Figure 4 As shown, in light load mode, when the load I LoadWhen the voltage of the load voltage detection signal VLoad increases, the hysteresis comparator HCMP compares the voltage of the load voltage detection signal VLoad with the second voltage threshold VH. When the voltage of the load voltage detection signal VLoad is less than or equal to the second voltage threshold VH, that is, the load voltage detection signal VLoad meets the first preset condition and does not meet the second preset condition, the hysteresis comparator HCMP maintains the first comparison signal, that is, maintains a high level signal.

[0105] At this time, the comparison delay signal Light_Load maintains the first comparison delay signal, that is, maintains a high level signal, and the mode switching signal Mode_Detec maintains the light load mode switching signal, that is, maintains a high level signal. The light load mode switching signal is an enable signal of the frequency detector 1121. Under the action of the light load mode switching signal, the frequency detector 1121 can determine the frequency detection signal Freq_detec according to whether the switching frequency of the voltage converter reaches the frequency of the clock signal CLK.

[0106] Among them, the frequency detection signal Freq_detec includes a high level signal and a low level signal. For example, in light load mode, when the switching frequency of the voltage converter reaches the frequency of the clock signal CLK, the frequency detection signal Freq_detec is a high level signal. When the switching frequency of the voltage converter does not reach the frequency of the clock signal CLK, the frequency detection signal Freq_detec is a low level signal.

[0107] With load I Load The voltage of the load voltage detection signal VLoad continues to increase, and the hysteresis comparator HCMP continues to output the first comparison signal until the voltage of the load voltage detection signal VLoad is greater than the second voltage threshold VH, and the load voltage detection signal VLoad meets the second preset condition, and the hysteresis comparator HCMP generates a second comparison signal, then the comparison signal jumps from the first comparison signal to the second comparison signal, that is, from a high level signal to a low level signal.

[0108] At this time, the delay device Delay delays the second comparison signal to obtain a second comparison delay signal, and the comparison delay signal Light_Load jumps from the first comparison delay signal to the second comparison delay signal, that is, jumps from a high level signal to a low level signal. The first logic unit 1122 generates a normal mode switching signal according to the frequency detection signal Freq_detec and the second comparison delay signal, and the mode switching signal Mode_Detec jumps from the light load mode switching signal to the normal mode switching signal, that is, jumps from a high level signal to a low level signal, and the voltage converter switches from the light load mode to the normal mode.

[0109] Thus, in the light load mode, when the voltage of the load voltage detection signal VLoad is greater than the second voltage threshold VH, the detection unit 112 generates a normal mode switching signal.

[0110] Continue to see Figure 5 The control module 120 further includes an error amplifier EA, a second comparator CMP2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2 and an adder Add.

[0111] Among them, the inverting input terminal of the error amplifier EA is connected to the feedback voltage Vfb, the non-inverting input terminal of the error amplifier EA is connected to the reference voltage Vref, the output terminal of the error amplifier EA is connected to the first plate of the first capacitor C1, the first plate of the second capacitor C2 and the inverting input terminal of the second comparator CMP2, and the non-inverting input terminal of the second comparator CMP2 is connected to the first end of the third resistor R3 and the output terminal of the adder Add. The first input terminal of the adder Add is connected to the slope compensation current signal Islope, the second input terminal of the adder Add is connected to the inductor sampling current signal Isense_L, the output terminal of the second comparator CMP2 is connected to the second input terminal of the selector MUX, the second plate of the second capacitor C2 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4, the second end of the third resistor R3 and the second plate of the first capacitor C1 are grounded.

[0112] Specifically, the error amplifier EA can calculate the error voltage between the feedback voltage Vfb and the reference voltage Vref, amplify the error voltage to obtain the error amplified voltage, the fourth resistor R4, the first capacitor C1, and the second capacitor C2 constitute a compensation circuit for the error amplified voltage, compensate the error amplified voltage to obtain the error adjustment voltage signal EAO, and input the error adjustment voltage signal EAO to the inverting input terminal of the second comparator CMP2.

[0113] The adder Add can calculate the sum of the inductor sampling current signal Isense_L and the slope compensation current signal Islope, i.e. Isense_L+Islope, and the sum of the inductor sampling current signal Isense_L and the slope compensation current signal Islope, i.e. Isense_L+Islope, can be converted into a corresponding voltage signal, i.e., the inductor sampling voltage signal R'*(Isense_L+Islope) through the third resistor R3. Wherein, R' is the resistance value of the resistor that affects the inductor current sampling coefficient, i.e., the resistance value of the third resistor R3.

[0114] The second comparator CMP2 can compare the error adjustment voltage signal EAO and the inductor sampling voltage signal R'*(Isense_L+Islope) to obtain a pulse width modulation signal PWM. When the voltage of the inductor sampling voltage signal R'*(Isense_L+Islope) is less than the voltage of the error adjustment voltage signal EAO, the pulse width modulation signal PWM is a low level signal. When the voltage of the inductor sampling voltage signal R'*(Isense_L+Islope) rises to be equal to the voltage of the error adjustment voltage signal EAO, the pulse width modulation signal PWM is a pulse signal.

[0115] Under the action of the normal mode switching signal, the selector MUX turns on the second input terminal of the selector MUX and the output terminal of the selector MUX, and the selector MUX selects to output the pulse width modulation signal PWM. Then, in the normal mode, the selector MUX can provide the pulse width modulation signal PWM to the driving module 130.

[0116] At this time, the mode switching signal Mode_Detec output by the detection module 110 is a normal mode switching signal, ie, a low level signal. The AND operation result of the undervoltage signal FBUV and the mode switching signal Mode_Detec is a low level signal. Then, the first AND gate AND1 will not provide the undervoltage signal FBUV to the driving module 130 .

[0117] Exemplarily, in the normal mode, the upper tube control signal Hsdr generated by the driving module 130 is the second upper tube control signal Hsdr2, and the lower tube control signal Lsdr generated by the driving module 130 is the second lower tube control signal Lsdr2. The second upper tube control signal Hsdr2 includes a second upper tube on signal and a second upper tube off signal, and the second lower tube control signal Lsdr2 includes a second lower tube on signal and a second lower tube off signal, for example, the second upper tube on signal and the second lower tube off signal are high level signals, and the second upper tube off signal and the second lower tube on signal are low level signals.

[0118] Figure 7 A timing diagram of a normal mode steady state provided by an embodiment of the present disclosure, such as Figure 7 As shown, in the normal mode, when the clock signal CLK is a high level signal, the driving module 130 generates a second upper tube on signal and a second lower tube off signal at the rising edge of the clock signal CLK.

[0119] After the upper tube Hs is turned on, when the pulse width modulation signal PWM received by the driving module 130 is a pulse signal for the first time, a second upper tube shutdown signal and a second lower tube opening signal are generated until the clock signal CLK jumps to a high level signal again, thereby generating a cycle of the second upper tube control signal Hsdr2 and the second lower tube control signal Lsdr2.

[0120] In some embodiments, Figure 8 A circuit diagram of another control module provided in an embodiment of the present disclosure, in Figure 5 Based on the embodiment shown, the control module 120 further includes an OR gate and a maximum duration detection unit 121, such as Figure 8 shown.

[0121] The output end of the maximum duration detection unit 121 is connected to the first input end of the OR gate OR, the output end of the timer Timer is connected to the second input end of the OR gate OR, and the output end of the OR gate OR is connected to the first input end of the selector MUX.

[0122] The maximum duration detection unit 121 is configured to, in the light load mode, when the upper tube is turned on for a duration T ON Reach the maximum opening time T ON _ MAX The maximum duration detection signal is outputted to shut down the upper tube Hs.

[0123] For example, in the light load mode, after the upper tube Hs is turned on, if the timer Timer obtains the upper tube turn-on time T according to the input voltage Vin and the output voltage Vout, ON Greater than the maximum opening time T ON_MAX , then the actual opening time of the upper tube Hs reaches the maximum opening time T ON_MAX , the fixed-frequency pulse signal on_timer continues to be a low-level signal.

[0124] At this time, the maximum duration detection unit 121 generates a high-level signal, namely the maximum duration detection signal, and the OR gate OR performs an OR operation on the maximum duration detection signal and the fixed-frequency pulse signal on_timer to obtain the maximum duration detection signal, and the selector MUX can provide the maximum duration detection signal to the driving module 130.

[0125] When receiving the maximum duration detection signal, the driving module 130 can pull down the first upper tube control signal Hsdr1 to generate a first upper tube shutdown signal, and pull up the first lower tube control signal Lsdr1 to generate a first lower tube start signal. Under the action of the first upper tube shutdown signal, the upper tube Hs switches from the on state to the off state until the undervoltage signal FBUV jumps to a high level signal again.

[0126] Thus, in light load mode, when the upper tube is turned on for a period of time T ON Reach the maximum opening time T ON_MAX The control module 120 can provide a maximum duration detection signal to the driving module 130, and the driving module 130 can generate a first upper tube shutdown signal based on the maximum duration detection signal to shut down the turned-on upper tube Hs, thereby limiting the maximum output energy in the light load mode so that when the load ILoad When the energy demand is greater than the supply, the light load mode is exited in time.

[0127] In some embodiments, Fig. 9 A circuit diagram of a driving module provided by an embodiment of the present disclosure is shown in FIG. Fig. 9 As shown, the driving module 130 includes a frequency limiting unit 131 and a second logic unit 132 .

[0128] Combination Figure 2 and Fig. 9 As shown, the first input end of the frequency limiting unit 131 is connected to the clock signal CLK, the second input end of the frequency limiting unit 131 is connected to the first output end of the control module 120, the output end of the frequency limiting unit 131 is connected to the first input end of the second logic unit 132, and the second input end of the second logic unit 132 is connected to the second output end of the control module 120. The first output end of the second logic unit 132 is connected to the control end of the upper tube Hs, and the second output end of the second logic unit 132 is connected to the control end of the lower tube Ls.

[0129] The frequency limiting unit 131 is configured to output the under-voltage signal FBUV and limit the switching frequency of the voltage converter to be less than or equal to the frequency of the clock signal CLK in the light-load mode, and output the clock signal CLK in the normal mode.

[0130] For example, Fig. 9 As shown, the second logic unit 132 includes a first NOR gate NOR1, a second NOR gate NOR2, a first inverter INV1 and a second inverter INV2. The first input end of the first NOR gate NOR1 is connected to the output end of the frequency limiting unit 131, the second input end of the first NOR gate NOR1 is connected to the output end of the second NOR gate NOR2 and the input end of the first inverter INV1, the output end of the first NOR gate NOR1 is connected to the first input end of the second NOR gate NOR2, and the second input end of the second NOR gate NOR2 is connected to the second output end of the control module 120.

[0131] The output end of the first inverter INV1 is connected to the input end of the second inverter INV2 and the control end of the lower tube Ls, and the output end of the second inverter INV2 is connected to the control end of the upper tube Hs.

[0132] Fig.10 A timing diagram of the mode switching before and after the embodiment of the present disclosure is provided, such as Fig.10 As shown, in light load mode, the load I LoadWhen the switching frequency of the undervoltage signal FBUV increases or remains at a relatively high level for a period of time, when the switching frequency of the undervoltage signal FBUV does not reach the upper limit under a certain duty cycle, the frequency limiting unit 131 provides the undervoltage signal FBUV to the second logic unit 132.

[0133] The second logic unit 132 pulls up the upper tube control signal Hsdr and pulls down the lower tube control signal Lsdr when the undervoltage signal FBUV is pulled high. When the fixed frequency pulse signal on_timer is a high level pulse, the upper tube control signal Hsdr is pulled down and the lower tube control signal Lsdr is pulled high. The upper tube is turned on for a time length T ON It is controlled by the fixed frequency pulse signal on_timer.

[0134] With load I Load The switching frequency of the undervoltage signal FBUV continues to increase, and the switching frequency of the undervoltage signal FBUV reaches an upper limit under a certain duty cycle, wherein the upper limit of the switching frequency may be less than or equal to the frequency of the clock signal CLK. In the light load mode, the switching frequency of FBUV is the switching frequency of the voltage converter, and the upper limit of the switching frequency of the voltage converter is less than or equal to the frequency of the clock signal CLK.

[0135] At this time, the error adjustment voltage signal EAO and the load voltage detection signal VLoad increase. When the voltage of the load voltage detection signal VLoad is higher than the second voltage threshold VH, the light load mode is exited and the normal mode is entered.

[0136] When the clock signal CLK is pulled high, the second logic unit 132 pulls up the upper tube control signal Hsdr and pulls down the lower tube control signal Lsdr. When the pulse width modulation signal PWM is a high level pulse, the upper tube control signal Hsdr is pulled down and the lower tube control signal Lsdr is pulled high. The upper tube is turned on for a time length T ON It is controlled by a pulse width modulation signal PWM.

[0137] In this way, when the switching frequency of the voltage converter reaches the upper limit in the light load mode, the light load mode is exited, the switching frequency of the voltage converter in the light load mode can be limited, the switching loss of the voltage converter in the light load mode can be reduced, and thus the light load efficiency can be improved. The maximum output energy in the light load mode can also be limited so that when the load I Load When the energy demand increases, the light load mode is exited in time after it exceeds the supply. In addition, since the upper limit of the switching frequency will not exceed the frequency of the clock signal CLK, smooth switching between the light load mode and the normal mode can be achieved.

[0138] In some embodiments, see Figure 3The first logic unit 1122 includes a second AND gate AND2, a third NOR gate NOR3, a fourth NOR gate NOR4, a third inverter INV3, a fourth inverter INV4 and a fifth inverter INV5.

[0139] Among them, the input end of the third inverter INV3 is connected to the output end of the delayer Delay and the first input end of the third NOR gate NOR3, the output end of the third inverter INV3 is connected to the first input end of the second AND gate AND2, the second input end of the third NOR gate NOR3 is connected to the output end of the fourth NOR gate NOR4 and the input end of the fourth inverter INV4, and the output end of the third NOR gate NOR3 is connected to the first input end of the fourth NOR gate NOR4.

[0140] The second input end of the second AND gate AND2 is connected to the output end of the frequency detector 1121, the output end of the second AND gate AND2 is connected to the second input end of the fourth NOR gate NOR4, the output end of the fourth inverter INV4 is connected to the input end of the fifth inverter INV5, and the output end of the fifth inverter INV5 is connected to the control end of the control module 120 and the enable end of the frequency detector 1121.

[0141] An embodiment of the present disclosure further provides a switching power supply, including a voltage converter and a control circuit 100 of the voltage converter provided by any of the above disclosed embodiments.

[0142] An embodiment of the present disclosure further provides a chip, comprising the control circuit 100 of the voltage converter provided by any of the above disclosed embodiments.

[0143] Exemplarily, the chip may be a switching power supply chip. By integrating the control circuit 100 of the voltage converter into the chip, the volume of the control circuit 100 of the voltage converter may be reduced, which is beneficial to the miniaturization of the control circuit 100 of the voltage converter.

[0144] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural form and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive, unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, the "example" is merely illustrative and should not be considered exclusive or comprehensive.

[0145] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A control circuit of a voltage converter, characterized in that: include: Detection module, control module and drive module; The detection module is configured to determine a load voltage detection signal according to an error adjustment voltage signal and a slope compensation current signal, wherein the error adjustment voltage signal depends on the inductor sampling current signal and the slope compensation current signal, and different duty cycles of the voltage converter correspond to different slope compensation current signals; when the load voltage detection signal satisfies a first preset condition, a light load mode switching signal is generated to enable the voltage converter to enter a light load mode; The control module is configured to determine an undervoltage signal according to a reference voltage and a feedback voltage of a voltage converter, and determine a fixed-frequency pulse signal according to an input voltage and an output voltage of the voltage converter; and provide the undervoltage signal and the fixed-frequency pulse signal to the driving module under the action of the light-load mode switching signal; The driving module is configured to generate a first upper tube control signal and a first lower tube control signal according to the undervoltage signal and the fixed-frequency pulse signal in the light-load mode.

2. The control circuit according to claim 1, characterized in that: The detection module is further configured to generate a normal mode switching signal when the load voltage detection signal satisfies a second preset condition, so that the voltage converter exits from the light load mode and enters the normal mode; The control module is further configured to determine an inductor sampling voltage signal according to the slope compensation current signal and the inductor sampling current signal, and determine a pulse width modulation signal according to the error adjustment voltage signal and the inductor sampling voltage signal; and provide the pulse width modulation signal to the driving module under the action of the normal mode switching signal; The driving module is further configured to generate a second upper tube control signal and a second lower tube control signal according to the pulse width modulation signal and the clock signal in the normal mode.

3. The control circuit according to claim 2, characterized in that: The detection module includes a signal processing unit and a detection unit; The input end of the signal processing unit is connected to the error adjustment voltage signal, the output end of the signal processing unit is connected to the first input end of the detection unit, the second input end of the detection unit is connected to the first voltage threshold, the third input end of the detection unit is connected to the second voltage threshold, and the output end of the detection unit is connected to the enable end of the detection unit and the control end of the control module; wherein the second voltage threshold is greater than the first voltage threshold; The signal processing unit is configured to convert the error adjustment voltage signal into an error amplified current signal, remove the slope compensation current signal from the error amplified current signal, and convert the error amplified current signal after removal into a voltage signal to obtain the load voltage detection signal; The detection unit is configured to, in the normal mode, generate the light load mode switching signal when the voltage of the load voltage detection signal is less than the first voltage threshold; in the light load mode, generate the normal mode switching signal when the voltage of the load voltage detection signal is greater than the second voltage threshold.

4. The control circuit according to claim 3, characterized in that: The signal processing unit includes an operational amplifier, a transistor, a current mirror structure, a first resistor, a second resistor and a current source; The non-inverting input terminal of the operational amplifier is connected to the error adjustment voltage signal, the inverting input terminal of the operational amplifier is connected to the first end of the first resistor and the first end of the transistor, the output terminal of the operational amplifier is connected to the control terminal of the transistor, and the second end of the first resistor is grounded; The second end of the transistor is connected to the first output end of the current mirror structure, the second output end of the current mirror structure is connected to the first end of the second resistor, the input end of the current source and the first input end of the detection unit, and the second end of the second resistor and the output end of the current source are grounded; wherein the resistance values ​​of the first resistor and the second resistor are equal; The current source is configured to provide the slope compensation current signal.

5. The control circuit according to claim 3, characterized in that: The detection unit includes a hysteresis comparator, a delay device, a frequency detector and a first logic unit; The first input end of the hysteresis comparator is connected to the output end of the signal processing unit, the second input end of the hysteresis comparator is connected to the first voltage threshold, the third input end of the hysteresis comparator is connected to the second voltage threshold, the output end of the hysteresis comparator is connected to the input end of the delay device, and the output end of the delay device is connected to the first input end of the first logic unit; The enable end of the frequency detector is connected to the output end of the first logic unit and the control end of the control module, and the output end of the frequency detector is connected to the second input end of the first logic unit; The hysteresis comparator is configured to generate a first comparison signal when the voltage of the load voltage detection signal is less than the first voltage threshold in the normal mode; In the light load mode, generating a second comparison signal when the voltage of the load voltage detection signal is greater than the second voltage threshold; The delay device is configured to, in the normal mode, delay the first comparison signal to obtain a first comparison delay signal; in the light load mode, delay the second comparison signal to obtain a second comparison delay signal; The frequency detector is configured to determine a frequency detection signal according to whether the switching frequency of the voltage converter reaches the frequency of the clock signal under the action of the light load mode switching signal; The first logic unit is configured to, in the light load mode, generate the normal mode switching signal according to the frequency detection signal and the second comparison delay signal; in the normal mode, generate the light load mode switching signal according to the first comparison delay signal.

6. The control circuit according to claim 4, characterized in that: The signal processing unit also includes a low-pass filter; The input end of the low-pass filter is connected to the second output end of the current mirror structure, the first end of the second resistor and the input end of the current source, and the output end of the low-pass filter is connected to the first input end of the detection unit.

7. The control circuit according to any one of claims 2 to 6, characterized in that: The control module includes a first comparator, a timer, a selector and an AND gate; The inverting input terminal of the first comparator is connected to the feedback voltage, the non-inverting input terminal of the first comparator is connected to the reference voltage, the output terminal of the first comparator is connected to the first input terminal of the AND gate, the second input terminal of the AND gate is connected to the output terminal of the detection module and the control terminal of the selector, and the output terminal of the AND gate is connected to the first input terminal of the driving module; The first input terminal of the timer is connected to the input voltage, the second input terminal of the timer is connected to the output voltage, the output terminal of the timer is connected to the first input terminal of the selector, and the output terminal of the selector is connected to the second input terminal of the driving module; The timer is configured to, when the upper tube is turned on, determine the turn-on time of the upper tube according to the input voltage and the output voltage, and generate the fixed-frequency pulse signal according to the turn-on time of the upper tube; The selector is configured to select and output the fixed-frequency pulse signal under the action of the light-load mode switching signal.

8. The control circuit according to claim 7, characterized in that: The control module further includes an error amplifier, a second comparator, a third resistor, a fourth resistor, a first capacitor, a second capacitor and an adder; The inverting input terminal of the error amplifier is connected to the feedback voltage, the non-inverting input terminal of the error amplifier is connected to the reference voltage, the output terminal of the error amplifier is connected to the first plate of the first capacitor, the first plate of the second capacitor and the inverting input terminal of the second comparator, and the non-inverting input terminal of the second comparator is connected to the first end of the third resistor and the output terminal of the adder; The first input end of the adder is connected to the slope compensation current signal, the second input end of the adder is connected to the inductor sampling current signal, the output end of the second comparator is connected to the second input end of the selector, the second plate of the second capacitor is connected to the first end of the fourth resistor, and the second end of the fourth resistor, the second end of the third resistor and the second plate of the first capacitor are grounded; The second comparator is configured to compare the error adjustment voltage signal with the inductor sampling voltage signal to obtain the pulse width modulation signal; The selector is further configured to select and output the pulse width modulation signal under the action of the normal mode switching signal.

9. The control circuit according to claim 7, characterized in that: The control module also includes an OR gate and a maximum duration detection unit; The output end of the maximum duration detection unit is connected to the first input end of the OR gate, the output end of the timer is connected to the second input end of the OR gate, and the output end of the OR gate is connected to the first input end of the selector; The maximum duration detection unit is configured to output a maximum duration detection signal to turn off the upper tube when the on-time of the upper tube reaches the maximum on-time in the light load mode.

10. The control circuit according to any one of claims 2 to 6, characterized in that: The driving module includes a frequency limiting unit and a second logic unit; The first input end of the frequency limiting unit is connected to the clock signal, the second input end of the frequency limiting unit is connected to the first output end of the control module, the output end of the frequency limiting unit is connected to the first input end of the second logic unit, and the second input end of the second logic unit is connected to the second output end of the control module; The second logic unit comprises a first NOR gate, a second NOR gate, a first inverter and a second inverter, wherein a first input end of the first NOR gate is connected to an output end of the frequency limiting unit, a second input end of the first NOR gate is connected to an output end of the second NOR gate and an input end of the first inverter, an output end of the first NOR gate is connected to a first input end of the second NOR gate, a second input end of the second NOR gate is connected to a second output end of the control module, an output end of the first inverter is connected to an input end of the second inverter and a control end of a lower tube, and an output end of the second inverter is connected to a control end of an upper tube; The frequency limiting unit is configured to, in the light load mode, output the undervoltage signal and limit the switching frequency of the voltage converter to be less than or equal to the frequency of the clock signal; and in the normal mode, output the clock signal.

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