A low-glitch level shifting circuit for I2C low-voltage detection

Abstract

The present invention discloses a low-glitch level conversion circuit for I2C low-voltage detection. The circuit includes a transmission response module, a voltage regulation module, a first level conversion module, a second level conversion module, and an electrostatic protection module. The transmission response module is used to pull down the external serial data SDA after the transmitter sends a byte of data. The voltage regulation module is used to output a first adjustable voltage Vb1 and a second adjustable voltage Vb2. The first level conversion module converts the external serial data SDA into high-voltage serial data SDA_IN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2. The second level conversion module converts the external clock pulse SCL into a high-voltage clock pulse SCL_IN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2. The electrostatic protection module is used to protect the external clock pulse SCL from high-voltage pulse discharge. The present invention is applicable to relatively low voltage detection and level conversion, allowing low-voltage serial data signals to be smoothly written to the target device.

Description

Technical Field

[0001] The present invention relates to a level conversion circuit, in particular to a low-glitch level conversion circuit for I2C low voltage detection, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] I2C is a two-wire serial communication protocol using the SDA (Serial Data Line) and the Serial Clock Line. It is primarily used for low-speed, short-distance communication. The protocol supports multiple target devices on the communication bus. Communications are sent in byte packets, and each target device has a unique address. In areas such as mobile phone CPUs, many I / O voltage domains operate at lower voltages, while peripheral circuits typically operate at 3.3V and 5V. When the CPU (side A) communicates with peripheral devices (side B), a voltage mismatch between the communication interfaces may occur, necessitating level conversion. The lower the voltage on the A side, the higher the low-voltage detection requirements of the level conversion circuit. Furthermore, parasitic capacitance introduced by ESD can cause spike currents during the high- and low-level transitions of the clock pulse signal during communication. Furthermore, stray inductance is often unavoidable during chip packaging processes, and this parasitic inductance can cause significant glitches due to the spike currents. Currently, many mobile phone manufacturers are placing higher demands on the voltage detection and glitches amplitude performance of level conversion circuits.

[0003] Chinese Patent Publication No. CN111313887B discloses a level conversion circuit and corresponding driver circuit. This circuit achieves high-speed conversion between two levels by connecting four modules: an input module, a positive feedback module, a level conversion module, and an output module. Chinese Patent Publication No. CN111313887B discloses an I2C level conversion circuit, implementation method, chip, and communication system. The provided I2C level conversion circuit can be used to transmit high and low levels between a master device and a slave device, enabling the master device to perform read or write operations on the slave device. Chinese Patent Publication No. CN118646404A discloses a level converter and digital logic circuit. This circuit achieves level conversion by sequentially coupling an input circuit, a protection circuit, a voltage holding circuit, and a latch circuit. The circuit outputs a corresponding switching signal based on the voltage of the voltage signal, which instructs the corresponding control module to conduct according to the switching signal, thereby achieving multi-mode compatibility of the level converter.

[0004] The existing technology does not consider the circuit's level conversion capability at extremely low voltages (as low as 0.8V) and the glitch interference that may occur during I2C data transmission. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a low-glitch level conversion circuit for I2C low voltage detection, which realizes level conversion at extremely low voltage and can prevent glitch interference.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A low-glitch level conversion circuit for I2C low-voltage detection includes a transmission response module, a voltage regulation module, a first level conversion module, a second level conversion module, and an electrostatic protection module. The transmission response module is used to pull down external serial data SDA after the transmitter sends a byte of data. The voltage regulation module is used to output a first adjustable voltage Vb1 and a second adjustable voltage Vb2. The first level conversion module converts the external serial data SDA into high-voltage serial data SDA_IN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2. The second level conversion module converts the external clock pulse SCL into a high-voltage clock pulse SCL_IN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2. The electrostatic protection module is used to protect the external clock pulse SCL from high-voltage pulse discharge.

[0008] Furthermore, the transmission response module includes an inverter G1, an inverter G2, an inverter G3, a resistor R1, a resistor R2, a capacitor C1, a PMOS tube M0, an NMOS tube M1 and an NMOS tube M2, the input end of the inverter G1 is connected to the transmission response signal SDA_OUT, the output end of the inverter G1 is connected to the input end of the inverter G2, the output end of the inverter G2 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the input end of the inverter G3 and one end of the capacitor C1. The other end of the capacitor C1 is grounded, the other end of the inverter G3 is connected to the gate of the PMOS tube M0 and the gate of the NMOS tube M1, the source of the PMOS tube M0 is connected to the power supply VDD, the drain of the PMOS tube M0 is connected to the drain of the NMOS tube M1 and one end of the resistor R2, the source of the NMOS tube M1 is grounded, the other end of the resistor R2 is connected to the gate of the NMOS tube M2, the drain of the NMOS tube M2 is connected to the external serial data SDA, and the source of the NMOS tube M2 is grounded.

[0009] Furthermore, the resistor R1 and the capacitor C1 form a first-order low-pass filter.

[0010] Furthermore, the voltage regulation module includes a capacitor C2, a capacitor C3, a capacitor C4, a resistor R3, a resistor R4, a resistor R5, an NMOS tube M3, an NMOS tube M4, a PMOS tube M5, a PMOS tube M6, an NMOS tube M7, an NMOS tube M8, a PMOS tube M9 and a PMOS tube M10. One end of the capacitor C2 is connected to the source of the PMOS tube M5, the source of the PMOS tube M6 and the source of the PMOS tube M9 and is connected to the power supply VDD. The other end of the capacitor C2 is connected to the gate of the NMOS tube M3 and the drain of the NMOS tube M4. The drain of the NMOS tube M3 is connected to the drain of the PMOS tube M6, the gate of the PMOS tube M6, the gate of the PMOS tube M5, the gate of the PMOS tube M9 and the drain of the NMOS tube M8. The gate of the OS transistor M4 is connected to the gate of the NMOS transistor M7, the drain of the NMOS transistor M7, the drain of the PMOS transistor M5, and the gate of the NMOS transistor M8. The source of the NMOS transistor M8 is connected to one end of the resistor R3. The drain of the PMOS transistor M9 is connected to one end of the resistor R4 and one end of the capacitor C4 to generate a first adjustable voltage Vb1. The other end of the resistor R4 is connected to one end of the resistor R5 and one end of the capacitor C3 to generate a second adjustable voltage Vb2. The other end of the resistor R5 is connected to the source of the PMOS transistor M10. The source of the NMOS transistor M4, the source of the NMOS transistor M3, the source of the NMOS transistor M7, the other end of the resistor R3, the drain of the PMOS transistor M10, the gate of the PMOS transistor M10, the other end of the capacitor C3, and the other end of the capacitor C4 are grounded.

[0011] Furthermore, the PMOS transistors M5 and M6, the NMOS transistors M7 and M8, and the resistor R3 form a current source independent of the power supply VDD, and the capacitor C2, the NMOS transistors M3 and M4 form a coupled startup circuit.

[0012] Furthermore, the first level conversion module and the second level conversion module respectively include a resistor R6, a resistor R7, an inverter G4, an inverter G5, an NMOS transistor M11, an NMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, an NMOS transistor M15, a PMOS transistor M16, a PMOS transistor M17, an NMOS transistor M18, a PMOS transistor M19, an NMOS transistor M20, an NMOS transistor M21, an NMOS transistor M22, a PMOS transistor M23 and a PMOS transistor M24, one end of the resistor R6 is connected to the external serial data SDA or the external clock pulse SCL, and the other end of the resistor R6 is connected to the external serial data SDA or the external clock pulse SCL. The gate of the PMOS transistor M13, the gate of the PMOS transistor M14, and the gate of the NMOS transistor M15 are connected. The source of the PMOS transistor M13 is connected to the source of the NMOS transistor M12. The gate of the NMOS transistor M12 is connected to the second adjustable voltage Vb2. The drain of the NMOS transistor M12 is connected to the source of the NMOS transistor M11. The gate of the NMOS transistor M11 is connected to the first adjustable voltage Vb1. The drain of the NMOS transistor M11 is connected to one end of the resistor R7. The other end of the resistor R7 is connected to the source of the PMOS transistor M23 and the source of the PMOS transistor M24 and to the power supply VDD. The drain of the PMOS transistor M13 is connected to the PMOS transistor M23. The source of the OS transistor M14, the source of the PMOS transistor M16, the source of the PMOS transistor M17, and the source of the PMOS transistor M19 are connected; the drain of the PMOS transistor M14 is connected to the drain of the NMOS transistor M15, the gate of the PMOS transistor M16, the gate of the PMOS transistor M17, and the gate of the NMOS transistor M18; the drain of the PMOS transistor M17 is connected to the drain of the NMOS transistor M18, the gate of the PMOS transistor M19, the gate of the NMOS transistor M20, and the gate of the NMOS transistor M21; the drain of the PMOS transistor M19 is connected to the drain of the NMOS transistor M20 and the gate of the NMOS transistor M22; The drain of transistor M21 is connected to the drain of PMOS transistor M23 and the gate of PMOS transistor M24. The drain of NMOS transistor M22 is connected to the input end of inverter G4, the drain of PMOS transistor M24, and the gate of PMOS transistor M23. The output end of inverter G4 is connected to the input end of inverter G5. The output end of inverter G5 generates high-voltage serial data SDA_IN or high-voltage clock pulse SCL_IN. The source of NMOS transistor M15, the drain of PMOS transistor M16, the source of NMOS transistor M18, the source of NMOS transistor M20, the source of NMOS transistor M21, and the source of NMOS transistor M22 are grounded.

[0013] Furthermore, the NMOS transistor M21, the NMOS transistor M22 and the PMOS transistor M23, the PMOS transistor M24 form a latch structure.

[0014] Furthermore, the electrostatic protection module includes a Zener diode Z1, a resistor R8 and an NMOS transistor M25, the cathode of the Zener diode Z1 is connected to the drain of the NMOS transistor M25 and connected to the external clock pulse SCL, the anode of the Zener diode Z1 is connected to the gate of the NMOS transistor M25 and one end of the resistor R8, and the other end of the resistor R8 and the source of the NMOS transistor M25 are grounded.

[0015] Compared with the prior art, the present invention has the following advantages and effects:

[0016] 1. The present invention provides a low-glitch level shifting circuit for I2C low-voltage detection, which can be applied to lower voltage (as low as 0.8V) detection and level shifting, so that low-voltage serial data signals can be smoothly written into the target device;

[0017] 2. The present invention can meet the conversion requirements of different low-voltage scenarios by adjusting device (resistance) parameters, thereby expanding the scope of application of level conversion circuits;

[0018] 3. The present invention can prevent spike voltage (burr) generated by parasitic inductance during data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The present invention is a schematic diagram of a low-glitch level conversion circuit for I2C low voltage detection.

[0020] Figure 2 1 is a circuit diagram of the voltage regulation module of the present invention.

[0021] Figure 3 4 is a circuit diagram of the first level conversion module and the second level conversion module of the present invention.

[0022] Figure 4 4 is a circuit diagram of the electrostatic protection module of the present invention. DETAILED DESCRIPTION

[0023] In order to elaborate on the technical solutions adopted by the present invention to achieve the predetermined technical purpose, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0024] like Figure 1As shown, a low-glitch level conversion circuit for I2C low voltage detection of the present invention includes a transmission response module, a voltage regulation module, a first level conversion module, a second level conversion module and an electrostatic protection module. The transmission response module is used to send a one-bit response signal to respond to the transmitter after the transmitter sends a byte of data, indicating that the transmission is completed. That is, when the transmitter sends a byte of data, the transmission response signal SDA_OUT will flip to a high level. At this time, the external serial data SDA is pulled to a low level, indicating that the transmission is successful. The voltage regulation module is used to output a first adjustable voltage Vb1 and a second adjustable voltage Vb2. The first level conversion module converts external serial data SDA into high-voltage serial data SDA_IN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2. The second level conversion module converts the external clock pulse SCL into a high-voltage clock pulse SCL_IN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2. The electrostatic protection module is used to provide discharge protection against high-voltage pulses caused by the human body, machines, electronic components, etc. At the same time, the module uses coupling to greatly enhance the discharge capability of the NMOS, thereby reducing the amplitude of burrs caused by parasitic capacitance and stray inductance.

[0025] like Figure 1 As shown, the transmission response module includes an inverter G1, an inverter G2, an inverter G3, a resistor R1, a resistor R2, a capacitor C1, a PMOS transistor M0, an NMOS transistor M1 and an NMOS transistor M2. The input end of the inverter G1 is connected to the transmission response signal SDA_OUT, the output end of the inverter G1 is connected to the input end of the inverter G2, the output end of the inverter G2 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the input end of the inverter G3 and one end of the capacitor C1. The other end of the capacitor C1 is grounded, the other end of the inverter G3 is connected to the gate of the PMOS transistor M0 and the gate of the NMOS transistor M1, the source of the PMOS transistor M0 is connected to the power supply VDD, the drain of the PMOS transistor M0 is connected to the drain of the NMOS transistor M1 and one end of the resistor R2, the source of the NMOS transistor M1 is grounded, the other end of the resistor R2 is connected to the gate of the NMOS transistor M2, the drain of the NMOS transistor M2 is connected to the external serial data SDA, and the source of the NMOS transistor M2 is grounded.

[0026] Among them, NMOS transistor M2 strongly pulls down the external serial data SDA to a low level, acting as an ACK signal to indicate the completion of signal transmission. That is, after the transmitter sends a byte of data, the transmission response signal SDA_OUT goes high, turning on NMOS transistor M2, thereby pulling down the external serial data SDA level to respond to the transmitter, indicating a successful transmission. In addition, NMOS transistor M2 also functions as an electrostatic discharge protection device. When a high-voltage pulse caused by the human body, machinery, electronic components, etc. occurs: if NMOS transistor M2 is turned off, it acts like a GGNMOS. That is, the high-voltage pulse breaks down the parasitic diode, turning on NMOS transistor M2 and dissipating the energy, thereby protecting the internal chip from damage. If NMOS transistor M2 is turned on, its sufficiently strong overcurrent capability can also discharge the energy, thereby protecting the internal chip from damage. The inverter formed by PMOS transistor M0 and NMOS transistor M1 drives NMOS transistor M2. Considering that NMOS transistor M2 not only provides a strong pull-down for the ACK signal but also serves as ESD protection for the SDA port, its size is much larger than that of a typical device. Therefore, a stronger pre-driver is required to quickly charge and discharge the gate capacitance of the NMOS transistor. Resistor R2 acts as a current-limiting resistor for protection. Inverters G1 and G2 rectify the transmission response signal SDA_OUT, preventing digital signals from being interfered with by long layout traces. Similarly, the first-order low-pass filter formed by resistor R1 and capacitor C1 filters out high-frequency glitches such as noise, ensuring correct signal transmission.

[0027] like Figure 2As shown, the voltage regulation module includes a capacitor C2, a capacitor C3, a capacitor C4, a resistor R3, a resistor R4, a resistor R5, an NMOS tube M3, an NMOS tube M4, a PMOS tube M5, a PMOS tube M6, an NMOS tube M7, an NMOS tube M8, a PMOS tube M9 and a PMOS tube M10. One end of the capacitor C2 is connected to the source of the PMOS tube M5, the source of the PMOS tube M6 and the source of the PMOS tube M9 and is connected to the power supply VDD. The other end of the capacitor C2 is connected to the gate of the NMOS tube M3 and the drain of the NMOS tube M4. The drain of the NMOS tube M3 is connected to the drain of the PMOS tube M6, the gate of the PMOS tube M6, the gate of the PMOS tube M5, the gate of the PMOS tube M9 and the drain of the NMOS tube M8. The gate of transistor M4 is connected to the gate of NMOS transistor M7, the drain of NMOS transistor M7, the drain of PMOS transistor M5, and the gate of NMOS transistor M8. The source of NMOS transistor M8 is connected to one end of resistor R3. The drain of PMOS transistor M9 is connected to one end of resistor R4 and one end of capacitor C4 to generate a first adjustable voltage Vb1. The other end of resistor R4 is connected to one end of resistor R5 and one end of capacitor C3 to generate a second adjustable voltage Vb2. The other end of resistor R5 is connected to the source of PMOS transistor M10. The source of NMOS transistor M4, the source of NMOS transistor M3, the source of NMOS transistor M7, the other end of resistor R3, the drain of PMOS transistor M10, the gate of PMOS transistor M10, the other end of capacitor C3, and the other end of capacitor C4 are grounded.

[0028] PMOS transistors M5 and M6, along with NMOS transistors M7 and M8, and resistor R3, form a current source independent of power supply VDD. This current source flows through resistors R4 and R5, and a diode-connected PMOS transistor M10 via a current mirror formed by PMOS transistors M6 and M9, thereby outputting a bias voltage independent of power supply voltage VDD, namely, a first adjustable voltage Vb1 and a second adjustable voltage Vb2. Capacitors C2, NMOS transistors M3, and NMOS transistors M4 form a coupled startup circuit. When the chip is powered on, VDD is coupled to the gate of NMOS transistor M3 via capacitor C2, turning it on. This lowers the gate voltages of PMOS transistors M5 and M6, helping the current source escape the zero-current merge point after power-on. When the current source is fully started, NMOS transistor M4 turns on, lowering the gate voltage of NMOS transistor M3, thereby shutting down NMOS transistor M3 and, consequently, the entire startup circuit. This reduces the chip's quiescent current. In addition, according to the need for low-voltage detection range in actual applications, the circuit can also use resistors R4 and R5 with different resistance values ​​to meet the needs of different application scenarios.

[0029] like Figure 3As shown, the first level conversion module and the second level conversion module respectively include a resistor R6, a resistor R7, an inverter G4, an inverter G5, an NMOS transistor M11, an NMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, an NMOS transistor M15, a PMOS transistor M16, a PMOS transistor M17, an NMOS transistor M18, a PMOS transistor M19, an NMOS transistor M20, an NMOS transistor M21, an NMOS transistor M22, a PMOS transistor M23 and a PMOS transistor M24, one end of the resistor R6 is connected to the external serial data SDA or the external clock pulse SCL, and the other end of the resistor R6 is connected to the PMOS transistor M16. The gate of the S transistor M13, the gate of the PMOS transistor M14, and the gate of the NMOS transistor M15 are connected. The source of the PMOS transistor M13 is connected to the source of the NMOS transistor M12. The gate of the NMOS transistor M12 is connected to the second adjustable voltage Vb2. The drain of the NMOS transistor M12 is connected to the source of the NMOS transistor M11. The gate of the NMOS transistor M11 is connected to the first adjustable voltage Vb1. The drain of the NMOS transistor M11 is connected to one end of the resistor R7. The other end of the resistor R7 is connected to the source of the PMOS transistor M23 and the source of the PMOS transistor M24 and to the power supply VDD. The drain of the PMOS transistor M13 is connected to the PMOS transistor M24. The source of the transistor M14, the source of the PMOS transistor M16, the source of the PMOS transistor M17 and the source of the PMOS transistor M19 are connected; the drain of the PMOS transistor M14 is connected to the drain of the NMOS transistor M15, the gate of the PMOS transistor M16, the gate of the PMOS transistor M17 and the gate of the NMOS transistor M18; the drain of the PMOS transistor M17 is connected to the drain of the NMOS transistor M18, the gate of the PMOS transistor M19, the gate of the NMOS transistor M20 and the gate of the NMOS transistor M21; the drain of the PMOS transistor M19 is connected to the drain of the NMOS transistor M20 and the gate of the NMOS transistor M22; the drain of the NMOS transistor M21 is connected to the drain of the NMOS transistor M22 and the gate of the NMOS transistor M23. The drain of M21 is connected to the drain of the PMOS transistor M23 and the gate of the PMOS transistor M24. The drain of the NMOS transistor M22 is connected to the input end of the inverter G4, the drain of the PMOS transistor M24, and the gate of the PMOS transistor M23. The output end of the inverter G4 is connected to the input end of the inverter G5. The output end of the inverter G5 generates high-voltage serial data SDA_IN or high-voltage clock pulse SCL_IN. The source of the NMOS transistor M15, the drain of the PMOS transistor M16, the source of the NMOS transistor M18, the source of the NMOS transistor M20, the source of the NMOS transistor M21, and the source of the NMOS transistor M22 are grounded.

[0030] The function of the NMOS transistors M11 and M12 is to compress the detection window of the level conversion circuit, thereby realizing the low input voltage detection function. The input detection voltage rail is determined by the gate voltage of the NMOS transistor M12, that is, the second adjustable voltage Vb2. The NMOS transistors M11 and M12 form a common source and common gate structure. As a common gate transistor, the NMOS transistor M12 also plays a role in shielding the power supply voltage jitter from interfering with the detection window voltage rail (the source voltage of the PMOS transistor M13). Similarly, the function of the PMOS transistors M14 and M16 is also to avoid the repeated flipping of the level shift signal caused by the jitter of the electrical signal under critical conditions. Hysteresis is introduced in the circuit. By adjusting the sizes of PMOS transistors M13, M14, and M16, the hysteresis interval can be changed, thereby ensuring the transmission reliability of the level shift circuit. The input signal is converted to the power supply voltage rail where PMOS transistors M23 and M24 and inverters G4 and G5 are located via the inverter formed by PMOS transistors M17 and M19 and NMOS transistors M18 and M20, and the low-voltage rail where NMOS transistors M21 and M22 are located. The latch structure formed by NMOS transistors M21 and M22 and PMOS transistors M23 and M24 accelerates signal flipping and reduces transmission delay, making this circuit also suitable for certain high-speed application scenarios.

[0031] like Figure 4 As shown, the electrostatic protection module includes a Zener diode Z1, a resistor R8 and an NMOS transistor M25. The cathode of the Zener diode Z1 is connected to the drain of the NMOS transistor M25 and to the external clock pulse SCL. The anode of the Zener diode Z1 is connected to the gate of the NMOS transistor M25 and one end of the resistor R8. The other end of the resistor R8 and the source of the NMOS transistor M25 are grounded.

[0032] Compared with the GGNMOS structure used in traditional ESD protection modules, the present invention adopts Zener diode coupling to greatly reduce the size of the NMOS tube M25 under the same discharge capacity of the circuit, that is, its parasitic capacitance is also reduced, which will reduce the peak current caused by the flip of the clock pulse signal SCL during the communication process. For the inevitable parasitic inductance caused by the chip package and the PCB board, the induced electromotive force against the rapid change of current will also be reduced, and the flip burrs reflected in the clock pulse will be greatly reduced, thereby meeting the new generation requirements of many mobile phone manufacturers such as Samsung and OPPO for level conversion circuits.

[0033] The present invention provides a low-glitch level-shifting circuit for I2C low-voltage detection. The circuit is applicable to relatively low voltage (as low as 0.8V) detection and level shifting, enabling low-voltage serial data signals to be smoothly written into a target device. The present invention can meet the conversion requirements of different low-voltage scenarios by adjusting device (resistance) parameters, thereby expanding the scope of application of the level-shifting circuit. The present invention can also prevent spike voltages (glitch) generated by parasitic inductance during data transmission.

[0034] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A low-glitch level shifting circuit for I2C low-voltage detection, characterized by: It includes a transmission response module, a voltage regulation module, a first level conversion module, a second level conversion module and an electrostatic protection module. The transmission response module is used to pull down the external serial data SDA after the transmitter sends one byte of data. The voltage regulation module is used to output a first adjustable voltage Vb1 and a second adjustable voltage Vb2. The first level conversion module converts the external serial data SDA into high-voltage serial data SDA_IN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2. The second level conversion module converts the external clock pulse SCL into a high-voltage clock pulse SCL_IN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2. The electrostatic protection module is used to perform high-voltage pulse discharge protection on the external clock pulse SCL; The transmission response module includes an inverter G1, an inverter G2, an inverter G3, a resistor R1, a resistor R2, a capacitor C1, a PMOS transistor M0, an NMOS transistor M1, and an NMOS transistor M2. The input end of the inverter G1 is connected to the transmission response signal SDA_OUT, the output end of the inverter G1 is connected to the input end of the inverter G2, the output end of the inverter G2 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the input end of the inverter G3 and one end of the capacitor C1, the other end of the capacitor C1 is grounded, the other end of the inverter G3 is connected to the gate of the PMOS transistor M0 and the gate of the NMOS transistor M1, the source of the PMOS transistor M0 is connected to the power supply VDD, the drain of the PMOS transistor M0 is connected to the drain of the NMOS transistor M1 and one end of the resistor R2, the source of the NMOS transistor M1 is grounded, the other end of the resistor R2 is connected to the gate of the NMOS transistor M2, the drain of the NMOS transistor M2 is connected to the external serial data SDA, and the source of the NMOS transistor M2 is grounded.

2. The low-glitch level shifting circuit for I2C low voltage detection according to claim 1, wherein: The resistor R1 and the capacitor C1 form a first-order low-pass filter.

3. The low-glitch level shifting circuit for I2C low voltage detection according to claim 1, wherein: The voltage regulation module includes a capacitor C2, a capacitor C3, a capacitor C4, a resistor R3, a resistor R4, a resistor R5, an NMOS tube M3, an NMOS tube M4, a PMOS tube M5, a PMOS tube M6, an NMOS tube M7, an NMOS tube M8, a PMOS tube M9 and a PMOS tube M10. One end of the capacitor C2 is connected to the source of the PMOS tube M5, the source of the PMOS tube M6 and the source of the PMOS tube M9 and is connected to the power supply VDD. The other end of the capacitor C2 is connected to the gate of the NMOS tube M3 and the drain of the NMOS tube M4. The drain of the NMOS tube M3 is connected to the drain of the PMOS tube M6, the gate of the PMOS tube M6, the gate of the PMOS tube M5, the gate of the PMOS tube M9 and the drain of the NMOS tube M8. The gate of M4 is connected to the gate of the NMOS transistor M7, the drain of the NMOS transistor M7, the drain of the PMOS transistor M5, and the gate of the NMOS transistor M8. The source of the NMOS transistor M8 is connected to one end of the resistor R3. The drain of the PMOS transistor M9 is connected to one end of the resistor R4 and one end of the capacitor C4 to generate a first adjustable voltage Vb1. The other end of the resistor R4 is connected to one end of the resistor R5 and one end of the capacitor C3 to generate a second adjustable voltage Vb2. The other end of the resistor R5 is connected to the source of the PMOS transistor M10. The source of the NMOS transistor M4, the source of the NMOS transistor M3, the source of the NMOS transistor M7, the other end of the resistor R3, the drain of the PMOS transistor M10, the gate of the PMOS transistor M10, the other end of the capacitor C3, and the other end of the capacitor C4 are grounded.

4. The low-glitch level shifting circuit for I2C low voltage detection according to claim 3, wherein: The PMOS transistors M5 and M6, the NMOS transistors M7 and M8, and the resistor R3 form a current source independent of the power supply VDD, and the capacitor C2, the NMOS transistors M3 and M4 form a coupled startup circuit.

5. The low-glitch level shifting circuit for I2C low voltage detection according to claim 1, wherein: The first level conversion module and the second level conversion module respectively include a resistor R6, a resistor R7, an inverter G4, an inverter G5, an NMOS transistor M11, an NMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, an NMOS transistor M15, a PMOS transistor M16, a PMOS transistor M17, an NMOS transistor M18, a PMOS transistor M19, an NMOS transistor M20, an NMOS transistor M21, an NMOS transistor M22, a PMOS transistor M23 and a PMOS transistor M24, one end of the resistor R6 is connected to the external serial data SDA or the external clock pulse SCL, and the other end of the resistor R6 is connected to the PMOS transistor M16. The gate of the transistor M13, the gate of the PMOS transistor M14, and the gate of the NMOS transistor M15 are connected, the source of the PMOS transistor M13 is connected to the source of the NMOS transistor M12, the gate of the NMOS transistor M12 is connected to the second adjustable voltage Vb2, the drain of the NMOS transistor M12 is connected to the source of the NMOS transistor M11, the gate of the NMOS transistor M11 is connected to the first adjustable voltage Vb1, the drain of the NMOS transistor M11 is connected to one end of the resistor R7, the other end of the resistor R7 is connected to the source of the PMOS transistor M23 and the source of the PMOS transistor M24 and to the power supply VDD, the drain of the PMOS transistor M13 is connected to the PMOS transistor M24. The source of the transistor M14, the source of the PMOS transistor M16, the source of the PMOS transistor M17 and the source of the PMOS transistor M19 are connected; the drain of the PMOS transistor M14 is connected to the drain of the NMOS transistor M15, the gate of the PMOS transistor M16, the gate of the PMOS transistor M17 and the gate of the NMOS transistor M18; the drain of the PMOS transistor M17 is connected to the drain of the NMOS transistor M18, the gate of the PMOS transistor M19, the gate of the NMOS transistor M20 and the gate of the NMOS transistor M21; the drain of the PMOS transistor M19 is connected to the drain of the NMOS transistor M20 and the gate of the NMOS transistor M22; the drain of the NMOS transistor M21 is connected to the drain of the NMOS transistor M22 and the gate of the NMOS transistor M23. The drain of M21 is connected to the drain of the PMOS transistor M23 and the gate of the PMOS transistor M24. The drain of the NMOS transistor M22 is connected to the input end of the inverter G4, the drain of the PMOS transistor M24, and the gate of the PMOS transistor M23. The output end of the inverter G4 is connected to the input end of the inverter G5. The output end of the inverter G5 generates high-voltage serial data SDA_IN or high-voltage clock pulse SCL_IN. The source of the NMOS transistor M15, the drain of the PMOS transistor M16, the source of the NMOS transistor M18, the source of the NMOS transistor M20, the source of the NMOS transistor M21, and the source of the NMOS transistor M22 are grounded.

6. The low-glitch level shifting circuit for I2C low voltage detection according to claim 5, characterized in that: The NMOS transistors M21 and M22 and the PMOS transistors M23 and M24 form a latch structure.

7. The low-glitch level shifting circuit for I2C low voltage detection according to claim 1, wherein: The electrostatic protection module includes a Zener diode Z1, a resistor R8 and an NMOS transistor M25. The cathode of the Zener diode Z1 is connected to the drain of the NMOS transistor M25 and to the external clock pulse SCL. The anode of the Zener diode Z1 is connected to the gate of the NMOS transistor M25 and one end of the resistor R8. The other end of the resistor R8 and the source of the NMOS transistor M25 are grounded.

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