Reduced header signal information test system and method

Abstract

The invention relates to a reduced header signal information testing system and method. The introduced embodiments facilitate efficient and efficient flexible implementation of different types of test processes in a test system. In some embodiments, a signal processing test method includes selecting a signal processing mode between a head-including mode, a reduced head training mode, and a reduced head mode; executing a signal processing information determination process according to a result of selecting the signal processing mode; and performing a modulation / demodulation related process in accordance with a result of the signal processing information determination process. In a reduced header mode, a process is performed on a communication signal in which header information is initially not readily available in the communication signal itself and demodulation parameter information is advantageously derived / developed / extrapolated from other information in the communication signal.

Description

[0001] Related Applications

[0002] This application claims the benefit of and priority to provisional application No. 63 / 512,605, filed on July 7, 2023, entitled “TECHNIQUES FOR HEADERLESS DEMODULATION OF A SIGNAL” (Agent Docket No. ATSY-0138-00.00US), which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to the fields of signal processing and electronic testing. Background Art

[0004] Electronic systems and devices have made significant contributions to the advancement of modern society and have facilitated increased productivity and reduced costs for analyzing and communicating information in a variety of commercial, scientific, educational, and entertainment applications. To meet the growing desire to communicate more information, new communication devices and communication protocols have been implemented. Proper transmission and processing (e.g., modulation, demodulation, etc.) of the signals conveying the information is critical to accurate information communication between electronic devices. With the large amounts of information being communicated and the development of new communication protocols, the ability of testing components to properly participate in information communication has historically required more time and resources, resulting in lower overall productivity and often higher costs for test systems and test operations.

[0005] In addition, as communication components and protocols evolve and change, testing to ensure accurate signal transmission and processing can become complex and cumbersome. Addressing changing communication protocol requirements traditionally leads to more complex test patterns (e.g., larger patterns on an individual basis, more patterns required overall, etc.), which in turn often leads to longer test times, which is undesirable. Traditionally, more electronic resources associated with testing (e.g., test scan chain components, waveform generation components, additional information storage capacity, etc.) are also required to address the increased amount of information and new communication protocol requirements. However, memory space and other resources on integrated circuits are typically limited, which in turn prompts a focus on allocating resources to normal operations (e.g., mission mode operations, non-test operations, terminal use operations, etc.) and functions. However, assigning and dedicating limited space to test resources for relatively infrequent test operations often becomes a costly, inefficient and / or undesirable allocation of resources. Providing sufficient time and resources to properly test an implementation of a new communication protocol in a device under test (DUT), such as via an automated test system (ATE), or the like, has traditionally been impractical and / or impossible. Summary of the invention

[0006] The embodiments of the present disclosure described herein facilitate flexible implementation of different types of test processes in a test system. The embodiments described herein enable efficient and effective testing of communication systems and methods on a component basis, where the resources supporting the components are limited. In fact, the embodiments of the present disclosure allow a communication device to be fully tested without adding additional electronic resources that the communication device does not need for its normal operation, thereby providing cost savings for the device manufacturing entity.

[0007] In some embodiments, a reduced header communication signal processing test method includes performing an autocorrelation of a cyclic prefix in a signal, wherein the signal is configured according to a communication protocol; identifying a start timing of a symbol in the signal based on the result of the autocorrelation, and wherein the symbol is defined by the communication protocol and includes an orthogonal frequency division modulation (OFDM) symbol. The method also includes determining an initial coarse frequency error correction based on the result of the autocorrelation; establishing a group of bins for the signal, wherein the group of bins includes a pilot bin and a data bin, wherein further, the group of bins corresponds to a group of subcarriers associated with the signal, and the pilot bin has a corresponding pilot subcarrier in the group of subcarriers, and the data bin corresponds to a data subcarrier in the group of subcarriers. The method also includes extracting an identification of the pilot bin according to a definition of the pilot subcarrier defined by the communication protocol; establishing an ideal constellation value and an ideal symbol value for the pilot bin and the data bin; and determining other demodulation parameter values ​​based on the results of the ideal constellation value and the ideal symbol value for the pilot bin and the data bin.

[0008] In other embodiments, a signal processing test system includes: a load board configured to couple with a plurality of devices under test (DUTs); a controller configured to direct testing of the plurality of DUTs, wherein the controller includes a test mode selection module operable to select between a plurality of test modes, wherein one of the plurality of test modes is associated with a reduced header communication signal test process applied to a signal; and test electronics configured to test the plurality of DUTs under control of the controller. The test electronics are coupled to the load board, and wherein the test electronics include: a demodulation information determination module operable to collect information associated with a demodulation operation, wherein the demodulation operation includes determining signal processing information based on information in a payload portion of the signal; and a demodulation module operable to perform the demodulation operation based on information received from the demodulation information determination module.

[0009] In other embodiments, a signal processing testing method includes: selecting a signal processing mode among a head mode, a reduced head training mode, and a reduced head mode; performing a signal processing information determination process according to a result of selecting the signal processing mode; and performing a modulation / demodulation related process according to a result of the signal processing information determination process. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings included in and forming a part of this specification are included for illustrative purposes to illustrate the principles of the present disclosure and are not intended to limit the present disclosure to the specific implementations illustrated therein. The drawings are not to scale unless otherwise specifically indicated.

[0011] Figure 1A is a block diagram of an exemplary test environment or system according to an embodiment of the present disclosure.

[0012] Figure 1B is a block diagram of an exemplary radio frequency (RF) integrated circuit device or DUT according to an embodiment of the present disclosure.

[0013] Figure 1C is a block diagram of an exemplary test environment or system according to an embodiment of the present disclosure.

[0014] Figure 2A is a block diagram of an exemplary DUT according to an embodiment of the present disclosure.

[0015] Figure 2B is a block diagram of an exemplary automatic test system (ATE) according to an embodiment of the present disclosure.

[0016] Figure 3A is a flow chart of an exemplary multi-mode modulation / demodulation parameter determination method including a novel header reduction process according to an embodiment of the present disclosure.

[0017] Figure 3B is a block diagram of an exemplary multi-mode modulation / demodulation parameter determination system according to an embodiment of the present disclosure.

[0018] Figure 4A is a block diagram of an exemplary PDU communication frame or packet according to an embodiment of the present disclosure.

[0019] Figure 4B is a block diagram of exemplary PDU communication frames or packets according to different communication protocol / model layers of an embodiment of the present disclosure.

[0020] Figure 4C Various exemplary data packets according to embodiments of the present disclosure are included, including the organization and configuration of information in a PPDU.

[0021] Figure 4Dis a diagram of a data packet including various exemplary organizations and configurations of information ("packets") in accordance with embodiments of the present disclosure.

[0022] Figure 4E is a block diagram of different exemplary signal physical layer protocol data unit (PPDU) organizations / configurations according to the IEEE 802.11 series of wireless network protocols / standards according to an embodiment of the present disclosure.

[0023] Figure 5A is a block diagram of an exemplary signal configuration according to an embodiment of the present disclosure.

[0024] Figure 5B is a block diagram of an exemplary subcarrier spectrum and corresponding bins according to an embodiment of the present disclosure.

[0025] Figure 5C is a graphical block diagram of an exemplary transmission scheme for OFDM symbol tones / signals in accordance with an embodiment of the present disclosure.

[0026] Figure 5D is a block diagram of an exemplary OFDM symbol payload portion transmission with reduced header information according to an embodiment of the present disclosure.

[0027] Figure 5E is a block diagram of various exemplary subcarrier configuration assignments according to an embodiment of the present disclosure.

[0028] Fig. 6A is a block diagram of several exemplary constellation diagrams associated with signal communications according to embodiments of the present disclosure.

[0029] Figure 6B is a block diagram of several exemplary constellation errors associated with signal communication according to an embodiment of the present disclosure.

[0030] Figure 7 is a logic flow diagram of an exemplary test mode selection process according to an embodiment of the present disclosure.

[0031] Figure 8 is a block diagram of an exemplary reduced header mode testing process according to an embodiment of the present disclosure.

[0032] Fig.9A is a block diagram of exemplary autocorrelation plot results according to an embodiment of the present disclosure.

[0033] Fig. 9B is a block diagram of an exemplary autocorrelation process according to an embodiment of the present disclosure.

[0034] Fig.10 is a flow chart of an exemplary equalizer value determination process according to an embodiment of the present disclosure.

[0035] Fig.11A is a flow chart of an exemplary ideal pilot tone determination process according to an embodiment of the present disclosure.

[0036] Fig. 11B is a graph of exemplary simulated channel responses when there is a signal with a full header or a signal with a non-blind known excitation according to an embodiment of the present disclosure.

[0037] Fig. 11C is a graph illustrating the locations of several exemplary pilot bin frequency responses according to an embodiment of the present disclosure.

[0038] Fig. 12A is a flow chart of an exemplary interpolation process with iterative updating / redetermination of equilibrium values ​​within bins according to an embodiment of the present disclosure.

[0039] Fig. 12B is an exemplary graph of the results of an interpolation process with iterative updating / redetermination of equilibrium values ​​within bins in accordance with an embodiment of the present disclosure.

[0040] Fig. 12C and Fig.12D is a flow chart of an exemplary interpolation process with iterative updating / redetermination of equilibrium values ​​within bins according to an embodiment of the present disclosure.

[0041] Fig.12E is a block diagram of an exemplary subcarrier binning configuration 1291 according to an embodiment of the present disclosure.

[0042] Fig.12F is a block diagram of exemplary signal information processing operations according to an embodiment of the present disclosure.

[0043] Figure 12G is a block diagram of exemplary signal information processing operations according to an embodiment of the present disclosure.

[0044] Fig.12H is a block diagram of exemplary signal information processing operations according to an embodiment of the present disclosure.

[0045] Fig.12I is a block diagram of a list 1293 of equalizer values ​​associated with bins of OFDM values ​​in a burst or frame.

[0046] Fig.12J is a flow chart of an average equalizer process 1500 according to some embodiments of the present disclosure.

[0047] Fig.13A is an exemplary graph of frequency response of bandwidth including multiple bins / subcarriers according to an embodiment of the present disclosure.

[0048] Fig. 13Bis an exemplary graph of frequency response of bandwidth including multiple bins / subcarriers according to an embodiment of the present disclosure.

[0049] Fig.14A is a flow chart of an exemplary enhanced equalizer process according to an embodiment of the present disclosure.

[0050] Fig. 14B is a block diagram of several exemplary signal information processing operations according to an embodiment of the present disclosure.

[0051] Fig.15 It is a flowchart of an exemplary current data bin label reassignment process according to an embodiment of the present disclosure.

[0052] Fig.16 is a flow chart of an exemplary reduced head band reference signal training mode test process according to an embodiment of the present disclosure.

[0053] Fig.17 is a block diagram of an example 802.11ax 20 MHz ideal waveform in accordance with an embodiment of the present disclosure.

[0054] Fig.18 is a graph of an exemplary payload-only ideal IQ waveform when the input parameter HeaderlessDemod is set to a training mode (eg, HeaderlessDemodTraining and Execute, etc.) according to an embodiment of the present disclosure.

[0055] Fig.19 is a graph of an exemplary extracted payload-only ideal signal according to an embodiment of the present disclosure.

[0056] Fig. 20 is a graph of a demodulated payload-only signal according to an embodiment of the present disclosure.

[0057] Fig.21 is a flow chart of an exemplary head mode testing process according to an embodiment of the present disclosure.

[0058] Fig. 22 is a block diagram of an exemplary electronic system that can be used as a platform to implement and control methods according to embodiments of the present disclosure.

[0059] Fig.23 is a block diagram of an exemplary algorithmic reduction header processing module 230 according to an embodiment of the present disclosure.

[0060] Fig.24 is a block diagram of an exemplary algorithmic interpolation module according to an embodiment of the present disclosure.

[0061] Fig.25 It is an extended version of the exemplary algorithm enhanced equalizer module and reassignment module.

[0062] Fig.26 is a block diagram of an exemplary algorithm training module processing module according to an embodiment of the present disclosure.

[0063] Fig. 27 It is a block diagram of an exemplary algorithm-leading bin ideal value module according to an embodiment of the present disclosure.

[0064] Fig.28 is a block diagram of an exemplary algorithm iterative interpolation module according to an embodiment of the present disclosure.

[0065] Fig.29 is a block diagram of an exemplary testing method according to an embodiment of the present disclosure.

[0066] Fig.30 is a block diagram of an exemplary reduced header mode testing process according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0067] The preferred embodiments of the present disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the present disclosure to these embodiments. On the contrary, the present disclosure is intended to cover the replacements, modifications and equivalents that may be included in the spirit and scope of the present disclosure as defined by the appended claims. In addition, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to those of ordinary skill in the art that the present disclosure can be implemented without these specific details. In other cases, well-known methods, processes, components and circuits are not described in detail to avoid unnecessarily obscuring various aspects of the present disclosure.

[0068] The described systems and methods include efficient and effective schemes for handling modulation / demodulation in various scenarios, including appropriately handling situations where signal modulation / demodulation would otherwise be difficult (e.g., due to limited capabilities / resources in the device, economically unfeasible, etc.). In some embodiments, demodulation of a communication signal need not rely on some demodulation parameters included in the signal that would otherwise be utilized in traditional schemes. In some exemplary implementations, a "reduced header information demodulation determination" process is performed on a communication signal, wherein header information (e.g., preamble information, channel estimation related information, reference information, etc.) is not initially readily available in the communication signal itself, and demodulation parameter information is advantageously derived / developed / extrapolated from other information in the communication signal. By reducing the size of the header, a resource-limited device under test (DUT) can be efficiently tested, thereby reducing testing costs and complexity.

[0069] In view of this, embodiments of the present disclosure enable efficient and effective signal processing component testing. In some embodiments, a "reduced header information demodulation" process is performed by an automated test equipment (ATE) system in response to a signal transmitted to a device under test (DUT) or transmitted by the DUT. The process is performed on the payload portion of the information in a test environment, where demodulation parameter information is typically included in other parts of the communication protocol. The DUT cannot easily obtain the demodulation parameter information in other ways. According to the "reduced header information demodulation" process, the results of up-converting and down-converting the signal in the DUT are captured and communicated to the ATE for post-processing. In some exemplary implementations, the reduced header information demodulation process is implemented by a computer algorithm running on a workstation associated with the ATE. The communication of the payload portion is carried out in accordance with the payload specification of the communication protocol, and information and data related to the demodulation parameters specified by other parts of the protocol are not included in the signal. In some exemplary implementations, the signal specifically includes less header / leading information associated with the communication protocol than would otherwise be included in the signal.

[0070] Figure 1A 1 is a block diagram of an exemplary test environment or test system 100A according to an embodiment of the present disclosure. The test system 100A is included in some embodiments of the signal processing test system. The test environment or test system 100A includes automated test equipment (ATE) 110A and a device under test (DUT) (e.g., 120A, 130A, etc.). The ATE 110A includes a controller 111A, a test electronics 114A, a test or load board 119A, and a user interface (not shown). In some embodiments, the controller 111A is configured to directly test multiple DUTs (e.g., DUT 120A, 130A, etc.). The test electronics 114A is configured to test multiple DUTs. The controller 111A is coupled to the test electronics 114A and the test board or load board 119A. The load board 119A is configured to be communicatively coupled to the test electronics 114A and multiple devices under test (e.g., DUT 120A, DUT 130A, etc.).

[0071] In some exemplary implementations, the controller 111A includes a test mode selection module 112A. The test mode selection module selects between 1) a reduced header signal processing test mode process, 2) a reduced header with reference signal training mode test process, and 3) a header test mode process. Additional characteristics / features and operations of these modes are described in other parts of this specification. The test electronics 114A is communicatively coupled to the controller 111A. It will be appreciated that various factors may be utilized in making mode selections. For example, a portion of the DUT is tested in one mode, while another portion of the DUT is tested in another mode. In some embodiments, the header test mode is selected for one burst (e.g., a burst with a few OFDM symbols in the payload, etc.), while the reduced header signal processing test mode process is selected for another burst (e.g., a burst with many OFDM symbols in the payload, etc.).

[0072] The test electronics 114A includes a demodulation information determination module 115A and a demodulation module 117A, which are communicatively coupled to each other. The demodulation information determination module 115A collects information associated with demodulation operations, including determining signal processing information that is not otherwise included in the reduced header information. The demodulation module 117A performs demodulation operations based on information received from the demodulation information determination module 115A. In some embodiments, the test electronics 114A directs the testing of the DUTs and includes resources assigned to the respective DUTs. In some implementations, the test electronics 114A may include a Field Programmable Gate Array (FPGA). Other features / characteristics and operations of the test mode selection module 112A and the demodulation information determination module 115A are described in other parts of this description.

[0073] In some embodiments, test mode selection module 112A selects a reduced header signal processing test procedure and demodulation information determination module 115A determines signal processing information associated with a demodulation operation, where the signal processing information is not otherwise included in a header portion of a signal associated with the demodulation operation.

[0074] Various information associated with testing the DUT (e.g., selection of a test mode, test results, preliminary analysis results, reconfigured test information, test instructions, etc.) is communicated between the test device 110A and the user test interface. In some exemplary implementations, the user test interface includes a processing unit, a memory, and a user input / output component (e.g., a display, a keyboard, etc.). The memory may store test-related information, the processing unit may process the information, and the user input / output component may communicate information to and from the user.

[0075] In some embodiments, the DUT (e.g., 120A, 130A, etc.) is considered a signal processing component. The DUT 120A may be configured for final implementation in an end-use device 190A. In some embodiments, the DUT 120A is configured for final end-use implementation in a communication device or system, such as a cellular phone, an Internet of Things (IoT) device, or a device that complies with the Institute of Electrical and Electronics Engineers (IEEE) 802.11 wireless network protocol / standard, etc. The device 190A includes a transceiver 191A, a signal processing core 192A, a processor / microcontroller 193A, a memory storage device 195A (e.g., ROM / RAM, etc.), and an I / O interface 194A (e.g., digital interface pins, etc.). The signal processing core 192A includes an analog signal processing component 172A, a baseband component 172A, a register 173A, and a cache 174A. Although DUT 120A is able to access other resources and capabilities (e.g., memory / storage 195, processor / microcontroller 193A, etc.) when integrated into device 190A, these resources are generally not available to DUT 120A during testing before DUT 120A is integrated into device 190A.

[0076] DUT 120A is primarily directed to performing analog operations. In some exemplary implementations, DUT 120 is a radio frequency (RF) integrated circuit chip. In some embodiments, DUT 120A is directed to performing communication operations. DUT 120A can be configured to perform transceiver operations, analog signal processing, and the like.

[0077] In some embodiments, the DUT is an RF component that performs various aspects of communication signal transmission and reception operations, including performing up-conversion and down-conversion operations on the signal. In the transmission activity, the modulation information (e.g., in the form of a modulation signal, I and Q signals, etc.) is combined and up-converted to an RF signal by multiplying the carrier frequency generated by the local oscillator with the baseband modulation signal. In the transmission activity, the modulation information (e.g., in the form of a modulation signal, I and Q signals, etc.) is combined and up-converted to an RF signal by multiplying the carrier frequency generated by the local oscillator with the baseband modulation signal. It can be understood that the DUT can have various interface configurations (e.g., analog, digital, etc.) for coupling with the baseband component. The RF component can perform filtering (e.g., a portion of interpolation can be performed in the analog domain and the digital domain, etc.) to meet spectral mask requirements. In some embodiments, the novel test system and method described herein receives information based on captured samples of the up-converted transmitted communication signal and the down-converted received communication signal. The novel ability to accurately process payload symbols with reduced header information enables testing of DUTs that have limited memory resources to store captured samples that would otherwise be overloaded with samples from a large header portion.

[0078] Figure 1B 1 is a block diagram of two exemplary radio frequency (RF) integrated circuit DUTs according to embodiments of the present disclosure. DUT 150A includes mixer 151A, mixer 152A, amplifier 153A, amplifier 154A, mixer 181A, mixer 182A, adder component 183A, amplifier 184A, and local oscillator 155A. Mixer 151A is coupled to amplifier 153A, and mixer 152A is coupled to amplifier 154A. Mixer 181A and mixer 182A are coupled to adder component 183A, and adder component 183A is coupled to amplifier 184A. Local oscillator 155A is coupled to mixer 151A, mixer 152A, mixer 181A, and mixer 182A. The local oscillator provides an in-phase signal to mixers 151A and 181A, while also providing a 90 degree phase shifted quadrature signal to mixers 152A and 182A. A radio frequency (RF) input signal 157A is fed to mixers 151A and 152A. Amplifiers 153A and 154A provide analog output signals 158A to the baseband assembly. The analog input signal 188A from the baseband assembly is fed to mixers 181A and 182A, which in turn provide inputs to adder assembly 183A. Adder assembly 183A combines the in-phase portion of the signal with the quadrature phase portion of the signal and forwards the result to amplifier 184A. Amplifier 184A provides an RF output signal 187A.

[0079] DUT 150B includes mixer 151B, mixer 152B, amplifier 153B, amplifier 154B, mixer 181B, mixer 182B, adder component 183B, amplifier 184B, local oscillator 155B and digital RF data component 159B. Mixer 151B is coupled to amplifier 153B, and mixer 152B is coupled to amplifier 154B. Local oscillator 155B is coupled to mixer 151B, mixer 152B, mixer 181B and mixer 182B. The local oscillator provides an in-phase signal to mixers 151B and 181B, and also provides a 90 degree phase shifted quadrature signal to mixers 152B and 182B. Radio frequency (RF) input signal 157B is fed to mixers 151B and 152B. The outputs of amplifier 153B and amplifier 154B are coupled to digital RF data component 159B. Digital RF data component 159B provides digital output signal 158B to the baseband component. Digital input signal 188B from the baseband component is fed to mixers 181B and 182B, which in turn provide input to adder component 183B. Adder component 183B combines the in-phase portion of the signal with the quadrature-phase portion of the signal and forwards the result to amplifier 184B. Amplifier 184B provides RF output signal 187B.

[0080] It is understood that there are various test scenarios. There can be different types of DUTs with various configurations. In some embodiments, the DUT can be configured as a more complete device / system (e.g., integrated system, circuit board level, etc.), closer to the final end-use configuration. Figure 1C is a block diagram of an exemplary test environment or test system 100C according to some embodiments. The exemplary test environment or test system 100C is similar to the exemplary test environment or test system 100A, except that a device circuit board 190C is tested as a DUT similar to DUT 190A.

[0081] Figure 1CThe test environment or test system 100C includes automated test equipment (ATE) 110C and a device under test (DUT) (e.g., 190C, 199C, etc.). The ATE 110C includes a controller 111C, a test mode selection module 112C, a test electronics 114C, a demodulation information module 115C, a demodulation module 117C, a test or load board 119C, and a user interface (not shown). In some exemplary implementations, the device 190C includes a transceiver 191C, a signal processing core 192C, a processor / microcontroller 193C, a memory storage device 195C (e.g., ROM / RAM, etc.), and an I / O interface 194C (e.g., ATE digital interface pins, etc.). In some embodiments, the DUT 199C is an end-use product (e.g., a cellular phone, a device that complies with the IEEE802.11 wireless network protocol / standard, etc.). Part of testing a DUT (eg, DUT 190C, DUT 199C, etc.) is directed to testing analog components within the DUT (eg, RF chip, RF processor, etc.).

[0082] As the DUT configuration approaches the end-use device level, utilizing the described schemes (e.g., reduced header demodulation, etc.) brings several advantages. Selecting between modes (e.g., full header mode, reduced header mode, etc.) enables flexible testing and has the potential to reduce test time overall. As the DUT configuration approaches the end-use level, reduced header demodulation still brings several advantages. When the goal is to directly test analog components within the DUT, a shortened length test style flow that is more targeted to analog components can be utilized. Implementing tests isolated to analog components reduces the risk of other components corrupting test results. The ability to isolate testing also facilitates "partitioning" testing or directing testing to different DUT components at different times, which in turn helps to simplify debugging issues, etc.

[0083] In some embodiments, the DUT may include testing capabilities. Figure 2A2 is a block diagram of an exemplary DUT 200 according to an embodiment of the present disclosure. It is understood that DUT 200 is similar to DUT 120A. DUT 200 includes a boundary scan register 210, a core 220, and a test access port 270. Boundary scan register 210 includes a plurality of boundary scan cells (Boundary Scan Cell, BSC). The boundary scan cell is similar to boundary scan cell 215. Boundary scan cell 215 includes multiplexers (MUX) 211 and 214 and flip-flops 212 and 213. MUX 211 is coupled to flip-flop 212, flip-flop 212 is coupled to flip-flop 213, and flip-flop 213 is further coupled to MUX 214. Based on the shift DR signal, MUX 211 can select and forward the normal operation data input or forward the scan test data input as a scan output signal, and also forward it to flip-flop 212 for latching in response to clock DR. Flip-flop 212 is updated with information in response to the update DR signal.

[0084] MUX 214 selects and forwards data in or information from flip-flop 213 based on the mode control signal. Core 220 includes scan chain region A, scan chain region B, and scan chain region C. Scan chain A region includes a combinational circuit and a plurality of scan cells (SC) coupled together in a scan chain manner. The combinational circuit performs normal functions during task mode operation. The scan cell can act as a sequential circuit during task mode operation, and can also support test operations (e.g., scan-in, capture, scan-out, etc.) during test mode operation. Test information can be transmitted from one scan cell to another scan cell in the scan chain. It is understood that the DUT may also include a flip-flop that does not belong to the scan chain and a flip-flop dedicated to scan chain operation. Scan cell (SC) 270 includes a multiplexer 271 and a flip-flop 272. Based on the scan enable signal, MUX 271 can select a task mode operation data input or a scan test data input in response to a clock and reset signal and forward it to the flip-flop 272. Information is output from the flip-flop 272 to other task mode operation circuits and other scan chain components.

[0085] A test access port (TAP) 230 includes a TAP controller coupled to a test reset input, a test clock input, a test mode input, a MUX 233, an instruction register, a bypass register, and an identification register, which are coupled to a MUX 232. MUX 232 is also coupled to MUX 225, an additional capture memory 231, a test block, and a bond scan register. MUX 233 is also coupled to an instruction register, MUX 232, and a test data output. The test data input is coupled to a boundary scan register, a debug block, a test block, a scan chain A, a scan chain B, and a scan chain C. DUT 200 may be compatible with various standards (e.g., JTAG, IEEE 1149.1, etc.).

[0086] Typically, without the novel schemes described in this specification, there are not enough memory resources in the DUT (e.g., scan test chain resources, capture memory resources, and waveguide generation resources, etc.) to conveniently support testing of various functions (e.g., communication functions, demodulation operations, etc.). Including a large number of dedicated circuits and other components for testing analog signal processing components encounters significant problems and challenges (e.g., limited chip space, relatively high costs for the limited number of times the components can be tested, etc.). In some embodiments, with respect to the DUT that primarily performs analog signal processing during normal non-test operations, signals are processed and forwarded to other components in the system without "storing" intermediate or final results on / in the analog DUT. The analog processing components do not include too many normal operating components (e.g., storage capabilities, flip-flops in scan chains, etc.) that can be used for normal / test dual operations. As technology and communication protocols advance, the problems and issues associated with the "lack" of storage capabilities available for test operations (e.g., capture, scan chains, etc.) become more severe.

[0087] Figure 2B 2 is a block diagram of an exemplary automatic test system (ATE) 250 according to an embodiment of the present disclosure. The automatic test system 250 includes a digital test function module 251, an arbitrary waveform generation module 252, an arbitrary waveform digitization (AWD) sequencer 253, a DC resource 254, and a time measurement resource 255, all of which are coupled to a master clock 257. The digital test function module 251 includes a vector memory coupled to a real-time comparator (which is coupled to a full memory) and a drive formatter, and an edge timing component. The edge timing component is coupled to a receive formatter, which is coupled to a digital capture memory. The pin electronics are coupled to the drive formatter, the receive formatter, the MUX time measurement, and the DC test unit.

[0088] The arbitrary waveform generation module 252 includes an arbitrary waveguide generation (AWG) component, which is coupled to the AWG sequencer component, waveform source memory, and amplifier / filter, which is in turn coupled to the SFG and MUX. The MUX is coupled to the DC offset component, test head No. 1 and test head No. 2. The arbitrary waveform digitization (AWD) sequencer 253 includes a waveguide digitizer coupled to the multi-mode modulation / demodulation parameter determination module, a digitizer sequencer, a waveform capture memory, and an amplifier / filter coupled to the MUX. The MUX is coupled to the test head No. 1 and the test head No. 2. The DC resource 254 includes a DC data memory and a time measurement resource module 255, which includes a time measurement unit / time interval analyzer.

[0089] In some embodiments, there are not enough memory resources (e.g., capture memory resources, waveguide generation resources, etc.) to conveniently support the testing of various functions (e.g., communication functions, demodulation operations, etc.). As more functions are integrated into the DUT and communication protocols become more complex, the testing of the DUT becomes more complex and the need for more capable test systems increases. Testing is further complicated by the need to test many DUTs in parallel at the same time. Although the test resources of the ATE may be considerable, they are not unlimited, and assigning resources for all different test activities becomes expensive and impractical, which complicates the assignment of test resources. Therefore, in traditional test systems, there is not enough memory available for some activities on an individual DUT basis (e.g., arbitrary waveguide generation, etc.).

[0090] The novel systems and methods described herein enable ATE systems to perform testing of DUT modulation and demodulation performance that would otherwise be impractical or impossible. The novel systems and methods also improve ATE system performance. Testing efficiency is improved by reducing the need for large test patterns associated with long header information (e.g., which would otherwise be time consuming, inefficient, error-prone, etc.). The amount of ATE resources (e.g., memory resources, etc.) that would otherwise be required to handle large test patterns is also reduced.

[0091] Figure 3A1 is a flow chart of an exemplary multi-mode modulation / demodulation parameter determination method 300 including a header reduction process according to an embodiment of the present disclosure. The multi-mode modulation / demodulation parameter determination method 300 is included in some embodiments of the signal processing test method. In an exemplary implementation, the multi-mode modulation / demodulation parameter determination method 300 is directed to testing operations in a radio frequency (RF) component (e.g., up-conversion operation, down-conversion operation, initial front-end transmission operation, initial front-end reception operation, etc.). The multi-mode modulation / demodulation parameter determination method 300 easily implements effective testing of the performance of the RF component in modulating and demodulating communication signals while reducing header information.

[0092] In block 310, a test mode selection process is performed. The test mode selection process enables flexible and efficient response to various test scenarios. The test mode has the ability to effectively solve different demodulation problems, such as communication bursts with very long headers, etc. Additional descriptions of the operation of the test mode selection process are presented in other parts of this specification (e.g., Figure 7 description of the test mode selection process shown, etc.).

[0093] exist Figure 3A In block 320, a demodulation information determination process is performed. In some embodiments, various types of demodulation information (e.g., timing information, frequency error, equalization value, etc.) are determined based on the reduced header mode operation. In some exemplary implementations, the determination of the demodulation information does not need to rely on the header information traditionally. Additional descriptions of the operation of the demodulation information determination process are introduced in other parts of this specification (e.g., blocks 730, 740, 750, 800, 1600, etc.). In block 330, full demodulation is performed. In some embodiments, full demodulation includes determining various parameters associated with demodulation. These parameters may include full equalizer values, frequency error values, and sampling clock errors, error vector magnitudes (EVM), etc. Additional descriptions of full demodulation operations are introduced in other parts of this specification.

[0094] In some embodiments, full demodulation is performed from the perspective of the DUT. In some exemplary implementations, the DUT is a radio frequency (RF) integrated circuit (e.g., similar to DUT 150A and 150B), and full demodulation is demodulation (158A, 158B) that produces an output signal of the DUT. It is understood that additional demodulation that is not considered part of full demodulation can be performed on the output signal of the DUT. In some exemplary implementations, additional demodulation operations (e.g., FFT, data bit decoding, etc.) may be performed on the communication signal by back-end baseband digital signal processing, but these operations are not considered part of full demodulation from the perspective of the radio frequency (RF) integrated circuit DUT. In other embodiments, additional demodulation operations (e.g., FFT, data bit decoding, etc.) may be performed on the communication signal by back-end baseband digital signal processing, but these operations are considered part of full demodulation (e.g., from the perspective of a different DUT (e.g., 190C, 199C, etc.)).

[0095] Figure 3B is a block diagram of an exemplary multi-mode modulation / demodulation parameter determination test environment. The multi-mode modulation / demodulation parameter determination test environment includes a test system 390 (e.g., similar to ATE 110A, 110C, etc.) and a DUT 391 (e.g., similar to DUT 120A, 150A, 150B, etc.). The test system 390 directs the testing of the DUT 391, wherein various types of signal processing tests are performed. In some embodiments, the test system 390 provides simulation test information to the DUT 391 and receives captured test information (e.g., information associated with a real in-phase (I) signal, a virtual quadrature phase (Q) signal, etc.). It is understood that for EVM, the test system 390 can direct the testing of transmitter RF output characteristics and receiver RF input characteristics. The DUT 391 performs operations associated with the receiving module 341A, the carrier demodulation module 342A, the transmitting module 341B, and the carrier modulation module 342B. The test system 390 includes a multi-mode modulation / demodulation parameter determination module 370 and a control module 371. The test system 390 performs operations associated with the cyclic prefix removal module 344, the Fast Fourier Transform (FFT) module 345, the equalization module 346, and the message decoder module 347. In some embodiments, portions of the operations of the carrier demodulation module 342A are performed in the test system 390. The reception module 341 performs various activities associated with the initial reception of communications (e.g., carrier bandpass filters, synchronization operations, automatic gain control, etc.).

[0096] The carrier demodulation module 342A performs various operations associated with demodulating the carrier frequency (e.g., local oscillator-based demodulation, coordinated 90-degree demodulation into in-phase (I) / "real" signal components and quadrature (Q) / "imaginary" signal components, etc.). The carrier modulation module 341B similarly performs various operations associated with modulating the carrier frequency. In some embodiments, operations associated with the receiving module 341A, the carrier demodulation module 342A, the transmitting module 341B, and the carrier modulation module 341B are performed by transceiver components and analog processing components (e.g., 191A, 172A, etc.).

[0097] Figure 3B The multi-mode modulation / demodulation parameter determination module 370 ascertains various modulation / demodulation parameters. In some embodiments, the multi-mode modulation / demodulation parameter determination module 370 performs a multi-mode modulation / demodulation parameter determination method. In some exemplary implementations, the multi-mode modulation / demodulation parameter determination method is similar to the method 300. The multi-mode modulation / demodulation parameter determination module 370 receives input from the test system 390. In some embodiments, the input indicates a test mode selection. The operations of the multi-mode modulation / demodulation parameter determination module 370 may be performed in the test system 390.

[0098] The cyclic prefix removal module 344 removes the cyclic prefix added to the signal (e.g., at the transmission source, etc.). The fast Fourier transform (FFT) module 345 transforms the signal into a signal corresponding to the discrete Fourier series configuration. The equalization module 346 performs an equalization operation on the signal based on the received information (e.g., inverse estimation value, etc.). The multi-mode modulation / demodulation parameter determination module 370 performs a data decoding operation (e.g., QAM demodulation / desampling operation, parallel to serial conversion, and MUX operation, etc.).

[0099] The message decoder module 347 performs various demodulation operations. In some embodiments, the message decoder module 347 outputs a data stream corresponding to the original transmitted data. In some exemplary implementations, the message decoder module 347 decodes the data symbols (e.g., QAM demodulation / desampling data constellation point information, and parallel to serial multiplexing (MUX) to concatenate logical bits corresponding to the constellation point information, etc.).

[0100] Communication information is organized in the form of information "blocks" that correspond to a portion of the signal communication (e.g., a header portion, a payload or body portion, etc.). In some exemplary implementations, the communication of information blocks is performed according to a protocol (e.g., a communication protocol, a network protocol, a storage protocol, etc.) that includes a definition of the organization and configuration of the blocks and information. In some embodiments, the information includes a header portion and a data / payload portion. In some embodiments, the communication protocol configures the information according to a communication protocol layer, and the header portion includes supplemental information associated with the protocol layer (e.g., signal processing related parameters, constants, metadata, etc.), and the data payload portion includes data / information from another protocol layer.

[0101] In addition, the communication protocol layer is organized by the communication protocol layer hierarchy. It is understandable that there can be several layers in the communication protocol layer hierarchy. In some exemplary implementations, the protocol layer is organized from the layer for the configuration of user / host application information / data to the layer for the configuration of the information actually sent / received on the physical communication medium, with multiple layers in between. In some embodiments, the relative position of each layer relative to each other in the hierarchy is called a higher layer or a lower layer. The layer for the configuration of user / host application information / data is called a higher layer, and the layer for the configuration of the information actually sent / received on the physical communication medium is called a lower layer. In some exemplary implementations, the layer for the configuration of user / host application information / data is called a lower layer, and the layer for the configuration of the information actually sent / received on the physical communication medium is called a higher layer.

[0102] The header portion is information transmitted before the payload portion. It will be appreciated that some protocols have different names for the information transmitted before the data / payload portion (e.g., preamble, header, etc.). To avoid confusion, when referred to herein, header information includes information received in the preamble portion of a signal, information received in the header portion of a signal, and a combination of information received in both the preamble portion and the header portion of a signal.

[0103] In some embodiments, the signal is configured in accordance with a protocol data unit (PDU) of a communication protocol. In some exemplary implementations, a PDU is a single information unit that is communicated (e.g., sent, received, etc.) between similar entities (e.g., entities considered in similar protocol levels, peer entities of a network, etc.). A PDU includes a portion of information associated with a header portion / segment and information associated with a data / payload portion or segment. The data / payload portion may be considered a service data unit (SDU). In some exemplary implementations, a service data unit is an information unit that is transmitted between a higher communication protocol level (e.g., a level closer to a user / host application level, etc.) and a lower communication protocol level (e.g., a level closer to a physical communication level, etc.) so as to provide services / encapsulation by the lower communication protocol level. It is understandable that a first communication protocol layer payload portion (e.g., from the perspective of a first communication protocol layer, etc.) may include information configured as a second communication protocol layer header information and a second communication protocol layer payload information in a second communication protocol layer. The first communication protocol layer is a higher communication protocol layer, and the second communication protocol layer is a lower communication protocol layer.

[0104] It is understood that the novel scheme described is flexible because it can be configured to be implemented in conjunction with various communication protocols. In some embodiments, the novel scheme described is compatible with the IEEE 802.11 series of wireless network protocols / standards (e.g., 802.11a / b / g / n / ac / ax / be, etc.). In other embodiments, the novel scheme described is compatible with the WIFI series of wireless network protocols / standards (e.g., WiFi4, 5, 6, 7, etc.). The novel scheme described can also be compatible with communication hierarchical models / suites (e.g., Open Systems Interconnection (OSI), Internet communication suites, Transmission Control Protocol / Internet Protocol (TCP / IP), etc.). The basic frame organization / configuration of the 802.11 series burst includes a header portion and a subsequent data / payload portion (which includes OFDM symbols).

[0105] Figure 4A4 is a block diagram of an exemplary PDU 401A frame or packet in accordance with some embodiments. The PDU 401A is configured in accordance with a communication protocol. The PDU 401A includes a header portion / segment 402A and a data / payload portion 403A. The header portion / segment 402A and the data / payload portion / segment 403A include information organized in fields. It is understood that the PDU 401A can be viewed as a communication frame, a communication packet, etc. It is understood that the communication information can be configured with other fields not shown (e.g., a tail portion / segment at the end of the PDU, etc.).

[0106] Figure 4B 401B is a block diagram of an exemplary PDU frame or packet for different communication protocol / model layers according to embodiments of the present disclosure. PDU 401B is a block diagram of an exemplary frame for the second communication protocol layer 409A. In some exemplary implementations, the communication configuration (or "frame") 401B includes a header portion / segment 402B and a data / payload portion 403B. PDU 401C is a block diagram of an exemplary frame for the first communication protocol layer 409B. In some exemplary implementations, the communication configuration (or "frame") 401C includes a header portion / segment 402C and a data / payload portion 403C.

[0107] As information "moves" from one layer to another in the communication protocol hierarchy, the information is processed as required by each layer. Processing often involves adding or deleting header information associated with the layer. Whether header information is added or deleted typically depends on whether the overall direction is higher or lower in the communication protocol hierarchy. In some embodiments, header information associated with the lower level is added when a PDU from a higher level is moved to a lower level to create a "new" PDU at the lower level. In some embodiments, a higher level PDU is considered to be a lower level service data unit (SDU) encapsulated by (e.g., "wrapped inside," etc.) a lower level PDU. Payload segment 403C includes SDU 404C (also known as PDU 401B from layer 409A) and is encapsulated with header segment 402C to form a "new" PDU 401C.

[0108] Whether the communication information / signal includes reduced header information / does not include header information is relative to / depends on the perspective of the communication protocol layer. From the perspective of one communication protocol layer, if the communication / signal lacks some or substantially all header information, then the communication / signal can be considered to be reduced header / headerless; while from the perspective of another communication protocol layer, the communication information can be considered to include header information or have a header. In some exemplary implementations, even if the SDU 404C includes header information from the header segment 402B of the PDU 401B, the payload segment 403C including the SDU 404C (also known as the PDU 401B) is still considered to be headerless. In some embodiments, if the header segment 402C is missing (e.g., not added to the information, etc.), the communication signal is also considered to be headerless. In some embodiments, the data / payload portion 403C includes the communication configuration PPDU 401B (which in turn includes the header portion / segment 402B and the data / payload portion 403B).

[0109] The reduced header information demodulation process of the present disclosure operates on the payload portion of the PDU. In some exemplary implementations, the payload portion of the PDU is considered a "headerless" process from the perspective of the communication protocol layer associated with the PDU. In some exemplary implementations, the reduced header information demodulation process operates on information that is headerless from the perspective of the first communication protocol layer 409B (the information includes data payload segment 403C information instead of information from header segment 402C). From the perspective of the protocol layer (e.g., 409B, etc.), the payload information (e.g., 403C, etc.) is considered to be "headerless", while the payload information includes "header" (e.g., 402B) information from another protocol layer.

[0110] It is understood that a communication protocol layer may have multiple sublayers. The sublayers have different functions and perform different operations associated with each communication protocol layer. Figure 4C Various exemplary organizations and configurations of information in a PPDU (also referred to as a "frame") are included in accordance with some embodiments.

[0111] Communication configuration 410A is a block diagram of an exemplary frame according to some embodiments. Communication configuration 410A is compatible with a physical protocol data unit (PDU) frame. Frame 410A includes a header portion / segment 420A and a data / payload portion 430A. Header portion / segment 420A and data / payload portion / segment 430A include information organized in fields.

[0112] Communication configuration 410B is a block diagram of an exemplary frame according to some embodiments. Frame 410B is compatible with a physical layer protocol data unit (PPDU). Frame 410B includes a header portion / segment 420B and a data / payload portion / segment 430B. In some embodiments, header portion / segment 420B includes a preamble field 421B and a signal field 422B.

[0113] Frame 410C is a block diagram of an exemplary communication information organization and configuration (also referred to as a "frame") in accordance with some embodiments. Frame 410C is compatible with a physical layer protocol data unit (PPDU). Frame 410C includes a header portion / segment 420C and a data / payload portion / segment 430C. In some embodiments, data / payload portion / segment 430C includes packet 430C and packet 450C. Packet 440C includes packet header portion / segment 441C and packet data / payload portion / segment 442C. Packet 450C includes packet header portion / segment 451C and packet data / payload portion / segment 452C.

[0114] Frame 410D is a block diagram of an exemplary communication information organization and configuration (also referred to as a "frame") in accordance with some embodiments. Frame 410D is compatible with a physical layer protocol data unit (PPDU). Frame 410D includes a header portion / segment 420D and a data / payload portion / segment 430D. In some embodiments, header segment 420D includes a preamble field 421D and a physical header 422D.

[0115] In some exemplary implementations, the data / payload portion / segment 430D includes a physical layer service data unit (SDU) 440D (also known as an MPDU) and a physical layer service data unit (SDU) 450D (also known as an MPDU). The physical layer service data unit (SDU) 440D includes a MAC layer PDU (MPDU). The MPDU 440D includes a MAC header portion / segment 441D and a MAC data / payload portion / segment 442D. The MPDU 450D includes a MAC header portion / segment 451D and a MAC data / payload portion / segment 452D. In some embodiments, the medium access control (MAC) layer protocol data unit (PDU) is a physical layer service data unit (SDU).

[0116] Figure 4DIncluding exemplary organization and configuration of information according to some embodiments. Communication configuration or frame 410F is a block diagram of an exemplary frame according to some embodiments. Frame 410F is compatible with frame configuration or physical layer protocol data unit (PPDU) configuration. Frame 410F includes a header part / segment 420F and a data / payload part / segment 430F. In some embodiments, the header part / segment 420F includes a preamble field 421F and a signal field 422F. The data / payload part / segment 430F includes orthogonal frequency division multiplexing OFDM symbols 441F, 442F to 448F. It can be understood that the modulation form of the OFDM symbol of the lower protocol level may include header information associated with the higher protocol level. OFDM symbols are configured for communication in the physical layer of the communication protocol, and some of the OFDM symbols include header information from the protocol layer (e.g., link layer, transport layer, etc.), although from the physical layer perspective, they are considered to be headerless payload data.

[0117] Figure 4E is a block diagram of different exemplary signal physical layer protocol data unit (PPDU) organizations / configurations (also referred to as "frames") according to the IEEE 802.11 family of wireless network protocols / standards, in accordance with some embodiments. The PPDU includes various physical layer header portions and a physical layer data portion. The header portion includes various training fields, which include reference training symbols, and a signal field (SIG) includes rate, length, and parity information. It will be appreciated that as new communication protocol organizations / configurations of the IEEE 802.11 family change (e.g., when a new version is released, etc.), the size of the header portion can grow significantly.

[0118] The PPDU configuration 451 complies with the IEEE 802.11a / g communication protocol, and the header includes a legacy short training field (L-STF), a legacy long training field (L-LTF), and a legacy signal field (L-SIG). On the other hand, the PPDU configuration 452 complies with the IEEE 802.11n high throughput (HT) communication protocol, and the header includes a legacy short training field (L-STF), a legacy long training field (L-LTF), a legacy signal field (L-SIG), a high throughput signal field (SIG), a high throughput short training field (STF), and 1 to 4 high throughput long training fields (HT LTF). The PPDU configuration 453 complies with the IEEE 802.11ac very high throughput (VHT) communication protocol, and the header includes a legacy short training field (L-STF), a legacy long training field (L-LTF), a legacy signal field (L-SIG), a very high throughput signal field-A (SIG-A), a very high throughput short training field (STF), 1 to 8 very high throughput long training fields (VHT LTF), and a very high throughput signal field-B (SIG-B).

[0119] In addition, PPDU configuration 454 complies with the IEEE 802.11ax high efficiency (HE) communication protocol, and the header includes a legacy short training field (L-STF), a legacy long training field (L-LTF), a legacy signal field (L-SIG), a repeated non-HT signal field (RL-SIG), a high efficiency signal field-A (SIG-A), a high efficiency short training field (STF), and 1 to 8 high efficiency long training fields (VHT LTF). Finally, PPDU configuration 455 complies with IEEE 802.11be (HET) and is a very high throughput communication protocol, and the header includes a legacy short training field (L-STF), a legacy long training field (L-LTF), a legacy signal field (L-SIG), a repeated legacy signal field (RL-SIG), a universal signal field (U-SIG), a high efficiency signal field (EHT-SIG), a high efficiency short training field (EHT-STF), and a high efficiency long training field (EHT-LFT). The EHT-LFT symbol duration depends on the GI+LFT size.

[0120] In some embodiments, the reduced header information demodulation test system and method according to the present disclosure is compatible with a subcarrier communication scheme. In some exemplary implementations, the subcarrier communication scheme includes multiple tones organized in a communication channel. These tones can be organized and configured according to the IEEE 802.11 wireless network protocol / standard.

[0121] There are at least two aspects of the ever-changing communication protocol standards that pose significant challenges to test operations. The first aspect is that the header portion and the corresponding header information grow with the new protocol standards, which means that more information needs to be sampled and captured during testing. The second aspect is that the bandwidth becomes larger, resulting in an increase in the sampling rate. In some exemplary implementations, the DUT requires 400 samples to test a signal that complies with OFDM 802.11a, and requires 15360 to 24320 samples to test a signal that complies with OFDM 802.11be. As shown above, many communication DUTs have limited resources (e.g., memory, scan test units, etc.) for test operations, and the increase in information required for testing (e.g., information associated with sampling capture, etc.) overwhelms the limited resources. The limited resources become full with information about the header portion, and therefore cannot cope with appropriate testing of the payload portion. The reduced header information demodulation test system and method according to the present disclosure overcomes these problems and advantageously achieves appropriate testing of the payload portion. The memory of the DUT and ATE system is also less stressed when storing information associated with the waveform (eg, AWG component output, etc.).

[0122] It is understood that different power levels may be assigned to different RUs, and that RUs may be assigned on various carrier bandwidths. There are more tones / subcarriers in a layer than there are tones assigned to user data communications. Some tones / subcarriers may be used for control operations (e.g., pilot, guard / no-space, etc.). It is understood that RUs and tones may be organized and configured in accordance with IEEE 802.11 wireless networking protocols / standards.

[0123] Figure 5Ais a block diagram of an exemplary signal configuration according to some embodiments. The tones are arranged in different levels based on the number of tones included in a resource unit (RU). In some exemplary implementations, a resource unit is used to represent a group of subcarriers (e.g., tones, etc.) used in a communication (e.g., a downlink transmission, an uplink transmission, etc.). For example, level 510 includes 37 RUs (1A to 37A), each of which includes 26 tones; level 520 includes 16 RUs (1B to 16B), each of which includes 52 tones; level 530 includes 8 RUs (1C to 8C), each of which includes 106 tones; level 540 includes 4 RUs (1D to 4D), each of which includes 242 tones; level 550 includes 2 RUs (1E and 2E), each of which includes 484 tones; and level 570 includes 1 RU (1F), which includes 996 tones.

[0124] In some embodiments, the subcarriers are associated with a frequency bandwidth or range. The frequency bandwidth is defined by a communication protocol (e.g., IEEE 802.11 wireless network protocol / standard, etc.). In other embodiments, the reference signal is associated with a known predetermined defined characteristic. Each received reference signal characteristic is determined and compared to the corresponding predetermined defined characteristic.

[0125] Figure 5B is a block diagram of an exemplary subcarrier spectrum and corresponding bins according to an embodiment of the present disclosure. Each frequency bin corresponds to a subcarrier. User subcarriers and corresponding bins are distributed throughout the spectrum (e.g., user 1 subcarrier, user 2 subcarrier, etc.). The block diagram also indicates the subcarrier positions / spacing of reference tones / signals (e.g., pilot tones, etc.) according to some embodiments. Between the pilot bins, there are data bins. At both ends of the spectrum, there are subcarriers / bins that act as guard subcarriers (e.g., to help mitigate interference from other spectra). In some exemplary implementations, there are non-pilot tone empty subcarrier bins at the center carrier frequency value.

[0126] Figure 5C is a graphical block diagram of an exemplary transmission of OFDM symbol tones / signals in accordance with an embodiment of the present disclosure. The transmission includes OFDM symbols 0, 1, and 2 concatenated in a "burst" frame sequence in the time domain. An OFDM burst includes an OFDM symbol. An OFDM symbol includes data bit streams 1 to n assigned to subcarriers 1 to N bins, respectively. A modulated subcarrier is equal to a point in frequency and time. An IFFT creates an OFDM waveform from the OFDM subcarriers. An OFDM symbol includes the IFFT OFDM waveform plus a guard interval.

[0127] The novel scheme introduced enables the start of each OFDM symbol 0, 1 and 2 to be determined based on information in the OFDM symbol in the payload portion of the "burst" frame, without relying on information from the header portion of the "burst" frame. It will be appreciated that the novel scheme described herein is compatible with implementations in various communication protocols (e.g., OFDM protocols, OFDMA protocols, etc.).

[0128] Figure 5D 1 is a block diagram of an exemplary OFDM symbol payload portion transmission with reduced header information according to an embodiment of the present disclosure. As previously shown, header information (e.g., preamble information, reference information, etc.) is often used to correct (e.g., equalize, etc.) problems in communication. OFDM symbol payload portion transmission 505 includes OFDM symbols 501, 502, and 503. OFDM symbols 501, 502, and 503 are configured in a cyclic pattern. In some embodiments, payload data is configured without preamble training. For example, the beginning of OFDM symbol 501 loops to the end of OFDM symbol 503 reference symbol. The pattern is considered to be continuous (e.g., no beginning and no end, etc.). OFDM symbol 502 includes a cyclic prefix portion 502A and an end portion 502B located at the beginning of OFDM symbol 502. Cyclic prefix portion 502A is a copy of end portion 502B. OFDM symbol 501 includes a cyclic prefix portion and an end portion 501B. The OFDM symbol 503 includes a cyclic prefix portion 503A located at the beginning of the OFDM symbol 503 and an end portion.

[0129] Figure 5E59 is a block diagram of various exemplary subcarrier configuration assignments according to an embodiment of the present disclosure. The dots or circles represent various subcarriers within the communication bandwidth. The solid dark circles represent pilot subcarrier signals, and the central transparent circles represent other subcarrier signals (e.g., data subcarriers, null subcarriers, etc.). The Y-axis corresponds to the frequency values ​​of the various subcarriers, and the X-axis represents the transmission of the subcarriers over time. Different pilot subcarrier configurations (e.g., block, comb, scattered, etc.) can be implemented to address different conditions or problems. Although the pilot signal provides valuable information about the performance of the DUT, if all subcarriers are always designated as pilots, communication of other data cannot be performed. Thus, the configuration of the pilot subcarrier is often a balanced trade-off between different objectives. In configuration 591, all subcarriers in the bandwidth are intermittently used as pilot subcarriers and provide an indication of all subchannel conditions. In configuration 592, intermittent subcarriers in the bandwidth are used as pilot subcarriers, which continuously provide an indication of subchannel conditions for these subcarriers. In configuration 593, one pilot subcarrier information is continuously transmitted, while other pilot subcarrier information is intermittent in frequency and time. The pilot subcarrier signal is a reference signal having a characteristic (e.g., BPSK modulation, etc.) that resists misinterpretation due to communication conditions (e.g., channel conditions, device oscillation differences, etc.).

[0130] Various subcarrier configurations are predetermined (e.g., known by ATE, etc.). The subcarrier configuration protocol may be publicly known (e.g., in accordance with a published industry standard, IEEE 802-11 series of protocols, etc.), or privately known (e.g., a private interpretation of an industry standard, a confidential configuration, a trade secret, etc.). The subcarrier configuration information may be accessed by the ATE and utilized to perform various novel reduced header systems and methods described in other portions of this specification. In some embodiments, the subcarrier configuration may be utilized to extract information (e.g., information related to timing, frequency error, ideal values, equalizers, etc.) from the payload portion of the communication. In some exemplary implementations, the information is extracted from a complex payload portion without relying on the availability of header information.

[0131] The intention is to accurately transmit the information in the original data stream. Figure 5C An exemplary data flow is illustrated in FIG. In the process of being communicated, the data is modulated according to several constellations. Errors or deviations from ideal values ​​in various constellations are often associated with communication problems (e.g., insufficient channel characteristics, frequency response characteristics, scattering, attenuation, power loss with distance, etc.).

[0132] Fig. 6A6 is a block diagram of several exemplary constellation diagrams associated with signal communication in accordance with embodiments of the present disclosure. Black dots represent symbols in ideal locations (e.g., ideal I and Q diagrams). Constellation diagram 610 is a BPSK diagram, which has 2 possible symbols and 1 information bit per symbol. Constellation diagram 620 is a QPSK diagram, which has 4 possible symbols and 2 information bits per symbol. Constellation diagram 630 is a 16QAM diagram, which has 16 possible symbols and 4 information bits per symbol. It will be appreciated that various other QAM configurations are possible (e.g., 64QAM, 256QAM, 1024QAM, etc.).

[0133] Figure 6B 6 is a block diagram of several exemplary constellation errors associated with signal communication in accordance with some embodiments. The constellation includes ideal symbol positions (e.g., 640, 650, 670, 680, etc.) shown as solid black dots and symbol positions associated with transmitted signals (e.g., 641, 642, 674, etc.) shown as hollow dots. The constellation shows an ideal or reference vector 690 and effort vectors 671 and 672.

[0134] Figure 7 7 is a flow chart of an exemplary test mode selection process 700 in accordance with an embodiment of the present disclosure. The test mode selection process 700 provides a flexible and adaptable selection between test modes (e.g., including head mode, reduced head training mode, reduced head mode, etc.). The test mode selection process 700 enables the ATE to perform a variety of test scenarios with different test characteristics and capabilities. In some embodiments, the selection enables "backward" compatibility with traditional test schemes, and also enables the implementation of novel test schemes described herein that would otherwise be impractical or impossible in traditional test schemes.

[0135] In block 710, a selection trigger is received. The selection trigger may be based on the communication protocol, or the overall test scheme, etc. You may want to do some testing of the DUT with a signal with a full header, and then do some testing of the DUT with another signal with a reduced header. You may want to get a statistical sampling of the full header processing capabilities of the DUT, and then use the reduced header to increase the overall throughput. For example, first test whether the header information portion is properly processed / stored in the limited chip memory, and then do a second "round" to see if the payload is processed / stored correctly.

[0136] In block 720, a test mode is determined based on the received trigger information. In response to selecting the trigger at 720, the capabilities of the different available test modes are taken into account. In some embodiments, selecting the trigger may indicate that the first DUT does not include sufficient memory to handle the testing of the communication burst with large header information. In some embodiments, when the DUT fails a first round of testing, the failure indication may serve as a trigger to perform a second round of testing using a different test mode.

[0137] At block 730, a reduced header mode test procedure is selected. In some embodiments, the DUT does not include sufficient resources (e.g., memory, etc.) to efficiently perform demodulation testing. When the communication protocol specifies relatively large header information that exceeds the ability of the DUT to adequately respond to the test scenario, the reduced header mode test procedure may be selected at 730 to overcome issues associated with the large amount of header information.

[0138] In block 740, a reduced header with reference signal mode test procedure is selected. In some embodiments, the reduced header with reference signal mode test procedure is selected as a secondary test. In some exemplary implementations, the reduced header mode test procedure is selected for a first round of testing on the DUT, and the reduced header with reference signal mode test is selected for a second round of testing. Performing the second round of testing using a different test mode may identify some anomalies that were not found in the first round of testing. These anomalies may be due to test characteristics of the first test mode, while the second test mode is less likely to be affected by such characteristics.

[0139] In block 750, a head mode test process is selected. In some embodiments, the head mode test process may produce more reliable results for certain complex test scenarios. In test scenarios requiring very high QAM demodulation, the results of the head mode test process may be more reliable than the reduced head mode test process and the reduced header with reference signal mode test process. The reduced head mode test process 800 is included in the demodulation determination process (e.g., similar to block 320, etc.).

[0140] Figure 88 is a block diagram of an exemplary reduced header mode test process 800 according to an embodiment of the present disclosure. In some embodiments, the reduced header mode test process 800 is included in a reduced header communication signal processing test method. The reduced header mode test process is utilized when reference signal information is reduced / unavailable. In some exemplary implementations, there is no reference signal to compare with the captured signal (e.g., determine / calculate impairments, etc.). The reduced header mode test process is utilized when the receiving component (e.g., DUT, etc.) has reduced information about the received signal (e.g., reduced modulation related information, header information, preamble information, signal configuration information, etc.). In some exemplary implementations, the reduced header (information) does not include various information fields (e.g., short training field, long training field, synchronization (Sync) field, header field, signal field, service field, modulation selection bit / field, rate field, etc.). In other exemplary implementations, a portion of the fields are included in the reduced header (information). The received information is less than what would otherwise be available in a normal field / non-test situation.

[0141] In block 810, reduced header mode test process guidance is accessed (e.g., no header no reference signal, etc.). In some exemplary implementations, the reduced header mode test process guidance is based on a selection of a reduced header mode test process (e.g., similar to the selection in block 710, etc.). This selection can be made based on various conditions (e.g., the DUT does not have sufficient resources to handle testing of communications with full header information, a smaller test pattern for testing payloads with reduced header information is desired, multiple rounds of testing with different test characteristics are desired, etc.).

[0142] In block 820, a reduced header demodulation information determination process is performed. In some embodiments, the reduced header demodulation information determination process determines information to be used for testing modulation / demodulation operations (e.g., signal processing operations, etc.). In some exemplary implementations, the reduced header demodulation information determination process includes blocks 821, 822, 823, 824, 825, and 826.

[0143] In block 821, an autocorrelation of a cyclic prefix in the signal is performed. In some embodiments, the signal is a cyclic signal (e.g., similar to Figure 5D In some exemplary implementations, the communication protocol corresponds to a communication protocol standard in the IEEE 802.11 wireless network protocol / standard family. In some embodiments, a peak search function is performed on the result of the autocorrelation.

[0144] In block 822, start timing of symbols in the signal is identified based on the results of the autocorrelation from block 821, where the symbols are defined by the communication protocol. The symbols may include orthogonal frequency division modulation (OFDM) symbols. In some exemplary implementations, the start and end positions / timing of the symbols relative to each other are identified (e.g., the start and end positions of one OFDM symbol relative to the start and end positions of other OFDM symbols, etc.).

[0145] In block 823, an initial coarse frequency error correction is determined based on the results of the autocorrelation from block 821. Phase differences and coarse frequency errors may also be determined by analysis of peaks in the autocorrelation results. In some embodiments, the difference in peak position from the expected peak position may indicate a phase difference and a corresponding frequency error. In some exemplary implementations, the initial coarse frequency error correction is determined by reference to Fig.9A and Fig. 9B As described in other parts of this description, the initial coarse frequency error correction can be an average of the individual frequency error corrections.

[0146] In block 824, a group of bins of the signal is established, wherein the group of bins includes a pilot bin and a data bin. The group of bins corresponds to a group of subcarriers associated with the signal, wherein the pilot bin corresponds to a pilot subcarrier in the group of subcarriers, and the data bin corresponds to a data subcarrier in the group of subcarriers. In some exemplary implementations, a fast Fourier transform (FFT) operation is performed on a portion of the signal associated with the OFDM symbol, and the result is used to establish the group of bins.

[0147] In block 825, identification of the leading bins is extracted according to the definition of the leading subcarriers defined by the communication protocol. In some embodiments, identification of the leading bins includes identifying the positions of the leading bins relative to each other and other bins in the group of bins. It is understood that the identification and definition of the configuration and positions of subcarriers (e.g., leading subcarriers, data subcarriers, null subcarriers, etc.) relative to each other can vary (e.g., as FIG. 5A to FIG. 5E description in the specification, the description in other parts of this specification, etc.).

[0148] In block 826, ideal constellation values ​​and ideal symbol values ​​are established for the pilot bin and for the data bin. In some embodiments, interpolation is used to establish the ideal constellation values ​​and ideal symbols for the data bin. It will be appreciated that various types of interpolation (e.g., straight line, least squares, iterative update / redetermination, etc.) are compatible with the reduced header pattern test process 800 and can be easily implemented therein. Additional descriptions of the operation of the interpolation process are presented in other portions of this specification (e.g., descriptions of processes 1200A, 1200B, etc.).

[0149] In block 827, other demodulation parameter values ​​are determined based on the results of the ideal constellation values ​​and ideal symbol values ​​for the pilot bin and the data bin (e.g., based on the results of block 826, etc.). In some embodiments, the equalizer value from the first bin is initially applied to the second bin and then updated based on the results of block 826. In some exemplary implementations, the first bin and the second bin are adjacent or proximate to each other. The communication protocol (e.g., industry standard, IEEE 802.11 series communication protocol, etc.) may define the configuration of the first bin and the second bin relative to being adjacent to each other.

[0150] In some embodiments, after the reduced header demodulation information determination process from block 820 is performed, operation proceeds to block 830 and an exemplary full demodulation is performed. The full demodulation is similar to block 330. In some embodiments, the full demodulation is similar to some aspects of conventional demodulation analysis. After the information from block 820 is available, the process can continue with full demodulation to determine information similar to conventional information that would otherwise not be conventionally available from the reduced header signal.

[0151] Fig.9A is a block diagram of exemplary autocorrelation plot results according to some embodiments. In some exemplary implementations, the autocorrelation is for a cyclic prefix in an OFDM symbol (e.g., similar to Figure 5D , etc.). The peaks in the graph are the locations of the resulting autocorrelations of the signal including the cyclic prefix and a delayed version of that signal. The Y-axis is the normalized correlation in increments of 0.1 (unitless), and the X-axis is samples in increments of 1000 samples per grid (unitless).

[0152] In some exemplary implementations, a reduced header demodulation information determination process is performed (e.g., similar to block 820). An autocorrelation is performed on the cyclic signal to produce a peak indication (e.g., similar to the peak indication) at the location of the OFDM symbol in the signal. Fig.9A , Fig. 9B The autocorrelation provides timing related information and coarse frequency error information. The timing of the concatenation boundaries of OFDM symbols within the cyclic signal is determined based on the peaks in the autocorrelation results. Based on the peak search of the autocorrelation results, the portions of the signal associated with different OFDM symbols (e.g., the beginning and end of an OFDM symbol, etc.) are identified. The beginning and end of an OFDM symbol are related to Figure 5C The start and end of OFDM symbols 0, 1 and 2 in are similar. Phase differences and coarse frequency errors can also be determined by analyzing the peaks in the autocorrelation results.

[0153] Fig. 9Bis a block diagram of an exemplary autocorrelation process according to an embodiment of the present disclosure. OFDM symbol 910A includes a cyclic prefix 911A and a corresponding end portion 912A. A copy OFDM symbol 920B includes a cyclic prefix 921B and a corresponding end portion 922B. The copy OFDM symbol 920B is a copy of the OFDM symbol 910A. The OFDM symbol copy 920B is offset in the time domain by an amount of time corresponding to the Fast Fourier Transform or FFT size, etc. As the autocorrelation is performed during the offset, an autocorrelation peak 930 is detected when the cyclic prefix 921B coincides with the end portion 912A in the time domain. The autocorrelation peak 930 has both amplitude and phase. When there is no coarse frequency error, the phase is zero. When there is a non-zero phase, there is a coarse frequency error. The coarse frequency error is defined as D theta divided by dt, where D theta is equal to the phase, and dt is the amount of time from the beginning of the OFDM symbol to the end of the OFDM symbol (excluding the cyclic prefix).

[0154] Fig. 9B The lower portion of includes a block diagram of the frequency domain spectrum, including the local oscillator spectrum, the signal spectrum, and other spectra (e.g., due to other components that introduce frequency response, digitizers, other out-of-band spectra, etc.). In some exemplary implementations, the local oscillator is there, while in other exemplary implementations, the local oscillator may not be there, or may be somewhere else. In some embodiments, coarse frequency error correction can make the response close to the true frequency error. In some exemplary implementations, coarse frequency error correction avoids a significant increase in EVM (e.g., if the spectrum is not clean, it is lower than the EVM associated with some residual frequency error, etc.). The timing information associated with the OFDM symbol and the coarse frequency error correction enables the ideal symbol to be reliably extracted later. Extracting the ideal symbol value and retrieving the captured value will provide information for the frequency domain analysis described in other parts of this specification (e.g., after FFT, etc.). The equalizer value is described in other parts of this specification (e.g., in process 1200A, 1200B).

[0155] refer to Fig.9A and Fig. 9B , in some embodiments, Fig.9A The determination of the coarse frequency error for each individual peak in (e.g., the peak corresponding to OFDM symbol 0, OFDM symbol 1, OFDM symbol 2, etc.) is similar to the error frequency determination for OFDM symbol 910A. Fig.9AIn some embodiments, for multiple peaks in the payload portion of a burst or frame, the individual frequency errors obtained are averaged. An average frequency error correction is determined based on the average frequency error value. The average frequency error correction is applied to the waveform (e.g., the payload portion of a burst or frame, etc.).

[0156] Performing an FFT operation on the respective portions of the signal associated with OFDM symbols 0, 1, and 2 produces the respective channel bandwidth subcarriers (e.g., similar to Figure 5C The subcarriers in the bins are bins 1 to subcarrier N, etc.). Although the values ​​of the subcarriers in each bin may change over time (e.g., there are different OFDM symbols, etc.), the respective positions of the bins in the bandwidth are defined by the communication protocol and remain fixed. Since the positions of the pilot bins are set by the communication protocol, it is easy to identify the subcarriers associated with each pilot bin. The communication protocol also specifies that BPSK modulation is used for the pilot subcarriers, and the BPSK analysis described in other parts of this specification is used to determine the ideal values ​​of the pilot subcarriers in each pilot bin.

[0157] Ideal constellation values ​​and ideal symbol values ​​are established for the pilot bins and the data bins (e.g., in block 826, etc.), and this includes determining equalizer values. In some exemplary implementations, an equalizer is established for the pilot subcarriers and data subcarriers associated with the respective pilot bins and data bins.

[0158] Fig.10 1 is a flow chart of an exemplary equalizer value determination process 1000 according to an embodiment of the present disclosure. In some embodiments, the equalizer value is obtained from the results of analyzing the frequency response in the pilot bin and the data bin. The equalizer value (e.g., for the pilot bin, for the data bin, etc.) is the reciprocal of the respective frequency response value. In some embodiments, this is for the OFDM symbols available in the capture and then averaged. It will be appreciated that the equalizer value determination and interpolation process described herein is applicable to both amplitude correction and phase correction. Interpolation process 1000 is included in some embodiments of the reduced head mode test process (e.g., process 800, etc.).

[0159] In block 1010, an equalizer value is determined for the pilot subcarrier at the pilot bin location based on the ideal pilot tone constellation value. In some embodiments, the frequency response is based on the difference between the ideal pilot tone constellation value and the received / captured pilot tone value. Additional description of determining the equalizer value is presented in other parts of this specification (e.g., description of process 1100 shown in FIG. 11, etc.).

[0160] In block 1020, an equalizer value is determined for the data subcarrier at the data bin position based on the ideal data tone constellation value. The equalizer value determined at the data bin position is based on the equalizer value result of the step of determining the equalizer value at the leading bin position. In some exemplary implementations, the equalizer value determined for the data subcarrier at the data bin position is based on an interpolation between the equalizer values ​​of the leading subcarriers of the leading bin position from block 1010.

[0161] In some embodiments, establishing ideal constellation values ​​and ideal symbol values ​​for the pilot bins (e.g., in block 826, etc.) includes performing an ideal pilot tone determination process. The ideal pilot tone determination process establishes ideal constellation values ​​and ideal symbol values ​​for the pilot bins. Other processes (e.g., interpolation, etc.) are used to establish ideal constellation values ​​and ideal symbol values ​​for the data bins.

[0162] Fig.11A 1 is a flow chart of an exemplary ideal pilot tone determination process 1100 according to an embodiment of the present disclosure. In some exemplary implementations, the ideal pilot tone value is obtained for the ideal pilot tone constellation point and the ideal symbol. In block 1110, a determination of a coarse frequency error is performed. In some embodiments, the results of the autocorrelation peak search function process are utilized in determining the coarse frequency error. The compensation value is the difference between the expected frequency of the pilot bin and the received or captured frequency of the pilot bin as defined by the communication protocol standard.

[0163] In block 1120, compensation is performed for the coarse frequency error. In some embodiments, compensating for the coarse frequency error includes adjusting the captured pilot binned subcarrier signal value with a compensation value. The magnitude of the compensation value is equal to the coarse error value and is the negative of it. For example, if the captured pilot binned subcarrier signal is 2.4499 GHz and the frequency error is 100 kHz lower than the expected value, the compensation is to add 100 kHz to 2.4499 GHz to obtain a value of 2.45 GHz. If the captured pilot binned subcarrier signal is 2.4501 GHz and the frequency error is 100 kHz higher than the expected value, the compensation is to subtract 100 kHz from 2.4501 GHz to obtain a value of 2.45 GHz.

[0164] In block 1130, a pilot tone value of the signal is obtained. In some embodiments, the pilot tone is modulated according to a binary phase shift keying BPSK protocol. In some exemplary implementations, the pilot tone is relatively immune to noise. Due to the low constellation density in the IQ plane, BPSK signals are more immune to noise. For example, in a 1024-QAM constellation type, a small amount of noise may cause a symbol error, while in a BPSK constellation plain, the same amount of noise will not cause a symbol error. There is an increasing inverse exponential relationship between the logarithmic bit error rate value and the signal-to-noise ratio dB value. The error probability and signal-to-noise ratio of different constellation types (BPSK error probability is the same as QPSK) increase as the QAM value increases. In some exemplary implementations, in order to have a symbol error rate of 10e-6 for a BPSK / QPSK signal, an SNR of about 13dB is required, while to achieve the same value for, for example, a 256QAM signal, an SNR of about 28dB must be achieved.

[0165] In block 1140, a decision is made as to whether a re-estimation of the frequency error is appropriate / necessary, and if so, an estimation of the fine-tuned frequency error is performed in block 1145, otherwise block 1150 is performed. If the user selected "LowSNR" for the frequency estimation method, the process proceeds to block 1145. If "HighSNR" was selected for the "Frequency Estimation Method," the process jumps to block 1050.

[0166] In block 1145, when the result of the decision in block 1040 is affirmative, a re-estimation process of the frequency error using the ideal pilot tone and / or data bin values ​​from block 1130 is optionally performed. In some embodiments, the re-estimation provides a more accurate frequency error estimate by also using the ideal pilot tone values ​​and / or data bin values.

[0167] In block 1150, the ideal pilot tone value is returned. In some embodiments, the ideal pilot tone value is associated with an ideal pilot bin value and an ideal pilot subcarrier value (e.g., an ideal pilot subcarrier symbol value, etc.). With the ideal pilot tone value returned, a more accurate frequency error estimate can be achieved.

[0168] The novel scheme presented overcomes many challenges faced in demodulation with reduced header information. Fig. 11B is an exemplary graph of simulated channel response in the presence of a signal with a full header or a signal with a non-blind known stimulus in accordance with some embodiments. The non-blind known stimulus may be similar to the PayloadOnlyIdealIQWaveform discussed in other parts of this specification. Fig. 11BAs shown, in some embodiments, the system is easily able to obtain a known channel response on each used subcarrier. However, traditionally, challenges arise when the system only has a pilot tone to obtain an initial frequency response. The Y-axis is the amplitude (dB), from -7.0dB to 1.0dB, with an increment of 1.0dB, and the X-axis is the subcarrier frequency, from -1000.0Hz to 1000.0Hz, with an increment of 50Hz.

[0169] Fig. 11C is a graph illustrating the locations of exemplary leading bin frequency responses according to some embodiments. The known leading bin frequency responses are not very dense compared to the otherwise unknown data bin frequency responses. In some embodiments, interpolation is performed to establish the frequency response values ​​of the data bins between the leading bins. It will be appreciated that Fig. 11C The frequency response shown for the data bins in is unknown before interpolation is performed. The Y-axis is the amplitude (dB), from -7.0 dB to 1.0 dB, in increments of 1.0 dB, and the X-axis is the subcarrier frequency, from -1000.0 Hz to 1000.0 Hz, in increments of 50 Hz.

[0170] Fig. 12A 1 is a flow chart of an exemplary interpolation process 1200A with iterative updating / redetermination of equalization values ​​within bins according to an embodiment of the present disclosure. The interpolation process 1200A is included in some embodiments of the reduced header communication signal processing test method. Compared with less iterative update interpolation processes such as traditional linear interpolation and traditional least squares interpolation, the exemplary interpolation process 1200A with iterative updating / redetermination of equalization values ​​provides a more accurate interpolation of equalization values. With a more accurate equalization rate, more accurate demodulation operations can be performed on the DUT, and corresponding test processes can be performed on these operations. This scheme enables the DUT to be tested in a test environment where a full frame or packet with complete header information cannot otherwise be easily handled / demodulated. It can be understood that the interpolation process 1200A with iterative updating / redetermination of equalization values ​​within bins is applicable to both amplitude correction and phase correction.

[0171] exist Fig. 12AIn block 1201 of , a new equalizer value for the pilot tone is determined. In some embodiments, the equalizer value is based on a pilot binary phase shift keying (BPSK) of an ideal / known or easily extracted pilot signal value, etc. As shown in exemplary constellation diagram 610, the BPSK analysis of the signal has only two constellation points on opposite portions of the x-axis. Since the distance between constellation points in BPSK is relatively large compared to other constellation diagrams (e.g., 620, 630, etc.), there is little chance of misassociating a received signal value with an erroneous ideal constellation point. In addition, the chance that the noise will be significantly large enough to add confusion to determining the appropriate constellation point is also small. Thus, the difference between the received or captured signal value and the ideal constellation point provides a reliable indication of the channel response. The inverse of the channel response is equal to the equalizer value.

[0172] In block 1202, it is determined whether the next bin is a data bin. In some embodiments, if the next bin does not have the characteristics of the leading bin or the empty bin, it is assumed to be a data bin. If the next bin is not one of the previously identified leading bins and it has some transmission signal characteristics (e.g., different from the empty bin that is expected not to have transmission signal characteristics), it is assumed to be a data bin.

[0173] In block 1203, the new equalizer value is applied to the data bin. In some embodiments, applying the new equalizer from the adjacent bin provides a more accurate estimate of the preliminary equalizer value for the current data bin. Applying the preliminary new equalizer from the adjacent bin to the current data bin provides a reasonable initial correction to the subcarrier values ​​corresponding to the current bin.

[0174] In block 1204, data subcarrier ideal signal values ​​are extracted for the data bins. In some embodiments, the data subcarrier ideal signal values ​​are based on the relationship between the results of block 1203 and known expected values ​​according to the communication protocol standard. By using the results of block 1203, the probability of misidentifying the appropriate corresponding ideal constellation point value is significantly reduced compared to other traditional schemes.

[0175] In block 1205, new equalizer values ​​are established based on the data subcarrier ideal signal values. Establishing new equalizer values ​​for the current data bin based on the data subcarrier ideal signal values ​​from block 1204 provides increasingly accurate interpolation results. Increasingly accurate estimates of appropriate equalization values ​​enable frequency response error problems to be avoided and often reversed.

[0176] Fig. 12Bis a graph of the results of an interpolation process with iterative updating / redetermination of equalization values ​​within bins in accordance with an embodiment of the present disclosure. The graph includes an indication of the relationship between various bins and associated subcarriers in the communication bandwidth. The graph also provides an illustration of the manner in which the described novel iterative interpolation scheme enables accurate adjustments to be utilized in efficient testing of DUT demodulation performance. The Y-axis is amplitude (dB), from -7.5dB to -4.0dB, in increments of 0.5dB, and the X-axis is subcarrier frequency, from -1012.0Hz to 975.0Hz, in increments of 1.0Hz.

[0177] Fig. 12C and Fig.12D 1 is a flow chart of an exemplary interpolation process 1200B with iterative updating / redetermination of equalization values ​​within bins according to an embodiment of the present disclosure. Interpolation process 1200B is included in some embodiments of the reduced head communication signal processing test method. In some embodiments, interpolation process 1200B is similar to interpolation process 1200A. Compared with less iterative update interpolation processes such as traditional linear interpolation or traditional least squares interpolation, etc., with iterative updating / redetermination of equalization values, interpolation process 1200B also provides a more accurate interpolation of equalization values. It can be understood that interpolation process 1200B with iterative updating / redetermination of equalization values ​​within bins is applicable to both amplitude correction and phase correction.

[0178] Process 1200B performs the functions of the analysis for the leader bins. In block 1207, one of the leader bins is selected and assigned the label of the current leader bin. In block 1210, an ideal value is extracted for the current leader bin, wherein the extraction of the ideal value for the current leader bin is based on binary phase shift keying (BPSK) analysis. In block 1215, a leader equalizer value based on the ideal value for the current leader bin from block 1210 and the known captured value of the current leader bin is extracted. In block 1217, the leader equalizer is inserted in a list of equalizers associated with the bins in the burst or frame packet.

[0179] The process performs the function of the analysis for the next data bin. In block 1220, one of the data bins adjacent to the current leading bin is selected and the label of the current data bin is assigned to the one of the data bins. In block 1221, the label of the current equalizer is assigned to the leading equalizer value. In block 1225, the current equalizer value is applied to the current data bin. In block 1230, an ideal constellation value is extracted for the current data bin. In block 1235, a new equalizer value is extracted based on the ideal constellation value from block 1230 and the known captured value of the current data bin. In block 1237, the new equalizer is inserted in the list of equalizers associated with the bins in the burst or frame packet.

[0180] The process includes checking for subsequent bins that are not data bins (e.g., predecessor bins, empty bins, etc.). In block 1240, determine whether the next bin in the group of bins is another predecessor bin. In block 1241, reassign the label of the current predecessor bin to another predecessor bin. In block 1242, determine whether the next bin in the group of bins is another data bin. In block 1243, skip the next bin (e.g., the result in the block indicates that the next bin is not a data bin, etc.). In some embodiments, if there is an empty bin between the predecessor bin and the data bin, the process "skips" the empty bin and analyzes the next data bin or predecessor.

[0181] The process also includes the possibility of dealing with special situations (e.g., dealing with data bins at the edge of the bandwidth, restarting analysis on subsequent leading bins, etc.). In block 1245, if the next bin is a bandwidth edge bin, it is determined when the next bin in the group of bins is another data bin. It is understood that when proceeding to blocks 1250 and 1270, the empty bins are skipped. In block 1250, when the result of the determination is negative, the new equalizer is applied to the next bin in the data bin. In block 1270, when the result of the determination is positive, the enhanced equalizer process is performed. In block 1261, it is determined whether the current bin iteration corresponds to the last bin (e.g., in a burst or frame packet, etc.). If the current bin is the last bin, the process proceeds to block 1262, and if the current bin is not the last bin, the process proceeds to block 1290. In block 1290, the current leading bin label reassignment process is performed. In block 1262, the average equalization process is performed.

[0182] In some embodiments, process 1200B proceeds until all bins in the bandwidth have been processed. The process may proceed in the direction of increasing frequency bins / subcarriers, decreasing frequency bins / subcarriers, or both. In some embodiments, a pilot is selected as an initial pilot, and the process proceeds in the direction of decreasing frequency bins / subcarriers. When it reaches the lowest frequency bin / subcarrier in the bandwidth, it returns to the initial pilot, and the process proceeds in the direction of increasing frequency bins / subcarriers until it reaches the highest frequency bin / subcarrier in the bandwidth. In some embodiments, a full demodulation process (e.g., similar to blocks 230, 830, etc.) is performed based on the results of interpolation process 1200B.

[0183] Fig.12E1 is a block diagram of an exemplary subcarrier binning configuration 1291 according to an embodiment of the present disclosure. The dots or circles represent various subcarrier bins (also referred to as transmit spectra within the communication bandwidth). The solid dark circles represent pilot subcarrier bins, also referred to as pilot bins, and the central transparent circles represent data subcarrier bins (also referred to as data bins). It is understood that the subcarrier binning configuration may also include other subcarrier bins (not shown). The Y-axis corresponds to the frequency values ​​of the various subcarriers, and the X-axis represents the transmission of the subcarriers over time.

[0184] It is understood that, according to some embodiments of the present disclosure, the subcarrier bin configuration 1291 represents a communication burst or frame of subcarrier bins and corresponding OFDM symbols. The bin columns correspond to the bins within each OFDM symbol. The bins are also tracked by bin rows (e.g., bin row 0, bin row 4, bin row 9, bin row 14, etc.). It is understood that the organization of the OFDM symbols included in the subcarrier bin configuration 1291 may be different. In some embodiments, each column is associated with a different OFDM symbol. In some exemplary implementations, the OFDM symbol is in a cycle that repeats in the subcarrier bin configuration (e.g., similar to the payload portion 505) (e.g., OFDM symbol 501 is repeated as 501A, 501B, 501C, 501D, etc.). Although subcarrier bin configuration 1291 is directed to subcarrier bin configuration, there are also equalization values ​​associated with each bin (e.g., an equalizer associated with the bin in column 0, an equalizer associated with the bin in column 9, an equalizer associated with the bin in column 19, etc.) The bins include 1274D, 1274H, 1271J, and in the expanded view portion, 1271A, 1272A, 1273A, 1274A, 1271B, 1272B, 1273B, 1274B, 1271C, 1271E, 1272E, 1273E, 1274E, 1271F, 1272F, 1273F, 1274F, and 1271G.

[0185] In some embodiments, the equalizer value associated with the bin is determined according to the interpolation process 1200B. Fig.12F , Figure 12G and Fig.12H 1 is a flowchart illustrating an exemplary implementation of the interpolation process 1200B according to some embodiments of the present disclosure. It can be understood that Fig.12F , Figure 12G and Fig.12H The blocks in (for example, Fig.12F 1210B, Figure 12G Block 1210E in Fig.12H The block 1210K, etc.) is Fig. 12C and Fig.12D The individual process blocks in Fig. 12Cdifferent iterations of blocks 1210, etc.).

[0186] Fig.12F 12 is a block diagram of an exemplary signal information processing operation according to an embodiment of the present disclosure. There are several bins, including a pilot bin 1271A, a data bin 1272A, a data bin 1273A, and a pilot bin 1271B. The process starts from the pilot bin 1271A in block 1210A, where an ideal constellation value (also known as a pilot bin ideal value) associated with the pilot bin value 1281A is extracted for the pilot bin 1271A. In block 1215A, a pilot equalizer 1282A is extracted. In block 1220A, the pilot equalizer 1282A is applied to the data bin 1272A. In block 1230A, an ideal constellation value 1283A for the data in the data bin 1272A is extracted. In block 1235A, a new equalizer 1284A is extracted. In block 1250A, the new equalizer 1284A is applied to data bin 1273A. In block 1230AA (e.g., the process returns to another iteration of block 1230, etc.), the ideal constellation value 1285A for the data in data bin 1273A is extracted. In block 1235AA, a new equalizer 1287A is extracted. The process proceeds in other blocks (not shown) and the process continues (e.g., the new equalizer is applied to the next data bin, etc.). In block 1240A, a determination is made as to whether the next bin is a leader bin. When the process encounters another leader (e.g., leader bin 1271B, etc.), the process returns and performs another iteration of block 1210 (e.g., in Figure 12G in, etc.).

[0187] Figure 12G12 is a block diagram of an exemplary signal information processing operation according to an embodiment of the present disclosure. There are several bins, including a pilot bin 1271B, a data bin 1272B, a data bin 1273B, and a pilot bin 1271C. The process starts from the pilot bin 1271B in block 1210B, where an ideal constellation value (also known as a pilot bin ideal value) associated with the pilot bin value 1281B is extracted for the pilot bin 1271B. In block 1215B, a pilot equalizer 1282B is extracted. In block 1220B, the pilot equalizer 1282B is applied to the data bin 1272B. In block 1230B, an ideal constellation value 1283B for the data in the data bin 1272B is extracted. In block 1235B, a new equalizer 1284B is extracted. In block 1250B, the new equalizer 1284B is applied to data bin 1273B. In block 1230BB (e.g., the process returns to another iteration of block 1230, etc.), the ideal constellation value 1285B for the data in data bin 1273B is extracted. In block 1235BB, a new equalizer 1287B is extracted. The process proceeds in other blocks (not shown) and the process continues (e.g., the new equalizer is applied to the next data bin, etc.). In block 1240B, it is determined whether the next bin is a leader bin. When the process encounters another leader (e.g., leader bin 1271C, etc.), the process returns and performs another iteration of block 1210.

[0188] For other bins in the OFDM symbol, the process proceeds in a similar manner from Fig.12F and Figure 12G Continue. Reference Fig.12E , the process continues to find the equalizer associated with bin 1274D. Thus, the process determines Fig.12E The equalizer values ​​for each bin in the equalizer column 0 in . The process returns to the next column and starts again from bin 1271E.

[0189] Fig.12H12 is a block diagram of an exemplary signal information processing operation according to an embodiment of the present disclosure. There are several bins, including a pilot bin 1271E, a data bin 1272E, a data bin 1273E, and a pilot bin 1271F. The process starts from the pilot bin 1271E in block 1210E, where an ideal constellation value (also known as a pilot bin ideal value) associated with the pilot bin value 1281E is extracted for the pilot bin 1271E. In block 1215E, a pilot equalizer 1282E is extracted. In block 1220E, the pilot equalizer 1282E is applied to the data bin 1272E. In block 1230E, an ideal constellation value 1283E for the data in the data bin 1272E is extracted. In block 1235E, a new equalizer 1284E is extracted. In block 1250E, the new equalizer 1284E is applied to data bin 1273E. In block 1230EE (e.g., the process returns to another iteration of block 1230, etc.), the ideal constellation value 1285E for the data in data bin 1273E is extracted. In block 1235EE, a new equalizer 1287E is extracted. The process proceeds in other blocks (not shown) and the process continues (e.g., the new equalizer is applied to the next data bin, etc.). In block 1240E, it is determined whether the next bin is a leader bin. When the process encounters another leader (e.g., leader bin 1271F, etc.), the process returns and performs another iteration of block 1210.

[0190] The process continues in a similar manner for other binning of OFDM symbols (e.g., in bursts, frames, etc.). Fig.12E , move up the second column bin 1274H, and return to the next column bin 1271J. When extracting the burst balance value, the process proceeds to the averaging process. Fig.12D , an averaging process is performed in block 1290. The averaging process is performed based on the equalization values ​​in the equalizer list (e.g., developed in blocks 1217, 1237, etc.). Fig.12I is a block diagram of a list 1293 of equalizer values ​​associated with bins of OFDM values ​​in a burst or frame. These bins correspond to Fig.12E , and the equalizer value corresponds to an exemplary implementation of the interpolation process 1200B (e.g., Fig.12F , Figure 12G , Fig.12H etc.). Fig.12F , in block 1215A, the equalizer 1282A is extracted from the leading bin 1271A. The equalizer 1282A is inserted into a list (e.g., equalizer value list 1293, etc.) according to the interpolation process 1200B in block 1217. It is understood that the equalizer value can be inserted into a list stored in a memory.

[0191] Fig.12J 1500 is a flow chart of an average equalizer process 1500 in accordance with some embodiments of the present disclosure. The average equalizer process 1500 provides an opportunity for overall improved handling and equalization correction of frequency errors. In some embodiments, averaging can help avoid overcorrection due to outliers or deviations in a particular bin. In some exemplary implementations, averaging can help smooth results that vary over time (e.g., in the horizontal row direction, etc.) and across subcarrier frequencies (e.g., in the vertical OFDM symbol direction, etc.). In some exemplary implementations, the average equalizer process 1500 is included in block 1262.

[0192] In block 1510, an equalizer value is accessed. In some embodiments, an equalizer value list 1293 is accessed. In some exemplary implementations, the accessed equalizer value is associated with an OFDM symbol in a communication burst or frame. The equalizer value may be accessed from a memory or other mechanism.

[0193] In block 1520, an average balance value is determined. It is understood that the average balance value can be for different average targets. Fig.12J and Fig.12I , the average equalization value may correspond to the average of the equalization values ​​in a row (e.g., bin row 0, bin row 5, etc.) of the equalizer value list 1293. The average equalization value may correspond to the average of the equalization values ​​in a column (e.g., equalizer column 0, equalizer column 9, etc.) of the equalizer value list 1293. The average equalization value may correspond to the average of the equalization values ​​in a burst or frame (e.g., burst or frame 1291, etc.).

[0194] In block 1530, average equalizer values ​​are applied to subcarriers in bins of OFDM symbols. In some embodiments, applying the average equalizer to the subcarriers brings the ability to mitigate residual errors. It will be appreciated that the average equalizer values ​​can be applied in different configurations. A first average equalizer value for a first row of subcarrier bins may be applied to corresponding subcarriers in the first row, and a second average equalizer value for a second row of subcarrier bins may be applied to corresponding subcarriers in the second row. A first average equalizer value for a first column of subcarrier bins may be applied to corresponding subcarriers in the first column, and a second average equalizer value for a second column of subcarrier bins may be applied to corresponding subcarriers in the second column. Average equalizer values ​​may be applied to subcarriers in bins of OFDM symbols in bursts, frames, and the like.

[0195] It will be appreciated that various forms of interpolation are compatible with the novel schemes described. In some embodiments, the accuracy of the interpolation schemes may vary. Fig.13Ais an exemplary graph of frequency response of bandwidths including multiple bins / subcarriers according to an embodiment of the present disclosure. Different bin / subcarrier values ​​are indicated by solid dots (e.g., 5071A, 5072, 5073, 5074, 5075, 5076, 5077, 5078, 5079, etc.). Fig.13A In FIG. 5 , the pilot bins are associated with points 5071A, 5073, 5075, 5077, and 5079, and the data bins are associated with the remaining points (e.g., 5072, 5074, 5076, 5078, etc.), and a straight line interpolation process is utilized to estimate the frequency response and the corresponding equalizer. Although the estimate is reasonable, there is a deviation from the true value.

[0196] Fig. 13B is an exemplary graph of frequency response of bandwidth including multiple bins / subcarriers according to an embodiment of the present disclosure. Fig. 13B Frequency response, bandwidth, multiple bins / subcarriers and corresponding signals in Fig.13A Similar to . Fig. 13B , the pilot bins are associated with points 5071A, 5073, 5075, 5077, and 5079, and the data bins are associated with the remaining points (e.g., 5072, 5074, 5076, 5078, etc.), and an iterative interpolation process (e.g., similar to, for example, 1200B) is utilized to estimate the frequency response and corresponding equalizer, etc. In some embodiments, the iterative interpolation process is similar to the interpolation process with iterative updating / redetermination of equalization values ​​within the bins (e.g., as in Fig. 12A , Fig. 12C , Fig.12D etc.). The iterative interpolation process produces values ​​that are very close to the true values. For example, Fig. 13B The deviation ratio between the interpolated value and the true value Fig.13A In some exemplary implementations, there is no sign error when extracting constellation information, and the iterative interpolation process value is the same as the true value.

[0197] In some implementations, the frequency line is fairly close to a flat or straight line for most of the bins / subcarriers in the large central portion of the bandwidth, but begins to have problems at the edges (e.g., due to filter performance / limitations, etc.). In the central portion (solid points between 5073 and 5077), the frequency is fairly flat, or has only a small ripple in the range 5091. Given that the bin / subcarrier frequency responses are relatively flat or close to each other (e.g., 5073 is relatively close to 5074, etc.), the equalizer value from one can serve as a relatively good initial equalizer value for the other. As the frequency reaches the lower and upper boundaries or edges of the bandwidth (e.g., 5071A, 5072, 5078, 5079, etc.), the frequency response range (e.g., 5092A, 5093, etc.) begins to decrease rapidly. In some embodiments, as the frequency decreases, the magnitude of the change in the response increases in the downward direction. In some embodiments, as the process traverses bins / subcarriers closer to the edge, the difference is added to the estimated equalizer value. The estimated equalizer for bin / subcarrier 5071B includes the equalizer from bin / subcarrier 5072 added to adjustment value 5092B (which is equal to the difference 5092A between the equalizer of bin / subcarrier 5073 and the equalizer of bin / subcarrier 5072) to provide an initial estimate of 5071B. For purposes of this graph, the estimated value 5071B is associated with fictitious bin / subcarrier 5071B to show that bin / subcarrier 5071B is relatively close to bin / subcarrier 5071A (e.g., similar to the way bin / subcarrier 5073 is relatively close to bin / subcarrier 5074) and serves as a relatively good initial equalization value for the other.

[0198] Fig.14A is a flow chart of an exemplary enhanced equalizer process according to an embodiment of the present disclosure. The enhanced equalizer process can be implemented to cope with special or unique data binning scenarios. In some exemplary implementations, the data bins are located at the edge of the bandwidth, so the difference between the equalization values ​​may vary more significantly from bin to bin. Thus, relying solely on the equalizer value from the previous bin may not be reliable enough. In some embodiments, adjusting according to the enhanced equalizer process provides more reliable interpolation and estimation of appropriate equalizer values.

[0199] In block 1470, when the result of ascertaining whether the next bin is a bandwidth edge bin (e.g., from block 1245, etc.) is positive, an enhanced equalizer process is performed. The enhanced equalizer process is similar to the enhanced equalizer process performed in block 1270. In block 1471, an incremental equalizer value is established based on the current equalizer value and the new equalizer value. The incremental equalizer value is the difference between the current equalizer value and the new equalizer value. In block 1472, the new equalizer value is added to the incremental equalizer value, and the label of the enhanced equalizer value is assigned to the result of the addition. Adding the new equalizer value to the incremental equalizer value provides a result that is much closer to the true equalizer value of the next bin. In block 1447, the enhanced equalizer is applied to the next data bin. Using the enhanced equalizer value provides a more reliable estimate of the appropriate equalizer value for the next data bin. Thus, when the enhanced equalizer is applied to the next data bin demodulation.

[0200] Fig. 14B is a block diagram of exemplary signal information processing operations according to an embodiment of the present disclosure. There are several bins, including data bin 7071, data bin 7072, and data bin 7073. The process starts with data bin 7071, and in block 1430R, an ideal constellation value 7081 is extracted for data bin 7071. In block 1435T, a new equalizer 7082 is extracted and applied to data bin 7071. In block 1445U, data equalizer 7082 is applied to data bin 7072. In block 1430V, an ideal constellation value 7083 for the data in data bin 7072 is extracted. In block 1435W, a new equalizer 7084 is extracted and applied to data bin 7072. In block 1445X, a new / incremental equalizer 7085 (e.g., a new equalizer 7084 plus a value similar to Fig. 13B 1430B, and so on) is applied to data bin 7073. In block 1430Y, (e.g., the process returns to another iteration of block 1430R, etc.) and ideal constellation values ​​7087 for the data in data bin 7073 are extracted. In block 1435Z, a new equalizer 7089 is extracted and applied to data bin 7073.

[0201] Fig.15It is a flowchart of an exemplary current data bin label reassignment process according to an embodiment of the present disclosure. The block diagram of the current data bin label reassignment process is similar to the block diagram of the current data bin label reassignment process of block 1290. In block 1590, the current data bin label reassignment process is performed. The current data bin label reassignment process 1590 includes the following operations. In block 1591, the next data bin is reassigned the label of the current data bin, where the next data bin becomes called the current bin. In block 1592, when the ascertainment result is negative, the new equalizer value is reassigned the label of the current equalizer value, where the new equalizer value becomes called the current equalizer value. In block 1595, when the ascertainment result is positive, the enhanced equalizer value is reassigned the label of the current equalizer value, where the enhanced equalizer value becomes called the current equalizer value.

[0202] In some embodiments, a full demodulation process (e.g., similar to blocks 230, 830, etc.) is performed based on the results of the interpolation process (e.g., 1200A, 1200B, etc.). In some embodiments, the manner in which full demodulation is performed is similar to the normal manner (e.g., similar to a non-test environment, similar to using full header information, etc.). Performing full demodulation is similar to demodulation in a real-world live environment. Performing full modulation is similar to performing modulation when associated header / preamble information is available in the signal transmission. In some exemplary implementations, performing full modulation includes determining full equalizer values, accurately establishing frequency errors, sampling clock errors, etc. In some embodiments, all result parameters required for testing RF WIFI components / devices are determined.

[0203] It is understood that other interpolation processes may be implemented. In some embodiments, a linear or polynomial fit response or interpretation is implemented. In some exemplary implementations, when the device capture may give larger than expected error values ​​for some interpolation bins (e.g., which in turn may cause larger channel response interpolation errors, etc.), an iterative interpolation process (e.g., 1200A, 1200B, etc.) is selected and implemented instead of linear or polynomial interpolation. In some embodiments, the interpolation pilot positions are not very dense.

[0204] Fig.161 is a flow chart of an exemplary reduced header with reference signal training mode test process 1600 in accordance with an embodiment of the present disclosure. In the reduced header with reference signal training mode test process, a known ideal payload signal is extracted from the full Wi-Fi signal. The ideal payload signal (e.g., PayLoadOnlyIdealIQWaveform, etc.) has no header information or only reduced header information. The ideal payload signal is played into the DUT. In some embodiments, the demodulator can be trained with the ideal waveform to provide an ideal payload portion (e.g., mostly data, data only, etc.) of a packet with reduced header information or no header information. A clean capture with low EVM is used to train the modulator to produce the ideal payload portion. This scheme also enables testing of the DUT in situations where it would otherwise not be able to easily cope with / demodulate a full frame or packet with full header information.

[0205] The process includes developing an ideal waveform based on information in a header portion of a signal. In block 1610, a reduced header with reference signal mode test process guide is accessed. In block 1620, a reduced header demodulation information determination process is performed based on reference signal training. In block 1630, a training process is performed. In block 1640, an ideal waveform including a training sequence is demodulated. In block 1641, a complete packet of the ideal waveform is accessed. In block 1642, a complete packet of the ideal waveform is demodulated. In block 1643, a payload portion of the ideal waveform is generated based on the demodulation of the complete packet ideal waveform. In some embodiments, the payload waveform is an ideal waveform containing only a payload (e.g., an IQ waveform, etc.).

[0206] The process includes a demodulation test based on the use of an ideal waveform. In block 1650, a reduced header demodulation is performed using the payload portion of the ideal waveform. The reduced header demodulation can be a headerless demodulation performed using the headerless payload portion of the ideal waveform. In block 1651, the payload portion ideal waveform is used as a reference and is loaded into the stimulus of the tester and used as a source for the DUT. In block 1652, an ideal reference trace process is performed. In some embodiments, the ideal reference trace process includes defining the constellation points of the ideal demodulated signal. In block 1653, a per-symbol ideal subcarrier type process is performed. In some embodiments, the input parameter IdealReferenceTrace defines the constellation points of the ideal demodulated signal, and the parameter IdealSubcarrierTypePerSymbol defines the subcarrier type of each element of the ideal reference trace. In some exemplary implementations, IdealReferenceTrace is a complex array whose length is twice that of IdealSubcarrierTypePerSymbol.

[0207] In block 1680, full demodulation is performed. In some embodiments, full demodulation is similar to some aspects of conventional demodulation analysis. After the information from block 1650 is available, the process can continue with full demodulation to determine information similar to conventional information that would otherwise not be conventionally available from the reduced header signal.

[0208] Fig.17 is a screenshot of an example 802.11ax 20MHz ideal waveform graphical user interface (GUI) in accordance with an embodiment of the present disclosure. The waveform in the GUI is a complete packet including a header portion and a data portion. In some embodiments, training includes a full burst in order to generate an ideal signal containing only the payload. The Y-axis is amplitude (unitless) in increments of 0.2, and the X-axis is time (uS) in increments of 2000.

[0209] Fig.18 18 is a screenshot of an exemplary payload-only ideal IQ waveform graphical user interface (GUI) when the input parameter HeaderlessDemod is set to training in accordance with some embodiments. The HeaderlessDemodTraining and Execute options are used to implement the development and creation of payload-only ideal IQ waveforms. The chart is provided by the PayloadOnlyIdealIQWaveform operation. Waveform 1810 is a waveform of a complete packet containing a header portion and a data payload portion of a communication, and waveform 1820 is a waveform of only the data payload portion of a communication. In waveform 1810, the Y axis is amplitude (volts) in increments of 0.5, and the X axis is time (uS) in increments of 2000. In waveform 1820, the Y axis is amplitude (volts) in increments of 2.0, and the X axis is time (uS) in increments of 2000.

[0210] Fig.19 is a screenshot of a graph of an exemplary extracted payload-only ideal signal in accordance with an embodiment of the present disclosure. Fig.19 Some characteristics of the operations in block 1653 are illustrated, such as the input parameter IdealReferenceTrace defines the constellation points of the ideal demodulated signal, and the parameter IdealSubcarrierTypePerSymbol defines the subcarrier type of each element of the ideal reference trace. In some exemplary implementations, IdealReferenceTrace is a complex array whose length is twice that of IdealSubcarrierTypePerSymbol. The Y axis is amplitude (volts) in increments of 0.5, and the X axis is time (uS) in increments of 2000.

[0211] Fig. 20is a screenshot of a graph of a demodulated payload-only signal within a GUI in accordance with an embodiment of the present disclosure. In order to perform headless demodulation using an ideal payload-only waveform, the input parameters for headless demodulation are based on training (e.g., DoHeaderlessDemod and set BurstSearchEnable to false, etc.). The Y-axis is amplitude (volts) in increments of 0.5, and the X-axis is time (uS) in increments of 2000.

[0212] Fig.21 21 is a flow chart of an exemplary head mode test process 2100 according to an embodiment of the present disclosure. In block 2110, the head mode test process guide is accessed. In some embodiments, the head mode test guide is accessed from a memory included in the ATE system. In block 2120, a parameter information determination process is performed. Parameters are associated with frequency offset, timing information, equalization, etc. These parameters are used in demodulation communication systems. In block 2125, demodulation parameter information is extracted from the header. The configuration of the information is defined by the communication protocol. The information is extracted from the fields in the header (e.g., short training field, long training field, signal field, etc.). In block 2130, a full demodulation is performed.

[0213] Much of the description is given with reference to public communication protocols. It is understood that the novel systems and methods described are also easily applicable to protocols that are not known to the public (e.g., established privately by a test entity, established by a DUT manufacturer and secretly communicated to an ATE entity, etc.). The type of modulation (e.g., BPSK, QPSK, etc.) can be assigned to subcarriers, and ideal values ​​can be established, which are then "known" by the ATE. Signals and corresponding information can be configured according to various types of protocols (e.g., public, private, etc.). Various values ​​(e.g., timing, frequency error, equalizer, EVM, performance values, modulation values, demodulation values, etc.) can be determined based on the captured information compared to the ideal values. These values ​​can be applied to other signals (e.g., adjacent subcarriers, etc.). The configuration or organization of subcarriers within a bandwidth (e.g., relative to each other, binned by frequency, etc.) can be established and known to the ATE. The novel iterative interpolation system and method described can be used to determine information about various signals (e.g., pilot subcarriers, data subcarriers, etc.). Thus, it can be appreciated that the novel systems and methods described are applicable to a wide variety of different test scenarios and conditions. In some exemplary implementations, the novel systems and methods described are readily applicable to protocols having predetermined characteristics and definitions (e.g., modulation definitions, configuration definitions, etc.).

[0214] Fig. 222200 is a block diagram of an exemplary electronic system 2200 that can be used as a platform to implement and control methods according to some embodiments. In some embodiments, the electronic system 2200 is a workstation that runs algorithms associated with the novel systems and methods described in this specification. The electronic system 2200 can be included in an ATE system (e.g., ATE 110A, ATE 110C, etc.). The electronic system 2200 can be a "server" computer system. The electronic system 2200 includes (one or more) central processors 2210, system memory 2215, mass storage 2225 (e.g., hard drive, external memory, etc.), input / output (I / O) devices 2230, communication components / ports 2240, and bus 2250. It will be appreciated that one or more non-transitory computer-readable media (e.g., system memory 2215, mass storage 2225, etc.) store instructions that, when executed by one or more processors (e.g., (one or more) central processing units, etc.), cause the one or more processors to perform the operations of the methods and processes described in other portions of the present description (e.g., methods 300, 700, 1000, 1100, 1200A, 1200B, 1590, 1600, etc.).

[0215] The bus 2250 is configured to communicatively couple and communicate information between other components (e.g., central processor(s) 2210, system memory 2215, mass storage 2225, input / output (I / O) devices 2230, communication components / ports 2240, etc.). The central processor(s) 2210 are configured to process information and instructions. The system memory 2221 (e.g., read only memory (ROM), random access memory (RAM), etc.) and mass storage (one or more) 2225 are configured to store information and instructions for the central processor complex 2215. The I / O device(s) 2230 can communicate information with the system (e.g., central processor 2210, memory 2225, etc.). The I / O device 2230 can be any suitable device for conveying information and / or commands to the electronic system (e.g., keyboard, button, joystick, microphone, touch sensitive digitizer panel, display component, light emitting diode (LED) display, etc.). The communication port 2240 is configured to exchange / communicate information with an external device / network (not shown). The communication port 2240 may have various configurations (e.g., RS-232 port, universal asynchronous receiver transmitter (UART), USB port, infrared light transceiver, Ethernet port, IEEE 13394, synchronous port, etc.), and may communicate with an external network.

[0216] In some embodiments, the methods and processes described in other parts of this specification are implemented by algorithms executed on a workstation (e.g., electronic system 2200, etc.). Algorithms for accessing information (e.g., retrieving from memory, downloading from a network, etc.) can be easily implemented for some method and process operations (e.g., 810, block 1610, etc.). Some aspects of the full demodulation blocks (e.g., 330, 830, 1680, etc.) that may be similar to the execution of conventional demodulation methods and processes can be implemented with algorithms similar to conventional algorithms. It is understood that the algorithm modules described herein are expressed in pseudocode, which can be easily converted to be implemented in various programming languages.

[0217] Fig.238 is a block diagram of a reduced header processing module 2300 according to an exemplary algorithm of an embodiment of the present disclosure. The reduced header processing module 2300 is directed to block 820 of the implementation method 800. The reduced header processing module 2300 includes an autocorrelation module 2310 (block 821), a coarse frequency error estimation module 2320 (block 823), a timing module 2330 (block 822), a bin group establishment module 2350 (block 824), an identification leader bin module 2360 (block 825), and an ideal leader bin establishment module 2370 (block 826). The autocorrelation module 2310 is directed to block 821. The coarse frequency error estimation module 2320 is directed to block 823. The timing module 2330 is directed to block 822. The bin group establishment module 2350 is directed to block 824. The identification leader bin module 2360 is directed to block 825. The module 2370 for establishing the ideal leader bin is directed to implementing block 826. The module 2380 for determining other demodulation parameters is directed to implementing block 827.

[0218] Fig.24 1 is a block diagram of an exemplary algorithm interpolation module 2400 according to an embodiment of the present disclosure. The interpolation module 2400 is directed to implementing the iterative interpolation process 1200B. The interpolation module 2400 includes a module 2410 for identifying a leading bin, a module 2420 for extracting an ideal leading bin value, a module 2430 for selecting an adjacent data bin, a module 2430 for applying a current equalizer to a data bin, a module 2440 for extracting an ideal value for a current data bin, a module 2450 for determining and applying a new equalizer value, a module 2460 for determining whether a subsequent bin is a data bin, a module 2480 for finding out whether the next bin is an edge data bin, a module 2485 for applying a conventional new equalizer, an enhanced equalizer module 2490, and a reassignment module 2495. Fig.25 It is an extended version of the exemplary enhanced equalizer module 2490 and the reassignment module 2495.

[0219] The modules within the interpolation module 2400 are directed to implementing blocks within the interpolation process 1200B. The identification leader bin module 2410 is directed to implementing block 1207. The extraction of ideal leader bin values ​​module 2420 is directed to implementing blocks 1210 and 1215. The selection of adjacent data bins module 2430 is directed to implementing block 1220. The application of the current equalizer to the data bin module 2430 is directed to implementing block 1225. The extraction of ideal values ​​for the current data bin module 2440 is directed to implementing block 1230. The determination and application of new equalizer values ​​module 2450 is directed to implementing blocks 1235 and 1237. The determination of whether the subsequent bin is a data bin module 2460 is directed to implementing blocks 1240-1243. The determination of whether the next bin is an edge data bin module 2480 is directed to implementing block 1245. The application of a conventional new equalizer module 2485 is directed to implementing block 1250. Enhanced equalizer module 2490 is directed to implementation block 1270. Average equalization module 2941 is directed to implementation blocks 1262 and 1500. Reassignment module 2495 is directed to implementation blocks 1290 and 1590.

[0220] Fig.26 1 is a block diagram of an exemplary algorithm training module processing module 2600 according to an embodiment of the present disclosure. The training module processing module 2600 includes a full ideal waveform demodulation training sequence module 2610 and a reduced header ideal payload reference demodulation module 2620. The training module processing module 2600 is directed to implementing block 1620. The full ideal waveform demodulation training sequence module 2610 is directed to implementing block 1630.

[0221] Fig. 27 1 is a block diagram of an exemplary algorithm leader bin ideal value module 2700 according to an embodiment of the present disclosure. The leader bin ideal value module 2700 is directed to the implementation block 1100. The leader bin ideal value module 2700 includes a coarse frequency error estimation module 2710, a compensation frequency error module 2720, an extraction ideal leader bin value module 2730, a re-estimation decision module 2740, a re-estimation module 2745, and a return module 2750. The coarse frequency error estimation module 2710 is directed to the implementation block 1110. The compensation frequency error module 2720 is directed to the implementation block 1120. The extraction ideal leader bin value module 2730 is directed to the implementation block 1130. The re-estimation decision module 2740 is directed to the implementation block 1140. The re-estimation module 2745 is directed to the implementation block 1145. The return module 2750 is directed to the implementation block 1150.

[0222] Fig.281 is a block diagram of an exemplary algorithm iterative interpolation module 2800 according to an embodiment of the present disclosure. The iterative interpolation module 2800 is directed to the implementation process 1200A. The iterative interpolation module 2800 includes an ideal leading bin establishment module 2810, a determination whether the subsequent bin is a data bin establishment module 2820, a new equalizer application module to the data bin establishment module 2830, an ideal value extraction module for the data bin establishment module 2840, and a new equalizer value establishment module 2850. The ideal leading bin establishment module 2810 is directed to the implementation block 1201. The determination whether the subsequent bin is a data bin establishment module 2820 is directed to the implementation block 1202. The application of the new equalizer to the data bin establishment module 2830 is directed to the implementation block 1203. The extraction of the ideal value module for the data bin establishment module 2840 is directed to the implementation block 1204. The establishment of the new equalizer value module 2850 is directed to the implementation block 1205.

[0223] Fig.29 29 is a block diagram of a test method 2900 according to an embodiment of the present disclosure. In block 2910, a reduced header payload test pattern is delivered to the DUT. In block 2910, the DUT performs a modulation / demodulation operation on the reduced header payload test pattern and captures the results. The capture information is received and a multi-mode modulation / demodulation parameter determination process is performed. The capture information is received and a multi-mode modulation / demodulation parameter determination process is performed.

[0224] Fig.30 is a block diagram of an exemplary reduced header mode test process 3000 according to an embodiment of the present disclosure. The reduced header mode test process 3000 is included in a reduced header communication signal processing method. The reduced header mode test process is utilized when reference signal information is reduced / unavailable. In some exemplary implementations, reference signal information (e.g., reference symbols, etc.) that would otherwise be included in a header portion or a preamble portion (e.g., included in a short training field, a long training field, etc.) is not available. The reduced header mode test process is utilized when a receiving component (e.g., a DUT, etc.) has reduced information about a received signal (e.g., reduced modulation-related information, header information, preamble information, signal configuration information, etc.). The received information is less than what would otherwise be available in a normal field / non-test situation.

[0225] In block 3010, reduced header mode test process guidance is accessed (e.g., no header no reference signal, etc.). In some exemplary implementations, the reduced header mode test process guidance is based on a selection of a reduced header mode test process (e.g., similar to the selection in block 710, etc.). This selection can be made based on various conditions (e.g., the DUT does not have sufficient resources to handle testing of communications with full header information, it is desirable to have a smaller test pattern for testing payloads with reduced header information, it is desirable to have multiple rounds of testing with different test characteristics, etc.).

[0226] In block 3020, a reduced header demodulation information determination process is performed. In some embodiments, the reduced header demodulation information determination process determines information to be used for testing modulation / demodulation operations (e.g., signal processing operations, etc.). In some exemplary implementations, the reduced header demodulation information determination process includes blocks 3021, 3022, 3023, 3024, 3025, and 3026.

[0227] In block 3021, a characteristic or feature of a signal associated with a payload portion of the information is identified. The characteristic or feature provides an indication of (e.g., has a correlation with, is associated with, etc.) timing information (e.g., a start time, an end time, etc.). The characteristic or feature may be included in a payload portion (e.g., a cyclic prefix, other configuration, etc.) within the signal. In some exemplary implementations, analysis of the characteristic or feature (e.g., autocorrelation analysis, comparative analysis, etc.) provides results that can be used to derive timing information (e.g., identifiable correlation peaks, identifiable amplitude configurations in the results, identifiable phase configurations in the results, etc.). In some embodiments, the timing information is associated with symbols included in the payload portion. In some embodiments, the symbols may be detected in a physical layer channel communication after modulation and before demodulation (e.g., after data encoding and IFFT in a modulation operation, before FFT and data decoding in a demodulation operation, etc.). The symbol may be an OFDM symbol, an OFDMA symbol, etc. In some embodiments, the signal is a cyclic signal (e.g., similar to Figure 5D The signals are configured according to a communication protocol (e.g., well-known, privately predetermined, etc.).

[0228] In block 3022, the start timing of symbols in the signal is identified based on the results from block 3021. Symbols are defined by the communication protocol. In other implementations, the start and end positions / timing of symbols relative to each other are identified (e.g., the start and end positions of a symbol relative to the start and end positions of other symbols, etc.).

[0229] In block 3023, an initial coarse frequency error correction is determined based on the results from block 3021. The difference in phase and the coarse frequency error may also be determined by analyzing the characteristics or features of the signal associated with the payload portion of the information. In some embodiments, the difference in the analysis result value from the expected value may indicate a phase difference and a corresponding frequency error. The expected value may be defined by the communication protocol or may be derived from a definition in the communication protocol.

[0230] In block 3024, a group of bins of the signal is established, wherein the group of bins includes a pilot bin and a data bin. The group of bins corresponds to a group of subcarriers associated with the signal, wherein the pilot bin corresponds to a pilot subcarrier in the group of subcarriers, and the data bin corresponds to a data subcarrier in the group of subcarriers. In some exemplary implementations, a fast Fourier transform (FFT) operation is performed on a portion of the signal associated with the symbol, and the result is used to establish the group of bins.

[0231] In block 3025, identification of the leading bins is extracted according to the definition of the leading subcarriers defined by the communication protocol. In some embodiments, identification of the leading bins includes identifying the positions of the leading bins relative to each other and other bins in the group of bins. It is understood that the identification and definition of the configuration and positions of subcarriers (e.g., leading subcarriers, data subcarriers, null subcarriers, etc.) relative to each other can vary (e.g., as FIG. 5A to FIG. 5E In some embodiments, the pilot signal is a special BPSK subcarrier signal that is more immune to symbol errors than the transmitted data symbols, and this relative immunity allows impairments in the pilot symbol (e.g., symbol error, frequency error, etc.) to be reliably determined and the equalizer value to be reliably determined.

[0232] In block 3026, ideal constellation values ​​and ideal symbol values ​​are established for the pilot bin and for the data bin. In some embodiments, interpolation is used to establish the ideal constellation values ​​and ideal symbols for the data bin. It will be appreciated that various types of interpolation (e.g., straight line, least squares, iterative update / redetermination, etc.) are compatible with the reduced head mode test process 3000 and can be easily implemented therein.

[0233] In block 3027, other demodulation parameter values ​​are determined based on the results of the ideal constellation values ​​and ideal symbol values ​​for the pilot bin and the data bin (e.g., based on the results of block 826, etc.). In some embodiments, the equalizer value from the first bin is initially applied to the second bin and then updated based on the results of block 826. In some exemplary implementations, the first bin and the second bin are adjacent or proximate to each other. The communication protocol (e.g., industry standard, IEEE 802.11 series communication protocol, etc.) can define the configuration of the first and second bins relative to being adjacent to each other.

[0234] In some embodiments, after the reduced header demodulation information determination process from block 3020 is performed, operation proceeds to block 3030 and an exemplary full demodulation is performed. Full demodulation is similar to block 330. Full demodulation is similar to some aspects of conventional demodulation analysis. After the information from block 3020 is available, the process can continue with full demodulation to determine information similar to conventional information that would otherwise not be conventionally available from the reduced header signal.

[0235] The header mode test process (e.g., blocks 750, 2100, etc.) performs modulation and demodulation testing using information in the header portion of a communication burst or frame. The header mode test process uses the header portion information to establish timing and reference values ​​for comparison with the leading values. In some embodiments, the header test process performs conventional testing of the communication information and implements the header test process using conventional algorithms.

[0236] Although the present disclosure has been described in conjunction with preferred embodiments, it will be understood that they are not intended to limit the present disclosure to these embodiments. On the contrary, the present disclosure is intended to cover substitutions, modifications and equivalents. The specification is not intended to be exhaustive or to limit the present disclosure to the exact form disclosed, and it is apparent that many modifications and variations are possible.

[0237] The novel test schemes described herein provide flexible and adaptable selection between test modes (e.g., including header mode, reduced header training mode, reduced header mode, etc.). In addition, the novel modes disclosed herein support efficient and effective testing of the demodulation performance of a communication DUT without relying on header information to perform demodulation. In some embodiments, the reduced header mode enables demodulation of communication signals (e.g., in bursts, packets, etc.) that are configured with less header information than would otherwise be typically included in accordance with the communication protocol.

[0238] The novel schemes described herein facilitate flexible determination of timing, frequency offset, channel response, and clock error, fine frequency error, sampling clock error, IQ gain and phase imbalance, error vector magnitude (EVM), etc. based on different amounts of physical layer communication protocol header information (e.g., from full header information to only data / payload portion without additional header information, etc.). The novel schemes described herein enable efficient and effective testing of demodulation components and functions, including improving overall test performance (e.g., reducing time, cost, etc.). The novel schemes described herein facilitate significant savings in test time and financial resources.

[0239] 1. In some embodiments, a reduced header communication signal processing test method includes: performing autocorrelation of a cyclic prefix in a signal, wherein the signal is configured according to a communication protocol, identifying the start timing of a symbol in the signal based on the result of the autocorrelation, wherein the symbol is defined by the communication protocol and includes an orthogonal frequency division modulation (OFDM) symbol, determining an initial coarse frequency error correction based on the result of the autocorrelation, establishing a group of bins for the signal, wherein the group of bins includes a pilot bin and a data bin, wherein the group of bins corresponds to a group of subcarriers associated with the signal, the pilot bin corresponds to a pilot subcarrier in the group of subcarriers and the data bin corresponds to a data subcarrier in the group of subcarriers, extracting an identifier of the pilot bin according to a definition of the pilot subcarrier defined by the communication protocol, establishing an ideal constellation value and an ideal symbol value for the pilot bin and for the data bin, and determining other demodulation parameter values ​​based on the results of the ideal constellation value and the ideal symbol value for the pilot bin and the data bin.

[0240] 2. A method as described in clause 1, wherein the signal is a cyclic signal including payload data without leading training reference symbols.

[0241] 3. A method as described in clause 1 or 2, wherein identifying includes performing a peak search function on the result of the autocorrelation and correlating the result of the peak search function with an indication of the start timing of the symbol.

[0242] 4. A method as described in any of clauses 1-3, wherein the communication protocol corresponds to one of the IEEE 802.11 wireless network communication protocol / standard family.

[0243] 5. A method as described in any of clauses 1-4, wherein the signal includes a physical layer payload portion of a protocol data unit without physical layer header information, wherein the configuration of the physical layer payload portion of the protocol data unit otherwise conforms to the configuration specifications of a communication protocol standard corresponding to one of the IEEE802.11 wireless network protocol / standard series.

[0244] 6. A method as described in any of clauses 1-5, wherein establishing an ideal constellation value and an ideal symbol value for a pilot bin includes completing a determination of a coarse frequency error, compensating for the coarse frequency error, obtaining an ideal pilot tone value in the signal, wherein the ideal pilot tone value includes an ideal constellation value and an ideal symbol value for the pilot bin and the corresponding pilot subcarrier, determining whether the user has selected "LowSNR" for the frequency estimation method, and if so, whether a re-estimation of the frequency error is appropriate, and when the result of the determination is affirmative, performing a re-estimation of the fine-tuning frequency error using the pilot tone and / or the data bin value in the signal, applying the fine-tuning frequency error to the signal, and returning an ideal pilot tone value, wherein the ideal pilot tone value includes an ideal constellation value and an ideal symbol value for the pilot bin and the corresponding pilot subcarrier.

[0245] 7. A method as described in clauses 1-7, wherein establishing ideal constellation values ​​and ideal symbol values ​​for the pilot bin and the data bin includes determining an equalizer value for the pilot subcarrier in the pilot bin based on the ideal pilot tone constellation value, and determining an equalizer value for the data subcarrier at the data bin position based on the ideal data tone constellation value.

[0246] 8. The method of clause 7, wherein the equalizer value of the pilot bin and the equalizer value of the data bin are the inverse of the respective channel response values.

[0247] 9. A method as described in clause 7 or 8, wherein determining an equalizer value for a data bin includes interpolating between equalizer values ​​of leading bins.

[0248] 10. A method as described in any of clauses 1-9, wherein establishing ideal constellation values ​​and ideal symbol values ​​for the leading bin and for the data bin includes selecting one of the leading bins and assigning a label of the current leading bin to one of the leading bins, extracting an ideal value for the current leading bin, wherein the extraction of the ideal value for the current leading bin is based on binary phase shift keying (BPSK) analysis, extracting a leading equalizer value based on the ideal value of the current leading bin and a known captured value of the current leading bin, inserting the leading equalizer into an equalizer list, selecting one of the data bins adjacent to the current leading bin and assigning the label of the current data bin to the one of the data bins, assigning the label of the current equalizer value to the leading equalizer value, applying the current equalizer value to the current data bin, and Extract the ideal constellation value, extract the new equalizer value based on the ideal constellation value and the known captured value of the current data bin, insert the new equalizer into the equalizer list, determine whether the next bin in the group bin is another leading bin, and reassign the label of the current leading bin to the other leading bin when the determination is affirmative, determine whether the next bin in the group bin is another data bin, when the next bin in the group bin is another data bin, find out whether the next bin is a bandwidth edge bin, when the finding is negative, apply the new equalizer value to the next bin, when the finding is affirmative, perform an enhanced equalizer process, determine whether the iteration of the current bin corresponds to the last bin, perform an average equalization process, and perform a current data bin label reassignment process.

[0249] 11. A method as described in any of clauses 1-10, wherein the enhanced equalizer process includes establishing an incremental equalizer value based on a current equalizer value and a new equalizer value, adding the new equalizer value to the incremental equalizer value, assigning a label of the enhanced equalizer value to the result of the addition, and applying the enhanced equalizer value to the next bin.

[0250] 12. A method as described in any one of clauses 1-10, wherein the current data bin label reassignment process includes reassigning the label of the current data bin to the next data bin, wherein the next data bin becomes called the current bin, when the determination is negative, reassigning the label of the current equalizer value to the new equalizer value, wherein the new equalizer value becomes called the current equalizer value, and when the determination is positive, reassigning the label of the current equalizer value to the enhanced equalizer value, wherein the enhanced equalizer value becomes called the current equalizer value.

[0251] 13. In some embodiments, a signal processing test system includes: a load board configured to couple with a plurality of devices under test (DUTs); a controller configured to direct testing of the plurality of DUTs, wherein the controller includes a test mode selection module operable to select between a plurality of test modes, wherein one of the plurality of test modes is associated with a reduced header communication signal test process applied to a signal, and a test electronics configured to test the plurality of DUTs under control of the controller, wherein the test electronics is coupled to the load board, and wherein the test electronics includes a demodulation information determination module operable to collect information associated with a demodulation operation, wherein the demodulation operation includes determining signal processing information based on information in a payload portion of the signal, and a demodulation module operable to perform the demodulation operation based on information received from the demodulation information determination module.

[0252] 14. A signal processing test system as described in clause 13, wherein the test mode selection module is operable to select a mode associated with a reduced header communication signal test process, and wherein, further, the demodulation information determination module determines signal processing information associated with a demodulation operation of the signal, and wherein the signal processing information is otherwise not included in the header portion of the signal.

[0253] 15. A signal processing test system as described in clause 13 or 14, wherein the demodulation information determination module is operable to determine signal processing information associated with multiple pilot tone subcarriers and multiple non-pilot tone subcarriers within a signal, wherein the configuration of the multiple pilot tone subcarriers and the multiple non-pilot tone subcarriers otherwise conforms to a communication protocol standard corresponding to one of the IEEE802.11 wireless network protocol / standard series.

[0254] 16. A signal processing test system as described in any of clauses 13-15, wherein the demodulation information determination module is operable to perform a reduced header communication signal processing test method, and wherein the reduced header communication signal includes a payload portion that is repeatedly transmitted in a loop, and the reduced header communication signal does not have a complete set of head training reference symbols specified in the communication protocol.

[0255] 17. In some embodiments, a signal processing test method includes selecting a signal processing mode among a head mode, a reduced head training mode, and a reduced head mode, performing a signal processing information determination process according to a result of selecting the signal processing mode, and performing a modulation / demodulation related process according to a result of the signal processing information determination process.

[0256] 18. A signal processing test method as described in clause 17, wherein the reduced header training mode includes performing a training process, which includes demodulating an ideal waveform including a training sequence, and performing an ideal headless demodulation using only a payload portion of the ideal waveform, and performing a full demodulation of another payload waveform using the result of the ideal headless demodulation.

[0257] 19. A signal processing test method as described in clause 17 or 18, wherein the reduced header mode includes performing an autocorrelation of a cyclic prefix in a signal, wherein the signal is configured according to a communication protocol, identifying the start timing of a symbol in the signal based on the result of the autocorrelation, wherein the symbol is defined by the communication protocol and includes an orthogonal frequency division modulation (OFDM) symbol, determining an initial coarse frequency error correction based on the result of the autocorrelation, establishing a group of bins for the signal, wherein the group of bins includes a pilot bin and a data bin, wherein the group of bins corresponds to a group of subcarriers associated with the signal, the pilot bin corresponds to a pilot subcarrier in the group of subcarriers, and the data bin corresponds to a data subcarrier in the group of subcarriers, extracting an identifier of the pilot bin according to a definition of the pilot subcarrier defined by the communication protocol, establishing an ideal constellation value and an ideal symbol value for the pilot bin and for the data bin, and determining other demodulation parameter values ​​based on the results of the ideal constellation value and the ideal symbol value for the pilot bin and the data bin.

[0258] 20. A signal processing testing method as described in any of clauses 17-19, wherein including a header mode comprises obtaining demodulation information from a header included in the signal.

[0259] In some embodiments, one or more non-transitory computer-readable media store instructions that, when executed by one or more processors of the ATE, cause the one or more processors to perform the operations of any of the methods of clauses 1-12 and 17-20.

[0260] In summary, the disclosed technology overcomes the limitations of conventional systems and methods by enabling accurate demodulation of the payload portion of a communication in accordance with a communication protocol without relying on header information that would otherwise be specified for use by the communication protocol. In some embodiments, the reduced header implementation includes a training aspect in which an ideal demodulated payload waveform is extracted from a completely ideal waveform (e.g., including header information, etc.) and the ideal demodulated payload waveform is used for demodulation of a received or captured signal. In some embodiments, a leading bin / subcarrier is identified in the payload portion of a cyclic communication signal and an ideal leading bin value is established. The beginning of a symbol (e.g., a transmission symbol, an OFDM symbol, etc.) is identified using autocorrelation of a cyclic prefix and performing a peak search function. The leading bin / subcarrier within the symbol and the corresponding ideal leading bin / subcarrier value are identified (e.g., by performing BPSK analysis, etc.), which are then used to establish an equalizer value. The equalizer value is applied to adjacent data bins to develop a new interpolated equalizer value for the data bin. The process iteratively applies the equalizer value from the previous data bin equalizer to the subsequent data bin and develops a new equalizer for the subsequent data bin until another leading bin is encountered.

[0261] At least one technical advantage of the disclosed technology is the ability to perform testing of demodulation operations on a DUT that would otherwise be impractical or impossible due to resource limitations. The ability of a DUT with limited memory to cope with newer communication protocols can be tested. The novel reduced header demodulation process described provides efficient and effective demodulation of the data payload portion of a communication signal (e.g., a portion that is traditionally unavailable without full header information, etc.). Although the limited test-related resources of the DUT may hinder demodulation test operations, the novel reduced header system and method described enables demodulation testing of the DUT by properly implementing and analyzing demodulation of the payload portion of the communication signal. Several demodulation-related parameters (e.g., timing, frequency offset, channel response, clock error, etc.) can be determined using the payload portion of the signal without relying on header information. In addition, the smaller capture size and corresponding test pattern associated with the reduced header payload signal reduces ATE upload and demodulation processing time. Test efficiency is improved by reducing the need for large test patterns associated with long header information (e.g., otherwise this would be time-consuming, inefficient, error-prone, etc.).

[0262] Any and all combinations of any claim elements recited in any claim and / or any elements described in the present application, in any manner, are within the scope and protection contemplated by the present disclosure.

[0263] The description of the various embodiments is given for purposes of illustration, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.

[0264] Aspects of the embodiments herein may be embodied as systems, methods, or computer program products. Therefore, aspects of the present disclosure may take the following forms: fully hardware embodiments, fully software embodiments (including firmware, resident software, microcode, etc.), or embodiments of combined software and hardware aspects that may all be collectively referred to herein as "modules," "systems," or "computers." In addition, any hardware and / or software techniques, processes, functions, components, engines, modules, or systems described in the present disclosure may be implemented as a circuit or a collection of circuits. In addition, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable media, on which computer-readable program code is embodied.

[0265] Any combination of one or more computer-readable media may be utilized. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the foregoing. More specific examples (non-exhaustive list) of computer-readable storage media will include the following: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium may be any tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment.

[0266] Aspects of the present disclosure are described above with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiments of the present disclosure. It will be understood that each square frame of the flowchart and / or block diagram and the combination of each square frame in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine. When the instruction is executed via the processor of a computer or other programmable data processing device, the function / action specified in one or more square frames of the flowchart and / or block diagram can be realized. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable gate array.

[0267] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architectures, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram may represent a module, a fragment or a part of a code, and the module, a fragment or a part of the code includes one or more executable instructions for implementing (one or more) specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings. For example, depending on the functions involved, two boxes shown in succession may actually be executed substantially simultaneously, or the boxes may sometimes be executed in the opposite order. It should also be noted that each box of the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions. Although the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be designed without departing from its basic scope, and its scope is determined by the appended claims.

[0268] Thus, embodiments of the present disclosure have been described. Although the present disclosure has been described in particular embodiments, it should be understood that the present disclosure should not be construed as limited by such embodiments but should be construed in accordance with the appended claims.

Claims

1. A reduced header communication signal processing test method, the method comprising: performing an autocorrelation of a cyclic prefix in a signal, wherein the signal is configured according to a communication protocol; identifying a start timing of a symbol in the signal based on a result of the autocorrelation, wherein the symbol is defined by the communication protocol and comprises an orthogonal frequency division modulation (OFDM) symbol; determining an initial coarse frequency error correction based on a result of the autocorrelation; establishing a set of bins for the signal, wherein the set of bins includes a pilot bin and a data bin, wherein the set of bins corresponds to a set of subcarriers associated with the signal, the pilot bin corresponds to a pilot subcarrier in the set of subcarriers and the data bin corresponds to a data subcarrier in the set of subcarriers; Extracting the identifier of the leading sub-bin according to the definition of the leading sub-carrier defined by the communication protocol; establishing ideal constellation values ​​and ideal symbol values ​​for the pilot bin and for the data bin; and Other demodulation parameter values ​​are determined based on the results of the ideal constellation values ​​and the ideal symbol values ​​of the pilot bin and the data bin.

2. The method of claim 1, wherein: The signal is a cyclic signal including payload data without leading training reference symbols.

3. The method of claim 2, wherein: The identification includes: performing a peak search function on the results of the autocorrelation; and A result of the peak search function is associated with an indication of a start timing of the symbol.

4. The method of claim 1, wherein: The communication protocol corresponds to one of the IEEE 802.11 wireless network communication protocol / standard family.

5. The method of claim 1, wherein: The signal includes a physical layer payload portion of a protocol data unit without physical layer header information, wherein the configuration of the physical layer payload portion of the protocol data unit otherwise conforms to the configuration specifications of a communication protocol standard corresponding to one of the IEEE802.11 wireless network protocol / standard series.

6. The method of claim 1, wherein: Establishing an ideal constellation value and an ideal symbol value for the pilot bin includes: Complete the determination of the rough frequency error; Compensating for the coarse frequency error; Obtaining an ideal pilot tone value in the signal, wherein the ideal pilot tone value includes an ideal constellation value and an ideal symbol value of the pilot bin and the corresponding pilot subcarrier; Determines whether the user has selected "LowSNR" for the frequency estimation mode, and if so, whether a re-estimation of the frequency error is appropriate; When the result of the determination is affirmative, performing a re-estimation of the fine frequency error using the pilot tone and / or the data bin values ​​in the signal; applying the fine frequency error to the signal; and The ideal pilot tone value is returned, wherein the ideal pilot tone value includes the ideal constellation value and the ideal symbol value of the pilot bin and the corresponding pilot subcarrier.

7. The method of claim 1, wherein: Establishing an ideal constellation value and an ideal symbol value for the pilot bin and the data bin includes: determining an equalizer value for a pilot subcarrier in the pilot bin based on an ideal pilot tone constellation value; and Equalizer values ​​are determined for data subcarriers at data bin locations based on ideal data tone constellation values.

8. The method of claim 7, wherein: The equalizer value of the pilot bin and the equalizer value of the data bin are reciprocals of the respective channel response values.

9. The method of claim 7, wherein: Determining an equalizer value for the data bin includes interpolating between the equalizer values ​​of the leading bins.

10. The method of claim 1, wherein: Establishing an ideal constellation value and an ideal symbol value for the pilot bin and for the data bin includes: Selecting one of the leading bins and assigning a label of the current leading bin to the one of the leading bins; Extracting an ideal value for the current leading bin, wherein extracting the ideal value for the current leading bin is based on binary phase shift keying (BPSK) analysis; extracting a lead equalizer value based on an ideal value for the current lead bin and a known captured value for the current lead bin; inserting the pilot equalizer into an equalizer list; Selecting one of the data bins adjacent to the current leading bin and assigning a label of the current data bin to the one of the data bins; assigning a label of a current equalizer value to the lead equalizer value; Applying the current equalizer value to the current data bin; Extracting an ideal constellation value for the current data bin; extracting new equalizer values ​​based on the ideal constellation values ​​and the known captured values ​​of the current data bin; inserting the new equalizer into the equalizer list; Determining whether the next sub-bin in the set of bins is another leading sub-bin; When the determination is positive, reassigning the label of the current leading sub-bin to the other leading sub-bin; Determining whether the next bin in the group of bins is another data bin; When the next bin in the group of bins is another data bin, finding out whether the next bin is a bandwidth edge bin; When the determination is negative, applying the new equalizer value to the next bin; When the determination is positive, performing an enhanced equalizer process; Determine whether the current iteration of the partition corresponds to the last partition; performing an average equalization process; and Execute the current data warehouse label reassignment process.

11. The method of claim 10, wherein: The enhanced equalizer process includes: establishing a delta equalizer value based on the current equalizer value and the new equalizer value; adding the new equalizer value to the incremental equalizer value and assigning a label of an enhanced equalizer value to the result of the addition; and Apply the enhanced equalizer value to the next bin.

12. The method of claim 10, wherein: The current data warehouse label reassignment process includes: reassigning a label of the current data bin to a next data bin, wherein the next data bin becomes the current bin; reassigning the label of the current equalizer value to the new equalizer value when the ascertainment is negative, wherein the new equalizer value becomes referred to as the current equalizer value; and When the determination is positive, the enhanced equalizer value is reassigned a label of the current equalizer value, wherein the enhanced equalizer value becomes referred to as the current equalizer value.

13. A signal processing test system, comprising: a load board configured to couple with a plurality of devices under test (DUTs); a controller configured to direct testing of the plurality of DUTs, wherein the controller includes a test mode selection module operable to select between a plurality of test modes, wherein one of the plurality of test modes is associated with a reduced header communications signal test procedure applied to a signal; as well as test electronics configured to test the plurality of DUTs under control of the controller, wherein the test electronics is coupled to the load board, and wherein the test electronics comprises: a demodulation information determination module operable to collect information associated with a demodulation operation, wherein the demodulation operation includes determining signal processing information based on information in a payload portion of the signal; and A demodulation module is operable to perform a demodulation operation based on the information received from the demodulation information determination module.

14. The signal processing test system according to claim 13, wherein: The test mode selection module is operable to select a mode associated with a reduced header communication signal test procedure, and wherein, further, the demodulation information determination module determines signal processing information associated with a demodulation operation of the signal, and wherein the signal processing information is otherwise not included in a header portion of the signal.

15. The signal processing test system according to claim 13, wherein: The demodulation information determination module is operable to determine signal processing information associated with a plurality of pilot tone subcarriers and a plurality of non-pilot tone subcarriers within the signal, wherein the plurality of pilot tone subcarriers and the plurality of non-pilot tone subcarriers are otherwise configured to conform to a communication protocol standard corresponding to one of the IEEE 802.11 family of wireless networking protocols / standards.

16. The signal processing test system according to claim 13, wherein: The demodulation information determination module is operable to perform a reduced header communication signal processing test method, wherein the reduced header communication signal includes a payload portion that is repeatedly transmitted in a loop, and wherein the reduced header communication signal does not have a complete set of header training reference symbols specified in a communication protocol.

17. A signal processing test method, comprising: selecting a signal processing mode between an included head mode, a reduced head training mode, and a reduced head mode; executing a signal processing information determination process according to a result of selecting a signal processing mode; and A modulation / demodulation related process is performed according to the result of the signal processing information determination process.

18. The signal processing test method according to claim 17, wherein: The reduced head training mode includes: Execute the training process, which includes: demodulating an ideal waveform including a training sequence; and An ideal headerless demodulation is performed using only the payload portion of the ideal waveform; and a full demodulation of another payload waveform is performed using the result of the ideal headerless demodulation.

19. The signal processing test method according to claim 17, wherein: The reduced header mode includes: performing an autocorrelation of a cyclic prefix in a signal, wherein the signal is configured according to a communication protocol; identifying a start timing of a symbol in the signal based on a result of the autocorrelation, wherein the symbol is defined by the communication protocol and comprises an orthogonal frequency division modulation (OFDM) symbol; determining an initial coarse frequency error correction based on a result of the autocorrelation; establishing a set of bins for the signal, wherein the set of bins includes a pilot bin and a data bin, wherein the set of bins corresponds to a set of subcarriers associated with the signal, the pilot bin corresponds to a pilot subcarrier in the set of subcarriers, and the data bin corresponds to a data subcarrier in the set of subcarriers; Extracting the identifier of the leading sub-bin according to the definition of the leading sub-carrier defined by the communication protocol; establishing ideal constellation values ​​and ideal symbol values ​​for the pilot bin and for the data bin; and Other demodulation parameter values ​​are determined based on the results of the ideal constellation values ​​and the ideal symbol values ​​of the pilot bin and the data bin.

20. The signal processing test method according to claim 17, wherein: The included header mode includes obtaining demodulation information from a header included in the signal.

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