A design method for high-speed dual-channel parallel 16b18b encoder based on HDMI 2.1 protocol

Abstract

The present invention provides a design method for a high-speed, dual-channel, parallel 16b18b encoder based on the HDMI 2.1 protocol. The method comprises: pre-analyzing and calculating the 16b18b encoding table to obtain an optimized code table; designing a BMG-based control module to replace the traditional 9b / 7b encoding module and the running disparity (RD) calculation module, thereby enabling the 16b18b encoding module to output results within a single clock delay. Furthermore, a dual-channel, parallel, redundant encoder architecture is designed based on the novel 16b18b encoding module, eliminating internal RD dependency and achieving true parallel operation without the need for internal clock multiplication. 32-bit data is passed through the improved dual-channel 16b18b encoder, resulting in the output of 36-bit encoded data. Compared with existing technical solutions, the present invention: 1) reduces the internal clock frequency required by the encoder, making it more stable; 2) achieves an encoding rate of 14.4 Gbps at a 400 MHz clock frequency; and 3) eliminates intermediate calculation steps in the encoding module, simplifying development.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, in particular to a design method for a high-speed dual-channel parallel 16b18b encoder based on the HDMI 2.1 protocol, which is suitable for encoding HDMI 2.1 video signals. Background Art

[0002] With the increasing popularity of 4K and 8K Ultra-HD TVs, high dynamic range (HDR) content, and higher refresh rates (such as 120Hz), the bandwidth limitations of the existing HDMI 2.0 standard began to become apparent. To support these new technological trends, the HDMI Forum launched the HDMI 2.1 standard in 2017. Compared to HDMI 2.0, its transmission rate has significantly increased from 18Gbps to 48Gbps. Both HDMI 2.1 and HDMI 2.0 require consideration of several issues inherent in information transmission, such as electromagnetic interference, clock skew, and DC balance. In serial data transmission systems, continuous "1s" or "0s" on a data transmission line can cause errors in the serial transmission line. In such cases, a coding scheme with no DC or only a constant DC component is required. HDMI 2.1 and earlier used 8b10b codecs, while HDMI 2.1 adopts 16b18b codecs.

[0003] There are two common approaches to implementing a 16b18b encoder: one based on a lookup table and the other on a combination of logical codes. While the first approach is relatively simple, it occupies a larger chip area, making it less suitable for encoders with larger code tables. Furthermore, encoder performance can be affected by data read latency. The second approach is more complex, and the resulting data may exhibit significant jitter, leading to encoder instability. Currently, more research and improvements are being conducted on the first approach than on the second.

[0004] To increase the encoding rate, most encoders are designed as multi-channel encoders. However, typical multi-channel encoders do not operate completely in parallel, as the operation of a particular encoding module often depends on the RD value output by the previous encoding module. Consequently, the multiple channel encoding modules within a multi-channel encoder are interdependent, resulting in significant latency. To address this issue, the operating clock frequency of a multi-channel encoder is typically higher than the data input clock frequency. Because the internal operating clock frequency is several times higher than the external data clock frequency, the encoder allows data to be input from multiple channels. However, this clock multiplication operation is limited by chip performance and is not suitable for larger and more complex 16b18b codecs.

[0005] To truly implement a low-latency multi-channel parallel encoder in engineering applications, it is necessary to address the delay problem caused by the strong dependence of the encoding and RD changes of traditional encoders on the previous RD. Secondly, it is necessary to overcome the delay problem caused by the RD dependence between channels in the multi-channel encoder. Summary of the Invention

[0006] The purpose of the present invention is to provide a design method for a high-speed dual-channel parallel 16b18b encoder, which aims to solve the 16b18b encoding problem of the new HDMI2.1 protocol signal transmission. It realizes 32-bit data parallel input on an existing FPGA and uses a lookup table for encoding.

[0007] The design method of the high-speed dual-channel parallel 16b18b encoder based on the HDMI 2.1 protocol of the present invention includes a novel 16b18b encoding module with encoding table optimization, encoding table storage optimization, and fast RD generation, including the following steps:

[0008] 1. A design method for a high-speed dual-channel parallel 16b18b encoder based on the HDMI 2.1 protocol, including the following steps:

[0009] Step 1: In a dual-channel parallel redundant 16b18b encoding method, a new 16b18b encoding module generated by fast RD is placed in channel 1 of the dual-channel encoder; two new 16b18b encoding modules generated by fast RD are placed in channel 2 of the dual-channel encoder; channel 1 is used to receive the upper 16 bits of the incoming 32-bit data, and channel 2 is used to receive the lower 16 bits of the incoming 32-bit data;

[0010] Step 2: Define RD+ as 1'b1 value; define RD- as 1'b0 value. The two encoding modules of channel 2 can be named RD- encoding module and RD+ encoding module, and input RD- and RD+ signals to them respectively.

[0011] Step 3: After a delay, the three encoding modules in the two channels simultaneously output the new RD value and 18-bit data. The RD output by the encoding module of channel 1 is used as the selection condition for the output of the encoding module of channel 2: if the RD value output by the encoding module of channel 1 is RD+, the RD+ encoding module in channel 2 is selected as the data outputter of the channel; if the RD value output by the encoding module of channel 1 is RD-, the RD- encoding module in channel 2 is selected as the data outputter of the channel;

[0012] Step 4: Store the RD data of the data outputter in channel 2 into the global RD register, and combine its 18-bit data output with the 18-bit data output by the encoding module of channel 1 into a 36-bit data as the final encoded data output of the entire system.

[0013] The new 16b18b encoding module generated by fast RD is based on the storage-optimized encoding table design and uses a lookup table for encoding. It includes a BMG data reading module, a data flag selection module, and an encoding conversion calculation module, which includes the following steps:

[0014] Step 1: After the optimized code table is stored in the RAM storage space created by the Block Memory Generator, the BMG data reading module reads data from the storage space according to the enable signal and input data, and then passes the data to the data flag selection module and the encoding transformation calculation module;

[0015] Step 2: After inputting 16-bit data, use the 16-bit data as the value address of BMG to obtain 22-bit data from RAM;

[0016] Step 3: After receiving the 22-bit data from the BMG data reading module, the data flag selection module selects each flag in the 22-bit data according to the current RD value;

[0017] Step 4: After receiving the flag and data, the coding transformation calculation module performs transformation calculation on the 10-bit data and the 8-bit data respectively according to the flag;

[0018] Step 5. Finally, the 18-bit data formed by combining the 10-bit data and the 8-bit data and the new RD value are output.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] 1. The 16b18b encoder can complete 38-bit data output after one clock delay, greatly reducing the operating clock frequency required by the encoder;

[0021] 2. The encoder has a simple design and can reach a rate of 14.4Gbps at a 400MHz clock.

[0022] 3. The new coding table breaks the RD dependency of coding and reduces the number of calculation steps in the coding process;

[0023] 4. The new coding table after storage optimization effectively reduces the storage requirement of the code table. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the design framework of a dual-channel parallel redundant encoder

[0025] Figure 2 Schematic diagram of the working process of dual-channel parallel redundant encoder

[0026] Figure 3Schematic diagram of the design framework of traditional single-channel encoder and multi-channel encoder

[0027] Figure 4 Schematic diagram of the design framework of the new 16b18b encoding module for fast RD generation

[0028] Figure 5 Schematic diagram of the workflow of the new 16b18b encoding module generated for fast RD DETAILED DESCRIPTION

[0029] The technical solution of the present invention is further described in detail below with reference to the accompanying drawings.

[0030] The design method of high-speed dual-channel parallel 16b18b encoder based on HDMI2.1 protocol is shown in the following diagram. Figure 1 As shown, its workflow is as follows Figure 2 As shown, it includes the following steps:

[0031] Step 1: When 32-bit data is input, it first passes through the data splitting module and is divided into two 16-bit data. The first 16-bit data is sent to the encoding module of channel 1, and the second 16-bit data is sent to the encoding module of channel 2.

[0032] Step 2: Given that each channel in a traditional multi-channel encoder depends on the RD value of the previous channel, and that there are only two possible RD values, two new 16b18b encoding modules are placed in channel 2, and fixed RD- and RD+ are input to each of these modules. This way, the two encoding modules in channel 2 are independent of the RD result of the encoding module in channel 1.

[0033] Step 3: After a clock delay, the three encoding modules simultaneously output their results. Next, the RD value output by the encoding module in channel 1 determines which encoding module in channel 2 to use. If the RD value output by channel 1 is RD-, the output of the RD- encoding module in channel 2 is selected; if the RD value output by channel 1 is RD+, the output of the RD+ encoding module in channel 2 is selected.

[0034] Step 4: Input the RD value of channel 2 into the global RD register. At the start of the next encoding round, the value in the RD register will be input into the encoding module of channel 1, and the dual-channel parallel 16b18b encoding will be completed in a cycle.

[0035] Traditional 16b18b encoding modules such as Figure 3As shown in (a), it includes a 9b encoding module, a 7b encoding module and two RD calculation modules. The operation of the second RD calculation module of the encoding module depends on the RD value output by the first RD calculation module

[21] . Figure 3 As shown in (b), the operation of each encoding module and RD calculation module depends on the output of the RD of the other encoder. This dependency ensures the balance of "0" and "1" in the encoded data stream, but also increases the encoder clock delay.

[0036] In order to save the RD calculation step of the 16b18b encoding module, the encoding table needs to be optimized. The optimization steps are as follows:

[0037] Step 1: Optimize the encoding table to save encoding steps:

[0038] 1) 16-bit input data has 65,536 possible output codes, each of which depends on the current RD state. Each encoding calculation requires splitting the 16 bits into 9 and 7 bits, then encoding them using the 9b10b and 7b8b code tables, respectively. Each encoding step also requires an RD calculation. These steps result in high clock latency for the encoder.

[0039] 2) Based on the 16b18b encoding principle, the input data, output data, and RD transformation are pre-paired one-to-one to form a coding table as shown in Table A. There are 65536 entries in the table, each corresponding to two output data. The output data width of a single column is 19 bits, of which the lower 18 bits [17:0] of any output data are the encoded data, and the highest bit is the flag bit, which indicates that the encoder needs to update to the RD value corresponding to the flag bit after selecting the encoding;

[0040] Table A Coding table with RD auxiliary information

[0041]

[0042] 3) The 16b18b encoder implemented based on this encoding table eliminates the process of calculating 9b encoding, 7b encoding and intermediate RD values, and can directly output 18b encoding and the encoded RD value after inputting 16b data.

[0043] Step 2: Reduce the storage space required for the encoding table:

[0044] 1) The coding table described in step 1 is still based on a theoretically constructed code table. Although this code table saves multiple calculation steps in the encoding module, in actual development, it occupies 2.375 Mb of storage space;

[0045] 2) To reduce storage requirements, by analyzing the 18-bit codes output by RD- and RD+, we found that after splitting the 18-bit code into 10-bit and 8-bit data, the 10-bit data of RD- and the 10-bit data of RD+ have identical or opposite relationships, and the 8-bit data also has a similar pattern. Therefore, two 1-bit flags can be used to indicate this identical or opposite relationship.

[0046] 3) Use 0 to indicate the same, and 1 to indicate the opposite. The final optimized code table is shown in Table B. Each entry contains 22 bits of data, with bit 21 designated as flag10b and bit 20 as flag8b, marking whether the 10b and 8b data need to be inverted, respectively. Bit 19 is designated as RD+_new, and bit 18 is designated as RD-_new. If the current RD value is RD+, RD+_new is selected as the new RD output of the encoding module; otherwise, RD-_new is selected. The remaining 18 bits [17:0] serve as temporary output data. Bit segment [17:8] is designated as temp10b, which serves as the temporary 10b output data, and bit segment [7:0] is designated as temp8b, which serves as the temporary 8b output data.

[0047] Table B: Encoding table with RD auxiliary information after storage optimization

[0048]

[0049] The design block diagram of the new 16b18b encoding module with fast RD generation in the high-speed dual-channel parallel 16b18b encoder design method is as follows Figure 4 As shown, the coding module workflow is as follows Figure 5 As shown, it includes the following steps:

[0050] Step 1: After the optimized code table is stored in the RAM storage space created by the Block Memory Generator, the BMG data reading module reads data from the storage space according to the enable signal and input data, and then passes the data to the data flag selection module and the encoding transformation calculation module;

[0051] Step 2: After inputting 16-bit data, use the 16-bit data as the value address of BMG to obtain 22-bit data from RAM;

[0052] Step 3: After receiving the 22-bit data from the BMG data reading module, the data flag selection module selects each flag in the 22-bit data according to the current RD value;

[0053] Step 4: After receiving the flag and data, the coding transformation calculation module performs transformation calculation on the 10-bit data and the 8-bit data respectively according to the flag;

[0054] Step 5. Finally, the 18-bit data formed by combining the 10-bit data and the 8-bit data and the new RD value are output.

Claims

1. A design method for a high-speed dual-channel parallel 16b18b encoder based on the HDMI 2.1 protocol, comprising the following steps: Step 1: In a dual-channel parallel redundant 16b18b encoding method, a new 16b18b encoding module generated by fast RD is placed in channel 1 of the dual-channel encoder; two new 16b18b encoding modules generated by fast RD are placed in channel 2 of the dual-channel encoder; channel 1 is used to receive the upper 16 bits of the incoming 32-bit data, and channel 2 is used to receive the lower 16 bits of the incoming 32-bit data; Step 2: Define RD+ as 1'b1 value; define RD- as 1'b0 value. Name the two encoding modules of channel 2 as RD- encoding module and RD+ encoding module, and input RD- and RD+ signals to them respectively. Step 3: After a delay, the three encoding modules in the two channels simultaneously output new RD values ​​and 18-bit data. The RD output by the encoding module of channel one is used as the selection condition for the output of the encoding module of channel two: if the RD value output by the encoding module of channel one is RD+, the RD+ encoding module in channel two is selected as the data outputter of the channel; if the RD value output by the encoding module of channel one is RD-, the RD- encoding module in channel two is selected as the data outputter of the channel; Step 4: Store the RD data of the data outputter in channel 2 into the global RD register, and combine its 18-bit data output with the 18-bit data output by the encoding module of channel 1 into a 36-bit data as the final encoded data output of the entire system.

2. The design method of a high-speed dual-channel parallel 16b18b encoder based on the HDMI 2.1 protocol according to claim 1, characterized in that: Including a new 16b18b encoding module for fast RD generation, The new 16b18b encoding module generated by fast RD modifies the traditional 9b encoding module, 7b encoding module and RD calculation module into BMG data reading module, data flag selection module and encoding conversion calculation module; The new 16b18b encoding module generated by fast RD receives 16-bit input data. There are 65536 possible 16-bit input data. Each input depends on the current RD state to determine the corresponding output encoding. To reduce the delay of the encoding module, according to the 16b18b encoding principle, the input data, output data and RD transformation are pre-matched one by one to form a new encoding table. This encoding table omits the intermediate calculations of the encoding module and directly outputs the final encoding result and the new RD value. To reduce the storage requirements of the code table, the 18-bit code output by RD- and RD+ is split into 10-bit and 8-bit data respectively. After analysis, the 10-bit data of RD- and RD+ have the same or opposite relationship, and the 8-bit data also has the same pattern. Two 1-bit flags are used to indicate this same or opposite relationship, ultimately forming a storage-optimized code table. Each entry in the optimized encoding table has 22 bits of data, of which the 21st bit is recorded as flag10b and the 20th bit is recorded as flag8b, which respectively mark whether the 10b and 8b data need to be inverted; The 19th bit is recorded as RD+_new, and the 18th bit is recorded as RD-_new. If the current RD value is RD+, RD+_new is selected as the new RD output of the encoding module; otherwise, RD-_new is selected, and the remaining 18 bits [17:0] are used as temporary output data. The bit segment [17:8] is recorded as temp10b as temporary 10b output data, and the bit segment [7:0] is recorded as temp8b as temporary 8b output data.

3. The design method of a high-speed dual-channel parallel 16b18b encoder based on the HDMI 2.1 protocol according to claim 1, characterized in that: Two new 16b18b encoding modules with fast RD generation are placed in channel 2, breaking the RD dependency between channels in traditional multi-channel parallel encoding methods; After resolving the RD dependency between channels, there is no need to multiply the operating clock frequency within the encoder, thereby enabling the maximum data clock frequency to be several times that of a conventional encoder.

4. The design method of a high-speed dual-channel parallel 16b18b encoder based on the HDMI 2.1 protocol according to claim 1, characterized in that: The working process of the novel 16b18b encoding module generated by fast RD in the method includes the following steps: Step 1: After the optimized code table is stored in the RAM storage space created by the Block Memory Generator, the BMG data reading module reads data from the storage space according to the enable signal and input data, and then passes the data to the data flag selection module and the encoding transformation calculation module; Step 2: After inputting 16-bit data, use the 16-bit data as the value address of BMG to obtain 22-bit data from RAM; Step 3: After receiving the 22-bit data from the BMG data reading module, the data flag selection module selects each flag in the 22-bit data according to the current RD value; Step 4: After receiving the flag and data, the coding transformation calculation module performs transformation calculation on the 10-bit data and the 8-bit data respectively according to the flag; Step 5. Finally, the 18-bit data formed by combining the 10-bit data and the 8-bit data and the new RD value are output.

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