Parallel-serial conversion circuit based on composite dielectric gate photosensitive detector

Abstract

The invention discloses a parallel-serial conversion circuit based on a composite dielectric gate photosensitive detector, and belongs to the field of integrated circuits. The parallel-serial conversion circuit comprises a composite dielectric gate photosensitive detector pixel, a ramp generator, a clamping circuit, a switch S1, a pre-charging circuit, a comparator, a counter, 8-256 decoders, a first AND gate, 256 second AND gates and a 256 input OR gate. According to the parallel-serial conversion circuit, all digital circuit parts are converted into analog circuits, so that the circuit design complexity is reduced, the circuit simulation and layout design iteration period is shortened, the power consumption and the area of a chip are effectively reduced, and the design of a subsequent miniaturized system is facilitated.

Description

Technical Field

[0001] The invention relates to a parallel-to-serial conversion circuit based on a composite dielectric grating photosensitive detector, and belongs to the field of integrated circuits. Background Art

[0002] Currently, CCD and CMOS-APS are the two most common imaging devices, but they each have certain limitations. CCD requires complex timing control and voltage requirements, which results in a slow operation speed and difficulty in achieving high integration; while CMOS-APS uses photodiodes and has a more complex structure, resulting in a lower fill factor and a smaller full-well charge capacity.

[0003] A Chinese patent with publication number CN102938409A discloses a composite dielectric gate dual-transistor photosensitive detector, which is characterized in that a single device has reset, photosensitivity and readout functions, thus forming a complete pixel. The detector with this structure can greatly improve the fill factor of the pixel, has a faster operating speed, a larger fill factor, more full well charge and can be integrated with CMOS technology. The device uses a MOSFET signal readout area with a variable threshold for readout, which gives it an inherent advantage over CCD and CMOS-APS.

[0004] Based on the above characteristics, a circuit that can quantify the device readout current and detect the change in the device readout current caused by the change in the threshold voltage can realize stable and high-speed readout of the composite dielectric gate dual transistor photosensitive detector. The Chinese patents with publication numbers CN116017184A and CN117135478A respectively proposed a composite dielectric gate dual transistor pixel readout circuit based on an inverter chain transimpedance amplifier and a composite dielectric gate transistor pixel readout circuit based on a dual transimpedance amplifier, using a ramp generator, a transimpedance amplifier, a driver stage and a counter to realize analog conversion and digital readout of the device current. However, converting the imaging device readout current of the analog circuit part into a digital output through a counter and then using a digital circuit to convert parallel data into serial data requires a mixed digital-analog circuit, which increases the difficulty of circuit design, verification and testing. In addition, the mixed digital-analog circuit also requires the integration of different process requirements and the matching of process parameters. At the same time, the process non-ideality will increase the difficulty of circuit layout design, require additional noise isolation and increase the complexity of wiring, resulting in the front-end circuit simulation and back-end layout design requiring a longer cycle to complete the iteration. Summary of the invention

[0005] In order to solve the problem of complex design of digital-analog hybrid circuits, the present invention provides a parallel-to-serial conversion circuit based on a composite dielectric grating photosensitive detector, which uses a pure analog circuit to convert the parallel imaging device readout current data into serial data, reducing the complexity of circuit design and shortening the circuit simulation and layout design iteration cycle.

[0006] The technical solution of the present invention is as follows:

[0007] The parallel-to-serial conversion circuit based on the composite dielectric grating photosensitive detector comprises a composite dielectric grating photosensitive detector pixel, a ramp generator, a clamping circuit, a switch S1, a precharge circuit, a comparator, a counter, an 8-256 decoder, a first AND gate and a second AND gate, and a 256-input OR gate. The gate end of the composite dielectric grating photosensitive detector pixel is connected to the ramp generator, the source end is grounded, and the drain end is connected to the input end of the clamping circuit.

[0008] Furthermore, the composite dielectric grating photosensitive detector pixel includes a MOS-C (Metal-Oxide-Semiconductor-Capacitor) signal collection area and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) signal readout area. In the exposure mode, the MOS-C signal collection area generates a depletion region in the substrate under the action of the gate-substrate forward bias to realize the collection of photogenerated carriers; in the readout mode, the transistor threshold voltage of the MOSFET signal readout area changes accordingly according to the collected photogenerated carrier charge, thereby realizing the readout of the photogenerated carrier signal.

[0009] Furthermore, the clamp circuit is composed of an amplifier and a transistor; the pre-charge circuit is composed of an integrating capacitor C INT and a transistor; the first AND gate serves as an enable switch of the counter.

[0010] Furthermore, the transistor in the clamping circuit is recorded as a first transistor M1, the gate end of the first transistor M1 is connected to the output end of the amplifier, the drain end of the composite dielectric grating photosensitive detector pixel is connected to an input end of the amplifier, and the other input end of the amplifier is provided with a clamping voltage V by an external source. REF,CLAMP ; The source end of the first transistor M1 is connected to the drain end of the composite dielectric gate photosensitive detector pixel to form a feedback loop; the drain end of the first transistor M1 is connected to one end of the switch S1.

[0011] Furthermore, the transistor in the pre-charging circuit is recorded as a second transistor M2, and the gate terminal of the second transistor M2 is connected to the pre-charging voltage V Precharge connected to the external power supply V DD connected, the source terminal and the integral capacitor C INT Connected; integrating capacitor C INT The other end is grounded.

[0012] Furthermore, the other end of the switch S1 is connected to the integral capacitor C INT , the source terminal of the second transistor M2 and one input terminal of the comparator; the other input terminal of the comparator is provided by an external reference voltage V REF,COMP .

[0013] Furthermore, the comparator output voltage V COMPOUT The output terminal of the first AND gate is connected to the input terminal of the counter together with the read enable signal EN_READ.

[0014] Furthermore, when the enable signal of the counter is logic 1, the counter is enabled; during the timing of the timer, at the end of each clock cycle, the value of the counter output port increases by 1.

[0015] Furthermore, all circuit parts from the negative feedback clamping circuit loop to the counter are readout circuits for a column of composite dielectric grating photosensitive detector pixels.

[0016] Furthermore, the input end of the 8-256 decoder is an 8-bit column selection signal provided externally, and the output end of the 8-256 decoder is connected to an input end of the second AND gate.

[0017] Furthermore, the output of the second AND gate is connected to one input of the 256-input OR gate; the readout circuit of the 256 columns of composite dielectric grating photosensitive detector pixels provides the input of the other end for the second AND gate. The output of the second AND gate is connected to the input of the 256-input OR gate.

[0018] Beneficial effects of the present invention:

[0019] The parallel-to-serial conversion circuit of the present invention converts all digital circuit parts into analog circuits. Pure analog circuits can directly process input signals without analog-to-digital conversion or digital-to-analog conversion, so signal processing is continuous and has a small delay. The digital part in a mixed digital-analog circuit usually relies on a clock signal, and problems such as clock deviation and clock jitter may occur, especially in high-speed digital circuits. These clock problems will affect the signal processing accuracy and system reliability. Pure analog circuits do not need to process internal clock signals, avoiding problems related to timing and synchronization. Since pure analog circuits do not have high-speed digital switching signals, electromagnetic interference and overall circuit noise are relatively low.

[0020] For circuits that do not require internal clocks, have short signal processing chains, and have relatively simple circuit topologies, mixed-analog circuits involve complex architectures, including analog-to-digital converters, digital-to-analog converters, and digital processing parts, which increase the complexity of circuit design, verification, and testing. Analog circuits are usually linear in structure, with relatively simple circuit topologies and short signal processing chains, which reduces the design steps and debugging process.

[0021] The present invention utilizes the 8-256 decoder, the AND gate implemented by the analog circuit and the 256-input OR gate to complete the conversion of parallel data into serial data, thereby reducing the complexity of circuit design, shortening the iteration cycle of circuit simulation and layout design, effectively reducing the power consumption and area of ​​the chip, and facilitating the design of subsequent miniaturized systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 It is a schematic diagram of a parallel-to-serial conversion circuit based on a composite dielectric grating photosensitive detector.

[0024] Figure 2 It is a 256-input OR gate block diagram based on analog circuit implementation.

[0025] Figure 3 It is a block diagram of the basic 4-input OR gate structure in the 256-input OR gate of the present invention.

[0026] Figure 4 It is a timing diagram of the working stages of the parallel-to-serial conversion circuit based on the composite dielectric grating photosensitive detector. DETAILED DESCRIPTION

[0027] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0028] Embodiment 1

[0029] This embodiment provides a parallel-to-serial conversion circuit based on a composite dielectric grating photosensitive detector, such as Figure 1 As shown. The circuit includes a composite dielectric grating photosensitive detector pixel, a ramp generator, a clamping circuit, a switch S1, a precharge circuit, a comparator, a counter, an 8-256 decoder, two AND gates (including a first AND gate and a second AND gate) and a 256-input OR gate. Among them, the gate end of the composite dielectric grating photosensitive detector pixel is connected to the ramp generator, the source end is grounded, and the drain end is connected to the input end of the clamping circuit; the clamping circuit is composed of an amplifier and a transistor M1 (hereinafter referred to as the first transistor M1); the precharge circuit is composed of an integral capacitor C INT and a transistor M2 (hereinafter referred to as the second transistor M2); the first AND gate serves as an enable switch of the counter.

[0030] In the clamping circuit, the gate end of the first transistor M1 is connected to the output end of the amplifier, the drain end of the composite dielectric grating photosensitive detector pixel is connected to one input end of the amplifier, and the other input end of the amplifier is provided with a clamping voltage V by an external source. REF,CLAMP The source terminal of the first transistor M1 is connected to the drain terminal of the composite dielectric gate photosensitive detector pixel to form a feedback loop.

[0031] The drain end of the first transistor M1 is connected to one end of the switch S1, and the other end of the switch S1 is connected to the integral capacitor C INT , the source terminal of the second transistor M2 and an input terminal of the comparator are connected; in the pre-charging circuit, the gate terminal of the second transistor M2 is connected to the pre-charging voltage V Precharge connected to the external power supply V DD connected, the source terminal and the integral capacitor C INT Connected; integrating capacitor C INT The other end is grounded.

[0032] The other input of the comparator is provided by an external reference voltage V REF,COMP , its output voltage V COMPOUT The output terminal of the first AND gate is connected to the input terminal of the counter, and the output voltage V COMPOUT The calculation result of the read enable signal EN_READ is used as the counting basis of the counter: when the enable signal of the counter is logic 1, the counter is enabled. During the timer timing process, the value of the counter output port increases by 1 at the end of each clock cycle.

[0033] All circuit parts from the negative feedback clamp circuit loop to the counter are readout circuits of a column of composite dielectric grating photosensitive detector pixels.

[0034] The input end of the 8-256 decoder is an 8-bit column selection signal provided externally, and the output end thereof is connected to an input end of the second AND gate.

[0035] The readout circuit of the 256 columns of composite dielectric grating photosensitive detector pixels provides the second AND gate with an input at the other end. The output end of the second AND gate is connected to the input end of the 256-input OR gate.

[0036] The circuit has three working stages, including exposure stage, readout stage and reset stage:

[0037] 1. Exposure stage: When the switch S1 is disconnected, the circuit is in the exposure stage, and the current signal path of the composite dielectric grating photosensitive detector pixel does not pass through the integral capacitor C INTThe negative feedback operational amplifier of the clamp circuit is still located in the signal path, so that the drain voltage of the composite dielectric grating photosensitive detector pixel remains constant at a stable voltage V REF,CLAMP The signal collection area of ​​the MOS-C pixel of the composite dielectric grating photosensitive detector generates a depletion region in the substrate under the action of the gate-substrate forward bias, thereby collecting photogenerated carriers and realizing exposure.

[0038] 2. Readout stage: When switch S1 is closed, the circuit is in the readout stage, and the precharge voltage V Precharge Pull down the integral capacitor C INT Precharge to external voltage V DD After that, the precharge voltage V Precharge Pull high to turn on the readout enable signal EN_READ, and the ramp generator provides the gate of the composite dielectric gate photosensitive detector pixel with a voltage from V RampStart The voltage starts to gradually increase until it reaches V RampEnd At this time, turn off the read signal EN_READ to enable reading.

[0039] 3. Reset stage: After the readout stage, switch S1 is disconnected and the circuit is in the reset stage. The drain voltage of the composite dielectric grating photosensitive detector pixel remains constant and is at a stable voltage V REF,CLAMP .

[0040] Please refer to Figure 4 , the following combination Figure 4 The timing diagram shown provides a detailed introduction to the working process of each stage of the circuit:

[0041] In the exposure phase, when the switch S1 is disconnected, the circuit is in the exposure phase, and the current signal path of the composite dielectric grating photosensitive detector pixel does not pass through the integral capacitor C INT The negative feedback operational amplifier of the clamp circuit is still located in the signal path, so that the drain voltage of the composite dielectric grating photosensitive detector pixel remains constant at a stable voltage V REF,CLAMP . Precharge voltage V Precharge At high level V DD , does not affect the integral capacitor C INT . Turn off the readout signal EN_READ to make the counter inoperative. The signal collection area of ​​the composite dielectric grating photosensitive detector pixel MOS-C generates a depletion region in the substrate under the action of the gate-substrate forward bias, realizing the collection of photogenerated carriers and realizing exposure.

[0042] In the readout stage, the drain voltage of the composite dielectric grating photosensitive detector pixel is stabilized at V REF,CLAMP The ramp generator maintains the initial voltage VRampStart unchanged, the pre-charge voltage V Precharge Pull low, transistor M2 is turned on and the integrating capacitor C INT Precharge to V DD , at this time the voltage on the integrating capacitor plate V X =V DD >V REF,COMP , so the comparator output V COMPOUT After the pre-charge is completed, the pre-charge voltage V Precharge Pull high to V DD , and at the same time turn on the read enable signal EN_READ, with V COMPOUT The counter starts counting with EN_READ as the enable signal through the AND gate. At the same time, the ramp voltage generated by the ramp generator increases from V RampStart The composite dielectric grating photosensitive detector pixel pair integral capacitance C INT Discharge, the voltage on the plate of the integrating capacitor V X Gradually decreases, when V X drops below the comparator reference level V REF,COMP When the comparator outputs V COMPOUT Flips from logic 1 to logic 0, and after passing through the AND gate with EN_READ, the output is logic 0, and serves as the enable signal of the counter to stop counting. The count value is V OUT,CNT After that, when the ramp voltage provided by the ramp generator reaches V RampEnd When , turn off the readout signal EN_READ to realize reading.

[0043] In the reset phase, a suitable negative bias voltage V is applied between the gate and substrate of the composite dielectric grating photosensitive detector pixel. Reset , the photoelectrons collected at the P-type substrate interface of MOS-C will leak out through the electrodes connected to the substrate under the action of the electric field. Turn off the readout enable signal EN_READ, and make the counter enable signal always logic 0 through the AND gate, and the counter count value remains V OUT,CNT constant.

[0044] All circuit parts from the negative feedback clamp circuit loop to the counter are the readout circuits of a row of composite dielectric grating photosensitive detector pixels, refer to Figure 1 The yellow dotted box in the middle. 256 columns of readout circuits are taken as a group. The present invention aims to convert 256 columns of parallel output data V OUT,CNT<255:0> is converted into serial output data through analog circuit. The 8-bit column selection signal input from the outside is converted into 256 columns of output enable signals through 8-256 decoders, where the output enable signal corresponding to the selected column is logic 1, and the output enable signals of the remaining 255 columns are all logic 0. The 256 column enable signals and the output signals of each bit of the counter of the 256 column readout circuit pass through 256 AND gates, and the output 256 voltages V OUT,256 Contains 255 logic 0s of unselected columns and the counter output signal V of the selected column. OUT,CNT The AND gate outputs 256 voltages V OUT,256 As the input of the 256-input OR gate, the output result is V FO The counter output signal V for the selected column OUT,CNT The present invention can select the corresponding column for reading by changing the externally input 8-bit column selection signal, thereby realizing the conversion of parallel output data into serial data.

[0045] Figure 1 The 256-input OR gate structure implemented based on analog circuits is as follows Figure 2 shown.

[0046] The 256-input OR gate is composed of four 64-input OR gates, one 4-input OR gate and a buffer composed of two NOT gates. The 64-input OR gate is composed of four 16-input OR gates, one 4-input OR gate and a buffer composed of two NOT gates, and the 16-input OR gate is composed of four 4-input OR gates, one 4-input OR gate and a buffer composed of two NOT gates. A single 4-input OR gate will output logic 1 when any input is logic 1, and will output logic 0 when all four inputs are logic 0. The 16-input OR gate divides the 16 input signals IN<15:0> into four groups of 4 signals each and inputs them into four 4-input OR gates. If any input signal in IN<15:0> is logic 1, then one of the signals in C<3:0> output by the corresponding 4-input OR gate is logic 1. Then C<3:0> is input as the input signal to the 4-input OR gate, and its output OUT is logic 1. The two NOT gates act as buffers to improve the driving capability of the circuit. If IN<15:0> are all logic 0, then the corresponding C<3:0> are also all logic 0, and the output signals OUT and OUT BUF It is also logic 0. Similarly, the 64-input OR gate and the 256-input OR gate use this structure to achieve corresponding functions.

[0047] Among them, a single 4-input OR gate is composed of a 4-input NOR gate and a NOT gate, such as Figure 3 As shown, the 4-input NOR gate is composed of 4 P-type MOSFET transistors and 4 N-type MOSFET transistors, and the NOT gate is composed of 1 P-type MOSFET transistor and 1 N-type MOSFET transistor.

[0048] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0049] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A parallel-to-serial conversion circuit based on a composite dielectric grating photosensitive detector, characterized in that: The circuit comprises a composite dielectric grating photosensitive detector pixel, a ramp generator, a clamping circuit, a switch S1, a pre-charging circuit, a comparator, a counter, an 8-256 decoder, a first AND gate and a second AND gate, and a 256-input OR gate; wherein the gate end of the composite dielectric grating photosensitive detector pixel is connected to the ramp generator, the source end is grounded, and the drain end is connected to the input end of the clamping circuit; the clamping circuit is composed of an amplifier and a transistor; the pre-charging circuit is composed of an integrating capacitor C INT and a transistor; the first AND gate serves as an enable switch of the counter.

2. The parallel-to-serial conversion according to claim 1, characterized in that: The transistor in the clamping circuit is recorded as the first transistor M1. The gate end of the first transistor M1 is connected to the output end of the amplifier. The drain end of the composite dielectric grating photosensitive detector pixel is connected to an input end of the amplifier. The other input end of the amplifier is provided with a clamping voltage V by an external source. REF,CLAMP ; The source end of the first transistor M1 is connected to the drain end of the composite dielectric gate photosensitive detector pixel to form a feedback loop; the drain end of the first transistor M1 is connected to one end of the switch S1.

3. The parallel-to-serial conversion according to claim 2, characterized in that: The transistor in the pre-charging circuit is denoted as the second transistor M2, and the gate terminal of the second transistor M2 is connected to the pre-charging voltage V Precharge connected to the external power supply V DD connected, the source terminal and the integral capacitor C INT Connected; integrating capacitor C INT The other end is grounded.

4. The parallel-to-serial conversion according to claim 3, characterized in that: The other end of the switch S1 is connected to the integral capacitor C INT , the source terminal of the second transistor M2 and one input terminal of the comparator; the other input terminal of the comparator is provided by an external reference voltage V REF,COMP .

5. The parallel-to-serial conversion according to claim 4, characterized in that: The comparator output voltage V COMPOUT The output of the first AND gate is connected to the input of the counter. The output voltage V COMPOUT The calculation result of the read enable signal EN_READ is used as the counting basis of the counter: when the enable signal of the counter is logic 1, the counter is enabled. During the timer timing process, the value of the counter output port increases by 1 at the end of each clock cycle.

6. The parallel-to-serial conversion according to claim 5, characterized in that: The input end of the 8-256 decoder is an 8-bit column selection signal provided externally, and the output end of the 8-256 decoder is connected to an input end of the second AND gate.

7. The parallel-to-serial conversion according to claim 6, characterized in that: The output of the second AND gate is connected to one input of the 256-input OR gate.

8. A composite dielectric grating photosensitive detector, characterized in that: The composite dielectric grating photosensitive detector comprises the parallel-to-serial conversion circuit based on the composite dielectric grating photosensitive detector according to any one of claims 1-7.

9. An imaging device, characterized in that: The imaging device comprises the parallel-to-serial conversion circuit based on the composite dielectric grating photosensitive detector according to any one of claims 1 to 6 or the composite dielectric grating photosensitive detector according to claim 7.

Images