Test circuit, test system and storage system

Abstract

The invention discloses a test circuit, a test system and a storage system. The test circuit comprises a logical algorithm vector generation module which is configured to receive initialization address information, process the initialization address information and then output initial test address information; and the address mask module is coupled with the logical algorithm vector generation module and is configured to shield part of address information in the initial test address information so as to output to-be-tested address information. The test circuit can shorten the chip test speed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor and integrated circuit technology, and in particular to a test circuit, a test system and a storage system. Background Art

[0002] A chip tester is a device used to detect the functions and performance of integrated circuits (ICs) and other semiconductor devices. Chip testers can use different technologies to implement tests according to different application requirements, including but not limited to tests for microcontrollers, field programmable gate arrays (FPGAs), single-chip microcomputers, etc. as core control units. In recent years, there have been many new technical trends in chip testers for high-density and complex function integrated circuits, including the following technical points.

[0003] Embedded test technology, with the increasing complexity of system-on-chip (SoC), traditional test methods are no longer applicable. Embedded test technology allows the integration of test functions in the chip design stage, which can not only improve product quality, but also significantly shorten the time of system verification, detection and debugging.

[0004] Low power design,As integrated circuits develop towards ultra-deep submicron technology, traditional dynamic power consumption has become a major challenge.,The low power design idea is achieved by reducing the number of circuit node flips during the test,,which is particularly important for maintaining low power consumption while improving fault coverage.

[0005] Parallel testing and test scheduling,In order to deal with the long test time and resource conflicts of high-density integrated circuits, parallel testing technology and effective test scheduling algorithms are used.,These technologies can reasonably allocate test resources and reduce the overall test time while ensuring test efficiency.

[0006] However, the test speed of existing chip test systems still needs to be improved. Summary of the invention

[0007] The main purpose of the present invention is to provide a test circuit, a test system and a storage system, aiming to shorten the test speed of the chip test system.

[0008] To achieve the above-mentioned purpose, the technical solution of the present application proposes a test circuit, including: a logic algorithm vector generation module, configured to receive initialization address information, and output initial test address information after processing the initialization address information; an address mask module, coupled to the logic algorithm vector generation module, configured to mask part of the address information in the initial test address information to output the address information to be tested.

[0009] In some embodiments, the address mask module includes: a mask memory configured to store mask information; a logic unit coupled to the mask memory and configured to mask partial bit address information in the initial test address information based on the mask information to output the address information to be tested.

[0010] In some embodiments, the address mask module also includes: a decoder, coupled to the logic algorithm vector generation module, configured to parse the initial test address information and output parsed information; the mask memory is coupled to the decoder, and the mask memory is configured to output the mask information to the logic unit according to the parsed information.

[0011] In some implementations, the method further includes: a scrambler coupled to the logic algorithm vector generation module, configured to scramble the initial test address information and output scrambled address information.

[0012] In some embodiments, it also includes: a scrambling memory, coupled to the logic algorithm vector generation module and the scrambler, and configured to: store scrambling configuration information; output corresponding scrambling configuration information to the scrambler according to the initial test address information; the scrambler is configured to scramble the initial test address information according to the scrambling configuration information to output scrambled address information.

[0013] In some embodiments, it further includes: a data buffer memory coupled to the scrambler and configured to: store test data information; output the test data information to the scrambler; the scrambler is configured to scramble the test data information and then output it.

[0014] In some implementations, the system further includes: an error data storage module configured to receive test data information in response to the address information to be tested, and output the test data information.

[0015] In some implementations, the system further includes: an interface module coupled to the address mask module, configured to output an interface signal according to the address information to be tested.

[0016] Correspondingly, the technical solution of the present application also provides a test system, including: a control module, configured to output initialization address information; a test circuit as described in any of the above items, coupled to the control module; a module to be tested, coupled to the test circuit, configured to receive the address information to be tested, and process based on the address information to be tested to output test data information; the test circuit is also configured to: feed back the test data information to the control module.

[0017] Correspondingly, the technical solution of the present application also provides a storage system, including: a control module, configured to output initialization address information; a test circuit as described in any of the above items, coupled to the control module; a storage module, coupled to the test circuit, configured to receive the address information to be tested, and process based on the address information to be tested to output test data information; the test circuit is also configured to: feed back the test data information to the control module.

[0018] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0019] In the test circuit of the technical solution of the present application, by setting an address mask module coupled to the logic algorithm vector generation module, part of the address information in the initial test address information output by the logic algorithm vector generation module is shielded, so that the logic address selected according to the preset rule can be converted into a discrete random address. Since the above-mentioned logic algorithm vector generation module can generate initial test address information with multiple discrete random addresses after obtaining a single initialization address information, it is beneficial to reduce the interaction frequency between the control module and the logic algorithm vector generation module, thereby reducing the test time of the discrete random address and improving the test efficiency. On the other hand, by shielding part of the address information in the initial test address information through the address mask module to generate the address information to be tested with multiple discrete random addresses, the complexity of program development can be reduced, which is beneficial to improve the efficiency of program development. In addition, by introducing the address mask module, the write disturb sampling density within the test address range can also be improved, that is, more write disturb addresses can be tested in a unit time, thereby increasing the number of sampled addresses and improving the credibility of the test results. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0021] Figure 1 is a schematic diagram of the structure of an embodiment of a test system;

[0022] Figure 2 is a structural schematic diagram of a test circuit in an embodiment of the present application;

[0023] Figure 3 yes Figure 2 A schematic diagram of the structure of an embodiment of the address mask module 220;

[0024] Figure 4 yes Figure 2 A schematic diagram of the structure of another embodiment of the address mask module 220;

[0025] Figure 5 is a structural schematic diagram of another test circuit in an embodiment of the present application;

[0026] Figure 6 It is a test system of an embodiment of the present application;

[0027] Figure 7 It is a storage system of an embodiment of the present application.

[0028] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0029] As described in the background art, the test speed of the chip test system needs to be improved urgently.

[0030] Figure 1 The present invention is a schematic diagram of a structure of a test system embodiment, comprising:

[0031] The control module 100 is used to output initialization information and address increment calculation information;

[0032] The test module 101 is coupled to the control module 100 and is used to process the initialization information and the address increment information and then output the test address information;

[0033] The module to be tested 102 is coupled to the testing module 101 and is used to perform a test according to the test address information to output test data information corresponding to the test address information;

[0034] The testing module 101 is further configured to feed back the testing data information to the control module 100 .

[0035] In some embodiments, the test module 101 is a storage module, which is a memory based on an architecture such as a phase-change memory (PCM); and the test module 101 is a test architecture including an algorithmic pattern generator (ALPG) unit, and the test module 101 is used to perform an aging test involving write interference on the module to be tested 102.

[0036] In the above embodiment, for the storage module, when the physical addresses are adjacent, the logical addresses are not necessarily adjacent. When it is necessary to perform a write interference test on the module to be tested 102, it is necessary to consider the interference between the storage cells with adjacent physical addresses. However, the logical addresses corresponding to the adjacent physical addresses are not necessarily adjacent. In order to meet the requirements of the write interference test for the physical address proximity, the corresponding logical addresses are usually discrete random addresses. When it is necessary to perform an aging test on the module to be tested 102, the logical address needs to be selected according to a preset rule; specifically, the logic algorithm vector generation unit in the test module 101 calculates the initialization information and the address increment information. Since the initialization address in the initialization information is fixed and the number of addresses set by the address increment information is limited, the generated test address information is usually a regular address.

[0037] Furthermore, when an aging test involving write disturbance is required for the module under test 102, in order to ensure the regularity of the physical address, the initialization state of the test module 101 needs to be repeatedly refreshed so that the corresponding discrete random logical address can be selected.

[0038] However, repeatedly refreshing the initialization state of the test module 101 will cause frequent switching of the communication direction between the control module 100 and the test module 101. The switching of the communication direction will introduce additional test time, which will cause the test time for discrete random logical addresses to be much longer than the theoretical test time.

[0039] In order to solve the above problems, the present application embodiment proposes a test circuit, please refer to Figure 2 , Figure 2 It is a structural diagram of a test circuit of an embodiment of the present application, including: a logic algorithm vector generation module 210, configured to receive initialization address information Init, and output initial test address information Addr_0 after processing the initialization address information Init; an address mask module 220, coupled to the logic algorithm vector generation module 210, configured to mask part of the address information in the initial test address information Addr_0 to output the address information to be tested Addr_1.

[0040] By setting an address mask module 220 coupled to the logic algorithm vector generation module 210, part of the address information in the initial test address information Addr_0 output by the logic algorithm vector generation module 210 is shielded, so that the logic address selected according to the preset rule can be converted into a discrete random address. Since the above-mentioned logic algorithm vector generation module 210 can generate the initial test address information Addr_0 with a multi-bit discrete random address after obtaining the single initialization address information, it is beneficial to reduce the interaction frequency between the control module and the logic algorithm vector generation module 210, thereby reducing the test time of the discrete random address and improving the test efficiency. On the other hand, by shielding part of the address information in the initial test address information Addr_0 through the address mask module 220 to generate the address information to be tested Addr_1 with a multi-bit discrete random address, the complexity of program development can be reduced, which is beneficial to improving program development efficiency. In addition, by introducing the address mask module 220, the write disturb sampling density within the test address range can be improved, that is, more write disturb addresses can be tested within a unit time, thereby increasing the number of sampled addresses and improving the credibility of the test results.

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0043] The logic algorithm vector generation module 210 is used to generate a test pattern according to the acquired information to test the module to be tested. Taking the high-speed memory test as an example, the logic algorithm vector generation module 210 can provide a comprehensive functional direct access test for the embedded memory, making it easy to perform a complete functional direct access test on the embedded memory with different data widths.

[0044] The logic algorithm vector generation module 210 is used to output a test mode according to the acquired initialization information, and the module to be tested coupled to the test circuit is tested according to the test mode. The initialization information includes the initialization address information Init, and the initialization address information Init is used to configure the address of the module to be tested. In addition, the initialization information also includes various types of initialization configuration information for configuring the initialization state of the module to be tested, and the initialization configuration information is used to initialize the configuration of the module to be tested.

[0045] In some embodiments, the initialization address information Init includes: an initial address and an address increment. The initial address is used to point to the initial address bit in the initial test address information Addr_0; the address increment information is used to point to each actual address bit that needs to be tested after the initial address bit. The logic algorithm vector generation module 210 is used to calculate the initialization information and the address increment information to obtain the initial address actually used for testing, that is, the initial test address information Addr_0.

[0046] The initial test address information Addr_0 includes an N-bit initial test address, where N is a natural number; in some embodiments, the initial test address includes at least a 3-bit address. Thus, after masking part of the address, the initial test address information Addr_0 can output a discrete address, namely, the address information to be tested Addr_1.

[0047] The address mask module 220 masks part of the address information in the initial test address information Addr_0, including: masks at least one bit of the initial test address in the N bits of the initial test address.

[0048] In one embodiment, the initial test address information Addr_0 includes an 8-bit initial test address, and the address mask module 220 masks the 2nd address, the 5th address, and the 7th address in the 8-bit initial test address. Then, the output address information to be tested Addr_1 is the 1st address, the 3rd address, the 4th address, the 6th address, and the 8th address in the 8-bit initial test address, that is, the address information to be tested Addr_1 is a discrete address.

[0049] In some embodiments, please refer to Figure 2 and Figure 3 , Figure 3 yes Figure 2A structural diagram of an embodiment of an address mask module 220 is shown in FIG. 2 , wherein the address mask module 220 comprises: a mask memory 221, configured to store mask information Addr_m; a logic unit 222, coupled to the mask memory 221, configured to mask part of the bit address information Addr_m in the initial test address information Addr_0 based on the mask information to output the address information Addr_1 to be tested.

[0050] The mask memory 221 is used to store mask information Addr_m; in some embodiments, the mask memory 221 is a random access memory (Random Access Memory, RAM for short); in other embodiments, the mask memory 221 can also be other types of memory.

[0051] Each of the mask information Addr_m includes the address bit information that needs to be masked in the corresponding initial test address information Addr_0. Since each address bit information that needs to be masked only needs to be stored with a capacity of 1 bit, the capacity of the mask memory 221 can store a large amount of the mask information Addr_m, and then in the case of limited FPGA resources, it is beneficial to mask more bits of the address in the initial test address information Addr_0 in a single masking process, thereby reducing the invalid test time.

[0052] The logic unit 222 is used to perform a logical operation on the mask information Addr_m and the initial test address information Addr_0 to output the masked random discrete address information to be tested Addr_1. In some embodiments, when the i-th bit in the mask information is "1", the i-th bit in the initial test address information Addr_0 needs to be tested; when the j-th bit in the mask information is "0", the j-th bit in the initial test address information Addr_0 needs to be masked. In other embodiments, when the i-th bit in the mask information is "0", the i-th bit in the initial test address information Addr_0 needs to be tested; when the j-th bit in the mask information is "1", the j-th bit in the initial test address information Addr_0 needs to be masked. Wherein, i and j are both natural numbers.

[0053] In some other embodiments, please refer to Figure 2 and Figure 4 , Figure 4 yes Figure 2The structural diagram of another embodiment of the address mask module 220 is as follows: the address mask module 220 includes: a decoder 223, coupled to the logic algorithm vector generation module 210, configured to parse the initial test address information Addr_0 and output the parsed information; a mask memory 221, coupled to the decoder 223, configured to store the mask information Addr_m, and output the mask information Addr_m according to the parsed information; a logic unit 222, coupled to the mask memory 221, configured to mask part of the bit address information in the initial test address information Addr_0 based on the mask information Addr_m, so as to output the address information to be tested Addr_1.

[0054] In some embodiments, please refer to Figure 5 , Figure 5 It is a structural schematic diagram of another test circuit of an embodiment of the present application, and the test circuit also includes: a scrambler (Scramble) 230, coupled to the logic algorithm vector generation module 210, configured to scramble the initial test address information Addr_0 and output the scrambled address information.

[0055] The scrambler 230 is used as an encryption interface for signal transmission between the logic algorithm vector generation module 210 and the module to be tested.

[0056] Please continue to refer to Figure 5 The test circuit further includes: a scrambling memory 231, coupled to the logic algorithm vector generation module 210 and the scrambler 230, and configured to: store scrambling configuration information; and output corresponding scrambling configuration information to the scrambler 230 according to the initial test address information Addr_0. The scrambler 230 is configured to scramble the initial test address information Addr_0 according to the scrambling configuration information to output scrambled address information.

[0057] In other embodiments, the test circuit may not include the scrambling memory 231 , and the scrambler 230 obtains the scrambling configuration information from a control module coupled to the test circuit.

[0058] In some other embodiments, please continue to refer to Figure 5 The test circuit further includes: a data buffer memory 240, coupled to the scrambler 230, configured to: store test data information; and output the test data information to the scrambler 230. The scrambler 230 is configured to scramble the test data information and then output it. The module to be tested coupled to the circuit to be tested is tested according to the address information to be tested Addr_1 and the test data information.

[0059] Please continue to refer to Figure 5 The test circuit further includes: an error data storage (Error Catch Ram, referred to as ECR) module 250, which is configured to receive test data information Data in response to the address information to be tested Addr_1, and output the test data information Data.

[0060] Please continue to refer to Figure 5 The test circuit further includes an interface module 206 coupled between the address mask module 220 and the module to be tested, and is configured to output an interface signal Cs_n to the module to be tested according to the address information Addr_1 to be tested.

[0061] Since the interface signal Cs_n corresponds to the address information to be tested Addr_1, the module to be tested can perform a test on the corresponding discrete address pointed to by the corresponding address information to be tested Addr_1 according to the interface signal Cs_n, and feed back corresponding test data information Data.

[0062] In some embodiments, the interface module 206 includes:

[0063] The timing generator 260 is configured to output a timing signal according to the control signal output by the control module;

[0064] The waveform generator 262 is coupled to the timing generator and the address mask module 220, and is configured to output an address waveform signal according to the address information Addr_1 to be tested and the timing signal;

[0065] A driving type unit 261, coupled to the timing generator, and configured to output a driving type signal according to the timing signal;

[0066] An interface driver 263, coupled to the waveform generator 262 and the drive type unit 261, and configured to output the interface signal Cs_n according to the address waveform signal and the drive type signal;

[0067] The input signal latch 264 is coupled to the error data storage module 250 and is configured to receive and store the test data information Data, where the test data information Data is a signal output by the module under test when the module under test is tested based on the interface signal Cs_n.

[0068] In summary, by setting an address mask module coupled to the logic algorithm vector generation module, part of the address information in the initial test address information output by the logic algorithm vector generation module is shielded, so that the logic address selected according to the preset rule can be converted into a discrete random address. Since the above-mentioned logic algorithm vector generation module can generate initial test address information with multiple discrete random addresses after obtaining a single initialization address information, it is beneficial to reduce the interaction frequency between the control module and the logic algorithm vector generation module, thereby reducing the test time of the discrete random address and improving the test efficiency. On the other hand, by shielding part of the address information in the initial test address information through the address mask module to generate the address information to be tested with multiple discrete random addresses, the complexity of program development can be reduced, which is beneficial to improving the efficiency of program development. In addition, by introducing the address mask module, the write interference sampling density within the test address range can also be improved, that is, more write interference addresses can be tested in a unit time, thereby increasing the number of sampled addresses and improving the credibility of the test results.

[0069] Accordingly, the embodiment of the present invention also provides a test system, please refer to Figure 6 , Figure 6 It is a test system of an embodiment of the present application, including: a control module 300, configured to output initialization address information Init; a test circuit 200, coupled to the control module 300, configured to receive the initialization address information Init, and process the initialization address information Init to output address information to be tested Addr_1; a module to be tested 400, coupled to the test circuit 200, configured to receive the address information to be tested Addr_1, and process based on the address information to be tested Addr_1 to output test data information Data; the test circuit 200 is also configured to feed back the test data information Data to the control module 300.

[0070] The following is a detailed description with reference to the accompanying drawings.

[0071] The test circuit is as follows Figures 2 to 5 As well as the description of the related embodiments, they are not elaborated here.

[0072] The control module 300 is a central processing unit (CPU) or an enhanced RISC (Reduced Instruction Set Computing) architecture processor (Advanced RISC Machines, ARM).

[0073] The module to be tested 400 includes a field programmable gate array (FPGA) or a memory array, etc.; the memory array includes a phase change memory (PCM).

[0074] The control module 300 is used to output the initialization address information Init. The test circuit 200 processes the initialization address new Init into the address information to be tested Addr_1 and outputs it to the module to be tested 400. After the module to be tested 400 performs a test according to the address information to be tested Addr_1, it outputs the test data information Data. The test data information Data is fed back to the control module 300 through the test circuit 200 so that the control module 300 can parse the test data information Data to obtain the test result.

[0075] Correspondingly, the embodiment of the present invention also proposes a storage system, please refer to Figure 7 , Figure 7 It is a storage system of an embodiment of the present application, including: a control module 300, configured to output initialization address information Init; a test circuit 200, coupled to the control module 300, configured to receive the initialization address information Init, and process the initialization address information Init to output address information to be tested Addr_1; a storage module 500, coupled to the test circuit 200, configured to receive the address information to be tested Addr_1, and process based on the address information to be tested Addr_1 to output test data information Data; the test circuit 200 is also configured to feed back the test data information Data to the control module 300.

[0076] The test circuit is as follows Figures 2 to 5 As well as the description of the related embodiments, they are not elaborated here.

[0077] The above descriptions are only optional embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings, or directly / indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A test circuit, characterized in that: include: A logic algorithm vector generation module is configured to receive initialization address information, process the initialization address information, and output initial test address information; The address mask module is coupled to the logic algorithm vector generation module and is configured to mask part of the address information in the initial test address information to output the address information to be tested.

2. The test circuit according to claim 1, characterized in that: The address mask module comprises: a mask memory configured to store mask information; The logic unit is coupled to the mask memory and is configured to mask part of the bit address information in the initial test address information based on the mask information to output the address information to be tested.

3. The test circuit according to claim 2, characterized in that: The address mask module also includes: A decoder, coupled to the logic algorithm vector generation module, configured to parse the initial test address information and output parsed information; The mask memory is coupled to the decoder, and is configured to output the mask information to the logic unit according to the parsing information.

4. The test circuit according to claim 1, characterized in that: Also includes: The scrambler is coupled to the logic algorithm vector generation module and is configured to perform scrambling processing on the initial test address information and output scrambled address information.

5. The test circuit according to claim 4, characterized in that: Also includes: A scrambling memory, coupled to the logic algorithm vector generation module and the scrambler, is configured as follows: Storing scrambling configuration information; Outputting corresponding scrambling configuration information to the scrambler according to the initial test address information; The scrambler is configured to perform scrambling processing on the initial test address information according to the scrambling configuration information to output scrambled address information.

6. The test circuit according to claim 4, characterized in that: Also includes: A data buffer memory, coupled to the scrambler, is configured to: Store test data information; Outputting test data information to the scrambler; The scrambler is configured to scramble the test data information and then output it.

7. The test circuit according to claim 1, characterized in that: Also includes: The error data storage module is configured to receive test data information in response to the address information to be tested and output the test data information.

8. The test circuit according to claim 1, characterized in that: Also includes: The interface module coupled to the address mask module is configured to output an interface signal according to the address information to be tested.

9. A testing system, characterized in that: include: A control module is configured to output initialization address information; The test circuit according to any one of claims 1 to 8, coupled to the control module; A module to be tested, coupled to the test circuit, and configured to receive the address information to be tested, and perform processing based on the address information to be tested to output test data information; The test circuit is further configured to feed back the test data information to the control module.

10. A storage system, characterized in that: include: A control module is configured to output initialization address information; The test circuit according to any one of claims 1 to 8, coupled to the control module; A storage module, coupled to the test circuit, configured to receive the address information to be tested, and perform processing based on the address information to be tested to output test data information; The test circuit is further configured to feed back the test data information to the control module.

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