Test method of storage chip, storage medium and electronic equipment

Abstract

The invention provides a test method of a memory chip, a storage medium and electronic equipment, and relates to the technical field of semiconductors. The test method of the memory chip comprises the following steps: sequentially determining n test word line addresses of a to-be-tested memory chip as target test word line addresses so as to traverse the n test word line addresses; the memory chip to be tested comprises a plurality of test word line groups, each test word line group comprises n word lines, and the n word lines in each test word line group respectively correspond to n test word line addresses; n is a multiple of 16; after the target test word line address is determined each time, controlling to apply an aging test voltage to a word line control circuit corresponding to the target test word line address; and detecting whether a word line control circuit of the to-be-tested memory chip is abnormal or not. The invention provides an aging test scheme which can detect the problem of local abnormality of the word line control circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a test method for a memory chip, a storage medium, and an electronic device. Background Art

[0002] As the feature size of semiconductor devices continues to shrink, the key size of memories such as DRAM (Dynamic Random Access Memory) is also getting smaller and smaller, and the process technology is increasingly prone to word line related defects, leading to word line failure and other problems.

[0003] In the related art, it is difficult to detect local abnormalities of word line control signals by testing word lines. Summary of the invention

[0004] The present disclosure provides a memory chip testing method, a storage medium and an electronic device, which at least to some extent solve the problem that it is difficult to detect a local abnormality of a word line control signal during a word line test.

[0005] According to a first aspect of the present disclosure, a method for testing a memory chip is provided, comprising: determining n test word line addresses of a memory chip to be tested as target test word line addresses in sequence to traverse the n test word line addresses; the memory chip to be tested comprises a plurality of test word line groups, each test word line group comprises n word lines, and the n word lines in each test word line group correspond to n test word line addresses respectively; n is a multiple of 16; after each determination of the target test word line address, controlling the application of an aging test voltage to a word line control circuit corresponding to the target test word line address; and detecting whether there is an abnormality in the word line control circuit of the memory chip to be tested.

[0006] Optionally, the detecting whether there is an abnormality in the word line control circuit of the memory chip to be tested includes: after the aging test voltage is applied to all the word line control circuits of the memory chip to be tested, determining whether there is an abnormality in the word line control circuit of the memory chip to be tested by reading data from the memory cell of the memory chip to be tested and comparing it with the written test data.

[0007] Optionally, the detecting whether there is an abnormality in the word line control circuit of the memory chip to be tested includes: in the process of applying an aging test voltage to the word line control circuit of the memory chip to be tested, determining whether there is an abnormality in the word line control circuit of the memory chip to be tested by monitoring the electrical parameters of the word line control circuit.

[0008] Optionally, among the n word lines of each test word line group, the first n / 2 word lines are connected to a main word line, and the last n / 2 word lines are connected to another main word line; the n test word line addresses of the memory chip to be tested are sequentially determined as target test word line addresses, including: determining the first n / 2 test word line addresses among the n test word line addresses as target test word line addresses; after the aging test voltage is applied to the word line control circuits corresponding to the first n / 2 test word line addresses, determining the last n / 2 test word line addresses among the n test word line addresses as target test word line addresses.

[0009] Optionally, the control applies an aging test voltage to the word line control circuit corresponding to the target test word line address, including: determining the corresponding m actual word line addresses according to the target test word line address, and controlling the application of the aging test voltage to the word line control circuit corresponding to the m actual word line addresses; m is the number of test word line groups in the memory chip to be tested.

[0010] Optionally, before sequentially determining the n test word line addresses of the memory chip to be tested as the target test word line address, the method further includes: controlling to turn off a bit line sense amplifier of the memory chip to be tested.

[0011] Optionally, the aging test voltage is greater than a word line turn-on control voltage.

[0012] Optionally, the n word lines in each test word line group are n word lines distributed continuously.

[0013] According to a second aspect of the present disclosure, a memory chip testing device is provided, comprising: a target test word line address determination module, configured to sequentially determine n test word line addresses of a memory chip to be tested as target test word line addresses, so as to traverse the n test word line addresses; the memory chip to be tested comprises a plurality of test word line groups, each test word line group comprises n word lines, and the n word lines in each test word line group correspond to n test word line addresses respectively; n is a multiple of 16; an aging test voltage application module, configured to control the application of an aging test voltage to a word line control line corresponding to the target test word line address after each determination of the target test word line address; and a word line control line abnormality detection module, configured to detect whether there is an abnormality in the word line control line of the memory chip to be tested.

[0014] According to a third aspect of the present disclosure, there is provided a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the method for testing a memory chip according to the first aspect and possible implementation methods thereof are implemented.

[0015] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the memory chip testing method of the above-mentioned first aspect and its possible implementation methods by executing the executable instructions.

[0016] The technical solution disclosed in this disclosure has the following beneficial effects:

[0017] An aging test scheme is provided. On the one hand, it can detect the problem of local abnormality of the word line control circuit and realize the reliability test of the word line control circuit. In particular, for the situation where multiple word line control circuits are turned on at the same time during defect detection, it can detect defects such as short circuit of the word line control circuit, and then take repair measures in time to ensure that the memory chip can meet the use requirements, reduce product DPPM, and improve yield. On the other hand, by compressing the word line address into n test word line addresses, applying the aging test voltage to the word line control circuit corresponding to at least one test word line address each time, it can save test time and improve efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A flow chart of a method for testing a memory chip in this exemplary embodiment is shown.

[0019] Figure 2 A schematic diagram showing a test word line group and a target test word line address in this exemplary embodiment is shown.

[0020] Figure 3 A flow chart for determining a target test word line address in this exemplary embodiment is shown.

[0021] Figure 4 A schematic structural diagram of a word line control circuit in this exemplary embodiment is shown.

[0022] Figure 5 FIG. 4 is a schematic diagram showing the structure of another word line control circuit in this exemplary embodiment.

[0023] Figure 6 A flow chart of another memory chip testing method in this exemplary embodiment is shown.

[0024] Figure 7 A schematic structural diagram of a memory chip testing device in this exemplary embodiment is shown.

[0025] Figure 8 A schematic structural diagram of an electronic device in this exemplary embodiment is shown. DETAILED DESCRIPTION

[0026] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings.

[0027] The accompanying drawings are schematic diagrams of the present disclosure and are not necessarily drawn to scale. The technical solution of the present disclosure can be implemented in various forms and should not be construed as being limited to the examples set forth herein. The features, structures or characteristics described in the present disclosure may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full description of the embodiments of the present disclosure. However, it will be understood by those skilled in the art that one or more specific details may be omitted when implementing the technical solution of the present disclosure, or one or more specific details may be replaced by other methods, components, structures, etc.

[0028] An exemplary embodiment of the present disclosure provides a method for testing a memory chip. Figure 1 An exemplary process of the method is shown, which may include the following steps S110 to S130:

[0029] Step S110, sequentially determining n test word line addresses of the memory chip to be tested as target test word line addresses to traverse the n test word line addresses; the memory chip to be tested includes a plurality of test word line groups, each test word line group includes n word lines, and the n word lines in each test word line group correspond to n test word line addresses respectively; n is a multiple of 16;

[0030] Step S120, after determining the target test word line address each time, controlling the application of an aging test voltage to the word line control circuit corresponding to the target test word line address;

[0031] Step S130, detecting whether the word line control circuit of the memory chip to be tested has any abnormality.

[0032] based on Figure 1 The method shown provides an aging test solution. On the one hand, it can detect the problem of local abnormality of the word line control circuit and realize the reliability test of the word line control circuit. In particular, for the situation where multiple word line control circuits are turned on at the same time during defect detection, it can detect defects such as short circuit of the word line control circuit, and then take repair measures in time to ensure that the memory chip can meet the use requirements, reduce the product DPPM (Defect Part Per Million), and improve the yield. On the other hand, by compressing the word line address into n test word line addresses, applying the aging test voltage to the word line control circuit corresponding to at least one test word line address each time, it can save test time and improve efficiency.

[0033] Below Figure 1 Provide detailed instructions for each step.

[0034] refer to Figure 1 In step S110, n test word line addresses of the memory chip to be tested are sequentially determined as target test word line addresses to traverse the n test word line addresses; the memory chip to be tested includes a plurality of test word line groups, each test word line group includes n word lines, and the n word lines in each test word line group correspond to n test word line addresses respectively; n is a multiple of 16.

[0035] Among them, the memory chip to be tested can be a chip of a memory device such as DRAM, which can be a chip on an uncut wafer or a chip after the wafer is cut. That is to say, this exemplary embodiment can test the chip on the wafer or the independent chip after the wafer is cut.

[0036] The memory chip to be tested includes memory cells distributed in rows and columns. The memory cells in each row correspond to a word line (WordLine, WL). The word line can control the gate of the transistor in the memory cell to realize the opening and closing of the transistor. The memory cells in each column correspond to a bit line (BitLine, BL). The bit line can charge and discharge the capacitor in the memory cell to realize data reading and writing. The memory chip to be tested may include z word lines, such as z can be 65536. These word lines can be divided into several test word line groups, each test word line group includes n word lines, and n is a multiple of 16, such as 16, 32, etc. The number of test word line groups in the memory chip to be tested is m=z / n. If z is 65536 and n is 16, then m is 4096.

[0037] The n word lines in each test word line group correspond to n test word line addresses respectively, and the word lines at the same position in different test word line groups correspond to the same test word line address. For example, the first word line in each test word line group may correspond to test word line address 0 (test word line address 0 represents the first test word line address), the second word line in each test word line group may correspond to test word line address 1, and so on.

[0038] Generally, different word lines in the memory chip to be tested have different actual word line addresses (which may be row addresses), and there are a total of z actual word line addresses in the memory chip to be tested. The test word line address is equivalent to compressing the actual word line address, and compressing the z actual word line addresses into n test word line addresses. Such a test word line address corresponds to multiple word lines, and multiple word lines can be controlled to be tested at the same time, thereby saving test time.

[0039] The target test word line address is the test word line address currently to be tested. At the same time, the target test word line address can be one address or multiple addresses. The target test word line address is determined in sequence among the n test word line addresses. For example, the n test word line addresses are test word line address 0, test word line address 1, ..., test word line address n-1. One test word line address can be determined as the target test word line address each time in the order of 0, 1, 2, ..., n-1, or n / k test word line addresses can be determined as the target test word line address each time, and k is 2, 4 or 8. By determining the target test word line address in sequence, traversing the n test word line addresses, each test word line address is tested as the target test word line address, so that all test word line addresses participate in the test.

[0040] In one embodiment, the n word lines in each test word line group are n word lines that are continuously distributed. Continuous distribution means that the n word lines are adjacent to each other in sequence, such as the first word line to the nth word line, the n+1th word line to the 2nth word line, etc. In this way, the different word lines corresponding to each test word line address are evenly distributed in the memory cell array of the memory chip to be tested, and the word lines and word line control circuit structures at different positions can be evenly tested in the aging test, thereby improving the test effect.

[0041] The actual word line address of the memory chip to be tested is compressed into n test word line addresses, where n is a multiple of 16. In this way, there is a large interval between the word lines corresponding to different test word line addresses, and abnormal word lines or word line control circuits can be quickly located in subsequent tests.

[0042] Continue to refer Figure 1 In step S120, after the target test word line address is determined each time, the aging test voltage is controlled to be applied to the word line control circuit corresponding to the target test word line address.

[0043] The word line control circuit may include one or more of a word line drive circuit, a main word line to which the word line belongs, and a main word line drive circuit. After determining the target test word line address, since the target test word line address corresponds to multiple word lines, an aging test voltage may be applied to the word line control circuits of these word lines.

[0044] The aging test voltage is usually a relatively high voltage, which can form a certain electrical stress between different word line control circuits to accelerate the aging of word lines, word line control circuits and related structures. In one embodiment, the aging test voltage can be greater than the word line turn-on control voltage. The word line turn-on control voltage is the voltage of the word line control circuit when the word line is normally turned on. The aging test voltage is greater than the word line turn-on control voltage, which means that the word line control circuit is at a higher voltage than the normal working voltage, thereby achieving the purpose of accelerating aging and accelerating testing.

[0045] In one embodiment, n is 16. Figure 2 As shown, every 16 word lines form a test word line group, and the memory chip to be tested may include 16 test word line addresses, and each test word line address may correspond to and control the bit lines in different test word line groups. For example, when the test word line address 1 is determined to be the target test word line address, an aging test voltage may be applied to the word line control line of the first word line in each test word line group. Then, when the test word line address 2 is determined to be the target test word line address, an aging test voltage may be applied to the word line control line of the second word line in each test word line group... Thus, by applying the aging test voltage 16 times, the aging test voltage may be applied to the word line control lines of all word lines.

[0046] Continue to refer Figure 1 In step S130, it is detected whether there is any abnormality in the word line control circuit of the memory chip to be tested.

[0047] Among them, by applying an aging test voltage to the word line control circuit, the hidden problems in the word line control circuit can be accelerated. For example, if there are hidden defects around the word line control circuit, such as physical defects of materials between the word line control circuits, by applying an aging test voltage, the development of hidden defects can be accelerated, such as developing into explicit problems such as short circuits of the word line control circuits. Therefore, by applying an aging test voltage, it is possible to detect whether there is an abnormality in the word line control circuit, such as by detecting the electrical parameters of the word line control circuit to determine whether there is an abnormality, or by detecting the data reading and writing of the word line controlled by the word line control circuit to determine whether there is an abnormality in the word line control circuit.

[0048] In one embodiment, the above-mentioned detection of whether the word line control circuit of the memory chip to be tested is abnormal may include the following steps:

[0049] After the aging test voltage is applied to all word line control lines of the memory chip to be tested, data is read from the memory cells of the memory chip to be tested and compared with the written test data to determine whether the word line control lines of the memory chip to be tested are abnormal.

[0050] Among them, writing test data to the storage unit can be done before applying the aging test voltage or after the aging test voltage is applied. When detecting a certain word line control circuit, the word line controlled by the word line control circuit can be turned on, and the data in the storage unit of the corresponding row can be read through the bit line. If the word line control circuit has defects such as short circuit, it may cause signals to be generated on other word line control circuits to mistakenly turn on the word lines controlled by other word line control circuits, so that multiple rows of storage cells in the memory chip to be tested are turned on, which will cause abnormal reading of data. In this way, it can be determined whether the word line control circuit is abnormal.

[0051] In one embodiment, the above-mentioned detection of whether the word line control circuit of the memory chip to be tested is abnormal may include the following steps:

[0052] During the process of applying the aging test voltage to the word line control circuit of the memory chip to be tested, the electrical parameters of the word line control circuit are monitored to determine whether the word line control circuit of the memory chip to be tested is abnormal.

[0053] Exemplarily, after each determination of the target test word line address, during the process of applying the aging test voltage to the word line control line corresponding to the target test word line address, the electrical parameters of the word line control line and other word line control lines can be detected, and whether the word line control line corresponding to the target test word line address is abnormal can be determined based on the detection result. For example, if it is detected that the current on the word line control line adjacent to the word line control line corresponding to the target test word line address is too high, it means that there may be a short circuit between the word line control line corresponding to the target test word line address and the word line control line adjacent to it. In this way, abnormal word line control lines can be discovered in a timely manner.

[0054] In one implementation, before sequentially determining the n test word line addresses of the memory chip to be tested as the target test word line address, the memory chip test method may further include the following steps:

[0055] The bit line sense amplifier of the memory chip to be tested is controlled to be turned off.

[0056] The bit line sense amplifier (SA) is connected to the bit line of the memory chip to be tested, and can capture the weak voltage fluctuation in the bit line and restore the capacitor voltage in the memory cell, thereby detecting the charge and discharge of the memory cell to realize data reading. A latch can also be set in the bit line sense amplifier to temporarily store the information of the memory cell for dynamic refresh.

[0057] Before determining the target test word line address, that is, before performing the aging test, the bit line sense amplifier can be turned off. In the process of applying the aging test voltage, there is no need to detect the voltage condition in the bit line through the bit line sense amplifier, and there is no need to parse and process the relevant data of the bit line sense amplifier. This can reduce the working time of the bit line sense amplifier and protect it, which is conducive to reducing the test cost and extending the life of the bit line sense amplifier.

[0058] In one embodiment, the bit line sense amplifier can be turned on again after the aging test voltage is applied. For example, after the aging test voltage is applied to all word line control lines, when the word line control lines need to be detected for abnormality, the bit line sense amplifier can be turned on to sense and amplify the bit line voltage, read the data of the storage unit, and then determine whether the word line control lines are abnormal.

[0059] In one embodiment, among the n word lines in each test word line group, the first n / 2 word lines are connected to a main word line (MWL), and the last n / 2 word lines are connected to another main word line. Figure 3 As shown, the above-mentioned determining the n test word line addresses of the memory chip to be tested as the target test word line address in sequence may include the following steps S310 and S320:

[0060] Step S310, determining the first n / 2 test word line addresses among the n test word line addresses as target test word line addresses;

[0061] Step S320 , after the aging test voltage is applied to the word line control circuits corresponding to the first n / 2 test word line addresses, the last n / 2 test word line addresses among the n test word line addresses are determined as target test word line addresses.

[0062] That is to say, the aging test process can be divided into two stages. In the first stage, n / 2 test word line addresses are the target test word line addresses. For example, if the memory chip to be tested has 16 test word line addresses, which are test word line address 0 to test word line address 15, test word line address 0 to test word line address 7 can be first determined as the target test word line address, and the aging test voltage is applied to the corresponding word line control line to end. After the second stage, n / 2 test word line addresses are the target test word line addresses, such as test word line address 8 to test word line address 15 are determined as the target test word line address, and the aging test voltage is applied to the corresponding word line control line to end. This can further improve the test efficiency.

[0063] Furthermore, when the aging test voltage is applied to the word line control circuit corresponding to the first n / 2 test word line addresses, it is equivalent to applying a higher voltage to the main word line connected to the first n / 2 word lines in each test word line group. When the aging test voltage is applied to the word line control circuit corresponding to the last n / 2 test word line addresses, it is equivalent to applying a higher voltage to the main word line connected to the last n / 2 word lines in each test word line group. An aging test of the main word line can be implemented to find abnormalities in the main word line.

[0064] Figure 4 and Figure 5 Figure 2 shows the structure diagram of two word line control circuits. Figure 4 or Figure 5 As shown, the main word line MWL0 can correspond to the control word lines (or sub-word lines) WL0-WL7, and the main word line MWL1 can correspond to the control word lines WL8-WL15 ( Figure 4 or Figure 5 Not all word lines WL are shown in the figure). When performing a word line test, if only one of the main word lines MWL0 and MWL1 is turned on at the same time, there is a certain voltage difference between the two main word lines, and an aging test of the main word line can be performed. If both the main word lines MWL0 and MWL1 are turned on at the same time, there is no voltage difference between the two main word lines, and an aging test of the main word line cannot be performed. In this exemplary embodiment, by setting the above-mentioned two-stage aging test, the first n / 2 test word line addresses and the last n / 2 test word line addresses are separately subjected to aging tests, which can ensure that voltage is not applied to two adjacent main word lines at the same time, thereby allowing an aging test of the main word line to be performed. Therefore, this exemplary embodiment is applied to Figure 4 or Figure 5 When the circuit structure is as follows, the aging test of the main word line can be realized.

[0065] In one embodiment, the above control of applying the aging test voltage to the word line control circuit corresponding to the target test word line address may include the following steps:

[0066] Determine the corresponding m actual word line addresses according to the target test word line address, and control the word line control circuits corresponding to the m actual word line addresses to apply an aging test voltage; m is the number of test word line groups in the memory chip to be tested.

[0067] Among them, each test word line address can correspond to m actual word line addresses. If a test word line address is determined as the target test word line address each time, the corresponding m actual word line addresses can be found. Exemplarily, if the n word lines in each test word line group are distributed continuously, the actual word line addresses of these n word lines are also distributed continuously. After determining the target test word line address add0, add0 itself can be determined to be an actual word line address, and add0 is added with n in sequence to obtain add0+n, add0+2n, add0+3n, ..., add0+(m-1)n, and a total of m actual word line addresses are obtained. Of course, the encoding method of the target test word line address and the actual word line address may be different. The target test word line address can be decoded and the corresponding m actual word line addresses can be obtained by the above calculation method.

[0068] When m actual word line addresses are determined, an aging test voltage may be applied to the word line control lines corresponding to the m actual word line addresses, thereby enabling accurate aging test.

[0069] In one embodiment, the process of the memory chip testing method can refer to Figure 6 As shown, the following steps are included:

[0070] Step S610, power on the test system and initialize it.

[0071] Step S620 , setting a burn-in (BI) test voltage, and turning off the bit line sense amplifier of the memory chip to be tested.

[0072] Step S630, obtaining 16 test word line addresses and corresponding BANK information, wherein, since the actual word line addresses are compressed into 16 test word line addresses, it is equivalent to compressing the BANK of the memory chip to be tested, such as compressing the BANK into 1 / 16.

[0073] Step S640: Using the test word line addresses 0 to 7 as target test word line addresses, an aging test voltage is applied to the word line control circuit, with a set pause time as an interval.

[0074] Step S650: Using the test word line addresses 8 to 15 as the target test word line addresses, applying an aging test voltage to the word line control circuit, with a set pause time as the interval.

[0075] Step S660, exit the setting of the aging test voltage, and the aging test ends.

[0076] The exemplary embodiment of the present disclosure also provides a test device for a memory chip. Figure 7 As shown, the memory chip testing device 700 may include the following modules:

[0077] The target test word line address determination module 710 is configured to sequentially determine n test word line addresses of the memory chip to be tested as target test word line addresses to traverse the n test word line addresses; the memory chip to be tested includes a plurality of test word line groups, each test word line group includes n word lines, and the n word lines in each test word line group correspond to n test word line addresses respectively; n is a multiple of 16;

[0078] The aging test voltage applying module 720 is configured to control the application of the aging test voltage to the word line control circuit corresponding to the target test word line address after determining the target test word line address each time;

[0079] The word line control circuit abnormality detection module 730 is configured to detect whether there is an abnormality in the word line control circuit of the memory chip to be tested.

[0080] In one embodiment, the above-mentioned detection of whether the word line control circuit of the memory chip to be tested is abnormal includes:

[0081] After the aging test voltage is applied to all word line control lines of the memory chip to be tested, data is read from the memory cells of the memory chip to be tested and compared with the written test data to determine whether the word line control lines of the memory chip to be tested are abnormal.

[0082] In one embodiment, the above-mentioned detection of whether the word line control circuit of the memory chip to be tested is abnormal includes:

[0083] During the process of applying the aging test voltage to the word line control circuit of the memory chip to be tested, the electrical parameters of the word line control circuit are monitored to determine whether the word line control circuit of the memory chip to be tested is abnormal.

[0084] In one embodiment, among the n word lines of each test word line group, the first n / 2 word lines are connected to one main word line, and the last n / 2 word lines are connected to another main word line. The above-mentioned n test word line addresses of the memory chip to be tested are sequentially determined as the target test word line addresses, including:

[0085] Determine the first n / 2 test word line addresses among the n test word line addresses as target test word line addresses;

[0086] After the aging test voltage is applied to the word line control lines corresponding to the first n / 2 test word line addresses, the last n / 2 test word line addresses among the n test word line addresses are determined as target test word line addresses.

[0087] In one embodiment, the control of applying an aging test voltage to a word line control circuit corresponding to a target test word line address includes:

[0088] Determine the corresponding m actual word line addresses according to the target test word line address, and control the word line control circuits corresponding to the m actual word line addresses to apply an aging test voltage; m is the number of test word line groups in the memory chip to be tested.

[0089] In one implementation, the target test word line address determination module 710 is further configured to:

[0090] Before the n test word line addresses of the memory chip to be tested are determined in sequence as the target test word line address, the bit line sense amplifier of the memory chip to be tested is controlled to be turned off.

[0091] In one embodiment, the burn-in test voltage is greater than the word line turn-on control voltage.

[0092] In one implementation, the n word lines in each test word line group are n word lines that are continuously distributed.

[0093] The specific details of each part of the above-mentioned device have been described in detail in the implementation method of the method part. The undisclosed details can be found in the implementation method of the method part, so they will not be repeated here.

[0094] The exemplary embodiments of the present disclosure also provide a computer-readable storage medium, which can be implemented in the form of a program product, which includes a program code, and when the program product is run on an electronic device, the program code is used to cause the electronic device to perform the steps described in the above "Exemplary Method" section of this specification according to various exemplary embodiments of the present disclosure. In an optional embodiment, the program product can be implemented as a portable compact disk read-only memory (CD-ROM) and includes program code, and can be run on an electronic device, such as a personal computer. However, the program product of the present disclosure is not limited to this, and in this document, the readable storage medium can be any tangible medium containing or storing a program, which can be used by or in combination with an instruction execution system, device or device.

[0095] The program product may use any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0096] Computer readable signal media may include data signals propagated in baseband or as part of a carrier wave, in which readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Readable signal media may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0097] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the foregoing.

[0098] Program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0099] The exemplary embodiment of the present disclosure also provides an electronic device, such as a main control computer of a test device that executes the test method of the above-mentioned memory chip. The electronic device may include a processor and a memory. The memory stores executable instructions of the processor, such as program codes. The processor executes the method in the exemplary embodiment by executing the executable instructions.

[0100] Reference below Figure 8 , the electronic device is exemplarily described in the form of a general-purpose computing device. It should be understood that Figure 8 The electronic device 800 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0101] like Figure 8 As shown, the electronic device 800 may include: a processor 810 , a memory 820 , a bus 830 , an I / O (input / output) interface 840 , and a network adapter 850 .

[0102] The memory 820 may include a volatile memory, such as a RAM 821, a cache unit 822, and may also include a non-volatile memory, such as a ROM 823. The memory 820 may also include one or more program units 824, such program units 824 include but are not limited to: an operating system, one or more application programs, other program units, and program data, each of which or a combination thereof may include the implementation of a network environment. For example, the program unit 824 may include each module in the above-mentioned device.

[0103] The bus 830 is used to realize the connection between different components of the electronic device 800, and may include a data bus, an address bus, and a control bus.

[0104] The electronic device 800 can communicate with one or more external devices 900 (eg, a keyboard, a mouse, an external controller, etc.) through the I / O interface 840 .

[0105] The electronic device 800 can communicate with one or more networks through the network adapter 850. For example, the network adapter 850 can provide mobile communication solutions such as 3G / 4G / 5G, or provide wireless communication solutions such as wireless LAN, Bluetooth, near field communication, etc. The network adapter 850 can communicate with other units of the electronic device 800 through the bus 830.

[0106] although Figure 8 Not shown, other hardware and / or software units may also be provided in the electronic device 800, including but not limited to: a display, a microcode, a device driver, a redundant processor, an external disk drive array, a RAID system, a tape drive, and a data backup storage system.

[0107] It should be noted that, although several units or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the exemplary embodiments of the present disclosure, the features and functions of two or more units or units described above can be embodied in one unit or unit. Conversely, the features and functions of one unit or unit described above can be further divided into multiple units or units to be embodied.

[0108] It will be appreciated by those skilled in the art that various aspects of the present disclosure may be implemented as a system, method or program product. Therefore, various aspects of the present disclosure may be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation combining hardware and software aspects, which may be collectively referred to herein as a "circuit", "unit" or "system". Those skilled in the art will readily think of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any variations, uses or adaptive changes of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and implementation are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0109] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A method for testing a memory chip, characterized in that: include: sequentially determining n test word line addresses of the memory chip to be tested as target test word line addresses to traverse the n test word line addresses; The memory chip to be tested includes a plurality of test word line groups, each test word line group includes n word lines, and the n word lines in each test word line group correspond to n test word line addresses respectively; n is a multiple of 16; After determining a target test word line address each time, controlling to apply an aging test voltage to a word line control circuit corresponding to the target test word line address; Detect whether a word line control circuit of the memory chip to be tested is abnormal.

2. The method according to claim 1, characterized in that The detecting whether a word line control circuit of the memory chip to be tested is abnormal comprises: After the aging test voltage is applied to all word line control lines of the memory chip to be tested, data is read from the memory cells of the memory chip to be tested and compared with the written test data to determine whether the word line control lines of the memory chip to be tested are abnormal.

3. The method according to claim 1, characterized in that The detecting whether a word line control circuit of the memory chip to be tested is abnormal comprises: In the process of applying the aging test voltage to the word line control circuit of the memory chip to be tested, it is determined whether the word line control circuit of the memory chip to be tested is abnormal by monitoring the electrical parameters of the word line control circuit.

4. The method according to claim 1, characterized in that: Among the n word lines of each test word line group, the first n / 2 word lines are connected to one main word line, and the last n / 2 word lines are connected to another main word line; The step of sequentially determining n test word line addresses of the memory chip to be tested as target test word line addresses comprises: Determine the first n / 2 test word line addresses among the n test word line addresses as target test word line addresses; After the aging test voltage is applied to the word line control lines corresponding to the first n / 2 test word line addresses, the last n / 2 test word line addresses among the n test word line addresses are determined as target test word line addresses.

5. The method according to claim 1, characterized in that The controlling of applying an aging test voltage to a word line control circuit corresponding to the target test word line address includes: Determine m corresponding actual word line addresses according to the target test word line address, and control the word line control circuits corresponding to the m actual word line addresses to apply an aging test voltage; m is the number of test word line groups in the memory chip to be tested.

6. The method according to claim 1, characterized in that Before sequentially determining the n test word line addresses of the memory chip to be tested as the target test word line addresses, the method further includes: The bit line sense amplifier of the memory chip to be tested is controlled to be turned off.

7. The method according to any one of claims 1 to 6, characterized in that: The aging test voltage is greater than the word line turn-on control voltage.

8. The method according to any one of claims 1 to 6, characterized in that: The n word lines in each test word line group are n word lines distributed continuously.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

10. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to perform the method of any one of claims 1 to 8 by executing the executable instructions.

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