Flash open block test method and related equipment thereof

Abstract

The embodiment of the invention provides a flash open block test method and related equipment thereof, and the method comprises the steps: obtaining a plurality of test samples of a flash open block, and selecting a plurality of test blocks from each test sample; carrying out a life early-stage data retention experiment on the plurality of selected test blocks, and obtaining the bit flipping number of each open case corresponding to the open block; a plurality of target open cases are selected from a plurality of open cases corresponding to the open block based on the number of bit flipping, and the plurality of target open cases are subjected to life middle and later period data retention experiments, so that the data retention performance of the open block is determined based on experimental data, the data retention performance of the open block can be rapidly and effectively evaluated, the test time of the 3D TLC flash memory is saved, and the test efficiency of the 3D TLC flash memory is improved. And the test conclusion is more stable and reliable.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic information technology, and in particular to a flash memory open block testing method and related equipment. Background Art

[0002] As a non-volatile storage medium, flash memory has been widely used in many application fields. Data retention capability is particularly critical to ensuring the reliability of flash memory, especially when dealing with incompletely programmed blocks (open blocks). Compared with fully programmed blocks (close blocks), the data retention characteristics of open blocks are often weaker. As the block size of 3D TLC flash memory increases, the number of blocks in the open state increases, which makes it more complicated to evaluate the data retention performance of open blocks.

[0003] Currently, methods for evaluating open block data retention performance must take into account all possible open states and the entire life cycle phase of the product, which results in a testing cycle that may be as long as several months or even a year, adversely affecting the product's time to market. Summary of the invention

[0004] The embodiment of the present application provides a flash memory open block testing method and related equipment, which can select multiple target open cases based on the number of bit flips at the beginning of life, and then conduct data retention experiments in the middle and late stages of life, so as to quickly and effectively evaluate the data retention performance of the open block, save the testing time of 3D TLC flash memory, and make the test conclusion more stable and reliable.

[0005] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present application provides a flash memory open block testing method, comprising: obtaining multiple test samples of a flash memory open block, and selecting multiple test blocks from each of the test samples; performing a pre-life data retention experiment on the selected multiple test blocks to obtain the number of bit flips for each open case corresponding to the flash memory open block; selecting multiple target open cases from the multiple open cases corresponding to the flash memory open block based on the number of bit flips, and performing a mid- and late-life data retention experiment on the multiple target open cases to determine the data retention performance of the flash memory open block based on the experimental data.

[0006] In some embodiments, the performing of a pre-life data retention experiment on the selected multiple test blocks to obtain the number of bit flips of each open case corresponding to the flash memory open block includes: erasing the selected multiple test blocks to a first target PEcycles to place the flash memory open block in an early stage of its service life; configuring a corresponding open case initial state for each of the test blocks to simulate a data retention experiment under preset environmental conditions, and reading and recording the number of bit flips of each open case in the experiment.

[0007] In some embodiments, selecting multiple target open cases from multiple open cases corresponding to the flash memory open block based on the number of bit flips includes: determining the number of state samples corresponding to the flash memory open block; sorting the multiple open cases corresponding to the flash memory open block based on the number of bit flips to obtain an open case sequence; and selecting multiple target open cases from the open case sequence according to the number of state samples.

[0008] In some embodiments, determining the number of state samples corresponding to the flash memory open block includes: obtaining the number of open case states corresponding to the flash memory open block; and determining the number of state samples according to the number of open case states and a preset sampling ratio.

[0009] In some embodiments, selecting multiple target open cases from the open case sequence according to the state sampling number includes: obtaining a first sampling number n1, a second sampling number n2, and a third sampling number n3 according to the state sampling number and a preset sampling distribution ratio; selecting n1 target open cases with the largest number of bit flips from the open case sequence; selecting n2 target open cases with the number of bit flips close to the median from the open case sequence; and selecting n3 target open cases with the smallest number of bit flips from the open case sequence.

[0010] In some embodiments, n1 accounts for 60% of the number of state samples, n2 accounts for 30% of the number of state samples, and n3 accounts for 10% of the number of state samples.

[0011] In some embodiments, the mid-to-late stage data retention experiment on the multiple target open cases includes: erasing the selected multiple test blocks to a second target PE cycles so that the flash memory open block is in the mid-stage of its service life, performing a data retention experiment on the multiple target open cases, and recording mid-stage experimental data of the multiple target open cases; erasing the selected multiple test blocks to a third target PE cycles so that the flash memory open block is in the late stage of its service life, performing a data retention experiment on the multiple target open cases, and recording late stage experimental data of the multiple target open cases.

[0012] To achieve the above-mentioned purpose, the second aspect of an embodiment of the present application provides a flash memory open block testing device, including: a data acquisition unit, used to acquire multiple test samples of a flash memory open block, and select multiple test blocks from each of the test samples; a pre-life experiment unit, used to erase the selected multiple test blocks to a first target PE cycles to perform a pre-life data retention experiment, and obtain the number of bit flips for each opencase corresponding to the flash memory open block; a mid- and late-life experiment unit, used to select multiple target open cases from the multiple open cases corresponding to the flash memory openblock based on the number of bit flips, and perform a mid- and late-life data retention experiment on the multiple target open cases to determine the data retention performance of the flash memory open block based on the experimental data.

[0013] To achieve the above-mentioned purpose, a third aspect of the embodiments of the present application proposes a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the flash memory open block testing method as described in any one of the embodiments of the first aspect.

[0014] To achieve the above-mentioned purpose, the fourth aspect of the embodiments of the present application proposes a computer program product, which includes a computer program stored in a computer-readable storage medium. The processor of the computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the flash memory open block test method as described in any one of the embodiments of the first aspect.

[0015] The flash memory open block test method and related equipment provided by the embodiment of the present application can ensure that different open states are covered by selecting multiple test blocks (blocks) from multiple flash memory samples; further, the selected test blocks are erased to a predetermined PE cycle (program / erase cycle) so that the flash memory enters the early stage of its service life and then a data retention experiment is performed to record the number of data bit flips in each open case state; further, based on the number of bit flips obtained in the early life experiment, multiple target open cases with a large number of bit flips are selected from all open cases to ensure that these open cases are representative; further, a data retention experiment is performed on the selected target open cases in the middle and late stages of the life, and an accelerated aging method such as high-temperature baking is used to simulate the real use environment to evaluate the data retention performance of these open cases at different stages of the flash memory life; it can be understood that compared with the traditional method that needs to cover all open states and life cycles, the present solution only needs to select multiple representative target open cases for the data retention experiment in the middle and late stages of the life, which can effectively shorten the test cycle to save the test time of the 3D TLC flash memory, and by screening the target open cases with a large number of bit flips case, ensuring the representativeness of the test results, improving the accuracy of the test, and making the test conclusions more stable and reliable, thereby ensuring the timely delivery of flash media performance data and ensuring that flash products can be launched on the market in a timely manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flowchart of a flash memory open block testing method provided in an embodiment of the present application;

[0017] Figure 2 A flowchart of a flash memory open block testing method provided in an embodiment of the present application;

[0018] Figure 3 A flowchart of a flash memory open block testing method provided in an embodiment of the present application;

[0019] Figure 4 A flowchart of a flash memory open block testing method provided in an embodiment of the present application;

[0020] Figure 5 A flowchart of a flash memory open block testing method provided in an embodiment of the present application;

[0021] Figure 6 A flowchart of a flash memory open block testing method provided in an embodiment of the present application;

[0022] Figure 7 An example flow chart of a flash memory open block testing method provided in an embodiment of the present application;

[0023] Figure 8 A data schematic diagram of a flash memory open block testing method provided in an embodiment of the present application;

[0024] Fig. 9 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0026] In some embodiments, although the functional units are divided in the system schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the unit division in the system or the order in the flowchart. The terms first, second, etc. in the specification, claims, and the above drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0027] In addition, unless otherwise clearly specified and limited, the term "connected" should be understood in a broad sense. For example, it can be a fixed connection or a movable connection, a detachable connection or a non-detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or the two can communicate with each other; it can be a direct connection or an indirect connection through an intermediate medium.

[0028] In the description of the embodiments of the present application, the description of reference terms "one embodiment / implementation", "another embodiment / implementation" or "certain embodiments / implementations", "in the above embodiments / implementations", etc. means that the specific features, structures, materials or characteristics described in combination with the implementation or example are included in at least two embodiments or implementations disclosed in the present application. In the disclosure of this application, the schematic representation of the above terms does not necessarily refer to the same embodiment or implementation. It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in an order different from that in the flowchart.

[0029] As a non-volatile storage medium, flash memory has been widely used in many application fields. Data retention capability is particularly critical to ensure the reliability of flash memory, especially when dealing with incompletely programmed blocks (open blocks). Compared with fully programmed blocks (close blocks), the data retention characteristics of open blocks are often weaker. As the block size of 3D TLC flash memory increases, the number of blocks in the open state increases, which makes it more complicated to evaluate the data retention performance of open blocks. Currently, the method for evaluating the data retention performance of open blocks must take into account all possible open states and the entire life cycle stage of the product, which results in a test cycle that may be as long as several months or even a year, thus adversely affecting the product's time to market.

[0030] Based on this, the present application provides an embodiment of the present application that provides a flash memory open block testing method and related equipment, the method comprising obtaining multiple test samples of the flash memory open block, and selecting multiple test blocks from each test sample; performing an early-life data retention experiment on the selected multiple test blocks to obtain the number of bit flips for each open case corresponding to the flash memory open block; selecting multiple target open cases from the multiple open cases corresponding to the flash memory open block based on the number of bit flips, and performing mid- and late-life data retention experiments on the multiple target open cases to determine the data retention performance of the flash memory open block based on the experimental data, wherein the present application can quickly and effectively evaluate the data retention performance of the openblock, save the testing time of the 3D TLC flash memory, and make the test conclusion more stable and reliable.

[0031] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0032] refer to Figure 1 , Figure 1 A flowchart of a flash memory open block test method provided in an embodiment of the present application; in some embodiments, the present application discloses a flash memory open block test method, including but not limited to the following steps:

[0033] Step S110, obtaining multiple test samples of the open block of the flash memory, and selecting multiple test blocks from each test sample;

[0034] In some embodiments, an open block refers to a flash memory block that is not completely filled with data. If some pages in a block have not been written with data, then this block is an open block; a test sample refers to a flash memory device or a partial area thereof used for testing; and a test block is a flash memory block selected from the test sample for performing a specific test.

[0035] Step S120, performing a pre-life data retention experiment on the selected multiple test blocks to obtain the number of bit flips of each open case corresponding to the flash memory openblock;

[0036] In some embodiments, the pre-life data retention experiment is a data retention capability test performed when the flash memory is in the early stages of its service life. Through programming and erasing operations (PE cycles), the flash memory is put into a certain wear state, and then the data retention test is performed. Open case: In an open block, different data writing modes or states, each open case represents a specific incompletely written state. Number of bit flips: In a data retention experiment, the number of times a data bit changes from 0 to 1 or from 1 to 0 due to factors such as aging. The number of bit flips reflects the strength of the data retention capability.

[0037] Step S130, selecting multiple target open cases from multiple open cases corresponding to the flash memory open block based on the number of bit flips, and performing mid- and late-life data retention experiments on the multiple target open cases to determine the data retention performance of the flash memory open block based on the experimental data.

[0038] In some embodiments, target open case: a representative open case screened out from all open cases, and open cases with a higher number of bit flips are usually selected as targets because these open cases are more likely to have problems; mid- and late-life data retention experiment: a data retention capability test performed when the flash memory enters the middle and late stages of its service life, and the data retention performance of the selected target open case is continuously monitored; data retention performance refers to the ability of the flash memory to retain data throughout its life cycle, that is, the ability of the data to not experience errors or bit flips during storage.

[0039] In some embodiments, the present application can ensure that different open states are covered by selecting multiple test blocks from multiple flash memory samples; further, the selected test blocks are erased to a predetermined PE cycle (program / erase cycle) to make the flash memory enter the early stage of its service life, and then a data retention experiment is performed to record the number of data bit flips in each open case state; further, based on the number of bit flips obtained in the early life experiment, multiple target open cases with a large number of bit flips are selected from all open cases to ensure that these open cases are representative; further, data retention experiments are performed on the selected target open cases in the middle and late stages of the life, and the real use environment is simulated by accelerated aging methods such as high-temperature baking to evaluate the data retention performance of these open cases at different stages of the flash memory life; it can be understood that compared with the traditional method that needs to cover all open states and life cycles, the present solution only needs to select multiple representative target open cases for data retention experiments in the middle and late stages of the life, which can effectively shorten the test cycle to save the test time of the 3D TLC flash memory, and by screening the target open cases with a large number of bit flips case, ensuring the representativeness of the test results, improving the accuracy of the test, and making the test conclusions more stable and reliable, thereby ensuring the timely delivery of flash media performance data and ensuring that flash products can be launched on the market in a timely manner.

[0040] In some embodiments, step S130 also includes: conducting data retention experiments in the middle and late stages of life under a variety of environmental conditions: in addition to conducting data retention experiments in a standard high temperature environment, experiments can also be conducted under other extreme conditions (such as extremely low temperature, high humidity, vibration, etc.) to evaluate the data retention performance of the flash memory in different usage environments, ensuring that the flash memory can maintain good data retention performance in various application scenarios.

[0041] refer to Figure 2 , Figure 2 A flowchart of a flash memory open block test method provided by an embodiment of the present application; in some embodiments, a pre-life data retention experiment is performed on a plurality of selected test blocks to obtain the number of bit flips of each open case corresponding to the flash memory open block, including but not limited to the following steps:

[0042] Step S210, erasing the selected multiple test blocks to the first target PE cycles, so that the flash memory open block is in the early stage of its service life;

[0043] In some embodiments, the first target PE cycles is a pre-set number of PE cycles used to erase the test block to a specific state so that the flash memory is in the early stage of its service life. For example, 1000 PE cycles can be selected as the first target PE cycles, and then by executing a certain number of PE cycles, the flash memory enters its early wear state, thereby simulating the early life stage of the flash memory in actual use.

[0044] Step S220 , respectively configuring a corresponding open case initial state for each test block to simulate a data retention experiment under a preset environmental condition, and reading and recording the number of bit flips of each open case in the experiment.

[0045] In some embodiments, the open case initial state is to set one or more incompletely programmed states in the test block. For example, some pages in a block may have been programmed, while other pages are still empty; preset environmental conditions: In order to simulate actual use conditions, the test needs to be carried out under specific environmental conditions, such as high temperature, high humidity, etc., to accelerate the aging process, place the configured test block in a preset environment for a period of time, simulate the data retention process, and then read the data in each open case state at the end of the experiment, record the number of bit flips in each state, to evaluate the data retention capability, and then quickly and effectively obtain the data retention performance of the flash memory open block in the early life, thereby providing basic data for subsequent tests.

[0046] In some embodiments, step S210 further includes: in the data retention experiment at the early stage of life, dynamically adjusting the number of PE cycles according to the preliminary experimental results. For example, if it is found that some open cases have already shown a high number of bit flips at a lower number of PE cycles, the number of PE cycles of these open cases can be appropriately reduced to reduce unnecessary testing time and cost. On the contrary, for those open cases that begin to show bit flips at a higher number of PE cycles, their number of PE cycles can be increased to more accurately evaluate their data retention performance.

[0047] refer to Figure 3 , Figure 3 A flowchart of a flash memory open block testing method provided by an embodiment of the present application; in some embodiments, multiple target open cases are selected from multiple open cases corresponding to the flash memory open block based on the number of bit flips, including but not limited to the following steps:

[0048] Step S310, determining the number of state samples corresponding to the open block of the flash memory;

[0049] In some embodiments, the state sampling quantity represents how many representative open cases need to be selected for further testing. This quantity can be determined according to the total number of open cases and test resources. For example, the state sampling quantity can be set to 50.

[0050] Step S320, sorting multiple open cases corresponding to the flash memory open block based on the number of bit flips to obtain an open case sequence;

[0051] In some embodiments, the number of bit flips is the number of bit flips of each open case recorded in the pre-life data retention experiment. All open cases are sorted from high to low according to the number of bit flips to form an open case sequence, so that the open case with a higher number of bit flips can be easily selected.

[0052] Step S330 , selecting multiple target open cases from the open case sequence according to the number of state samples.

[0053] In some embodiments, according to the number of state samples determined in step S310, a corresponding number of target open cases are selected from the open case sequence obtained in step S320. For example, if the number of state samples is 50, the first 50 open cases with the highest number of bit flips are selected from the sequence as target open cases, so as to conduct a more in-depth data retention experiment in the middle and late stages of life, and ensure the representativeness and reliability of the test results.

[0054] In some embodiments, step S330 further includes: optimizing the selection of target open cases based on a machine learning algorithm, introducing a machine learning algorithm (such as a decision tree, a random forest, or a neural network, etc.) to train the data obtained in the data retention experiment in the early stage of the life cycle, and establishing a model that can predict the data retention performance of the open cases in the middle and late stages of the life cycle. Through this model, those open cases that may have a large number of bit flips in the middle and late stages of the life cycle can be more accurately selected as target open cases, thereby further improving the efficiency and accuracy of the test.

[0055] refer to Figure 4 , Figure 4A flowchart of a flash memory open block test method provided by an embodiment of the present application; in some embodiments, determining the number of state samples corresponding to the flash memory open block includes but is not limited to the following steps:

[0056] Step S410, obtaining the number of open case states corresponding to the flash memory open block;

[0057] Step S420, determining the state sampling quantity according to the open case state quantity and a preset sampling ratio.

[0058] In some embodiments, corresponding to step S410, it is first necessary to determine how many possible states an open block has. For example, in 3D TLC (triple-layer cell) flash memory, since each cell can store 3 bits of information, there will be a large number of different states in the openblock depending on the written data. The number of open case states mentioned here refers to the total number of these different states; corresponding to step S420, after determining the number of open case states, it is then necessary to determine how many states need to be tested based on a predetermined sampling strategy. The sampling ratio refers to extracting a certain proportion of states from all possible states for testing. The selection of the sampling ratio is usually based on a balance between test efficiency and test coverage. For example, the states with the largest number of bit flips may be chosen to be tested because they often represent the most vulnerable parts. At the same time, some states with medium and fewer bit flips will also be selected to ensure the comprehensiveness of the test.

[0059] refer to Figure 5 , Figure 5 A flowchart of a flash memory open block testing method provided by an embodiment of the present application; in some embodiments, multiple target open cases are selected from an open case sequence according to the number of state samples, including but not limited to the following steps:

[0060] Step S510, obtaining a first sampling number n1, a second sampling number n2 and a third sampling number n3 according to the state sampling number and a preset sampling distribution ratio;

[0061] Step S520, selecting n1 target open cases with the largest number of bit flips from the open case sequence;

[0062] Step S530, selecting n2 target open cases whose bit flip numbers are close to the median from the open case sequence;

[0063] Step S540: Select n3 target open cases with the smallest number of bit flips from the open case sequence.

[0064] In some embodiments, n1 accounts for 60% of the state sampling number, n2 accounts for 30% of the state sampling number, and n3 accounts for 10% of the state sampling number, wherein three different sampling numbers are calculated according to the total sampling number and the preset sampling distribution ratio, namely n1, n2 and n3, which represent the target open case number of the maximum bit flip number, the bit flip number near the median, and the minimum bit flip number selected from the open case sequence. For example, if the total sampling number is 100, then according to the given ratio, n1 will be 60, n2 will be 30, and n3 will be 10.

[0065] Further, select n1 open cases with the largest number of bit flips from all open cases. These open cases are usually considered to be the weakest, that is, the cases with the worst data retention capabilities, so they are very important for testing and can help identify potential problems; select n2 open cases with bit flips near the median. These open cases represent more common situations and help understand the performance of data retention under general conditions; select n3 open cases with the smallest number of bit flips. These open cases perform relatively strongly even in the open state, but they still need to be tested to ensure a comprehensive evaluation of the overall data retention characteristics.

[0066] In some embodiments, n1 selects the open cases with the largest number of bit flips, which indicates that these open cases are usually the cases with the weakest data retention capabilities, that is, the areas where data loss or corruption is most likely to occur. Selecting more open cases of this type can ensure that the most vulnerable links are fully considered during the test process, thereby improving the reliability of the test. n2 selects open cases with a number of bit flips close to the median, which represent the performance of open blocks in most cases. By selecting these open cases, the data retention performance under normal use conditions can be more accurately evaluated to ensure the representativeness of the test results. n3 selects the open cases with the smallest number of bit flips. Such open cases have good data retention capabilities even in the open state. Although they are also important, they have lower risks than weaknesses and typical cases. Therefore, reducing the number of tests for such open cases can save time and resources without affecting the overall test effect. Therefore, selecting a sampling distribution ratio such as n1>n2>n3 can maximize the coverage of various possibilities within a limited test time, ensure the comprehensiveness and accuracy of the test results, and effectively utilize test resources.

[0067] It can be understood that by sampling according to the number of bit flips, the present application can cover various situations from the worst to the best, so that the test is not only focused on the most likely places for problems, but also takes into account the evaluation of the overall performance. In this way, the time and resources required for the test can be effectively reduced while still maintaining the accuracy of the test.

[0068] refer to Figure 6 , Figure 6 A flow chart of a flash memory open block test method provided in an embodiment of the present application; in some embodiments, a mid- to late-life data retention experiment is performed on multiple target open cases, including but not limited to the following steps:

[0069] Step S610, erasing the selected multiple test blocks to the second target PE cycles, so that the flash memory open block is in the mid-term stage of its service life, performing data retention experiments on multiple target open cases, and recording mid-term experimental data of multiple target open cases;

[0070] Step S620, erasing the selected multiple test blocks to the third target PE cycles, so that the flash memory open block is in the later stage of its service life, performing data retention experiments on multiple target open cases, and recording the later stage experimental data of the multiple target open cases.

[0071] In some embodiments, step S610: At this stage, the selected test block will be erased to the second target erase cycle (PE cycles) to reach the mid-term service life of the flash memory open block. At this point, the open block has experienced a certain degree of wear, but has not yet reached its service life limit. By performing data retention experiments on these open cases, their data retention in the mid-term stage can be recorded. The data at this stage is crucial for evaluating the performance of the open block after a period of use. Step S620: Continue to erase the selected test block to the third target erase cycle, which will put the flash memory open block in the late stage of its service life. During this period, the open block has experienced a large number of erase cycles and is close to or has reached its expected service life. By performing data retention experiments on the selected target open cases again and recording their data retention in the later stages, it is possible to understand the performance of the open block when its life is nearing the end. Among them, the experimental data in the middle and late stages include the number of bit reversals in the middle and late stages. Based on the experimental data in the middle and late stages, the data retention performance of the flash memory open block in the middle and late stages can be quickly and effectively determined. It can not only predict the performance degradation of the flash memory in long-term use in advance, but also provide important reference information for product designers to improve product design or formulate more reasonable usage strategies.

[0072] In some embodiments, the present application provides a flash memory open block testing device, including: a data acquisition unit, used to acquire multiple test samples of the flash memory open block, and select multiple test blocks from each test sample; a pre-life experiment unit, used to erase the selected multiple test blocks to a first target PE cycles to perform a pre-life data retention experiment, and obtain the number of bit flips for each open case corresponding to the flash memory open block; a mid- and late-life experiment unit, used to select multiple target open cases from the multiple open cases corresponding to the flash memory open block based on the number of bit flips, and perform mid- and late-life data retention experiments on the multiple target open cases to determine the data retention performance of the flash memory open block based on the experimental data.

[0073] In some embodiments, reference Figure 7 and Figure 8 , Figure 7 This is an example flow chart of a flash memory open block test method provided in an embodiment of the present application. Figure 8 A data schematic diagram of a flash memory open block test method provided by an embodiment of the present application; wherein, Figure 7 and Figure 8 As shown, this application takes a typical 3D TLC flash memory particle as an example, assuming that the TLC block of the flash memory has 1000 open cases. The overall process is as follows:

[0074] (1) Select several samples, 1000 blocks from each sample, and program these blocks to a specified PE (Program / Erase) cycle, usually 100 cycles, which represents the typical early stage of the flash memory life.

[0075] (2) Write the selected blocks of each sample into the specified open case state.

[0076] (3) Perform data retention experiments at the beginning of the life cycle and organize the experimental results into a table, that is, count the open case numbers and the corresponding flash memory data bit flips (fail counts), such as Figure 8 shown.

[0077] (4) Select 50 open cases from the table. The selection principle is to sort the open cases according to the failure count, select fewer open cases from cases with smaller failure counts, and select more open cases from cases with larger failure counts. The 50 open cases selected in this way not only cover all types of open cases, but also focus on selecting weaker open cases.

[0078] (5) 50 blocks are selected from each sample and erased to the middle and late stages of its life.

[0079] (6) Based on the selected 50 open cases, erase the specified block to the specified open case state.

[0080] (7) Perform data retention experiments in the middle and late stages of the life cycle to evaluate the data security status in the middle and late stages of the life cycle.

[0081] Among them, the present application can screen out open case solutions by adjusting the number of flips of zoom data bits in the early stage of product life, and significantly shorten the test cycle compared with the prior art while ensuring the accuracy of the test.

[0082] In some embodiments, the method further includes, after the experimental data collection is completed, using statistical methods (such as box plots) to identify and remove outliers in the number of bit flips to improve the accuracy of subsequent analysis.

[0083] In some embodiments, after obtaining the number of bit flips of each open case corresponding to the flash memory open block, the method further includes obtaining the number of erase times and the erase temperature, and using statistical techniques such as multiple regression analysis to analyze the influence coefficients of the number of bit flips and the number of erase times and the erase temperature on the data retention performance of the open case. Accordingly, the present application can optimize the selection strategy of the open case to identify multiple target open cases; for example, during the test process, the number of bit flips of each open case under different erase times and the temperature during the erase are recorded. The number of erase times reveals the frequency of the flash memory block being erased, while the erase temperature affects the stability of data retention. These two parameters have a direct impact on the data retention performance of the open case. Through the multiple regression analysis method, the number of bit flips is used as the dependent variable, the number of erase times and the erase temperature are used as independent variables, and the present application can construct a mathematical model to predict and analyze the relationship between these variables. This helps to determine the influence coefficients of the number of erase times and the erase temperature on the number of bit flips (i.e., data retention performance). Based on the results of the multiple regression analysis, the present application can quantify the degree of influence of the number of erase times and the erase temperature on the data retention performance of the open case. For example, if an increase in the number of erase and write times leads to a significant increase in the number of bit flips, then the open case may have poor data retention performance after multiple erases and writes; vice versa. Furthermore, based on the obtained influence coefficient, the present application can adjust the open case selection strategy. Those open cases that can maintain good data retention performance even under high erase and write times and high temperature conditions are selected as target open cases. The purpose of this is to ensure that the test results are more representative and to be able to more accurately evaluate the data retention capabilities of the flash memory in actual use.

[0084] For example, after the data retention experiment at the beginning of life, the present application found that certain open cases had fewer bit flips at low erase times and lower temperatures, but significantly increased bit flips at high erase times and higher temperatures. These open cases can be selected as one of the specific target open cases to better improve the accuracy of subsequent analysis.

[0085] Some embodiments of the present application provide an electronic device, Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application, referring to Fig. 9 The electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the flash memory openblock test method of any of the above embodiments is implemented, for example, the above described Figure 1 Steps S110 to S130 of the method, Figure 2 Steps S210 to S220 of the method, Figure 3 Steps S310 to S330 of the method, Figure 4 Steps S410 to S420 of the method, Figure 5 Steps S510 to S540 of the method, Figure 6 Method steps S610 to S620.

[0086] The electronic device 900 of the embodiment of the present application includes one or more processors 910 and a memory 920. Fig. 9 In the figure, a processor 910 and a memory 920 are taken as an example.

[0087] The processor 910 and the memory 920 may be connected via a bus or other means. Fig. 9 The example of connecting through bus is taken in the following.

[0088] The memory 920, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer executable programs. In addition, the memory 920 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 920 may optionally include a memory 920 remotely disposed relative to the processor 910, and these remote memories may be connected to the electronic device 900 via a network. At the same time, examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0089] In some embodiments, when the processor executes the computer program, the flash memory open block testing method of any one of the above embodiments is performed at a preset interval.

[0090] Those skilled in the art will understand that Fig. 9 The device structure shown in the figure does not constitute a limitation on the electronic device 900, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0091] exist Fig. 9 In the electronic device 900 shown, the processor 910 can be used to call the flash memory open block test method stored in the memory 920, so as to implement the flash memory open block test method.

[0092] Based on the hardware structure of the above-mentioned electronic device 900, various embodiments of the multi-agent interaction system of the present application are proposed. At the same time, the non-volatile software programs and instructions required to implement the flash memory open block testing method of the above-mentioned embodiments are stored in the memory. When executed by the processor, the flash memory open block testing method of the above-mentioned embodiments is executed.

[0093] The present application also provides a computer program product, which includes a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the flash memory open block test method implementing any one of the above embodiments, for example, executing the above described Figure 1 Steps S110 to S130 of the method, Figure 2 Steps S210 to S220 of the method, Figure 3 Steps S310 to S330 of the method, Figure 4 Steps S410 to S420 of the method, Figure 5 Steps S510 to S540 of the method, Figure 6 Method steps S610 to S620.

[0094] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network nodes. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0095] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed method above can be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, and the computer-readable medium can include a computer-readable storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those skilled in the art, the term computer-readable storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program units or other data). Computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD to ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media generally contain computer readable instructions, data structures, program elements, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0096] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation mode. Technical personnel familiar with the field can also make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A flash memory open block testing method, characterized in that: include: Acquire multiple test samples of the open block of the flash memory, and select multiple test blocks from each of the test samples; Performing a pre-life data retention experiment on the selected multiple test blocks to obtain the number of bit flips of each open case corresponding to the open block of the flash memory; Based on the bit flip number, multiple target open cases are selected from multiple open cases corresponding to the flash memory open block, and mid- and late-life data retention experiments are performed on the multiple target open cases to determine the data retention performance of the flash memory open block based on the experimental data.

2. The flash memory open block testing method according to claim 1, characterized in that: The performing of a pre-life data retention experiment on the selected multiple test blocks to obtain the number of bit flips of each open case corresponding to the open block of the flash memory includes: Erasing the selected test blocks to a first target PE cycles, so that the flash memory open block is in an early stage of its service life; A corresponding open case initial state is configured for each of the test blocks respectively to simulate a data retention experiment under preset environmental conditions, and the number of bit flips of each open case is read and recorded in the experiment.

3. The flash memory open block testing method according to claim 1, characterized in that: The selecting a plurality of target open cases from a plurality of open cases corresponding to the flash memory open block based on the number of bit flips includes: Determine the number of state samples corresponding to the flash memory open block; Sort multiple open cases corresponding to the flash memory open block based on the bit flip number to obtain an open case sequence; A plurality of target open cases are selected from the open case sequence according to the number of state samples.

4. The flash memory open block testing method according to claim 3, characterized in that: The determining the number of state samples corresponding to the open block of the flash memory includes: Obtain the number of open case states corresponding to the flash memory open block; The state sampling quantity is determined according to the open case state quantity and a preset sampling ratio.

5. The flash memory open block testing method according to claim 3, characterized in that: The selecting a plurality of target open cases from the open case sequence according to the number of state samples includes: Obtaining a first sampling number n1, a second sampling number n2, and a third sampling number n3 according to the state sampling number and a preset sampling distribution ratio; Select n1 target open cases with the largest number of bit flips from the open case sequence; Select n2 target open cases whose bit flip numbers are close to the median from the open case sequence; Select n3 target open cases with the smallest number of bit flips from the open case sequence.

6. The flash memory open block testing method according to claim 5, characterized in that: The n1 accounts for 60% of the number of state samples, the n2 accounts for 30% of the number of state samples, and the n3 accounts for 10% of the number of state samples.

7. The flash memory open block testing method according to claim 1, characterized in that: The performing of mid- to late-life data retention experiments on the multiple target open cases includes: Erasing the selected test blocks to a second target PE cycles, so that the flash memory open block is in the mid-term stage of its service life, performing data retention experiments on the multiple target open cases, and recording mid-term experimental data of the multiple target open cases; The selected test blocks are erased to a third target PE cycles to put the flash memory open block in a later stage of its service life, data retention experiments are performed on the target open cases, and later stage experimental data of the target open cases are recorded.

8. A flash memory open block testing device, characterized in that: include: A data acquisition unit, used for acquiring a plurality of test samples of an open block of a flash memory, and selecting a plurality of test blocks from each of the test samples; A pre-life experiment unit, used for erasing the selected test blocks to a first target PE cycles to perform a pre-life data retention experiment, and obtaining the number of bit flips of each open case corresponding to the open block of the flash memory; A mid- to late-life experiment unit is used to select multiple target open cases from multiple open cases corresponding to the flash memory open block based on the number of bit flips, and perform a mid- to late-life data retention experiment on the multiple target open cases to determine the data retention performance of the flash memory open block based on the experimental data.

9. A computer-readable storage medium storing computer-executable instructions, characterized in that: The computer executable instructions are used to execute the flash memory open block testing method as described in any one of claims 1 to 7.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the flash memory open block testing method described in any one of claims 1 to 7 is implemented.

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