Circuit board and electronic equipment

Abstract

The invention relates to the technical field of electronics, and discloses a circuit board and electronic equipment, the circuit board comprises a board body, the surface of the board body is provided with a chip mounting area and a signal plug connector mounting area which are arranged along a first direction; one end, far away from the signal plug connector mounting area, of the chip mounting area is provided with a first signal pin area, and in the chip mounting area, the first signal pin area is farthest from the signal plug connector mounting area; pins of the first signal pin area are in signal connection with corresponding pins of the signal plug connector installation area through first signal wires, and the first signal wires penetrate through the part, located on the bottom side of the chip installation area, of the board body, so that the first signal wires can be prevented from bypassing the part, on the periphery of the chip installation area, of the board body. And the space on the bottom side of the chip mounting area is directly used as a channel of the first signal wire, so that the length of the first signal wire can be greatly shortened, and the loss is reduced.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a circuit board and electronic equipment. Background Art

[0002] At present, as the capacity of switching chips increases, the rate of serdes (SERializer / DESerializer) is getting higher and higher, from the early 10Gbps to the current 112Gbps. The higher the signal rate, the greater the loss per unit length of the signal on the transmission line. How to shorten the length of high-speed traces on PCB (Printed Circuit Board) and reduce the total loss is a very core content in SI (Signal Integrity) design.

[0003] Taking the standard of direct drive system as an example, the wiring loss on PCB is limited to 7Db, which is equivalent to a wiring length of about 9 inches, and the current M8 level (highest level) PCB must be used to meet the standard requirements.

[0004] refer to Figure 1 Taking the PCB design of switch equipment as an example, the current industry's top switching chip 02 is used. The surface of PCB 01 has 512 pairs of high-speed serdes, which are distributed in the outer part of the entire chip 02, and the middle area of ​​the chip is the power pin of chip 02. Chip 02 is placed in the middle of PCB 01, and the lower side of PCB 01 is all set with optical port devices 03. The high-speed traces 04 in the top area of ​​chip 02 (the area far away from the optical port devices 03) are interconnected with the optical port devices 03 in the front row. In order to avoid crossing between traces 04, the top area can only be connected to the optical port devices 03 at the two ends. The length of trace 04 is relatively large, close to 12 inches, which does not meet the standard requirements. Summary of the invention

[0005] The invention discloses a circuit board and electronic equipment, which are used to shorten the length of wiring without increasing the cost, thereby reducing signal loss.

[0006] In a first aspect, a circuit board is provided, comprising: a board body, a surface of the board body having a chip mounting area and a signal connector mounting area arranged along a first direction; an end of the chip mounting area away from the signal connector mounting area having a first signal pin area, and in the chip mounting area, the first signal pin area is farthest from the signal connector mounting area; pins of the first signal pin area are connected to corresponding pin signals of the signal connector mounting area through first signal routing lines, and the first signal routing lines run through a portion of the board body located at the bottom side of the chip mounting area, thereby avoiding the first signal routing lines from detouring to the portion of the board body outside the chip mounting area, and directly using the space on the bottom side of the chip mounting area as a channel for the first signal routing lines can significantly shorten the length of the first signal routing lines and reduce losses.

[0007] Optionally, at least one end in the second direction of the chip mounting area has a second signal pin area, and a power pin area is provided on the side of the second signal pin area away from the corresponding side of the chip mounting area, and the first signal routing runs through the part of the board body located on the bottom side of the second signal pin area, and the second direction is perpendicular to the first direction.

[0008] Optionally, the board body includes a first board layer and a second board layer which are stacked, and the chip mounting area and the signal connector mounting area are located on the surface of the first board layer away from the second board layer; each of the second signal pin areas includes a first sub-area, and the pins of the first sub-area are connected to the corresponding pin signals of the signal connector mounting area through a first sub-signal routing, and the first sub-signal routing runs through a portion of the first board layer located on the bottom side of the first sub-area; the first signal routing runs through a portion of the second board layer located on the bottom side of the first sub-area.

[0009] Optionally, each second signal pin area also includes a second sub-area, and in each second signal pin area, the second sub-area is located between the first sub-area and the corresponding side of the chip mounting area; the pins of each second sub-area are connected to the corresponding pin signals of the signal connector mounting area through second sub-signal routing, and the second sub-signal routing fans out from the second sub-area in a direction away from the corresponding first sub-area; along the direction approaching the signal connector mounting area, the second sub-signal routing corresponding to the pins of the second sub-area is gradually arranged inward, and the inward refers to the side of the second sub-area in the direction pointing to the corresponding first sub-area.

[0010] Optionally, both the first signal routing line and the first sub-signal routing line are located inside any second sub-signal routing line in the corresponding second sub-area.

[0011] Optionally, the second sub-signal routing line runs through both the first board layer and the second board layer; or, the second sub-signal routing line runs through the second board layer.

[0012] Optionally, a third signal pin area is provided at one end of the chip mounting area close to the signal connector mounting area; the pins of the third signal pin area are connected to the corresponding pin signals of the signal connector mounting area through a second signal routing line, and the second signal routing line runs through the board body and fans out toward the signal connector mounting area along the first direction.

[0013] Optionally, the first board layer includes a first dielectric layer and a first metal layer which are alternately arranged in sequence, the first board layer has a first metal via which penetrates the first board layer along the thickness direction and is connected to the first metal layer, and the first sub-signal routing is formed using the first metal layer and the first metal via; the second board layer includes a second dielectric layer and a second metal layer which are alternately arranged in sequence, the second board layer has a second metal via which penetrates the second board layer along the thickness direction and is connected to the second metal layer, and the first signal routing is formed using the second metal layer and the second metal via.

[0014] Optionally, the first board layer and the second board layer are independently formed single boards, and are pressed to form the board body.

[0015] In a second aspect, an electronic device is provided, comprising: a chip, a signal connector and a circuit board as described in any of the above technical solutions, wherein the chip is installed in the chip installation area and is connected to the pin signal of the chip installation area, and the signal connector is installed in the signal connector installation area and is connected to the pin signal of the signal connector installation area.

[0016] Compared with the prior art, the electronic device has the same advantages as the circuit board, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the structure of the circuit board, chip and optical port device in the related technical solution;

[0018] Figure 2 A schematic diagram of the structure of the circuit board and the signal connector provided in the embodiment of the present application;

[0019] Figure 3 express Figure 2 A schematic diagram of the chip mounting area in FIG.

[0020] Figure 4 express Figure 3 A cross-sectional view of the circuit board at AA shown;

[0021] Figure 5 express Figure 2 A partial longitudinal cross-sectional view of the circuit board shown;

[0022] Figure 6 express Figure 2 A schematic diagram of the structure of the first board layer in the circuit board shown. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] Combination Figure 2 and Figure 3 :

[0025] The circuit board provided in the embodiment of the present application includes but is not limited to a PCB (Printed Circuit Board), the circuit board comprising: a board body 1, the surface of the board body 1 having a chip mounting area S and a signal connector mounting area P arranged along a first direction (reference y-axis direction); the chip mounting area S having a first signal pin area S1 at one end away from the signal connector mounting area P, and in the chip mounting area S, the first signal pin area S1 is farthest from the signal connector mounting area P; the pins of the first signal pin area S1 are connected to the corresponding pins of the signal connector mounting area P through a first signal wiring B1 (the position of which can be referred to as Figure 6 The first signal trace B1 passes through the bottom portion of the board 1 located at the chip mounting area S, which can avoid the first signal trace B1 from going around to the board 1 outside the chip mounting area S. The space at the bottom of the chip mounting area S is directly used as the channel for the first signal trace B1, which can greatly shorten the length of the first signal trace B1 and reduce the loss. Among them, the pin can be serdes (SERializer / DESerializer, serializer / deserializer).

[0026] In a specific embodiment, at least one end of the chip mounting area S in the second direction (reference direction of the x-axis) has a second signal pin area S2. Figure 2 and Figure 3In the embodiment, both ends of the chip mounting area S respectively have a second signal pin area S2, and the second signal pin area S2 extends along the corresponding side of the chip mounting area S to make full use of the space of each side of the chip mounting area S to increase the number of output lines. A power pin area S4 is provided on the side of the second signal pin area S2 away from the corresponding side of the chip mounting area S. The first signal wiring B1 runs through the part of the board 1 located at the bottom side of the second signal pin area S2, and does not interfere or interfere with the capacitor and other devices of the power pin area S4, thereby improving the signal transmission performance and avoiding increasing the thickness or number of layers of the board 1. The second direction (reference x-axis direction) is perpendicular to the first direction (reference y-axis direction).

[0027] In a specific embodiment, in combination Figures 4 to 6 The board body 1 includes a first board layer 11 and a second board layer 12 stacked together, the chip mounting area S and the signal connector mounting area P are located on the surface of the first board layer 11 away from the second board layer 12; each second signal pin area S2 includes a first sub-area S21, and the pins of the first sub-area S21 are connected through a first sub-signal routing ( Figure 2 (not shown) is connected to the corresponding pin signal of the signal connector installation area P, and the first sub-signal routing runs through the portion of the first board layer 11 located on the bottom side of the first sub-area S21; the first signal routing B1 runs through the portion of the second board layer 12 located on the bottom side of the first sub-area S21. In this way, in order to form a first sub-signal routing for routing the pins of the first sub-area S21, it is necessary to open a metal via along the thickness direction (reference z-axis direction). If the first sub-signal routing is set in the second board layer 12, the metal via corresponding to the first sub-signal routing will pass through the portion of the first board layer 11 corresponding to the first sub-area S21, resulting in the inability to route in the corresponding portion of the first board layer 11, and the first signal routing B1 cannot pass here. On the contrary, if Figure 4 In this way, the first sub-signal routing is set in the first board layer 11 corresponding to the first sub-area S1, and the metal via corresponding to the first sub-signal routing will only pass through the first board layer 11, and will not interfere with the second board layer 12 corresponding to the first sub-area S21. The clearance space reserved in the second board layer 12 corresponding to the first sub-area S21 can be used to form the routing channel K of the first signal routing B1. At the same time, Figure 6 The opening of the metal via of the first plate 11 is shown. It can be seen that at the position corresponding to the first sub-area S21, the first plate 11 is not blocked by the metal via, and this part of the area corresponds to the above-mentioned wiring channel K. Metal layers and dielectric layers can be alternately arranged in the wiring channel K, and the first signal wiring B1 can be formed by using metal vias and metal layers.

[0028] refer to Figure 2The first signal routing B1 first fans out in a direction away from the signal connector installation area P, and then extends in two ways along the second direction (reference x-axis direction) to the first sub-areas S21 on both sides, and then extends along the first direction (reference y-axis direction) along the routing channel K toward the signal connector installation area P after reaching the top of the first sub-area S21; the first sub-signal routing directly extends along the first direction (reference y-axis direction) toward the signal connector installation area P. Since the first signal routing B1 and the first sub-signal routing are distributed in different board layers, the two will not interfere with each other or cross each other, and can be respectively connected to different signal connectors 2 signals in the signal connector installation area P.

[0029] In a specific embodiment, each second signal pin area S2 also includes a second sub-area S22. In each second signal pin area S2, the second sub-area S22 is located between the first sub-area S21 and the corresponding side of the chip mounting area S, that is, the second sub-area S22 is located outside the corresponding first sub-area S21; the pins of each second sub-area S22 are connected to the corresponding pin signals of the signal connector mounting area P through the second sub-signal routing line B22, and the second sub-signal routing line B22 fans out from the second sub-area S22 in a direction away from the corresponding first sub-area S21. In the process of fanning out, the second sub-signal routing line B22 gradually moves toward the direction of the signal connector mounting area P; along the direction close to the signal connector mounting area P, the second sub-signal routing lines B22 corresponding to the pins of the second sub-area S22 are gradually arranged inwardly, and the inward side refers to the side of the second sub-area S22 in the same second signal pin area S2 pointing to the corresponding first sub-area S21, so as to prevent the formation of intersections between different signal routings and increase the thickness or number of layers of the circuit board. Observation Figure 2 , the farther the pin in the second sub-area S22 is from the signal connector mounting area P, the farther the pin in the signal connector mounting area P corresponding to the pin is from the chip mounting area S in the second direction (reference x-axis direction), and different second sub-signal traces B22 are not easy to cross each other. Since the second sub-area S22 is located outside the corresponding first sub-area S21, the second sub-area S22 can fan out in a direction away from the corresponding first sub-area S22. If, on the contrary, the second sub-area S22 is located inside the corresponding first sub-area S21, the second sub-signal trace B22 will be blocked by the first signal trace B1 and the first sub-signal trace, and cannot fan out.

[0030] In a specific embodiment, the first signal routing B1 and the first sub-signal routing are both located on the inner side of any second sub-signal routing B22 of the corresponding second sub-area S22, and the definition of "inside" refers to the previous text to prevent the second sub-signal routing B22 from crossing the first signal routing B1 and the first sub-signal routing.

[0031] In a specific embodiment, the second sub-signal route B22 runs through the first board layer 11 and the second board layer 12 at the same time to increase the fan-out number of the second sub-signal route B22 in the second sub-area S22, which is beneficial to increase the number of pins and improve performance; alternatively, the second sub-signal route B22 runs through the second board layer 12, and the second sub-signal route B22 only runs through the second board layer 12, which is beneficial to avoid the first sub-signal route of the first board layer 11 and provide fan-out space for the first sub-signal route.

[0032] In a specific embodiment, a third signal pin area S3 is provided at one end of the chip mounting area S close to the signal connector mounting area P; the pins of the third signal pin area S3 are connected to the corresponding pin signals of the signal connector mounting area P through the second signal wiring B3, the second signal wiring B3 runs through the board body 1, and fans out toward the signal connector mounting area P along the first direction (reference y-axis direction), the second signal wiring B3 has the shortest wiring length, and is not easy to interfere with other signal wirings.

[0033] In a specific embodiment, reference Figure 5 The first board layer 11 includes a first dielectric layer 112 and a first metal layer 111 which are alternately arranged in sequence. The first board layer 11 has a first metal via T1 which penetrates the first board layer 11 along the thickness direction (referenced to the direction where the z-axis is located) and is connected to the first metal layer 111. The first metal layer 111 and the first metal via T1 are used to form a first sub-signal routing line, which is convenient for processing and stably transmits the pin signal of the first sub-area S21; the second board layer 12 includes a second dielectric layer 122 and a second metal layer 121 which are alternately arranged in sequence. The second board layer 12 has a second metal via T2 which penetrates the second board layer 12 along the thickness direction (referenced to the direction where the z-axis is located) and is connected to the second metal layer 121. The second metal layer 121 and the second metal via T2 are used to form a first signal routing line B1, which is convenient for processing and stably transmits the pin signal of the first signal pin area S1. The first metal via T1 and the second metal via T2 can respectively form a metal via that passes through the first plate 11 and a metal via that passes through the second plate 12. For example, this form of metal vias can be used to form the above-mentioned sub-signal routing and the first signal routing B1 respectively; when it is necessary to form a second sub-signal routing B22 that passes through the first board layer 11 and the second board layer 12 at the same time, a through hole T that passes through the entire board body 1 can be formed as a metal via.

[0034] In a specific embodiment, the first board layer 11 and the second board layer 12 are independently formed single boards, and are pressed to form the board body 1. The first board layer 11 serves as the upper N board, and the second board layer 12 serves as the lower N board. Due to technical limitations, when forming metal vias, it is only possible to completely penetrate the board. In some cases (such as forming the first sub-signal routing), only the first metal via T1 needs to be formed at the corresponding position of the first board 11. In this case, only the first metal via T1 needs to be formed in the first board layer 11 as a single board, and there is no need to form the second metal via T2 at the corresponding position of the second board layer 12, which is beneficial to saving the routing space in the second board layer 12; similarly, it is also beneficial to saving the routing space in the first board layer 11. After the first board layer 11 and the second board layer 12 are pressed together, a through hole T that penetrates the entire board body 1 is punched.

[0035] The upper N-board and the lower N-board are used to realize the reuse of the wiring space in the chip via-dense area. In some specific embodiments, after testing, the first signal line B1 of the first signal pin area S1 is relative to Figure 1 The corresponding technical solution can shorten the wiring by about 30%. The wiring space can be fully utilized, and the wiring can be output from all four sides at the same time, which can solve the problem of wiring crossing.

[0036] Under the condition that the loss remains unchanged, the solution can reduce the board material by one level. After testing in some specific embodiments, the overall cost of PCB can be reduced by about 20%. In addition, the solution provided by the above embodiment can simplify the architecture and can meet the requirements of direct drive pure PCB solution.

[0037] Based on the same inventive concept, the embodiment of the present application also provides an electronic device, which can be a switch, a router or a server. The electronic device includes: a chip, a signal connector 2 and a circuit board provided in the above embodiment, the chip is installed in the chip mounting area S and is connected to the pin signal of the chip mounting area S, the signal connector 2 is installed in the signal connector mounting area P and is connected to the pin signal of the signal connector mounting area P. The effect can refer to the circuit board mentioned above. The signal connector 2 can be an optical port device such as an optical module.

[0038] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A circuit board, characterized in that: It comprises: a board body, the surface of which has a chip mounting area and a signal connector mounting area arranged along a first direction; The chip mounting area has a first signal pin area at one end away from the signal connector mounting area; The pins of the first signal pin area are signal-connected to the corresponding pins of the signal connector mounting area through first signal traces, and the first signal traces run through a portion of the board body located at the bottom side of the chip mounting area.

2. The circuit board according to claim 1, characterized in that: At least one end of the chip mounting area in the second direction has a second signal pin area, and a power pin area is provided on a side of the second signal pin area away from the corresponding side of the chip mounting area. The first signal routing runs through the part of the board body located on the bottom side of the second signal pin area, and the second direction is perpendicular to the first direction.

3. The circuit board according to claim 2, characterized in that: The board body comprises a first board layer and a second board layer which are stacked, and the chip mounting area and the signal connector mounting area are located on a surface of the first board layer which is away from the second board layer; Each of the second signal pin regions includes a first sub-region, wherein the pins of the first sub-region are connected to the corresponding pins of the signal connector installation region through a first sub-signal routing line, and the first sub-signal routing line runs through a portion of the first board layer located at the bottom side of the first sub-region; The first signal wiring runs through a portion of the second board layer located at the bottom side of the first sub-area.

4. The circuit board according to claim 3, characterized in that: Each of the second signal pin regions further includes a second sub-region, and in each of the second signal pin regions, the second sub-region is located between the first sub-region and a corresponding side edge of the chip mounting region; The pins of each second sub-area are connected to the corresponding pins of the signal connector installation area through second sub-signal routing lines, and the second sub-signal routing lines fan out from the second sub-area in a direction away from the corresponding first sub-area; Along the direction approaching the signal connector installation area, the second sub-signal traces corresponding to the pins of the second sub-area are gradually arranged inwardly, where the inwardly refers to the side of the second sub-area in the direction pointing to the corresponding first sub-area.

5. The circuit board according to claim 4, characterized in that: The first signal routing line and the first sub-signal routing line are both located inside any second sub-signal routing line in the corresponding second sub-area.

6. The circuit board according to claim 4, characterized in that: The second sub-signal routing line runs through both the first board layer and the second board layer; or, The second sub-signal routing runs through the second board layer.

7. The circuit board according to claim 1, characterized in that: The chip mounting area has a third signal pin area at one end close to the signal connector mounting area; The pins of the third signal pin area are connected to the corresponding pin signals of the signal connector installation area through second signal traces. The second signal traces run through the board and fans out toward the signal connector installation area along the first direction.

8. The circuit board according to any one of claims 3 to 7, characterized in that: The first board layer includes a first dielectric layer and a first metal layer which are alternately arranged in sequence, the first board layer has a first metal via which penetrates the first board layer in a thickness direction and is connected to the first metal layer, and the first sub-signal routing is formed by using the first metal layer and the first metal via; The second board layer includes a second dielectric layer and a second metal layer that are alternately arranged in sequence. The second board layer has a second metal via that penetrates the second board layer along the thickness direction and is connected to the second metal layer. The first signal routing is formed by using the second metal layer and the second metal via.

9. The circuit board according to any one of claims 3 to 7, characterized in that: The first board layer and the second board layer are independently formed single boards, and are pressed to form the board body.

10. An electronic device, characterized in that: include: A chip, a signal connector and a circuit board as described in any one of claims 1 to 9, wherein the chip is mounted in the chip mounting area and connected to the pin signals of the chip mounting area, and the signal connector is mounted in the signal connector mounting area and connected to the pin signals of the signal connector mounting area.

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