Memory and manufacturing method thereof

Abstract

The invention relates to the field of semiconductors, and provides a memory and a manufacturing method thereof. The memory includes: a memory array including a plurality of vertical transistors and a plurality of memory cells; a plurality of bit lines located at one side of the vertical transistor away from the memory cell; the first interconnection structure is located on the side, away from the storage array, of the bit line; the second interconnection structure is located on the side, away from the bit line, of the first interconnection structure; the bonding interface is located between the first interconnection structure and the second interconnection structure; the peripheral circuit is located on the side, away from the first interconnection structure, of the second interconnection structure. Wherein the bit line is correspondingly coupled with the peripheral circuit through the first interconnection structure, the bonding interface and the second interconnection structure. Wherein the first interconnection structure comprises a first interconnection layer, the first interconnection layer comprises a plurality of first bonding pads and a plurality of first leads, the plurality of first bonding pads are correspondingly coupled with the plurality of bit lines through the plurality of first leads and a plurality of first contact plugs, and for the plurality of first leads, the larger the extension length is, the larger the width is.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory and a method for manufacturing the same. Background Art

[0002] With the development of the semiconductor field, the memory density using planar memory cells is approaching the upper limit. At present, the three-dimensional memory architecture can solve the density limitation in the planar memory cell. In the three-dimensional memory architecture, the memory cell array and the peripheral circuit are located on different wafers and bonded together in a face-to-face manner. However, in the wafer where the memory cell array is located, the bit line contact plug has the problem of small size and layout limitations, which is not conducive to the coupling of the bit line with the peripheral circuit. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure provide a memory and a method for manufacturing the same in order to solve or improve the technical problems existing in the background technology.

[0004] The present disclosure provides a memory, comprising: a memory array, comprising a plurality of vertical transistors arranged in an array and a plurality of memory cells coupled to the plurality of vertical transistors in a one-to-one correspondence, wherein an active region of each of the vertical transistors extends along a first direction, and a first end of each of the vertical transistors is coupled to a first end of a memory cell; a plurality of bit lines, located on a side of the plurality of vertical transistors away from the plurality of memory cells, extending along a second direction perpendicular to the first direction, and respectively coupled to second ends of the plurality of vertical transistors in a corresponding manner; a first interconnection structure, located on a side of the plurality of bit lines away from the memory array; a second interconnection structure, located on a side of the first interconnection structure away from the plurality of bit lines; a bonding interface, located on the between the first interconnect structure and the second interconnect structure; a peripheral circuit, located on a side of the second interconnect structure away from the first interconnect structure, wherein the plurality of bit lines are correspondingly coupled to the peripheral circuit through the first interconnect structure, the bonding interface and the second interconnect structure; wherein the first interconnect structure comprises a plurality of interconnect layers, the plurality of interconnect layers comprises a first interconnect layer close to the plurality of bit lines, the first interconnect layer comprises a plurality of first pads and a plurality of first leads, the plurality of first pads are correspondingly coupled to the plurality of bit lines through the plurality of first leads and a plurality of first contact plugs, the plurality of first pads have the same size, the plurality of first contact plugs have the same size, and for the plurality of first leads, the greater the extension length, the greater the width.

[0005] In some embodiments, the resistances of the plurality of first leads are substantially the same.

[0006] In some embodiments, the multiple first contact plugs are alternately arranged on both sides of a perpendicular midline of the multiple bit lines, the extension direction of the perpendicular midline is respectively perpendicular to the first direction and the second direction, and the multiple first contact plugs are equidistant from the perpendicular midline; the first contact plugs located on one side of the perpendicular midline are coupled to the odd-numbered bit lines, and the first contact plugs located on the other side of the perpendicular midline are coupled to the even-numbered bit lines.

[0007] In some embodiments, the first pads coupled to the first contact plugs located on the same side of the midline are also located on the same side of the midline and are staggered along an extension direction of the midline.

[0008] In some embodiments, the multiple first contact plugs are arranged in sequence along the midpoint of the multiple bit lines, and the extension direction of the midpoint is perpendicular to the first direction and the second direction respectively; the first pad located on one side of the midpoint is coupled to the first contact plug of the odd sequence, and the first pad located on the other side of the midpoint is coupled to the first contact plug of the even sequence.

[0009] In some embodiments, the first pads located on the same side of the perpendicular midline are arranged in a staggered manner along the extension direction of the perpendicular midline.

[0010] In some embodiments, the multiple interconnection layers also include a second interconnection layer away from the multiple bit lines, the second interconnection layer includes a plurality of evenly distributed second pads, and the plurality of second pads are correspondingly coupled to the plurality of bit lines through a plurality of second contact plugs and other interconnection layers except the second interconnection layer.

[0011] In some embodiments, the multiple interconnection layers also include at least one intermediate interconnection layer located between the first interconnection layer and the second interconnection layer, the intermediate interconnection layer includes multiple intermediate pads and multiple intermediate leads, the multiple intermediate pads are correspondingly coupled to the multiple bit lines through the multiple intermediate leads, multiple intermediate contact plugs, and other interconnection layers located between the intermediate interconnection layer and the multiple bit lines; the occupied area of ​​the intermediate pad is larger than the occupied area of ​​the first pad, and the occupied area of ​​the second pad is larger than the occupied area of ​​the intermediate pad.

[0012] In some embodiments, the memory further includes: a plurality of word lines extending along a third direction, respectively covering partial side walls of the active regions of the plurality of vertical transistors, wherein the third direction is perpendicular to the first direction and intersects with the second direction; a plurality of word line contact plugs located between the plurality of word lines and the first interconnect structure; wherein the plurality of word lines are correspondingly coupled to the peripheral circuit via the plurality of word line contact plugs, the first interconnect structure, the bonding interface and the second interconnect structure.

[0013] In some embodiments, the multiple word line contact plugs are distributed at opposite ends of the multiple word lines, the word line contact plug located at one end of the multiple word lines is coupled to the word lines of odd sequence, and the word line contact plug located at the other end of the multiple word lines is coupled to the word lines of even sequence.

[0014] The present disclosure also provides a method for manufacturing a memory, comprising: forming a first semiconductor structure, wherein the first semiconductor structure comprises a memory array, a plurality of bit lines and a first interconnect structure; the memory array comprises a plurality of vertical transistors arranged in an array and a plurality of memory cells coupled to the plurality of vertical transistors in a one-to-one correspondence, the active region of each of the vertical transistors extending along a first direction, the first end of each of the vertical transistors coupled to the first end of each of the memory cells; the plurality of bit lines are located on a side of the plurality of vertical transistors away from the plurality of memory cells, the plurality of bit lines extend along a second direction perpendicular to the first direction, and are respectively coupled to the second ends of the plurality of vertical transistors; the first interconnect structure is located on a side of the plurality of bit lines away from the memory array; forming a second semiconductor structure, wherein the second semiconductor The body structure includes a peripheral circuit and a second interconnect structure located on the peripheral circuit; the first semiconductor structure and the second semiconductor structure are bonded by forming a bonding interface between the first interconnect structure and the second interconnect structure, so that the plurality of bit lines are correspondingly coupled to the peripheral circuit through the first interconnect structure, the bonding interface and the second interconnect structure; wherein the first interconnect structure includes a plurality of interconnect layers, the plurality of interconnect layers include a first interconnect layer close to the plurality of bit lines, the first interconnect layer includes a plurality of first pads and a plurality of first leads, the plurality of first pads are correspondingly coupled to the plurality of bit lines through the plurality of first leads and a plurality of first contact plugs, the plurality of first pads have the same size, the plurality of first contact plugs have the same size, and for the plurality of first leads, the larger the extension length, the larger the width.

[0015] In some embodiments, forming the first semiconductor structure includes: etching the substrate from the first side to form a plurality of active regions arranged in an array and a trench structure defining the plurality of active regions, each of the active regions extending along a first direction perpendicular to the substrate; forming an isolation structure in the trench structure; etching a portion of the isolation structure from the first side to form a plurality of word line trenches extending along a third direction, each of the word line trenches exposing a portion of each of the active regions arranged along the third direction, the third direction being perpendicular to the first direction; sequentially forming a gate dielectric layer and a word line in each of the word line trenches; etching each of the word line trenches ... word line trenches The first end of the active region is doped to form a first source and drain region; the plurality of memory cells are formed on the first surface, and the first end of each of the memory cells is coupled to one of the first source and drain regions; the substrate is thinned from the second surface to expose the second end of each of the active regions; the second end of each of the active regions is doped from the second surface to form a second source and drain region; a plurality of bit lines extending along the second direction are formed on the second surface, and the plurality of bit lines are respectively coupled to the second source and drain regions of the plurality of active regions, and the second direction is perpendicular to the first direction and intersects with the third direction; a first interconnect structure is formed on the second surface.

[0016] In some embodiments, a first interconnect structure is formed on the second surface, comprising: forming the first interconnect layer on the second surface, the first interconnect layer being located on the plurality of bit lines; forming at least one intermediate interconnect layer on the first interconnect layer, the intermediate interconnect layer comprising a plurality of intermediate pads and a plurality of intermediate leads, the plurality of intermediate pads being coupled to the plurality of bit lines correspondingly through the plurality of intermediate leads, a plurality of intermediate contact plugs, and other interconnect layers located between the intermediate interconnect layer and the plurality of bit lines; wherein the occupied area of ​​the intermediate pads is greater than the occupied area of ​​the first pads.

[0017] In some embodiments, a first interconnect structure is formed on the second surface, and further includes: forming a second interconnect layer on the intermediate interconnect layer, the second interconnect layer including a plurality of evenly distributed second pads, the plurality of second pads being coupled to the plurality of bit lines correspondingly through a plurality of second contact plugs and other interconnect layers except the second interconnect layer; wherein an occupied area of ​​the second pads is greater than an occupied area of ​​the intermediate pads.

[0018] In some embodiments, forming the first semiconductor structure further includes: forming a plurality of word line contact plugs, wherein the plurality of word line contact plugs are located between the plurality of word lines and the first interconnect structure; wherein the plurality of word lines are correspondingly coupled to the peripheral circuit via the plurality of word line contact plugs, the first interconnect structure, the bonding interface and the second interconnect structure.

[0019] It can be seen that the embodiment of the present disclosure provides a memory and a manufacturing method thereof. The memory includes: a memory array, including a plurality of vertical transistors arranged in an array and a plurality of memory cells coupled to the plurality of vertical transistors in a one-to-one correspondence, wherein the active region of each vertical transistor extends along a first direction, and the first end of each vertical transistor is coupled to the first end of a memory cell; a plurality of bit lines, located on a side of the plurality of vertical transistors away from the plurality of memory cells, extending along a second direction perpendicular to the first direction, and respectively coupled to the second ends of the plurality of vertical transistors in a corresponding manner; a first interconnect structure, located on a side of the plurality of bit lines away from the memory array; a second interconnect structure, located on a side of the first interconnect structure away from the plurality of bit lines; a bonding interface, a bit line, and a bonding interface. between the first interconnect structure and the second interconnect structure; a peripheral circuit is located on a side of the second interconnect structure away from the first interconnect structure, wherein the plurality of bit lines are correspondingly coupled to the peripheral circuit through the first interconnect structure, the bonding interface and the second interconnect structure; wherein the first interconnect structure comprises a plurality of interconnect layers, the plurality of interconnect layers comprises a first interconnect layer close to the plurality of bit lines, the first interconnect layer comprises a plurality of first pads and a plurality of first leads, the plurality of first pads are correspondingly coupled to the plurality of bit lines through the plurality of first leads and the plurality of first contact plugs, the plurality of first pads have the same size, the plurality of first contact plugs have the same size, and for the plurality of first leads, the greater the extension length, the greater the width. On the one hand, the present disclosure solves or improves the problem that the first contact plugs are small in size and are not conducive to the coupling of the bit lines with the peripheral circuits by setting a first interconnection structure, setting a plurality of first pads and a plurality of first leads in the first interconnection layer of the first interconnection structure, and correspondingly coupling with the plurality of bit lines through a plurality of first contact plugs; at the same time, the greater the extension length of the plurality of first leads, the greater their width, so that the difference in the resistance value of the transmission path caused by the distance difference when the plurality of first pads are correspondingly coupled with the plurality of bit lines can be compensated. On the other hand, the present disclosure also sets a second interconnection structure, and forms a bonding interface between the first interconnection structure and the second interconnection structure, so that the plurality of bit lines can be correspondingly coupled with the peripheral circuits through the first interconnection structure, the bonding interface and the second interconnection structure. In this way, the stability of the coupling between the bit lines and the peripheral circuits is further improved, and the performance and yield of the memory are improved.

[0020] The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1A schematic diagram of a wafer bonding method provided for related technology;

[0023] Figure 2 A three-dimensional schematic diagram of a memory provided for related technology;

[0024] Figure 3 A three-dimensional schematic diagram of a memory provided by an embodiment of the present disclosure;

[0025] Figure 4 A schematic top view of a memory provided by an embodiment of the present disclosure;

[0026] Figure 5 A vertical cross-sectional schematic diagram of a memory provided by an embodiment of the present disclosure, wherein (a) is a ... Figure 4 Schematic diagram of the vertical section along the a-a' line in (b). Figure 4 Schematic diagram of the vertical section of the c-c' line in FIG.

[0027] Figure 6 A schematic diagram of a first interconnection structure provided in an embodiment of the present disclosure;

[0028] Figure 7 A schematic diagram of a first interconnection layer provided in an embodiment of the present disclosure;

[0029] Figure 8 A schematic diagram of a layout of a first contact plug provided for related technology;

[0030] Fig. 9 A schematic diagram of the layout of a first contact plug provided in an embodiment of the present disclosure;

[0031] Fig.10 A schematic diagram of the layout of a first pad and a first lead provided in an embodiment of the present disclosure;

[0032] Fig.11 A schematic diagram of a layout of another first contact plug provided in an embodiment of the present disclosure;

[0033] Fig.12 A schematic diagram of a layout of a first pad and a first lead provided in another embodiment of the present disclosure;

[0034] Fig.13 A schematic diagram of a second interconnection layer provided in an embodiment of the present disclosure;

[0035] Fig.14 A schematic diagram of coupling a first contact plug to a second interconnect layer provided in an embodiment of the present disclosure;

[0036] Fig.15 A schematic diagram of the layout of a contact plug provided in an embodiment of the present disclosure;

[0037] Fig.16 A schematic diagram of a method for manufacturing a memory provided by an embodiment of the present disclosure;

[0038] Figures 17 to 28 A schematic diagram of the structure of the memory provided in the embodiment of the present disclosure during the manufacturing process, wherein: Figures 17 to 20 For along Figure 4 Schematic diagram of the vertical section of the a-a' line in Figure 21 to Figure 23 , Fig.25 This is a three-dimensional schematic diagram of the memory during the manufacturing process. Fig.24 , Figure 26 to Figure 28 For along Figure 4 Schematic diagram of the vertical section along the c-c' line in FIG. DETAILED DESCRIPTION

[0039] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0040] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0041] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0042] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0043] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0044] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "composition" and / or "comprising" when used in this specification determine the existence of the features, integers, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items. All numerical ranges herein include endpoint values.

[0045] In the related art, heterogeneous integration technology on chip (HITOC) technology can form a memory cell array with vertical transistors and a peripheral circuit on a first wafer and a second wafer respectively, and bond them face to face to form a three-dimensional memory (such as Figure 1 As shown in FIG. 1 ). Due to the face-to-face bonding of the wafers, the bit line contact plugs and word line contact plugs in the first wafer can only be set at the edges of the bit lines and word lines (as shown in FIG. 1 ). Figure 2 As shown in FIG. 1 , the layout of the plurality of contact plugs in the first wafer has certain limitations, which is not conducive to bonding the first wafer and the second wafer.

[0046] In addition, when preparing the first wafer, a bit line groove can be first formed on the substrate, and a metal material can be deposited in the bit line groove to form a bit line; then, a vertical transistor is formed on the bit line. In this preparation process, due to the large depth of the bit line groove in the substrate, it is difficult to fill the metal material and the bit line preparation process is complicated. In addition, there is a problem of doping difficulty near one end of the bit line of the subsequently formed vertical transistor. In addition, a vertical transistor can be first formed on the substrate, and then the bottom of the vertical transistor is doped through an ion implantation process to form a bit line. The disadvantage of this process is that the bit line doping region is a heavily doped region, which easily leads to a high leakage current (High leakage through Sub) in the substrate.

[0047] Based on this, the present disclosure proposes the following technical solutions:

[0048] The present disclosure provides a memory, Figure 3 A three-dimensional schematic diagram of a memory provided by an embodiment of the present disclosure; Figure 4 A schematic top view of a memory provided by an embodiment of the present disclosure; Figure 5 A vertical cross-sectional schematic diagram of a memory provided by an embodiment of the present disclosure, wherein (a) is a ... Figure 4 Schematic diagram of the vertical section along the a-a' line in (b). Figure 4 Schematic diagram of the vertical section of the c-c' line in FIG. Figure 6 A schematic diagram of a first interconnection structure provided in an embodiment of the present disclosure; Figure 7 A schematic diagram of a first interconnection layer provided in an embodiment of the present disclosure.

[0049] See also Figures 3 to 5The memory comprises: a memory array 11, comprising a plurality of vertical transistors 12 arranged in an array and a plurality of memory cells 13 coupled to the plurality of vertical transistors 12 in a one-to-one correspondence, wherein an active region 120 of each vertical transistor 12 extends along a first direction x, and a first end A1 of each vertical transistor 12 is coupled to a first end B1 of a memory cell 13;

[0050] A plurality of bit lines 14 are located at a side of the plurality of vertical transistors 12 away from the plurality of memory cells 13 , extend along a second direction y perpendicular to the first direction x, and are respectively coupled to the second ends A2 of the plurality of vertical transistors 12 ;

[0051] A first interconnect structure 21 is located on a side of the plurality of bit lines 14 away from the memory array 11;

[0052] The second interconnect structure 41 is located at a side of the first interconnect structure 21 away from the plurality of bit lines 14;

[0053] The bonding interface 40 is located between the first interconnect structure 21 and the second interconnect structure 41;

[0054] The peripheral circuit 42 is located on a side of the second interconnect structure 41 away from the first interconnect structure 21, wherein the plurality of bit lines 14 are correspondingly coupled to the peripheral circuit 42 through the first interconnect structure 21, the bonding interface 40 and the second interconnect structure 41;

[0055] The first interconnect structure 21 includes a plurality of interconnect layers 210, wherein the plurality of interconnect layers 210 include a first interconnect layer 211 (eg, Figure 6 and Figure 7 As shown), the first interconnect layer 211 includes a plurality of first pads 2112 and a plurality of first leads 2111 (as shown Fig.10 As shown), a plurality of first pads 2112 are coupled to a plurality of bit lines 14 through a plurality of first leads 2111 and a plurality of first contact plugs 31, and the plurality of first pads 2112 have the same size, and the plurality of first contact plugs 31 have the same size.

[0056] For the plurality of first lead lines 2111 , the greater the extension length, the greater the width.

[0057] It should be noted that, in order to clearly illustrate the content of this embodiment, Figure 3 Only some of the memory devices are shown. Figure 4 and Figure 5 The second direction y and the third direction z are both perpendicular to the first direction x. The second direction y and the third direction z may be perpendicular to each other or at any angle, and the second direction y being perpendicular to the third direction z is exemplified below and will not be described in detail below.

[0058] In the embodiments of the present disclosure, see Figure 4 , the size of the storage array 11 satisfies 4F 2 (F: minimum pattern size obtainable under given process conditions.) That is, the distance between the center points of two adjacent vertical transistors 12 in the second direction y is 2F, and the distance between the center points of two adjacent vertical transistors 12 in the third direction z is also 2F. In this way, vertical transistors are used instead of planar transistors, and the integration density of the memory is improved.

[0059] In the embodiments of the present disclosure, see Figure 5 As shown in FIG. 2( b ), the memory array 11 includes a dynamic random access memory (DRAM) cell array.

[0060] It should be noted that the memory array 11 is not limited to a DRAM cell array, but may also include other suitable memory arrays that can use transistors as switches and selection devices, such as a static random access memory (SRAM) cell array, a resistive memory cell array, and a magnetic memory cell array.

[0061] In the embodiments of the present disclosure, see Figure 5 , the memory cell 13 is a capacitor for storing electric charge as binary information stored by a corresponding DRAM cell. Specifically, the memory cell 13 is a vertical capacitor.

[0062] In the embodiments of the present disclosure, see Figure 5 In (a), the first end A1 and the second end A2 of the vertical transistor 12 are two opposite ends along the first direction x. In addition, a first source-drain region and a second source-drain region are formed at the first end A1 and the second end A2 of the vertical transistor 12, respectively. The first source-drain region and the second source-drain region may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)).

[0063] In the embodiments of the present disclosure, see Figure 5 In FIG. (a), the first interconnection structure 21 and the second interconnection structure 41 may include multiple interconnection layers, and the multiple interconnection layers may be connected by multiple contact plugs. Here, the material of the interconnection layer includes but is not limited to tungsten, cobalt, copper, aluminum, titanium nitride, tungsten nitride or any combination thereof.

[0064] In the embodiments of the present disclosure, see Figure 5 In FIG. 5( b ), the bonding interface 40 (Hybrid Bonding Interface) may be a bonding layer having a certain thickness formed by hybrid bonding of the first interconnect structure 21 and the second interconnect structure 41 .

[0065] It can be understood that by providing the first interconnect structure 21 and the second interconnect structure 41 and forming the bonding interface 40 between the first interconnect structure 21 and the second interconnect structure 41, the plurality of bit lines 14 can be coupled to the peripheral circuit 42 through the first interconnect structure 21, the bonding interface 40 and the second interconnect structure 41. In this way, the stability of the coupling between the bit line 14 and the peripheral circuit 42 is improved, and the performance and yield of the memory are improved.

[0066] In the embodiments of the present disclosure, see Figure 5 As shown in FIG. 1(a), the peripheral circuit 42 may include one or more of a page buffer, a decoder, a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a sub-circuit) of the above functional circuits, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor).

[0067] Figure 8 A schematic diagram of a layout of a first contact plug provided for related technology; Fig. 9 A schematic diagram of the layout of a first contact plug provided in an embodiment of the present disclosure; Fig.10 A schematic diagram of the layout of a first pad and a first lead provided in an embodiment of the present disclosure; Fig.11 A schematic diagram of a layout of another first contact plug provided in an embodiment of the present disclosure; Fig.12 A schematic diagram of the layout of another first pad and a first lead provided in an embodiment of the present disclosure.

[0068] See also Figure 8 It can be seen that the first contact plug 31 is set at the edge of the bit line 14. In this case, there is a problem of large transmission resistance between the first contact plug 31 and the storage unit on the corresponding coupled bit line 14 away from the first contact plug 31, which leads to a reduction in the sensing margin of the memory.

[0069] In the present disclosure, see Fig. 9 and Fig.11 , the first contact plug 31 can be arranged in the middle section of the bit line 14 (i.e., the area between the two ends of the bit line). This is because the first contact plug 31 is located on the side of the bit line 14 away from the vertical transistor 12, that is, between the bit line 14 and the first interconnect structure 21. Therefore, the layout of the first contact plug 31 is not limited by devices such as vertical transistors and word lines. In this way, the problem of limitations in the layout of the first contact plug 31 is improved, and at the same time, the transmission resistance between the first contact plug 31 and the storage cells at both ends of the bit line 14 can be reduced, thereby improving the sensing margin of the memory.

[0070] In the embodiments of the present disclosure, see Fig.10 and Fig.12 , the size of the first pad 2112 is much larger than the size of the first contact plug 31. In this way, the plurality of first pads and the plurality of first leads are coupled to the plurality of bit lines through the plurality of first contact plugs, which can improve the problem of the small size of the first contact plug 31 and facilitate the coupling of the bit line 14 with the peripheral circuit 42.

[0071] In some embodiments of the present disclosure, see Fig.10 and Fig.12 , the resistances of the plurality of first leads 2111 are substantially the same.

[0072] It should be noted that the resistance of the plurality of first leads 2111 being substantially the same can be understood as the resistance of the plurality of first leads 2111 being equal, but a certain difference is allowed within a certain error range. Specifically, the resistance error range can include a small design error range that does not affect the electrical performance of the memory, provided that the plurality of first pads 2112 are coupled to the plurality of bit lines 14 correspondingly through the plurality of first leads 2111 and the plurality of first contact plugs 31. The resistance error range can also include error differences caused by manufacturing. The resistance error range includes but is not limited to the above two situations.

[0073] It can be understood that the resistance of the first lead 2111 is R=ρL / S. Wherein, ρ is the resistivity of the first lead material, L is the length of the first lead, and S is the cross-sectional area of ​​the first lead. According to the resistance calculation formula, the resistance value increases with the increase of the length of the first lead. Therefore, the greater the extension length of the plurality of first leads 2111, the greater the width thereof, so that the resistance value difference of the transmission path caused by the distance difference can be compensated, and the stability of the coupling between the bit line 14 and the peripheral circuit 42 can be improved.

[0074] In order to facilitate the preparation of multiple first pads 2112 and multiple first leads 2111 while ensuring consistent resistance values ​​when the bit lines 14 and the peripheral circuits 42 are coupled, the layout of the multiple first pads 2112 and multiple first leads 2111 and the coupling with the multiple first contact plugs 31 can be standardized.

[0075] In some embodiments of the present disclosure, see Fig. 9 and Fig.10 , multiple first contact plugs 31 are alternately arranged on both sides of the midpoint line 140 of the multiple bit lines 14, the extension direction of the midpoint line 140 is perpendicular to the first direction x and the second direction y, respectively, and the distances between the multiple first contact plugs 31 and the midpoint line 140 are equal; the first contact plugs 31 located on one side of the midpoint line 140 are coupled to the odd-numbered bit lines 14, and the first contact plugs 31 located on the other side of the midpoint line 140 are coupled to the even-numbered bit lines 14.

[0076] Here, the perpendicular midline 140 refers to a straight line that divides the plurality of bit lines 14 extending along the second direction y into two halves.

[0077] It can be understood that arranging multiple first contact plugs 31 in an alternating manner on both sides of the midpoint line 140 of multiple bit lines 14 is beneficial to increasing the setting space of the first contact plugs 31, thereby increasing the size of the first contact plugs 31, increasing the contact area between the first contact plugs 31 and the bit lines 14, and then reducing the contact resistance between the first contact plugs 31 and the bit lines 14.

[0078] In addition, when the plurality of first contact plugs 31 are arranged in a staggered manner on both sides of the midpoint perpendicular line 140 of the plurality of bit lines 14, the first pads 2112 coupled to the first contact plugs 31 located on the same side of the midpoint perpendicular line 140 are also located on the same side of the midpoint perpendicular line 140, and are arranged in a staggered manner along the extension direction of the midpoint perpendicular line 140. Here, the first pads 2112 are arranged in a staggered manner, which can increase the setting space of the first pads 2112, thereby increasing the size of the first pads 2112, and further improving the problem of the small size of the first contact plugs 31.

[0079] In other embodiments of the present disclosure, see Fig.11 and Fig.12 , a plurality of first contact plugs 31 are sequentially arranged along the midpoint perpendicular lines 140 of the plurality of bit lines 14 , and the extending directions of the midpoint perpendicular lines 140 are respectively perpendicular to the first direction x and the second direction y;

[0080] The first pads 2112 located on one side of the midline 140 are coupled to the first contact plugs 31 of odd number sequence, and the first pads 2112 located on the other side of the midline 140 are coupled to the first contact plugs 31 of even number sequence. Moreover, the first pads 2112 located on the same side of the midline 140 are arranged in a staggered manner along the extension direction of the midline 140. Here, the first contact plugs 31 are arranged in sequence along the midline 140, and the preparation process of the plurality of first contact plugs 31 is simplified; at the same time, the first pads 2112 are arranged in a staggered manner, which can ensure that the plurality of first pads have a larger setting space, which is beneficial to reduce the contact resistance of the coupling between the bit line 14 and the peripheral circuit 42 when connecting with other interconnection layers later.

[0081] Fig.13 A schematic diagram of a layout of a second interconnection layer provided in an embodiment of the present disclosure; Fig.14 A schematic diagram of coupling a first contact plug to a second interconnect layer provided in an embodiment of the present disclosure.

[0082] In some embodiments of the present disclosure, see Fig.13 and Fig.14The plurality of interconnection layers 210 further include a second interconnection layer 212 away from the plurality of bit lines 14, the second interconnection layer 212 includes a plurality of second pads 2121 evenly distributed, the plurality of second pads 2121 being connected to the plurality of second contact plugs 32 (eg Figure 6 As shown in FIG. 2 , the first interconnect structure 21 and the second interconnect structure 41 are connected to the second interconnect structure 41 and the second interconnect structure 41. The second ...

[0083] In the embodiments of the present disclosure, see Fig.14 The plurality of second pads 2121 are evenly distributed on both sides of the midline, and the plurality of first contact plugs 31 located on one side of the midline are correspondingly coupled to the plurality of second pads 2121 on the same side.

[0084] In the embodiment of the present disclosure, the second pad 2121 may also be coupled to structures such as word lines and storage cells 13 through a plurality of second contact plugs 32 and other interconnection layers except the second interconnection layer 212 .

[0085] In some embodiments of the present disclosure, see Figure 6 The plurality of interconnection layers 210 further include at least one intermediate interconnection layer 213 located between the first interconnection layer 211 and the second interconnection layer 212, wherein the intermediate interconnection layer 213 includes a plurality of intermediate pads and a plurality of intermediate leads ( Figure 6 (not shown), the plurality of intermediate pads are coupled to the plurality of bit lines 14 correspondingly through the plurality of intermediate leads, the plurality of intermediate contact plugs 33, and other interconnection layers located between the intermediate interconnection layer 213 and the plurality of bit lines 14;

[0086] The occupied area of ​​the middle pad is larger than the occupied area of ​​the first pad 2112 , and the occupied area of ​​the second pad 2121 is larger than the occupied area of ​​the middle pad.

[0087] It is understandable that the area occupied by the middle pad is set to be larger than the area occupied by the first pad 2112, and the area occupied by the second pad 2121 is larger than the area occupied by the middle pad. In this way, the contact resistance of the coupling between the bit line 14 and the peripheral circuit 42 can be further reduced.

[0088] In some embodiments of the present disclosure, see Figure 5 (b) of FIG. 1 , the memory further includes:

[0089] A plurality of word lines 15 extending along a third direction z and respectively covering a portion of sidewalls of the active regions 120 of the plurality of vertical transistors 12;

[0090] a plurality of word line contact plugs 34, located between the plurality of word lines 15 and the first interconnect structure 21;

[0091] The plurality of word lines 15 are correspondingly coupled to the peripheral circuit 42 through the plurality of word line contact plugs 34 , the first interconnect structure 21 , the bonding interface 40 and the second interconnect structure 41 .

[0092] Fig.15 A schematic diagram of the layout of a contact plug provided in an embodiment of the present disclosure.

[0093] In some embodiments of the present disclosure, see Fig.15 , a plurality of word line contact plugs 34 are distributed at opposite ends of a plurality of word lines 15, a word line contact plug 34 at one end of the plurality of word lines 15 is coupled to an odd-numbered word line 15, and a word line contact plug 34 at the other end of the plurality of word lines 15 is coupled to an even-numbered word line 15. In this way, the arrangement space of the word line contact plugs 34 can be further increased, and the contact resistance between the word line contact plugs 34 and the word lines 15 can be reduced.

[0094] In the embodiments of the present disclosure, see Fig.15 The pitch between the plurality of first contact plugs 31 is D1 = 1*BL pitch (ie, one time the bit line pitch), and the pitch between the plurality of word line contact plugs 34 is D2 = 2*WL pitch (ie, twice the word line pitch).

[0095] In the embodiments of the present disclosure, see Fig.15 The memory further includes a capacitor contact plug 30 for correspondingly coupling the plurality of memory cells 13 to the peripheral circuit 42 through the first interconnect structure 21 , the bonding interface 40 and the second interconnect structure 41 .

[0096] The present disclosure also provides a method for manufacturing a memory. Fig.16 A schematic diagram of a method for manufacturing a memory provided by an embodiment of the present disclosure is shown in FIG. Fig.16 As shown, the method comprises the following steps:

[0097] Step S101: forming a first semiconductor structure, wherein the first semiconductor structure includes a memory array 11, a plurality of bit lines 14, and a first interconnect structure 21; the memory array 11 includes a plurality of vertical transistors 12 arranged in an array and a plurality of memory cells 13 coupled to the plurality of vertical transistors 12 in a one-to-one correspondence, the active region 120 of each vertical transistor 12 extends along a first direction x, and the first end A1 of each vertical transistor 12 is coupled to the first end B1 of each memory cell 13; the plurality of bit lines 14 are located on a side of the plurality of vertical transistors 12 away from the plurality of memory cells 13, the plurality of bit lines 14 extend along a second direction y perpendicular to the first direction x, and are respectively coupled to the second ends A2 of the plurality of vertical transistors 12 in a corresponding manner; the first interconnect structure 21 is located on a side of the plurality of bit lines 14 away from the memory array 11;

[0098] Step S102: forming a second semiconductor structure, wherein the second semiconductor structure includes a peripheral circuit 42 and a second interconnect structure 41 located on the peripheral circuit 42;

[0099] Step S103: bonding the first semiconductor structure and the second semiconductor structure by forming a bonding interface 40 between the first interconnect structure 21 and the second interconnect structure 41, so that the plurality of bit lines 14 are correspondingly coupled to the peripheral circuit 42 through the first interconnect structure 21, the bonding interface 40 and the second interconnect structure 41; wherein the first interconnect structure 21 includes a plurality of interconnect layers 210, the plurality of interconnect layers 210 include a first interconnect layer 211 close to the plurality of bit lines 14, the first interconnect layer 211 includes a plurality of first pads 2112 and a plurality of first leads 2111, the plurality of first pads 2112 are correspondingly coupled to the plurality of bit lines 14 through the plurality of first leads 2111 and the plurality of first contact plugs 31, the plurality of first pads 2112 have the same size, the plurality of first contact plugs 31 have the same size, and for the plurality of first leads 2111, the larger the extension length, the larger the width.

[0100] Figures 17 to 28 Schematic diagram of the structure of the memory in the manufacturing process of the embodiment of the present disclosure, wherein: Figures 17 to 20 For along Figure 4 Schematic diagram of the vertical section of the a-a' line in Figure 21 to Figure 23 , Fig.25 This is a three-dimensional schematic diagram of the memory during the manufacturing process. Fig.24 , Figure 26 to Figure 28 For along Figure 4 A vertical cross-section diagram of the c-c' line in FIG. Figures 17 to 28 The manufacturing method of the memory provided in the embodiment of the present disclosure is further described.

[0101] It should be noted that, in order to clearly illustrate the content of this embodiment, Figure 21 to Figure 23 , Fig.25 Only some devices such as the vertical transistor 12, the word line 15 and the bit line 14 are shown.

[0102] First, step S101 is performed: forming a first semiconductor structure.

[0103] In some embodiments of the present disclosure, see Figures 17 to 28 , forming a first semiconductor structure, comprising:

[0104] The substrate 50 is etched from the first surface 501 to form a plurality of active regions 120 arranged in an array and a trench structure T1 defining the plurality of active regions 120. Each active region 120 extends along a first direction x perpendicular to the substrate 50 (eg, Fig.17 shown);

[0105] An isolation structure 51 (such as Fig.18 shown);

[0106] Etching a portion of the isolation structure 51 from the first surface 501 to form a plurality of word line trenches extending along a third direction z, each word line trench exposing a portion of each active region 120 arranged along the third direction z, the third direction z being perpendicular to the first direction x;

[0107] A gate dielectric layer 52 and a word line 15 (such as Fig.19 shown);

[0108] Doping the first end C1 of each active region 120 from the first surface 501 to form a first source and drain region;

[0109] A plurality of memory cells 13 are formed on the first surface 501, and a first terminal B1 of each memory cell 13 is coupled to a first source / drain region (eg, Fig. 20 shown);

[0110] The substrate 50 is thinned from the second surface 502 (eg Fig. 22 ), to expose the second end C2 of each active region 120; doping the second end C2 of each active region 120 from the second surface 502 to form a second source and drain region (as shown in FIG. Fig.23 , 24 shown);

[0111] A plurality of bit lines 14 extending along a second direction y are formed on the second surface 502. The plurality of bit lines 14 are respectively coupled to the second source and drain regions of the plurality of active regions 120. The second direction y is perpendicular to the first direction x and intersects with the third direction z (eg Fig.25 shown);

[0112] A first interconnect structure 21 is formed on the second face 502 .

[0113] In the embodiments of the present disclosure, see Fig. 20 The first surface 501 and the second surface 502 are two opposite surfaces of the substrate 50 along the first direction x. The first end C1 and the second end C2 of the active region 120 are two opposite ends along the first direction x.

[0114] In the embodiments of the present disclosure, see Fig. 20 The substrate 50 may include at least one of the semiconductor materials, for example, Group IV elements such as silicon (Si), germanium (Ge), silicon germanium (SiGe), or Group III-V compounds such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), etc. The substrate 50 including silicon is exemplified below.

[0115] In the embodiments of the present disclosure, see Fig. 20 The isolation structure 51 may include materials such as silicon oxide, silicon nitride, etc.; the material of the gate dielectric layer 52 includes but is not limited to silicon oxide, silicon nitride or a dielectric material of a high-k dielectric; the material of the word line 15 includes but is not limited to tungsten, cobalt, copper, titanium nitride, polysilicon, silicide or any combination thereof.

[0116] In the embodiment of the present disclosure, the first end C1 and the second end C2 of the active region 120 may be doped by an ion implantation process and / or a thermal diffusion process to form a first source-drain region and a second source-drain region. The first source-drain region and the second source-drain region may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)).

[0117] In the embodiments of the present disclosure, see Figure 26 to Figure 28 After doping the second end C2 of each active area 120 from the second surface 502, the specific steps of forming multiple bit lines 14 include: depositing and etching the bit line connecting material 53 and the bit line conductive material 54 on the second surface 502, and the remaining bit line connecting material 53 and the bit line conductive material 54 located on the second end C2 are respectively formed into the bit line connecting layer 141 and the bit line conductive layer 142 in the bit line 14.

[0118] In the embodiment of the present disclosure, the material of the bit line connection layer 141 may include polysilicon, and the material of the bit line conductive layer 142 may include titanium nitride.

[0119] In the embodiment of the present disclosure, after forming the plurality of bit lines 14, the method further includes: forming a plurality of first contact plugs 31 (such as Figure 5 As shown in FIG. (a) of FIG. 1 ). Since the first contact plug 31 is located at the side of the bit line 14 away from the memory array 11, the first contact plug 31 is a backside contact plug (Backside Contact) of the bit line 14. The backside here refers to the side of the bit line 14 away from the memory array 11.

[0120] In the embodiments of the present disclosure, see Fig. 9 , the first contact plug 31 can be arranged in the middle region of the bit line 14 (i.e., the region between the two ends of the bit line), and the layout of the first contact plug 31 is not limited by devices such as vertical transistors and word lines. In this way, the problem of limitations in the layout of the first contact plug 31 is improved, and at the same time, the transmission resistance between the first contact plug 31 and the memory cells at both ends of the bit line 14 can be reduced, thereby improving the sensing margin of the memory.

[0121] In the embodiments of the present disclosure, see Fig.10 and Fig.12, the size of the first pad 2112 is much larger than the size of the first contact plug 31. In this way, the problem of the small size of the first contact plug 31 can be improved, which is beneficial for coupling the bit line 14 with the peripheral circuit 42.

[0122] It is understandable that the bit line 14 is prepared from the second surface 502 of the substrate 50 by thinning the second surface 502 of the substrate 50. In this way, the preparation of the bit line 14 can be performed at the end of the entire process steps, thereby simplifying the bit line preparation process.

[0123] In some embodiments of the present disclosure, forming a first semiconductor structure further includes:

[0124] Form a plurality of word line contact plugs 34 (eg Figure 5 As shown in FIG. 1( b ), a plurality of word line contact plugs 34 are located between a plurality of word lines 15 and a first interconnect structure 21 ; wherein the plurality of word lines 15 are correspondingly coupled to a peripheral circuit 42 via a plurality of word line contact plugs 34 , a first interconnect structure 21 , a bonding interface 40 and a second interconnect structure 41 .

[0125] In the disclosed embodiment, the word line contact plug 34 is also a back side contact plug of the word line 15 . The back side here refers to the side of the word line 15 away from the memory cell 13 .

[0126] In the embodiments of the present disclosure, see Fig.15 , multiple word line contact plugs 34 are distributed at opposite ends of multiple word lines 15, the word line contact plug 34 located at one end of the multiple word lines 15 is coupled to the odd-numbered word lines 15, and the word line contact plug 34 located at the other end of the multiple word lines 15 is coupled to the even-numbered word lines 15.

[0127] In some embodiments of the present disclosure, forming a first interconnect structure 21 on the second surface 502 includes:

[0128] A first interconnect layer 211 (eg, Figure 6 As shown), the first interconnect layer 211 is located on the plurality of bit lines 14;

[0129] At least one intermediate interconnection layer 213 (eg, Figure 6 As shown), the intermediate interconnect layer 213 includes a plurality of intermediate pads and a plurality of intermediate leads ( Figure 6 (not shown), multiple intermediate pads are coupled to multiple bit lines 14 through multiple intermediate leads, multiple intermediate contact plugs 33 and other interconnect layers located between the intermediate interconnect layer 213 and the multiple bit lines 14; wherein the occupied area of ​​the intermediate pads is larger than the occupied area of ​​the first pad 2112.

[0130] In the embodiment of the present disclosure, a specific method for forming the first interconnect layer 211 includes: forming a dielectric layer on the first contact plug 31; forming a plurality of first pads 2112 and a plurality of first leads 2111 in the dielectric layer. Here, the material of the dielectric layer includes but is not limited to one or more of silicon oxide, silicon nitride, silicon oxynitride or silicon oxycarbide; the material of the first pads 2112 and the first leads 2111 includes a conductive material, for example, copper, aluminum, tungsten or tin.

[0131] In the embodiment of the present disclosure, the first interconnection layer 211 may be formed by depositing a conductive material through one or more thin film deposition processes (including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating or any combination thereof). The manufacturing process for forming the interconnection layer may also include photolithography, chemical mechanical polishing (CMP), wet / dry etching or any other suitable process.

[0132] It should be noted that the subsequent formation of other interconnection layers may adopt the same materials and process methods as those used to form the first interconnection layer 211 , which will not be described in detail below.

[0133] In the embodiment of the present disclosure, the resistances of the plurality of first lead lines 2111 are substantially the same.

[0134] In one embodiment of the present disclosure, see Fig. 9 and Fig.10 , multiple first contact plugs 31 are alternately arranged on both sides of the midpoint line 140 of the multiple bit lines 14, the extension direction of the midpoint line 140 is perpendicular to the first direction x and the second direction y, respectively, and the distances between the multiple first contact plugs 31 and the midpoint line 140 are equal; the first contact plugs 31 located on one side of the midpoint line 140 are coupled to the odd-numbered bit lines 14, and the first contact plugs 31 located on the other side of the midpoint line 140 are coupled to the even-numbered bit lines 14.

[0135] It can be understood that arranging multiple first contact plugs 31 in an alternating manner on both sides of the midpoint line 140 of multiple bit lines 14 is beneficial to increasing the setting space of the first contact plugs 31, thereby increasing the size of the first contact plugs 31, increasing the contact area between the first contact plugs 31 and the bit lines 14, and then reducing the contact resistance between the first contact plugs 31 and the bit lines 14.

[0136] In the embodiment of the present disclosure, when the plurality of first contact plugs 31 are arranged in a staggered manner on both sides of the midpoint perpendicular line 140 of the plurality of bit lines 14, the first pads 2112 coupled to the first contact plugs 31 located on the same side of the midpoint perpendicular line 140 are also located on the same side of the midpoint perpendicular line 140, and are arranged in a staggered manner along the extension direction of the midpoint perpendicular line 140. Here, the first pads 2112 are arranged in a staggered manner, which can increase the setting space of the first pads 2112, thereby increasing the size of the first pads 2112, and further improving the problem of the small size of the first contact plugs 31.

[0137] In another embodiment of the present disclosure, see Fig.11 and Fig.12 , a plurality of first contact plugs 31 are sequentially arranged along the midpoint perpendicular lines 140 of the plurality of bit lines 14 , and the extending directions of the midpoint perpendicular lines 140 are respectively perpendicular to the first direction x and the second direction y;

[0138] The first pads 2112 located on one side of the midline 140 are coupled to the odd-numbered first contact plugs 31, and the first pads 2112 located on the other side of the midline 140 are coupled to the even-numbered first contact plugs 31. Furthermore, the first pads 2112 located on the same side of the midline 140 are staggered along the extending direction of the midline 140.

[0139] In some embodiments of the present disclosure, forming the first interconnect structure 21 on the second surface 502 further includes:

[0140] A second interconnect layer 212 (eg, Fig.13 As shown), the second interconnect layer 212 includes a plurality of uniformly distributed second pads 2121, and the plurality of second pads 2121 are coupled to the plurality of bit lines 14 through a plurality of second contact plugs 32 and other interconnect layers except the second interconnect layer 212; wherein the occupied area of ​​the second pads 2121 is greater than the occupied area of ​​the middle pads.

[0141] Here, the plurality of second pads 2121 are evenly distributed on the second interconnect layer 212 , which is beneficial for bonding the first interconnect structure 21 with the second interconnect structure 41 , thereby improving the stability of coupling between the plurality of bit lines 14 and the peripheral circuit 42 .

[0142] Then, step S102 is performed: forming a second semiconductor structure, wherein the second semiconductor structure includes a peripheral circuit 42 and a second interconnect structure 41 (such as Figure 5 (as shown in Figure (a)).

[0143] In the embodiment of the present disclosure, forming the second interconnect structure 41 includes forming a plurality of interconnect layers. The method of forming the second interconnect structure 41 is similar to the method of forming the first interconnect structure 21 , and will not be described in detail herein.

[0144] Finally, step S103 is performed: the first semiconductor structure and the second semiconductor structure are bonded by forming a bonding interface 40 between the first interconnect structure 21 and the second interconnect structure 41, so that the plurality of bit lines 14 are correspondingly coupled to the peripheral circuit 42 through the first interconnect structure 21, the bonding interface 40 and the second interconnect structure 41 (e.g., Figure 5 (as shown in Figure (b)).

[0145] In the embodiment of the present disclosure, a hybrid bonding technique may be used to form the bonding interface 40. Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)), and can simultaneously obtain metal-metal (e.g., copper-copper) bonding and dielectric-dielectric (e.g., silicon oxide-silicon oxide) bonding.

[0146] In the embodiments of the present disclosure, see Figure 5 As shown in (a) and (b), the first contact plug 31 and the word line contact plug 34 are both back contact plugs of the bit line 14 and the word line 15, so the first semiconductor structure and the second semiconductor structure can be hybrid bonded in a back-to-face manner.

[0147] It can be understood that after the bonding interface 40 is formed between the first interconnect structure 21 and the second interconnect structure 41, the plurality of bit lines 14 can be coupled to the peripheral circuit 42 through the first interconnect structure 21, the bonding interface 40 and the second interconnect structure 41. In this way, the stability of the coupling between the bit line 14 and the peripheral circuit 42 is improved, and the performance and yield of the memory are improved.

[0148] It should be noted that the memory provided by the embodiments of the present disclosure can be applied to DRAM structures or other semiconductor devices, and no further limitation is given here. The technical features in the technical solutions recorded in the embodiments of the memory provided by the present disclosure can be arbitrarily combined without conflict.

[0149] The above are only preferred embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A memory, characterized in that: include: A memory array, comprising a plurality of vertical transistors arranged in an array and a plurality of memory cells coupled to the plurality of vertical transistors in a one-to-one correspondence, wherein an active region of each of the vertical transistors extends along a first direction, and a first end of each of the vertical transistors is coupled to a first end of one of the memory cells; a plurality of bit lines, located on a side of the plurality of vertical transistors away from the plurality of memory cells, extending along a second direction perpendicular to the first direction, and respectively coupled to the second ends of the plurality of vertical transistors; a first interconnect structure, located on a side of the plurality of bit lines away from the memory array; a second interconnect structure located on a side of the first interconnect structure away from the plurality of bit lines; a bonding interface located between the first interconnect structure and the second interconnect structure; a peripheral circuit located on a side of the second interconnect structure away from the first interconnect structure, wherein the plurality of bit lines are correspondingly coupled to the peripheral circuit through the first interconnect structure, the bonding interface and the second interconnect structure; The first interconnect structure includes a plurality of interconnect layers, the plurality of interconnect layers include a first interconnect layer close to the plurality of bit lines, the first interconnect layer includes a plurality of first pads and a plurality of first leads, the plurality of first pads are coupled to the plurality of bit lines via the plurality of first leads and a plurality of first contact plugs, the plurality of first pads have the same size, and the plurality of first contact plugs have the same size. For the plurality of first lead lines, the greater the extension length, the greater the width.

2. The memory according to claim 1, characterized in that: The resistances of the plurality of first lead lines are substantially the same.

3. The memory according to claim 1 or 2, characterized in that: The plurality of first contact plugs are arranged alternately on both sides of the midpoint perpendicular lines of the plurality of bit lines, the extending directions of the midpoint perpendicular lines are respectively perpendicular to the first direction and the second direction, and the plurality of first contact plugs are equidistant from the midpoint perpendicular lines; The first contact plug located on one side of the midline is coupled to the odd-numbered bit lines, and the first contact plug located on the other side of the midline is coupled to the even-numbered bit lines.

4. The memory according to claim 3, characterized in that: The first pads coupled to the first contact plugs located on the same side of the midline are also located on the same side of the midline and are staggered along the extending direction of the midline.

5. The memory according to claim 1 or 2, characterized in that: The plurality of first contact plugs are sequentially arranged along perpendicular midlines of the plurality of bit lines, and the extending directions of the perpendicular midlines are respectively perpendicular to the first direction and the second direction; The first pads located on one side of the midline are coupled to the first contact plugs of odd number sequence, and the first pads located on the other side of the midline are coupled to the first contact plugs of even number sequence.

6. The memory according to claim 5, characterized in that: The first pads located on the same side of the perpendicular midline are arranged in a staggered manner along the extending direction of the perpendicular midline.

7. The memory according to claim 1 or 2, characterized in that: The plurality of interconnection layers further include a second interconnection layer away from the plurality of bit lines, the second interconnection layer includes a plurality of evenly distributed second pads, the plurality of second pads are correspondingly coupled to the plurality of bit lines through a plurality of second contact plugs and other interconnection layers except the second interconnection layer.

8. The memory according to claim 7, characterized in that: The plurality of interconnection layers further include at least one intermediate interconnection layer located between the first interconnection layer and the second interconnection layer, the intermediate interconnection layer including a plurality of intermediate pads and a plurality of intermediate leads, the plurality of intermediate pads being coupled to the plurality of bit lines via the plurality of intermediate leads, a plurality of intermediate contact plugs, and other interconnection layers located between the intermediate interconnection layer and the plurality of bit lines; The occupied area of ​​the middle pad is larger than the occupied area of ​​the first pad, and the occupied area of ​​the second pad is larger than the occupied area of ​​the middle pad.

9. The memory according to claim 1 or 2, characterized in that: The memory also includes: a plurality of word lines extending along a third direction and respectively covering a portion of sidewalls of active regions of the plurality of vertical transistors, wherein the third direction is perpendicular to the first direction and intersects the second direction; a plurality of word line contact plugs located between the plurality of word lines and the first interconnect structure; The plurality of word lines are correspondingly coupled to the peripheral circuits through the plurality of word line contact plugs, the first interconnect structure, the bonding interface and the second interconnect structure.

10. The memory according to claim 9, characterized in that: The multiple word line contact plugs are distributed at opposite ends of the multiple word lines. The word line contact plug located at one end of the multiple word lines is coupled to the word lines of odd sequence, and the word line contact plug located at the other end of the multiple word lines is coupled to the word lines of even sequence.

11. A method for manufacturing a memory, characterized in that: include: A first semiconductor structure is formed, wherein the first semiconductor structure includes a memory array, a plurality of bit lines and a first interconnection structure; the memory array includes a plurality of vertical transistors arranged in an array and a plurality of memory cells coupled to the plurality of vertical transistors in a one-to-one correspondence, the active region of each of the vertical transistors extends along a first direction, the first end of each of the vertical transistors is coupled to the first end of each of the memory cells; the plurality of bit lines are located on a side of the plurality of vertical transistors away from the plurality of memory cells, the plurality of bit lines extend along a second direction perpendicular to the first direction, and are respectively coupled to the second ends of the plurality of vertical transistors in a corresponding manner; the first interconnection structure is located on a side of the plurality of bit lines away from the memory array; forming a second semiconductor structure, wherein the second semiconductor structure includes a peripheral circuit and a second interconnect structure located on the peripheral circuit; The first semiconductor structure and the second semiconductor structure are bonded by forming a bonding interface between the first interconnect structure and the second interconnect structure, so that the plurality of bit lines are coupled to the peripheral circuit through the first interconnect structure, the bonding interface and the second interconnect structure; wherein the first interconnect structure comprises a plurality of interconnect layers, the plurality of interconnect layers comprises a first interconnect layer close to the plurality of bit lines, the first interconnect layer comprises a plurality of first pads and a plurality of first leads, the plurality of first pads are coupled to the plurality of bit lines through the plurality of first leads and a plurality of first contact plugs, the plurality of first pads have the same size, the plurality of first contact plugs have the same size, and for the plurality of first leads, the larger the extension length, the larger the width.

12. The method for manufacturing a memory according to claim 11, characterized in that: Forming the first semiconductor structure includes: Etching the substrate from the first surface to form a plurality of active regions arranged in an array and a trench structure defining the plurality of active regions, each of the active regions extending along a first direction perpendicular to the substrate; forming an isolation structure in the trench structure; Etching a portion of the isolation structure from the first surface to form a plurality of word line trenches extending along a third direction, each of the word line trenches exposing a portion of each of the active regions arranged along the third direction, the third direction being perpendicular to the first direction; forming a gate dielectric layer and a word line in each of the word line trenches in sequence; Doping the first ends of the active regions from the first surface to form first source and drain regions; Forming the plurality of memory cells on the first surface, wherein a first end of each memory cell is coupled to one of the first source and drain regions; Thinning the substrate from the second surface to expose the second end of each active region; doping the second end of each active region from the second surface to form a second source and drain region; forming a plurality of bit lines extending along the second direction on the second surface, the plurality of bit lines being respectively coupled to the second source and drain regions of the plurality of active regions, the second direction being perpendicular to the first direction and intersecting the third direction; A first interconnect structure is formed on the second side.

13. The method for manufacturing a memory according to claim 12, characterized in that: A first interconnect structure is formed on the second surface, comprising: forming the first interconnect layer on the second surface, the first interconnect layer being located on the plurality of bit lines; At least one intermediate interconnect layer is formed on the first interconnect layer, the intermediate interconnect layer includes a plurality of intermediate pads and a plurality of intermediate leads, the plurality of intermediate pads are correspondingly coupled to the plurality of bit lines through the plurality of intermediate leads, a plurality of intermediate contact plugs, and other interconnect layers located between the intermediate interconnect layer and the plurality of bit lines; wherein the occupied area of ​​the intermediate pads is greater than the occupied area of ​​the first pads.

14. The method for manufacturing a memory according to claim 13, characterized in that: Forming a first interconnect structure on the second surface, further comprising: A second interconnect layer is formed on the intermediate interconnect layer, the second interconnect layer includes a plurality of evenly distributed second pads, the plurality of second pads are coupled to the plurality of bit lines correspondingly through a plurality of second contact plugs and other interconnect layers except the second interconnect layer; wherein an occupied area of ​​the second pads is greater than an occupied area of ​​the intermediate pads.

15. The method for manufacturing a memory according to claim 12, characterized in that: The first semiconductor structure is formed, further comprising: A plurality of word line contact plugs are formed, wherein the plurality of word line contact plugs are located between the plurality of word lines and the first interconnect structure; wherein the plurality of word lines are correspondingly coupled to the peripheral circuit through the plurality of word line contact plugs, the first interconnect structure, the bonding interface and the second interconnect structure.

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