3D stacked semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a 3D stacked semiconductor device, a manufacturing method thereof and electronic equipment, and the manufacturing method comprises the steps: sequentially and alternately depositing a first insulating layer and a conductive layer on a substrate, and obtaining a stacked structure; etching in the stack structure to form a first groove extending along a first direction parallel to the substrate and a second groove extending along a second direction parallel to the substrate; sequentially depositing a first barrier layer and a first isolation layer covering the inner wall of the first groove and the inner wall of the second groove on the substrate; the first trench is filled with a first insulating material; depositing a second isolation layer covering the inner wall of the second groove on the substrate; a second barrier layer fully filling the second groove is deposited on the substrate to obtain an isolation layer located in the second groove, and the isolation layer comprises a second isolation layer and a second barrier layer; under the same etching condition, the etching selection ratios of the second isolation layer and the second barrier layer are different. The 3D stacked semiconductor device manufactured by the manufacturing method provided by the embodiment of the invention is relatively good in structural stability.

Description

Technical Field

[0001] The embodiments of the present application relate to but are not limited to the field of design and manufacturing of semiconductor devices, and in particular to a 3D stacked semiconductor device and a manufacturing method thereof and an electronic device. Background Art

[0002] Semiconductor storage can be divided into volatile memory (Random Access Memory, RAM) and non-volatile memory based on application. RAM includes dynamic random access memory (Dynamic Random Access Memory, DRAM) and static random access memory (Static Random-Access Memory, SRAM). Non-volatile memory includes read-only memory (Read-Only Memory, ROM) and non-ROM.

[0003] Taking DRAM as an example, the conventional DRAM has multiple repeated "memory cells", each of which has a capacitor and a transistor. The capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively. The transistor is the switch that controls the charging and discharging of the capacitor.

[0004] In order to reduce the cost of products as much as possible, people hope to make as many storage units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0006] The embodiments of the present application provide a 3D stacked semiconductor device and a manufacturing method thereof, and an electronic device. The 3D stacked semiconductor device manufactured by the manufacturing method has good structural stability.

[0007] The embodiment of the present application provides a method for manufacturing a 3D stacked semiconductor device, wherein the 3D stacked semiconductor device comprises: different layers of memory cells stacked and distributed along a direction perpendicular to a substrate, and a plurality of bit lines spaced and distributed along a direction perpendicular to the substrate; each memory cell comprises a transistor and a capacitor; two adjacent columns of memory cells located in the same layer are connected to the same bit line, and two adjacent columns of memory cells in different layers connected by the plurality of bit lines stacked and distributed along a direction perpendicular to the substrate constitute a memory repeating unit, and two adjacent memory repeating units are insulated by an isolation layer;

[0008] The manufacturing method comprises:

[0009] Alternatingly depositing a first insulating layer and a conductive layer on a substrate in sequence to obtain a stacked structure;

[0010] The stacked structure is pattern-etched along a direction toward the substrate, so that a first groove extending along a first direction parallel to the substrate and a second groove extending along a second direction parallel to the substrate are formed in the stacked structure, and the first direction intersects with the second direction; the first groove separates each layer of the conductive layer into the bit line and a plurality of conductive parts spaced and distributed on at least one side of the bit line, and the conductive parts include the first electrode and the second electrode of the transistor and the third electrode of the capacitor; the second groove is used to separate two adjacent storage repeating units, and the first groove is located between two adjacent second grooves;

[0011] Depositing a first barrier layer and a first isolation layer on the substrate in sequence, the first barrier layer and the first isolation layer covering at least the inner wall of the first trench and the inner wall of the second trench;

[0012] Filling the first trench with a first insulating material forming the first insulating layer;

[0013] depositing a second isolation layer covering the inner wall of the second trench on the substrate;

[0014] Depositing a second barrier layer filling up the second trench on the substrate to obtain an isolation layer located in the second trench, wherein the isolation layer at least includes the second isolation layer and the second barrier layer;

[0015] Wherein, under the same etching conditions, the etching selectivity ratios of the first barrier layer and the first isolation layer are different; under the same etching conditions, the etching selectivity ratios of the second isolation layer and the second barrier layer are different.

[0016] Exemplarily, the manufacturing method may further include: after depositing a second barrier layer filling up the second trench on the substrate, performing the following process:

[0017] Removing the first insulating material in a partial area of ​​the first trench near the second trench to expose the first isolation layer on a partial sidewall of the first trench and the first isolation layer in the second trench;

[0018] Etching and removing the first isolation layer exposed on the sidewall of the first trench and the first isolation layer at the end of the first trench and located in the second trench, exposing the first barrier layer on the inner wall of the first trench and the first insulating material in the first trench, and exposing the second barrier layer in the second trench;

[0019] Etching and removing the first barrier layer exposed on the inner wall of the first trench, so that the inner wall of the first trench exposes a partial area of ​​the patterned stack structure;

[0020] The first insulating layer in the patterned stacked structure exposed by the sidewall of the first trench is laterally etched, and the second barrier layer exposed in the second trench is removed by etching, so that the second barrier layer in the isolation layer is disconnected at the first trench.

[0021] Exemplarily, patterning and etching the stacked structure in a direction toward the substrate may include:

[0022] The stack structure is patterned and etched along a direction toward the substrate, so that a plurality of first grooves extending along the first direction and spaced apart along the second direction are formed in the stack structure, and a plurality of second grooves extending along the second direction and spaced apart along the first direction are formed in the stack structure, and the second grooves intersect with the first grooves; the plurality of conductive portions are connected on both sides of the bit line, and the plurality of conductive portions on the same side of the bit line are spaced apart along the second direction.

[0023] Exemplarily, sequentially depositing a first barrier layer and a first isolation layer covering an inner wall of the first trench and an inner wall of the second trench on a substrate may include:

[0024] Depositing a first barrier layer on the substrate, covering the inner wall of the first trench, the inner wall of the second trench, and covering the top surface between the adjacent first trenches and the sidewall of the second trench between the adjacent storage repeating units;

[0025] A first isolation layer is deposited on the substrate to cover each region of the first barrier layer.

[0026] Exemplarily, filling the first trench with the first insulating material may include:

[0027] Filling the first trench and the second trench with the first insulating material;

[0028] The first insulating material in the second trench is removed by etching.

[0029] Exemplarily, depositing a second isolation layer covering an inner wall of the second trench on the substrate may include:

[0030] A second isolation layer covering the inner wall of the second trench, the top surface of the patterned stack structure and the first trench is deposited on the substrate.

[0031] Exemplarily, depositing a second barrier layer filling the second trench on the substrate may include:

[0032] A second barrier layer is deposited on the substrate to fill the second trench and cover the top surface of the patterned stack structure and the first trench.

[0033] Exemplarily, the capacitor comprises a third electrode connected to the transistor located in the same storage unit;

[0034] Removing the first insulating material from a partial area of ​​the first trench near the second trench includes:

[0035] The first insulating material in a partial area of ​​the first trench close to the second trench is removed so that the length of the position occupied by the removed first insulating material in the first trench in the first direction is equal to the length of the third electrode of the capacitor to be formed, the third electrode is connected to the second electrode of a transistor, and the first electrode of the transistor is connected to the bit line.

[0036] Exemplarily, etching and removing the first isolation layer exposed on the sidewall of the first trench and the first isolation layer at the end of the first trench and located in the second trench may include:

[0037] The first barrier layer on the inner wall of the first trench and the second barrier layer in the second trench are used as etching barrier layers, and the first isolation layer exposed on the sidewall of the first trench and the first isolation layer at the end of the first trench and located in the second trench are removed simultaneously by one wet etching.

[0038] Exemplarily, laterally etching the first insulating layer in the patterned stacked structure exposed by the sidewall of the first trench, and etching away the second barrier layer exposed in the second trench, may include:

[0039] Wet etching or gas etching is used to simultaneously remove the first insulating layer in the patterned stacked structure and the second barrier layer exposed in the second groove through one etching, exposing one end of each conductive portion away from the bit line, and the exposed end of the conductive portion is the third electrode of the capacitor.

[0040] Exemplarily, the manufacturing method may further include: after exposing the third electrode, performing the following process:

[0041] A dielectric layer and a fourth electrode are deposited on the third electrode, and the third electrode, the dielectric layer and the fourth electrode constitute the capacitor.

[0042] Exemplarily, the manufacturing method may further include: before or after forming the capacitor, performing the following process:

[0043] Etching the patterned conductive layer in a direction toward the substrate to form a through hole penetrating the conductive portion of each conductive layer, wherein the through hole separates the first electrode and the second electrode of the transistor;

[0044] A semiconductor layer and a gate insulating layer are sequentially deposited on the side walls of the through hole, and a gate electrode is filled in the through hole; the semiconductor layer between the first electrode and the second electrode, the first electrode, the second electrode and the gate electrode constitute the transistor; the gate electrodes of the transistor located in different layers are connected together to form a word line extending in a direction perpendicular to the substrate.

[0045] An embodiment of the present application also provides a 3D stacked semiconductor device, and the 3D stacked semiconductor device is obtained by the manufacturing method of the 3D stacked semiconductor device provided in the embodiment of the present application as above.

[0046] Exemplarily, the second isolation layer may include a first sub-isolation layer and a second sub-isolation layer, and the second barrier layer is located between the first sub-isolation layer and the second sub-isolation layer.

[0047] Illustratively, the bit line may extend along a second direction parallel to the substrate.

[0048] Exemplarily, the first sub-isolating layer may extend along the second direction, and the second sub-isolating layer and the second barrier layer may both be disconnected between the memory cells spaced apart from each other along the second direction.

[0049] Exemplarily, the isolation layer may further include a first barrier layer, the first barrier layer is located between the memory cells and the second sub-isolation layer, and the first barrier layer is disconnected between the memory cells spaced apart from each other along the second direction.

[0050] Exemplarily, the isolation layer may further include a first isolation layer, the first isolation layer is located between the first blocking layer and the second sub-isolation layer, and the first isolation layer is disconnected between the memory cells spaced apart and distributed along the second direction.

[0051] Exemplarily, the first isolation layer and the second sub-isolation layer may be an integrated structure.

[0052] Exemplarily, the second sub-isolation layer may extend to the surface of the memory cell at the uppermost layer away from the substrate. Exemplarily, the 3D stacked semiconductor device may further include a plurality of first insulating layers and a plurality of conductive layers located at different layers, the plurality of first insulating layers and the conductive layers being alternately distributed from bottom to top in a direction perpendicular to the substrate; the transistor includes a first electrode and a second electrode; the first electrode, the second electrode of the transistor of the memory cell located at the same layer, the third electrode of the capacitor, and the bit line are located at the same conductive layer;

[0053] The first insulating layer, the first barrier layer, and the second barrier layer are made of the same material.

[0054] An embodiment of the present application further provides an electronic device, which includes the semiconductor device provided in the above embodiment of the present application.

[0055] The manufacturing method of the 3D stacked semiconductor device of the embodiment of the present application deposits a first barrier layer on the patterned stacked structure, and the first barrier layer can be used as an etching barrier layer for the conductive layer in the patterned stacked structure in the subsequent etching process to prevent the conductive layer from being exposed and causing metal contamination of the machine. In addition, the first barrier layer can be used as an etching barrier layer in the subsequent etching process, so that when etching the second isolation layer in the capacitor area, the second isolation layer on the conductive layer will not be cut off, and the continuous second isolation layer can form a more complete isolation layer with the second barrier layer, thereby providing better support for the storage repeating unit.

[0056] The 3D stacked semiconductor device of the embodiment of the present application uses an isolation layer formed by the second isolation layer and the second barrier layer to insulate two adjacent storage repeating units. The isolation layer can provide better support for the storage repeating units, making the structural stability of the storage repeating units better.

[0057] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The objects and advantages of the present application can be realized and obtained by the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0059] Figure 1 A schematic top view of a 3D stacked semiconductor device provided by an exemplary embodiment of the present application;

[0060] Figure 2 A process flow chart of a method for manufacturing a 3D stacked semiconductor device provided for an exemplary embodiment of the present application;

[0061] Figure 3A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after forming a stacked structure;

[0062] Figure 3B for Figure 3A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0063] Figure 3C for Figure 3A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0064] Figure 3D for Figure 3A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0065] Figure 4A A schematic cross-sectional view of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after forming a first trench and a second trench on a cross section parallel to a substrate;

[0066] Figure 4B for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the a-a' direction;

[0067] Figure 4C for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0068] Figure 4D for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0069] Figure 4E for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0070] Figure 5A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after a first insulating layer is filled in a first trench and a second trench;

[0071] Figure 5B for Figure 5A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0072] Figure 5C for Figure 5A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0073] Figure 5D for Figure 5A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0074] Fig. 6A A schematic longitudinal cross-sectional view in the aa' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after removing the first insulating layer exposed in the second trench;

[0075] Figure 6B for Fig. 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0076] Figure 6C for Fig. 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0077] Fig.6D for Fig. 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0078] Fig. 7A A schematic longitudinal cross-sectional view in the a-a' direction after depositing a second barrier layer on a substrate in a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application;

[0079] Figure 7B for Fig. 7A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0080] Figure 7C for Fig. 7A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0081] Fig.7D for Fig. 7A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0082] Fig. 8A A schematic longitudinal cross-sectional view in the aa' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after removing a first insulating layer from a partial region of a first trench close to a second trench;

[0083] Figure 8B for Fig. 8A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0084] Figure 8C for Fig. 8A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0085] Fig.8D for Fig. 8A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0086] Fig. 9A A schematic longitudinal cross-sectional view in the aa' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after removing the first isolation layer exposed by the first trench and the second trench;

[0087] Fig. 9B for Fig. 9A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0088] Fig. 9C for Fig. 9A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0089] Fig.9D for Fig. 9A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0090] Fig. 10A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after lateral etching of the exposed first insulating layer of the stacked structure;

[0091] Fig. 10B for Fig. 10A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0092] Fig. 10C for Fig. 10A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0093] Fig. 10D for Fig. 10A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0094] Fig.11A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after forming a capacitor;

[0095] Fig. 11B for Fig.11A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0096] Fig. 11C for Fig.11AA schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0097] Fig.11D for Fig.11A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction;

[0098] Fig. 12A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after forming a word line;

[0099] Fig. 12B for Fig. 12A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction;

[0100] Fig. 12C for Fig. 12A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0101] Fig.12D for Fig. 12A The semiconductor device shown is a schematic longitudinal cross-sectional view along the d-d' direction.

[0102] The meanings of the symbols in the accompanying drawings are:

[0103] 10-substrate; 11-first insulating layer; 12-conductive layer; 13-second insulating layer; 14-first blocking layer; 15-first isolation layer; 16-second isolation layer; 161-first sub-isolation layer; 162-second sub-isolation layer; 17-second blocking layer; 18-polysilicon layer; 21-first trench; 22-second trench; 31-bit line; 32-first conductive portion; 33-second conductive portion; 41-first electrode; 42-second electrode; 43-third electrode; 44-fourth electrode; 60-word line; 61-gate electrode; 70-storage repeating unit; 71-storage unit; 80-isolation layer; 90-semiconductor layer. DETAILED DESCRIPTION

[0104] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0105] The embodiments of the present application are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present application are not limited to the shapes or values ​​shown in the drawings.

[0106] The ordinal numbers such as "first" and "second" in this application are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0107] In this application, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0108] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0109] In this application, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, a channel region refers to a region where current mainly flows.

[0110] In the present application, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present application, unless otherwise specified, the "source electrode" and the "drain electrode" may be interchanged.

[0111] In the present disclosure, "electrical connection" or "connection" includes situations where constituent elements are connected together through an element having some electrical function, such as electrical signal connection (coupled connection, such as coupled to), or physical direct connection. There is no particular limitation on "element having some electrical function" as long as it can transfer electrical signals between connected constituent elements. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0112] In this application, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0113] In some embodiments of the present application, "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced with "conductive film". Similarly, "insulating film" can sometimes be replaced with "insulating layer".

[0114] The term "A and B are arranged in the same layer" in this application means that A and B are distributed on the same horizontal plane, or although not on the same horizontal plane, they are in different areas of the same support surface. In one embodiment, A and B are formed simultaneously by subjecting the same film layer to the same patterning process.

[0115] In the embodiments of the present application, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned on a film layer to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process, or B is directly grown on A by epitaxy, and the materials of the two may not be exactly the same.

[0116] In various embodiments of the present application, the first direction parallel to the substrate can be understood as a lateral direction. In various embodiments of the present application, the interval distribution can be understood as a separate, independent distribution.

[0117] An embodiment of the present application provides a method for manufacturing a 3D stacked semiconductor device.

[0118] Figure 1 A schematic top view of a 3D stacked semiconductor device provided by an exemplary embodiment of the present application; Figure 2A process flow chart of a method for manufacturing a 3D stacked semiconductor device provided for an exemplary embodiment of the present application.

[0119] The 3D stacked semiconductor device comprises: different layers of memory cells stacked and distributed along a direction perpendicular to the substrate, and a plurality of bit lines 31 spaced and distributed along a direction perpendicular to the substrate; Figure 1 As shown, each layer includes multiple columns of memory cells 71, and each memory cell 71 includes a transistor; two adjacent columns of memory cells 71 located in the same layer are connected to the same bit line 31, and two adjacent columns of memory cells 71 in different layers connected by multiple bit lines 31 stacked and distributed in a direction perpendicular to the substrate constitute a memory repetition unit 70, and two adjacent memory repetition units 70 are insulated by an isolation layer 80.

[0120] like Figure 2 As shown, the manufacturing method comprises:

[0121] Alternatingly depositing a first insulating layer and a conductive layer on a substrate in sequence to obtain a stacked structure;

[0122] The stacked structure is pattern-etched along a direction toward the substrate, so that a first groove extending along a first direction parallel to the substrate and a second groove extending along a second direction parallel to the substrate are formed in the stacked structure, and the first direction intersects with the second direction; the first groove separates each layer of the conductive layer into the bit line and a plurality of conductive parts spaced and distributed on at least one side of the bit line, and the conductive parts include the first electrode and the second electrode of the transistor and the third electrode of the capacitor; the second groove is used to separate two adjacent storage repeating units, and the first groove is located between two adjacent second grooves;

[0123] Depositing a first barrier layer and a first isolation layer on the substrate in sequence, the first barrier layer and the first isolation layer covering at least the inner wall of the first trench and the inner wall of the second trench;

[0124] Filling the first trench with a first insulating material forming the first insulating layer;

[0125] depositing a second isolation layer covering the inner wall of the second trench on the substrate;

[0126] Depositing a second barrier layer filling up the second trench on the substrate to obtain an isolation layer located in the second trench, wherein the isolation layer at least includes the second isolation layer and the second barrier layer;

[0127] Wherein, under the same etching conditions, the etching selectivity ratios of the first barrier layer and the first isolation layer are different; under the same etching conditions, the etching selectivity ratios of the second isolation layer and the second barrier layer are different.

[0128] The manufacturing method of the 3D stacked semiconductor device of the embodiment of the present application deposits a first barrier layer on the patterned stacked structure, and the first barrier layer can be used as an etching barrier layer for the conductive layer in the patterned stacked structure in the subsequent etching process to prevent the conductive layer from being exposed and causing metal contamination of the machine. In addition, the first barrier layer can be used as an etching barrier layer in the subsequent etching process, so that when etching the second isolation layer in the capacitor area, the second isolation layer on the conductive layer will not be cut off, and the continuous second isolation layer can form a more complete isolation layer with the second barrier layer, thereby providing better support for the storage repeating unit.

[0129] Exemplarily, the manufacturing method may further include: after depositing a second barrier layer filling up the second trench on the substrate, performing the following process:

[0130] Removing the first insulating material in a partial area of ​​the first trench near the second trench to expose the first isolation layer on a partial sidewall of the first trench and the first isolation layer in the second trench;

[0131] Etching and removing the first isolation layer exposed on the sidewall of the first trench and the first isolation layer at the end of the first trench and located in the second trench, exposing the first barrier layer on the inner wall of the first trench and the first insulating material in the first trench, and exposing the second barrier layer in the second trench;

[0132] Etching and removing the first barrier layer exposed on the inner wall of the first trench, so that the inner wall of the first trench exposes a partial area of ​​the patterned stack structure;

[0133] The first insulating layer in the patterned stacked structure exposed by the sidewall of the first trench is laterally etched, and the second barrier layer exposed in the second trench is removed by etching, so that the second barrier layer in the isolation layer is disconnected at the first trench.

[0134] Exemplarily, patterning and etching the stacked structure in a direction toward the substrate may include:

[0135] The stack structure is patterned and etched along a direction toward the substrate, so that a plurality of first grooves extending along the first direction and spaced apart along the second direction are formed in the stack structure, and a plurality of second grooves extending along the second direction and spaced apart along the first direction are formed in the stack structure, and the second grooves intersect with the first grooves; the plurality of conductive portions are connected on both sides of the bit line, and the plurality of conductive portions on the same side of the bit line are spaced apart along the second direction.

[0136] Exemplarily, sequentially depositing a first barrier layer and a first isolation layer covering an inner wall of the first trench and an inner wall of the second trench on a substrate may include:

[0137] Depositing a first barrier layer on the substrate, covering the inner wall of the first trench, the inner wall of the second trench, and covering the top surface between the adjacent first trenches and the sidewall of the second trench between the adjacent storage repeating units;

[0138] A first isolation layer is deposited on the substrate to cover each region of the first barrier layer.

[0139] Exemplarily, filling the first trench with the first insulating material includes:

[0140] Filling the first trench and the second trench with the first insulating material;

[0141] The first insulating material in the second trench is removed by etching.

[0142] Exemplarily, depositing a second isolation layer covering an inner wall of the second trench on the substrate may include:

[0143] A second isolation layer covering the inner wall of the second trench, the top surface of the patterned stack structure and the first trench is deposited on the substrate.

[0144] Exemplarily, depositing a second barrier layer filling the second trench on the substrate may include:

[0145] A second barrier layer is deposited on the substrate to fill the second trench and cover the top surface of the patterned stack structure and the first trench.

[0146] Exemplarily, the capacitor comprises a third electrode connected to the transistor located in the same storage unit;

[0147] Removing the first insulating material from a partial region of the first trench close to the second trench may include:

[0148] The first insulating material in a partial area of ​​the first trench close to the second trench is removed so that the length of the position occupied by the removed first insulating material in the first trench in the first direction is equal to the length of the third electrode of the capacitor to be formed, the third electrode is connected to the second electrode of a transistor, and the first electrode of the transistor is connected to the bit line.

[0149] Exemplarily, etching and removing the first isolation layer exposed on the sidewall of the first trench and the first isolation layer at the end of the first trench and located in the second trench may include:

[0150] The first barrier layer on the inner wall of the first trench and the second barrier layer in the second trench are used as etching barrier layers, and the first isolation layer exposed on the sidewall of the first trench and the first isolation layer at the end of the first trench and located in the second trench are removed simultaneously by one wet etching.

[0151] Exemplarily, laterally etching the first insulating layer in the patterned stacked structure exposed by the sidewall of the first trench, and etching away the second barrier layer exposed in the second trench, may include:

[0152] Wet etching or gas etching is used to simultaneously remove the first insulating layer in the patterned stacked structure and the second barrier layer exposed in the second groove through one etching, exposing one end of each conductive portion away from the bit line, and the exposed end of the conductive portion is the third electrode of the capacitor.

[0153] Exemplarily, the manufacturing method may further include: after exposing the third electrode, performing the following process:

[0154] A dielectric layer and a fourth electrode are deposited on the third electrode, and the third electrode, the dielectric layer and the fourth electrode constitute the capacitor.

[0155] Exemplarily, the manufacturing method may further include: before or after forming the capacitor, performing the following process:

[0156] Etching the patterned conductive layer in a direction toward the substrate to form a through hole penetrating the conductive portion of each conductive layer, wherein the through hole separates the first electrode and the second electrode of the transistor;

[0157] A semiconductor layer and a gate insulating layer are sequentially deposited on the side walls of the through hole, and a gate electrode is filled in the through hole; the semiconductor layer between the first electrode and the second electrode, the first electrode, the second electrode and the gate electrode constitute the transistor; the gate electrodes of the transistor located in different layers are connected together to form a word line extending in a direction perpendicular to the substrate.

[0158] The technical solution of the embodiment of the present application is further explained below through the manufacturing process of the 3D stacked semiconductor device of the exemplary embodiment. The "patterned etching" mentioned in this embodiment includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature preparation process in the relevant technology. The "photolithography" process mentioned in this embodiment includes coating of film layers, mask exposure and development, which is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here.

[0159] Figure 3A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after a stacked structure is formed; Figure 3B for Figure 3A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 3C for Figure 3A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Figure 3D for Figure 3A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction; Figure 4A A schematic cross-sectional view of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after forming a first trench and a second trench on a cross section parallel to a substrate;

[0160] Figure 4B for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the a-a' direction; Figure 4C for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 4D for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Figure 4E for Figure 4A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction; Figure 5A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after a first insulating layer is filled in a first trench and a second trench; Figure 5B for Figure 5A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 5C for Figure 5A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction;

[0161] Figure 5D for Figure 5A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction; Fig. 6A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after removing the first insulating layer exposed in the second trench; Figure 6B for Fig. 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 6C for Fig. 6A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Fig.6D for Fig. 6AA schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction; Fig. 7A A schematic longitudinal cross-sectional view in the a-a' direction after depositing a second barrier layer on a substrate in a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application; Figure 7B for Fig. 7A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 7C for Fig. 7A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Fig.7D for Fig. 7A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction; Fig. 8A A schematic longitudinal cross-sectional view in the aa' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after removing a first insulating layer from a partial region of a first trench close to a second trench; Figure 8B for Fig. 8A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Figure 8C for Fig. 8A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Fig.8D for Fig. 8A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction; Fig. 9A A schematic longitudinal cross-sectional view in the aa' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after removing the first isolation layer exposed by the first trench and the second trench; Fig. 9B for Fig. 9A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Fig. 9C for Fig. 9A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Fig.9D for Fig. 9A A schematic longitudinal cross-sectional view of the semiconductor device shown in the d-d' direction; Fig. 10A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after lateral etching of the exposed first insulating layer of the stacked structure; Fig. 10B for Fig. 10A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Fig. 10C for Fig. 10A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Fig. 10D for Fig. 10A The semiconductor device shown is a schematic longitudinal cross-sectional view along the d-d' direction.

[0162] like 3A to 10DAs shown, exemplarily, the method for manufacturing the 3D stacked semiconductor device may include:

[0163] S10: providing a substrate 10, and alternately depositing a first insulating layer 11 and a conductive layer 12 on the substrate 10 in sequence to obtain a stacked structure consisting of the first insulating layer 11 and the conductive layer 12 distributed in layers, wherein the top layer of the stacked structure is the first insulating layer 11, and the material of the first insulating layer 11 is the first insulating material, such as FIG. 3A to FIG. 3D shown.

[0164] Exemplarily, the material of the first insulating layer may be a low-K dielectric material, ie, a dielectric material with a dielectric constant K<3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing film layers.

[0165] In an exemplary embodiment of the application, the material of the conductive layer can be any one or more of conductive metal, conductive metal nitride and polysilicon (Poly); the conductive metal includes but is not limited to tungsten (W), cobalt (Co), titanium (Ti), etc.

[0166] The conductive layer may be a single layer or a multilayer structure, for example, a multilayer structure formed by Ti, TiN and W. For example, Ti, TiN and W may be deposited in sequence on the side of the first insulating layer 11 away from the substrate 10 to form a conductive layer of a multilayer structure. Providing TiN between the side of W close to the substrate 10 and the first insulating layer 11 can prevent W from being oxidized by the oxygen-containing first insulating layer 11, so the film layer formed by TiN can be called an anti-oxidation layer. Of course, the first insulating layer may be an oxygen-free film layer, and then the conductive layer does not need to be added with an anti-oxidation layer.

[0167] For example, Ti may be deposited by a chemical vapor deposition (CVD) process; TiN may be deposited by an atomic layer deposition (ALD) process; and W may be deposited by a CVD or ALD process.

[0168] Exemplarily, the substrate 10 may be a supporting structure, such as a silicon substrate, or a supporting structure on which other film layers or functions or circuits are already distributed, and the device involved in the inventive construction of the embodiment of the present application is arranged on the main surface of the supporting structure.

[0169] FIG. 3A to FIG. 3D The stacked structure shown in the figure includes four first insulating layers 11 and three conductive layers 12, which is only an example. In other embodiments, the stacked structure may include more or fewer first insulating layers 11 and conductive layers 12 that are alternately arranged.

[0170] S20: Pattern-etch the stacked structure.

[0171] Exemplarily, step S20 may include: depositing a second insulating layer 13 on the surface of the stacked structure; defining a photolithography pattern by photolithography, and etching the second insulating layer 13 and the stacked structure along the direction toward the substrate 10 to form in the stacked structure a plurality of first trenches 21 extending along a first direction and spaced apart in the first and second directions, and a plurality of second trenches 22 extending along the second direction and spaced apart in the first direction, where the first direction intersects with the second direction, to obtain a patterned stacked structure composed of alternately stacked patterned first insulating layers 11 and patterned conductive layers 12;

[0172] The first trenches 21 space the conductive layer 12 into bit lines 31 to be formed, a plurality of spaced-apart first conductive portions 32, and a plurality of spaced-apart second conductive portions 33, that is, each patterned conductive layer 12 includes bit lines 31 to be formed, a plurality of spaced-apart first conductive portions 32, and a plurality of spaced-apart second conductive portions 33; wherein, the bit lines 31 connect the first conductive portions 32 and the second conductive portions 33, the plurality of spaced-apart first conductive portions 32 and the plurality of spaced-apart second conductive portions 33 are respectively located on both sides of the bit lines 31, the bit lines 31, the plurality of first conductive portions 32, and the plurality of second conductive portions 33 may form a "丰" (Chinese character for abundance) shaped structure, the bit lines 31 serve as the main stem of the "丰" shaped structure, and the plurality of first conductive portions 32 and the plurality of second conductive portions 33 serve as the branches of the "丰" shaped structure; the first conductive portions 32 may extend along the first direction, the second conductive portions 33 may extend along the first direction, and the bit lines 31 may extend along the second direction; the same bit line 31 may be connected to adjacent two columns of memory cells to be formed in the same layer, and adjacent two columns of memory cells connected by a plurality of bit lines 31 stacked and distributed along a direction perpendicular to the substrate 10 in different layers form a memory repeating unit, and the second trenches 22 are used to space apart adjacent two memory repeating units in the first direction; the first trenches 21 are located between adjacent two second trenches 22, and there are two first trenches 21 between adjacent two second trenches 22 in the first direction; the pattern of the patterned first insulating layer 11 is the same as the pattern of the patterned conductive layer 12, as FIG. 4A to FIG. 4E shown.

[0173] One end of the first conductive portion 32 connected to the bit line 31 serves as the first electrode 41 of the transistor, that is, the bit line 31 and the second electrode 42 of the transistor connected thereto are an integrated structure, or the bit line 31 and the second electrode 42 of the transistor connected thereto are shared, and the end of the first conductive portion 32 away from the bit line 31 is subsequently disconnected from the bit line 31 to form the second electrode 42 of a transistor; the end of the second conductive portion 33 away from the bit line 31 is subsequently disconnected from the bit line 31 to form the second electrode 42 of another adjacent transistor, and the bit line 31 serves as the first electrode 41 of the transistor.

[0174] For example, the first direction and the second direction may both be parallel to the substrate 10. For example, the first direction may be Figure 1 The b-b' direction shown in FIG. 1 , the second direction may be as follows Figure 1 d-d' direction shown.

[0175] Exemplarily, the material of the second insulating layer may be any one or more of silicon oxide (e.g., SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN), and the material of the second insulating layer is different from that of the first insulating layer, so that when one of the insulating layers is subsequently etched and removed, the first insulating layer and the second insulating layer may have different etching rates, thereby removing the insulating layer that is desired to be removed. For example, in this embodiment, the material of the first insulating layer may be silicon oxide, and the material of the second insulating layer may be silicon nitride.

[0176] S30: A first barrier layer 14 and a first isolation layer 15 are sequentially deposited on the inner walls of the first groove 21 and the second groove 22 and the top surface of the patterned stacking structure (the purpose is to cover the top surface between adjacent first grooves 21 and the side walls of the second grooves 22 between adjacent storage repeating units), and the first insulating material is filled in the first groove 21 and the second groove 22.

[0177] Exemplarily, step S30 may include: sequentially depositing a first barrier layer 14 and a first isolation layer 15 on the substrate 10, covering the inner wall (including the side wall and the bottom wall) of the first trench 21, the inner wall (including the side wall and the bottom wall) of the second trench 22, and the top surface of the patterned stack structure, and then depositing a first insulating material filling the first trench 21 and the second trench 22 on the substrate 10, and planarizing the first insulating material on the top surface of the substrate 10 by a chemical mechanical polishing (CMP) process until the second insulating layer 13 on the top surface of the substrate 10 is exposed and then stopping the planarization, such as FIG. 5A to FIG. 5D shown.

[0178] Exemplarily, the material of the first barrier layer 14 is the same as that of the first insulating layer 11 , for example, both can be silicon oxide. The first barrier layer 14 can be formed by the same deposition method as that of the first insulating layer 11 .

[0179] Exemplarily, the material of the first isolation layer 15 is the same as that of the second insulating layer 13 , for example, both may be silicon nitride. The first isolation layer 15 may be formed by the same deposition method as that of the second insulating layer 13 .

[0180] S40 : etching and removing the first insulating material exposed in the second trench 22 .

[0181] Exemplarily, step S40 may include: defining a photolithography pattern by photolithography, and then removing the first insulating material exposed in the second trench 22 by dry etching, such as FIG. 6A to FIG. 6D shown.

[0182] S50 : depositing a second isolation layer 16 on the inner wall of the second trench 22 and on the top surface of the patterned stack structure, and then depositing a second barrier layer 17 in the second trench 22 and on the top surface of the patterned stack structure.

[0183] Exemplarily, step S50 may include: depositing a second isolation layer 16 of the first insulating material covering the inner wall of the second trench 22, the top surface of the patterned stacked structure, and the first trench 21 on the substrate 10, and then depositing a second barrier layer 17 filling the second trench 22 and covering the second isolation layer 16 on the substrate 10, such as FIG. 7A to FIG. 7D shown.

[0184] For example, the material of the second isolation layer 16 in the second trench 22 may be the same as that of the first isolation layer 15, for example, both may be silicon nitride. Figure 7B As shown, the material of the second isolation layer 16 in the second trench 22 is the same as that of the first isolation layer 15 , but the side close to the second barrier layer 17 is the second isolation layer 16 , and the side away from the second barrier layer 17 is the first isolation layer 15 .

[0185] Exemplarily, the material of the second barrier layer may be the same as that of the first barrier layer, for example, both may be silicon oxide.

[0186] S60 : removing the first insulating material in a partial area of ​​the first trench 21 close to the second trench 22 .

[0187] Exemplarily, step S60 may include: removing the first insulating material in a partial area of ​​the first trench 21 near the second trench 22 by dry etching, exposing the first isolation layer 15 on a partial sidewall of the first trench 21, and exposing the first isolation layer 15 in the second trench 22; wherein the length of the position occupied by the etched first insulating material in the first trench 21 in the first direction is equal to the desired length of the third electrode 43 (for example, the inner electrode) of the capacitor to be formed, such as FIG. 8A to FIG. 8D shown.

[0188] S70: etching and removing the first isolation layer 15 exposed on the sidewall of the first trench 21 and the first isolation layer 15 exposed at the end of the first trench 21 and in the second trench 22, such as 9A to 9D shown.

[0189] Exemplarily, step S70 may include: removing the first isolation layer 15 exposed on the sidewall of the first trench 21 and the first isolation layer 15 exposed at the end of the first trench 21 and in the second trench 22 by wet etching, so that part of the sidewall of the first trench 21 exposes the first barrier layer 14 .

[0190] Since the second isolation layer 16 in the second trench 22 is made of the same material as the first isolation layer 15, Fig. 9B As shown, when the first isolation layer 15 in the second trench 22 is etched, the second isolation layer 16 in the second trench 22 is also etched away.

[0191] like Fig. 9B As shown, due to the presence of the second barrier layer 17 on the sidewall of the second trench 22, the second isolation layer 16 covered by the second barrier layer 17 on the sidewall of the second trench 22 will not be etched away, and can be used as a support layer for supporting the storage repeating unit in the future, thereby improving the structural stability of the semiconductor device.

[0192] like Fig. 9A , Fig. 9C and Fig.9D As shown, due to the presence of the second barrier layer 17 on the surface of the substrate 10, the second isolation layer 16 and the first isolation layer 15 on the surface of the substrate 10 covered by the second barrier layer 17 will not be etched away, and can serve as a supporting layer (or frame) to provide support for the storage unit, thereby improving the structural stability of the storage unit.

[0193] like Fig.9D As shown, due to the presence of the first barrier layer 14 on the side wall of the first trench 21, the conductive layer 12 is covered by the first barrier layer 14 and will not be exposed. Therefore, when the first isolation layer 15 on the side wall of the first trench 21 is removed by wet etching, the conductive layer will not come into contact with the chemical reagents used in the wet etching, thereby preventing the machine from being contaminated by metals such as W in the conductive layer.

[0194] S80: etching and removing the first barrier layer 14 exposed on the sidewall and bottom surface of the first trench 21 to expose a partial area of ​​the patterned stacked structure; performing lateral etching on the exposed first insulating layer 11 of the patterned stacked structure, such as FIG. 10A to FIG. 10D shown.

[0195] For example, step S80 may use wet etching or gas etching to laterally etch the exposed first insulating layer 11 of the patterned stacked structure, and the first insulating layer 11 is etched so that the end surface and sidewall of the conductive layer 12 near the second groove 22 are exposed. Here, the exposed area of ​​the conductive layer 12 near the second groove 22 is the third electrode of the capacitor to be formed. FIG. 10A to FIG. 10D As shown, since the second barrier layer 17 on the top surface of the substrate is made of the same material as the first barrier layer 14 and / or the first insulating layer 11, the second barrier layer 17 on the top surface of the substrate will also be etched away. Fig. 10B As shown, a portion of the first insulating layer 11 exposed in the first trench 21 is also etched away.

[0196] In the description of the embodiments of the present application, "gas etching" is defined as an etching method that uses only gas as an etching agent, and the gas only exists in a molecular state during the etching process and does not form plasma, ions, etc.

[0197] Exemplarily, the storage unit of the 3D stacked semiconductor device may also include a capacitor, and the manufacturing method may further include a process of forming the capacitor and a process of forming a gate electrode of a transistor, a semiconductor layer located between the first electrode and the second electrode, and a gate electrode after completing step S80.

[0198] Fig.11A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after forming a capacitor; Fig. 11B for Fig.11A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Fig. 11C for Fig.11A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Fig.11D for Fig.11A The semiconductor device shown is a schematic longitudinal cross-sectional view along the d-d' direction.

[0199] like FIG. 11A to FIG. 11D As shown, the process of forming a capacitor may include:

[0200] S90 : depositing a dielectric layer and a fourth electrode in sequence on an exposed area of ​​the conductive layer 12 close to the second trench 22 (ie, the third electrode of the capacitor).

[0201] Exemplarily, step S90 may include: sequentially covering the exposed end surface and side wall of the third electrode 43 and the dielectric layer (not shown in the figure) and the conductive film layer covering the top surface of the substrate 10 on the substrate 10, wherein the conductive film layer wrapping the third electrode 43 serves as the fourth electrode 44 of the capacitor, and the third electrode 43, the dielectric layer and the fourth electrode 44 constitute a capacitor; and then filling the empty space of the first trench 21 with a polysilicon layer 18, such as FIG. 11A to FIG. 11D shown.

[0202] Exemplarily, the material of the dielectric layer may be silicon oxide or a High-K dielectric material, that is, a dielectric material with a dielectric constant K≥3.9. The High-K dielectric material may include but is not limited to at least one of the following: aluminum oxide (Al2O3) and hafnium oxide.

[0203] Exemplarily, the material of the fourth conductive layer includes but is not limited to at least one of the following: polysilicon, tungsten, and titanium nitride.

[0204] For example, before depositing the fourth electrode, TiN or the like may be deposited on the surface of the dielectric layer to form an anti-oxidation layer to prevent the tungsten metal forming the fourth electrode 63 from being oxidized by the oxygen-containing dielectric layer such as silicon oxide. Of course, if the dielectric layer is an oxygen-free film layer, there is no need to add an anti-oxidation layer.

[0205] Fig. 12A A schematic longitudinal cross-sectional view in the a-a' direction of a method for manufacturing a 3D stacked semiconductor device according to an exemplary embodiment of the present application after forming a word line; Fig. 12B for Fig. 12A A schematic longitudinal cross-sectional view of the semiconductor device shown in the bb' direction; Fig. 12C for Fig. 12A A schematic longitudinal cross-sectional view of the semiconductor device shown in the c-c' direction; Fig.12D for Fig. 12A The semiconductor device shown is a schematic longitudinal cross-sectional view along the d-d' direction.

[0206] like FIG. 12A to FIG. 12D As shown, the process of forming the semiconductor layer and gate electrode of the transistor may include:

[0207] S100 : etching the patterned stacked structure along a direction toward the substrate 10 to form a through hole K penetrating each patterned conductive layer 12 , and forming a semiconductor layer 90 and a gate electrode 61 in the through hole K.

[0208] Exemplarily, step S100 may include:

[0209] S101: disconnecting the dielectric layer and the conductive film layer on the top surface of the substrate 10 to prevent the capacitor from being connected to the subsequently formed word line, and then depositing a first insulating material and a second insulating layer 13 on the surface of the substrate 10;

[0210] S102: etching the patterned stacked structure along a direction toward the substrate 10 to form a through hole K penetrating each patterned conductive layer 12;

[0211] S103: a semiconductor layer 90 and a gate insulating layer are sequentially deposited on the inner wall of the through hole K, and a gate electrode material is filled in the through hole K; the semiconductor layer 90 (i.e., the semiconductor layer 90 in the parasitic MOS region) on the side wall of the through hole K between two adjacent conductive layers is removed, so that the semiconductor layer 90 is disconnected between the two adjacent conductive layers, and the semiconductor layer 90 on the side wall of the through hole K in the conductive layer that remains forms a channel region of the transistor, and the gate electrode material on the side wall of the through hole K in the conductive layer forms a gate electrode 61 of the transistor, and the first electrode 41, the second electrode 42, and the semiconductor layer 90 and the gate electrode 61 between the first electrode 41 and the second electrode 42 constitute a transistor; the gate electrode material in the entire through hole K forms a word line 60 that runs through transistors of different layers, which can also be understood as the gate electrodes 61 of transistors of different layers being connected together to form a word line 60, such as FIG. 12A to FIG. 12D shown.

[0212] Exemplarily, the through hole K may extend in a direction perpendicular to the substrate 10 , and the word line 60 may extend in a direction perpendicular to the substrate 10 .

[0213] The present application also provides a 3D stacked semiconductor device, such as Figure 1 and FIG. 12A to FIG. 12D As shown, the 3D stacked semiconductor device includes: different layers of memory cells 71 and bit lines 31 stacked and distributed in a direction perpendicular to the substrate 10;

[0214] Each layer includes a plurality of columns of memory cells 71, each memory cell 71 including a transistor;

[0215] The bit line 31 extends along a second direction parallel to the substrate 10. The second direction may be as follows: Figure 1 d-d' direction shown; two adjacent columns of memory cells 71 located in the same layer are connected to the same bit line 31, and two adjacent columns of memory cells 71 in different layers connected by a plurality of bit lines 31 stacked and distributed in a direction perpendicular to the substrate 10 constitute a memory repeating unit 70; two adjacent memory repeating units 70 are insulated by an isolation layer 80;

[0216] The isolation layer 80 includes a second isolation layer 16 and a second barrier layer 17 , and the second isolation layer 16 and the second barrier layer 17 are made of different materials.

[0217] The 3D stacked semiconductor device of the embodiment of the present application uses an isolation layer formed by the second isolation layer and the second barrier layer to insulate two adjacent storage repeating units. The isolation layer can provide better support for the storage repeating units, making the structural stability of the storage repeating units better.

[0218] Exemplarily, the material of the second isolation layer may be any one or more of silicon oxide (eg, SiO 2 ), silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN).

[0219] Exemplarily, the material of the second barrier layer may be any one or more of silicon oxide (e.g., SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN). However, the material of the second barrier layer is different from that of the second isolation layer. For example, the material of the second isolation layer may be silicon nitride, and the material of the second barrier layer may be silicon oxide.

[0220] For example, Figure 1 and Fig. 12A As shown, the second isolation layer 16 may include a first sub-isolation layer 161 and a second sub-isolation layer 162 , and the second barrier layer 17 is located between the first sub-isolation layer 161 and the second sub-isolation layer 162 .

[0221] For example, Figure 1 , Fig. 12A and Fig. 12B The first sub-isolating layer 161 may extend along the second direction, and the second sub-isolating layer 162 and the second barrier layer 17 may be disconnected between the memory cells 71 spaced apart from each other along the second direction.

[0222] Exemplarily, the first sub-isolating layer and the second sub-isolating layer may be made of the same material, for example, may be formed by patterning the same film layer.

[0223] For example, Figure 1 and Fig. 12A As shown, the isolation layer 80 may further include a first barrier layer 14, the first barrier layer 14 is located between the memory cells 71 and the second sub-isolation layer 162, and the first barrier layer 14 is disconnected between the memory cells 71 spaced apart along the second direction.

[0224] Exemplarily, the material of the first barrier layer may be the same as the material of the second barrier layer, for example, both may be silicon oxide.

[0225] For example, Figure 1 and Fig. 12AAs shown, the isolation layer 80 further includes a first isolation layer 15 , which is located between the first barrier layer 14 and the second sub-isolation layer 162 , and the first isolation layer 15 is disconnected between the storage units 71 spaced apart along the second direction.

[0226] Exemplarily, the material of the first isolation layer and the material of the second sub-isolation layer may be the same, for example, both may be silicon nitride.

[0227] For example, Figure 1 As shown, the first isolation layer 15 and the second sub-isolation layer 162 are an integrated structure. For example, the first isolation layer 15 and the second sub-isolation layer 162 can be located in different areas of the integrated structure.

[0228] For example, Fig. 12A As shown, the second sub-isolation layer 162 extends to a surface of the uppermost memory cell 71 away from the substrate 10 .

[0229] Exemplarily, the first isolation layer may extend to a surface of an uppermost memory cell away from the substrate.

[0230] Exemplarily, the 3D stacked semiconductor device may further include a plurality of first insulating layers 11 and a plurality of conductive layers 12 located at different layers, wherein the plurality of first insulating layers 11 and the plurality of conductive layers 12 are alternately distributed from bottom to top in a direction perpendicular to the substrate 10; the transistor includes a first electrode 41 and a second electrode 42; the first electrode 41, the second electrode 42 and the bit line 31 of the transistor of the memory cell 71 located at the same layer are located at the same conductive layer 12;

[0231] The first insulating layer 11 , the first barrier layer 14 , and the second barrier layer 17 are made of the same material.

[0232] For example, Figure 1 and Fig. 12A As shown, the transistor further includes a semiconductor layer 90 and a gate electrode 61 located between the first electrode 41 and the second electrode 42, and the semiconductor layer 90 and the gate electrode 61 have a gate insulating layer (not shown in the figure) for insulation.

[0233] For example, Figure 1 and Fig. 12A As shown, the semiconductor layer 90 may surround the gate electrode 61 .

[0234] Surrounding can be understood as partially surrounding or completely surrounding. Figure 1 and Fig. 12AAs shown, in some embodiments, the surrounding can be a full surrounding, that is, at least the entire side wall of the gate electrode 61 is surrounded by the semiconductor layer 90, and the cross section of the semiconductor layer 90 after the surrounding is a closed ring. The cross section is intercepted along the direction parallel to the substrate. In some other embodiments, the surrounding can be a partial surrounding, that is, part of the side wall of the gate electrode 61 is surrounded by the semiconductor layer 90, and the cross section after the surrounding is not closed, but presents a ring shape. For example, a ring with an opening or two independent semiconductor layers 90. For example, the opposite side surfaces of the gate electrode 61 are surrounded by the semiconductor layer 90, and the cross section of the semiconductor layer 90 is a ring with two openings.

[0235] In the embodiments of the present application, the semiconductor layer can be understood as a semiconductor material, where its shape and structure are not emphasized but only its function.

[0236] Exemplarily, the material of the semiconductor layer may be a material such as silicon or polysilicon with a band gap smaller than 1.65 eV, or may be a wide band gap material, such as a metal oxide material with a band gap larger than 1.65 eV.

[0237] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may contain compounds of other elements, such as N, Si, etc., and may contain other small amounts of doping elements.

[0238] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.

[0239] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0240] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0241] Exemplarily, the electrode material of the gate electrode may be any one or more of the following different types of materials:

[0242] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0243] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as metal oxide materials with high conductivity such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO, etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0244] Of course, it can also be polysilicon material; it can also be conductive material doped semiconductor material, such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0245] Exemplarily, the material of the gate insulating layer may include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of the present application will be exemplarily described below.

[0246] Low-K materials, such as silicon oxide.

[0247] High-K materials, in some embodiments, may include oxides of one or more of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0248] For example, Figure 1 and Fig. 12A As shown, the 3D stacked semiconductor device may further include a word line 60 , and the word line 60 runs through memory cells 71 at different layers.

[0249] Exemplarily, the word line 60 may extend in a direction perpendicular to the substrate 10; the gate electrode 61 is part of the word line 60, and the gate electrodes 61 of transistors in a column of memory cells 71 located at different layers are connected together to form a word line 60; or, the gate electrodes 61 of transistors in a column of memory cells 71 located at different layers are connected to the same word line 60.

[0250] Exemplarily, the material of the bit line can be selected from any one or more of other metal materials with similar properties such as tungsten, molybdenum, cobalt, etc. The bit line can be a single-layer or multi-layer structure, for example, a multi-layer structure formed of titanium (Ti), titanium nitride (TiN) and tungsten (W).

[0251] Exemplarily, the memory cell may be a memory cell including a transistor, the transistor may be an access transistor, and the memory cell may further include other components, such as a capacitor in a 1T1C or 2T1C memory cell, or a read transistor and a storage node in a 1T0C or 2T0C memory cell.

[0252] Exemplarily, the storage unit may include a capacitor, such as Figure 1 and Fig. 12A The capacitor shown includes a third electrode 43, a fourth electrode 44, and a dielectric layer (not shown) located between the third electrode 43 and the fourth electrode 44. The third electrode 43 of the capacitor is connected to the second electrode 42 of the transistor located in the same storage unit, and the connected third electrode 43 and second electrode 42 can be an integrated structure. The dielectric layer and the fourth electrode 44 can surround the third electrode 43.

[0253] Exemplarily, the material of the dielectric layer may be silicon oxide or a High-K dielectric material. In some embodiments, the High-K material may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0254] For example, Figure 1 As shown, the fourth electrodes 44 of the capacitors of a column of storage cells 71 located in the same layer and spaced apart along the second direction may be an integrated structure.

[0255] Exemplarily, the 3D stacked semiconductor device may be a 3D memory, such as a 3D DRAM or other memory. The 3D memory may be a 1T1C, 2T1C structure, or a 1T0C or 2T0C (including a read transistor and a write transistor) structure.

[0256] The 3D stacked semiconductor device provided in the above embodiment of the present application can be obtained by the manufacturing method of the 3D stacked semiconductor device provided in the embodiment of the present application.

[0257] An embodiment of the present application further provides an electronic device, which includes the 3D stacked semiconductor device provided in the above embodiment of the present application.

[0258] Exemplarily, the electronic device may be: a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power source, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0259] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. A method for manufacturing a 3D stacked semiconductor device, characterized in that: The 3D stacked semiconductor device comprises: different layers of memory cells stacked and distributed along a direction perpendicular to a substrate, and a plurality of bit lines spaced and distributed along a direction perpendicular to the substrate; each memory cell comprises a transistor and a capacitor; two adjacent columns of memory cells located in the same layer are connected to the same bit line, and two adjacent columns of memory cells in different layers connected by the plurality of bit lines stacked and distributed along a direction perpendicular to the substrate constitute a memory repeating unit, and two adjacent memory repeating units are insulated by an isolation layer; The manufacturing method comprises: Alternatingly depositing a first insulating layer and a conductive layer on a substrate in sequence to obtain a stacked structure; The stacked structure is pattern-etched along a direction toward the substrate, so that a first groove extending along a first direction parallel to the substrate and a second groove extending along a second direction parallel to the substrate are formed in the stacked structure, and the first direction intersects with the second direction; the first groove separates each layer of the conductive layer into the bit line and a plurality of conductive parts spaced and distributed on at least one side of the bit line, and the conductive parts include the first electrode and the second electrode of the transistor and the third electrode of the capacitor; the second groove is used to separate two adjacent storage repeating units, and the first groove is located between two adjacent second grooves; Depositing a first barrier layer and a first isolation layer on the substrate in sequence, the first barrier layer and the first isolation layer covering at least the inner wall of the first trench and the inner wall of the second trench; Filling the first trench with a first insulating material forming the first insulating layer; depositing a second isolation layer covering the inner wall of the second trench on the substrate; Depositing a second barrier layer filling up the second trench on the substrate to obtain an isolation layer located in the second trench, wherein the isolation layer at least includes the second isolation layer and the second barrier layer; Wherein, under the same etching conditions, the etching selectivity ratios of the first barrier layer and the first isolation layer are different; under the same etching conditions, the etching selectivity ratios of the second isolation layer and the second barrier layer are different.

2. The manufacturing method according to claim 1, characterized in that: Also includes: After depositing a second barrier layer filling up the second trench on the substrate, the following process is performed: Removing the first insulating material in a partial area of ​​the first trench near the second trench to expose the first isolation layer on a partial sidewall of the first trench and the first isolation layer in the second trench; Etching and removing the first isolation layer exposed on the sidewall of the first trench and the first isolation layer at the end of the first trench and located in the second trench, exposing the first barrier layer on the inner wall of the first trench and the first insulating material in the first trench, and exposing the second barrier layer in the second trench; Etching and removing the first barrier layer exposed on the inner wall of the first trench, so that the inner wall of the first trench exposes a partial area of ​​the patterned stack structure; The first insulating layer in the patterned stacked structure exposed by the sidewall of the first trench is laterally etched, and the second barrier layer exposed in the second trench is removed by etching, so that the second barrier layer in the isolation layer is disconnected at the first trench.

3. The manufacturing method according to claim 2, characterized in that: The stacked structure is patterned and etched in a direction toward the substrate, comprising: The stack structure is patterned and etched along a direction toward the substrate, so that a plurality of first grooves extending along the first direction and spaced apart along the second direction are formed in the stack structure, and a plurality of second grooves extending along the second direction and spaced apart along the first direction are formed in the stack structure, and the second grooves intersect with the first grooves; the plurality of conductive portions are connected on both sides of the bit line, and the plurality of conductive portions on the same side of the bit line are spaced apart along the second direction.

4. The manufacturing method according to claim 2, characterized in that: A first barrier layer and a first isolation layer covering the inner wall of the first trench and the inner wall of the second trench are sequentially deposited on the substrate, comprising: Depositing a first barrier layer on the substrate, covering the inner wall of the first trench, the inner wall of the second trench, and covering the top surface between the adjacent first trenches and the sidewall of the second trench between the adjacent storage repeating units; A first isolation layer is deposited on the substrate to cover each region of the first barrier layer.

5. The manufacturing method according to claim 2, characterized in that: Filling the first trench with the first insulating material comprises: Filling the first trench and the second trench with the first insulating material; Etching and removing the first insulating material in the second trench; and / or, depositing a second isolation layer covering the inner wall of the second trench on the substrate, comprising: Depositing a second isolation layer covering the inner wall of the second trench, the top surface of the patterned stacked structure and the first trench on the substrate; and / or, depositing a second barrier layer filling the second trench on the substrate, comprising: A second barrier layer is deposited on the substrate to fill the second trench and cover the top surface of the patterned stack structure and the first trench.

6. The manufacturing method according to any one of claims 2 to 5, characterized in that: The capacitor includes a third electrode connected to the transistor located in the same memory cell; Removing the first insulating material from a partial area of ​​the first trench near the second trench includes: The first insulating material in a partial area of ​​the first trench close to the second trench is removed so that the length of the position occupied by the removed first insulating material in the first trench in the first direction is equal to the length of the third electrode of the capacitor to be formed, the third electrode is connected to the second electrode of a transistor, and the first electrode of the transistor is connected to the bit line.

7. The manufacturing method according to any one of claims 2 to 5, characterized in that: The method of etching and removing the first isolation layer exposed on the sidewall of the first trench and the first isolation layer at the end of the first trench and located in the second trench comprises: The first barrier layer on the inner wall of the first trench and the second barrier layer in the second trench are used as etching barrier layers, and the first isolation layer exposed on the sidewall of the first trench and the first isolation layer at the end of the first trench and located in the second trench are removed simultaneously by one wet etching.

8. The manufacturing method according to any one of claims 2 to 5, characterized in that: Laterally etching the first insulating layer in the patterned stacked structure exposed by the sidewall of the first trench, and etching away the second barrier layer exposed in the second trench, comprising: Wet etching or gas etching is used to simultaneously remove the first insulating layer in the patterned stacked structure and the second barrier layer exposed in the second groove through one etching, exposing one end of each conductive portion away from the bit line, and the exposed end of the conductive portion is the third electrode of the capacitor.

9. The manufacturing method according to claim 8, characterized in that: Also includes: After the third electrode is exposed, the following process is performed: A dielectric layer and a fourth electrode are deposited on the third electrode, and the third electrode, the dielectric layer and the fourth electrode constitute the capacitor.

10. The manufacturing method according to claim 9, characterized in that: Also includes: Before or after forming the capacitor, the following process is performed: Etching the patterned conductive layer in a direction toward the substrate to form a through hole penetrating the conductive portion of each conductive layer, wherein the through hole separates the first electrode and the second electrode of the transistor; Depositing a semiconductor layer and a gate insulating layer on the sidewall of the through hole in sequence, and filling a gate electrode in the through hole, wherein the semiconductor layer between the first electrode and the second electrode, the first electrode, the second electrode and the gate electrode constitute the transistor; Gate electrodes of the transistors located at different layers are connected together to form a word line extending in a direction perpendicular to the substrate.

11. A 3D stacked semiconductor device, characterized in that: Obtained by the production method according to any one of claims 1 to 10.

12. The 3D stacked semiconductor device according to claim 11, characterized in that: The second isolation layer includes a first sub-isolation layer and a second sub-isolation layer, and the second barrier layer is located between the first sub-isolation layer and the second sub-isolation layer.

13. The 3D stacked semiconductor device according to claim 12, characterized in that: The bit line extends along a second direction parallel to the substrate; The first sub-isolation layer extends along the second direction, and the second sub-isolation layer and the second barrier layer are both disconnected between the memory cells spaced apart and distributed along the second direction.

14. The 3D stacked semiconductor device according to claim 13, characterized in that: The isolation layer further includes a first barrier layer, the first barrier layer is located between the storage unit and the second sub-isolation layer, and the first barrier layer is disconnected between the storage units spaced apart along the second direction; and / or, The isolation layer further includes a first isolation layer, the first isolation layer is located between the first barrier layer and the second sub-isolation layer, and the first isolation layer is disconnected between the storage units spaced apart along the second direction; and / or, The first isolation layer and the second sub-isolation layer are an integrated structure.

15. The 3D stacked semiconductor device according to any one of claims 12 to 14, characterized in that: The second sub-isolation layer extends to a surface of the memory cell that is away from the uppermost layer of the substrate.

16. The 3D stacked semiconductor device according to claim 14, characterized in that: It also includes a plurality of first insulating layers and a plurality of conductive layers located in different layers, wherein the plurality of first insulating layers and the conductive layers are alternately distributed from bottom to top in a direction perpendicular to the substrate; the transistor includes a first electrode and a second electrode; the first electrode, the second electrode and the bit line of the transistor of the memory cell located in the same layer are located in the same conductive layer; The first insulating layer, the first barrier layer, and the second barrier layer are made of the same material.

17. An electronic device, characterized in that: Comprising a semiconductor device according to any one of claims 11 to 16.

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