Monolithic integrated CMOS circuit based on GaN base

Abstract

The invention belongs to the technical field of power semiconductors, and particularly relates to a monolithic integrated CMOS circuit based on a GaN base. According to the circuit, a traditional AlGaN barrier layer with a fixed Al component is replaced with a linear gradually-changing AlGaN barrier layer with the Al component linearly changing gradually, specifically, the linear gradually-changing AlGaN barrier layer with the Al component linearly changing gradually from bottom to top, 3DHG induced by polarization difference of the linear gradually-changing AlGaN barrier layer and 2DHG formed by a GaN channel and a heterojunction interface of the linear gradually-changing AlGaN barrier layer are added, the overall concentration of hole gas is increased, and the hole gas efficiency is improved. And thus, the conduction current density of the p-FETs is improved. According to the structure, the conduction current density of the p-FETs can be improved, the P / N channel compatibility can be improved, the conduction mismatch degree of the p- / n-FETs in monolithic integration can be reduced, and the development of a full GaN monolithic power integrated circuit (IC) based on a complementary metal oxide semiconductor (CMOS) can be promoted.

Description

Technical Field

[0001] The invention belongs to the technical field of power semiconductors, and in particular relates to a GaN-based monolithic integrated CMOS circuit. Background Art

[0002] Compared with traditional Si-based devices, GaN power devices have significant advantages in electron saturation velocity, bandgap width, and critical breakdown electric field. For example, the high concentration and high mobility 2DEG at the AlGaN / GaN heterojunction has become a unique feature of GaN power devices. Monolithic integration based on on-chip GaN CMOS not only simplifies circuit design, but also reduces the influence of parasitic inductance, and realizes the most energy-saving and efficient integrated topology with low static power consumption and strong anti-noise capability for the entire power switch system. GaN-based P-channel field effect transistors (FETs) provide the possibility of on-chip CMOS. However, due to the low hole mobility of GaN at room temperature and the difficulty in significantly improving it, and the high ohmic contact resistivity of the device drain and source, the on-current density of GaN p-FETs is much lower than that of the corresponding n-FETs, which is the main obstacle to the current realization of CMOS monolithic integration.

[0003] Therefore, to solve this problem, the most effective method is to increase the on-current density of p-FETs by increasing the hole concentration. At present, the GaN-based P / N double-channel stacked heterojunction epitaxial structure based on increasing the heterojunction polarization strength to increase the hole concentration will lead to the degradation of the threshold voltage of n-FETs devices, the reduction of on-current density, the increase of leakage current, the poor compatibility of P / N channel performance, and the excessive coupling of P / N channel cooperative regulation. Summary of the invention

[0004] In view of the above problems, in order to realize enhanced GaN p-FETs with high on-current density, and monolithically integrate CMOS devices with enhanced n-FETs on the same epitaxial structure, and avoid the degradation of n-FETs threshold voltage and improve P / N channel compatibility, the present invention proposes a GaN-based epitaxial structure and a monolithically integrated CMOS circuit.

[0005] The technical solution adopted by the present invention is:

[0006] A GaN-based monolithic integrated CMOS circuit includes p-FETs and n-FETs, wherein the common structure of the p-FETs and the n-FETs is a substrate 01, a group III nitride buffer layer 02, a GaN channel layer 03, and an AlGaN barrier layer 04 which are stacked in sequence in a vertical direction, wherein the Al component in the AlGaN barrier layer 04 is linearly gradient, and the gradient mode is gradually reduced from bottom to top, and the AlGaN barrier layer of the p-FETs is isolated from the AlGaN barrier layer of the n-FETs;

[0007] The AlGaN barrier layer of the p-FETs has a polarization-induced 3DHG distributed across it due to the gradual change of polarization intensity, a GaN channel layer 05 is provided on the upper surface of the AlGaN barrier layer, a 2DEG is formed at the interface between the AlGaN barrier layer of the p-FETs and the GaN channel layer 05, and a P-type heavily doped GaN layer 06 is provided on the upper surface of the GaN channel layer 05; the upper surfaces of the P-type heavily doped GaN layer 06 have a p-FETs source ohmic metal 07 and a p-FETs drain ohmic metal 08 at both ends thereof, respectively. 8, wherein the p-FETs drain ohmic metal 08 is located on the side close to the n-FETs; a trench gate structure is provided between the p-FETs source ohmic metal 07 and the p-FETs drain ohmic metal 08, the trench gate structure comprising a gate dielectric 13 and a first gate metal 09, the gate dielectric 13 is located in a groove formed on the upper surface of the P-type heavily doped GaN layer 06, wraps the lower part of the first gate metal 09 and contacts the p-FETs source ohmic metal 07 and the p-FETs drain ohmic metal 08 on both sides respectively;

[0008] The AlGaN barrier layer structure of the n-FETs also has a GaN channel layer 05 on its upper surface, and a P-type heavily doped GaN layer 06 on its upper surface; unlike p-FETs, part of the upper layer of the AlGaN barrier layer, the GaN channel layer 05 and both sides of the P-type heavily doped GaN layer 06 of the n-FETs are etched away, leaving only a portion of the middle gate region; a 2DEG is formed at the interface between the AlGaN barrier layer of the n-FETs and the GaN channel layer 03, and both sides of the upper surface of the AlGaN barrier layer of the n-FETs have an n-FETs drain ohmic metal 10 and an n-FETs source ohmic metal 1, respectively, wherein the n-FETs drain ohmic metal 10 is located on the side close to the p-FETs; a second gate metal 12 is provided on the upper surface of the P-type heavily doped GaN layer 06 of the n-FETs to form a planar gate;

[0009] The p-FETs source ohmic metal 07 is a high-level signal port of the CMOS circuit, the n-FETs source ohmic metal 1 is a low-level signal port of the CMOS circuit, the first gate metal 09 and the second gate metal 12 are connected to form an input-level signal port of the CMOS circuit, and the p-FETs drain ohmic metal (8) and the n-FETs drain ohmic metal 10 are connected to form an output-level signal port of the CMOS circuit.

[0010] Furthermore, the material used for the substrate 01 is one of Si, sapphire and SiC.

[0011] Furthermore, the material used for the p-FETs source ohmic metal 07 and the p-FETs drain ohmic metal 08 is any one of Pd / Au / Ni, Ni / Au, and Pd / Ni.

[0012] Furthermore, the material of the first gate metal 09 is any one of Ti / Au, W / Au, Ni / Au, Mo / Au, and Ru.

[0013] Furthermore, the gate dielectric 13 is any one of an oxide layer and an insulating layer.

[0014] Furthermore, the material used for the n-FETs drain ohmic metal 10 and the n-FETs source ohmic metal 1 is any one of Ti / Au, Ti / Al / Ni / Au, and Ti / Al.

[0015] Furthermore, the contact between the second gate metal 12 and the P-type heavily doped GaN layer 06 is an ohmic contact, and the material used for the second gate metal 12 is Ni / Au.

[0016] The beneficial effect of the present invention is that, based on the epitaxial structure of commercial enhanced p-GaN gate HEMTs, the AlGaN barrier layer with a fixed Al component is replaced by a linearly gradient AlGaN barrier layer with a linearly decreasing Al component from bottom to top, and the 3DHG induced by the polarization difference of the linear gradient AlGaN barrier layer plus the 2DHG formed at the heterojunction interface between the GaN channel and the linear gradient AlGaN barrier increases the overall concentration of the hole gas, thereby increasing the on-current density of the p-FETs. At the same time, the 3DHG widens the spatial distribution of the P channel and improves the conductivity of the barrier layer. The gradient AlGaN barrier layer can also help the P-type heavily doped GaN to deplete the 2DEG concentration at the AlGaN / GaN heterojunction interface, thereby increasing the threshold voltage of the n-FETs. In the process of preparing the p-GaN gate of n-FETs, etching away the P-type heavily doped GaN layer, GaN channel layer and part of the linear gradient AlGaN barrier layer in the gate-drain / gate-source region helps to restore the 2DEG depleted by the P-type heavily doped, 2DHG and 3DHG. The linear gradient AlGaN barrier layer is etched to different depths, and the 2DEG concentration in the gate-drain / gate-source region of n-FETs is different, realizing an adjustable N-channel. The adjustability of the N-channel conduction characteristics helps to improve the compatibility of the P / N channels, reduce the mismatch of the p- / n-FETs conduction current in monolithic integration, and promote the development of CMOS-based all-GaN monolithic power integrated ICs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the epitaxial structure of the device proposed in the present invention.

[0018] Figure 2 This is the variation trend of the Al component size in the linear gradient AlGaN barrier layer of the present invention.

[0019] Figure 3This is a schematic diagram of the structure of the device proposed in the present invention after etching out the p-FETs gate groove in the p-FETs area, etching out the P-type heavily doped GaN layer, GaN channel layer and part of the linear gradient AlGaN barrier layer in the n-FETs gate-drain / gate-source area, and etching out the p-FETs and n-FETs device isolation area.

[0020] Figure 4 This is a schematic diagram of the complete structure of a GaN-based CMOS device based on a graded AlGaN barrier layer and an adjustable N-channel monolithic integrated epitaxial structure proposed by the present invention.

[0021] Figure 5 It is a schematic diagram of the topological structure of the CMOS circuit of the present invention. DETAILED DESCRIPTION

[0022] The technical solution of the present invention is described in detail below in conjunction with the attached drawings.

[0023] The present invention provides a GaN-based monolithic integrated CMOS circuit, the preparation method of which is to first prepare Figure 1 The epitaxial structure shown in Figure 1 The epitaxial structure obtained from the growth direction

[0001] in the middle is from bottom to top, including a substrate 01, a III-nitride buffer layer 02 located above the substrate 01, a GaN channel layer 03 located above the III-nitride buffer layer 02, a linearly graded AlGaN barrier layer 04 located above the GaN channel layer, a GaN channel layer 05 located above the linearly graded AlGaN barrier layer 04, and a P-type heavily doped GaN layer 06 located above the GaN channel layer 05.

[0024] The GaN channel layer 05, the linear gradient AlGaN barrier layer 04 and the GaN channel layer 03 form a multi-dimensional heterojunction. A 2DHG is formed at the heterojunction interface between the GaN channel layer 05 and the linear gradient AlGaN barrier layer 04, a 3DHG is formed in the linear gradient AlGaN barrier layer 04, and a 2DEG is formed at the heterojunction interface between the linear gradient AlGaN barrier layer 04 and the GaN channel layer 03. The variation trend of the Al component size in the linear gradient AlGaN barrier layer is shown in the figure. Figure 2 shown.

[0025] From left to right along the lateral direction, the surface of the CMOS device includes the p-FETs device area, the isolation area formed by etching or ion implantation between the p-FETs and n-FETs, and the n-FETs device area. The P-type heavily doped GaN layer 06, the GaN channel layer 05, and part of the linear gradient AlGaN barrier layer 04 in the drain / gate source area of ​​the n-FETs area are etched away. Figure 3 shown.

[0026] The surface of the p-FETs device is shown from left to right along the lateral direction: a source structure composed of a P-type heavily doped GaN layer 06 and a source metal 07 in the source region of the p-FETs, wherein the source ohmic metal 07 contacts the top of the P-type heavily doped GaN layer 06. A drain structure composed of a P-type heavily doped GaN layer 06 and a drain metal 08 in the drain region of the p-FETs, wherein the other end of the drain ohmic metal 08 on the upper surface of the p-FETs device away from the source structure contacts the top of the P-type heavily doped GaN layer 06. The p-FETs gate structure etches away part or all of the P-type heavily doped GaN layer 06 outside the drain and source regions, or etches away part or all of the P-type heavily doped GaN layer 06 in the gate region, and is located on the P-type heavily doped GaN layer 06 or the GaN channel layer 05 between the source structure and the drain structure. The gate structure includes a gate metal 09 deposited on the gate groove and a gate dielectric 13 deposited on the gate groove and on the surface of the P-type heavily doped GaN layer 06 or the GaN channel layer 05 between the drain and source.

[0027] The surface of the n-FETs device is arranged from left to right along the lateral direction: a drain structure composed of a linearly graded AlGaN barrier layer 04 and a drain metal 10 in the drain region of the n-FETs, wherein the drain ohmic metal 10 contacts the top of the linearly graded AlGaN barrier layer 04 remaining after etching. A source structure composed of a linearly graded AlGaN barrier layer 04 and a source metal 11 in the source region of the n-FETs, wherein the other end of the source ohmic metal 11 on the upper surface of the n-FETs device away from the drain structure contacts the top of the linearly graded AlGaN barrier layer 04 remaining after etching. The n-FETs p-GaN gate structure is located between the n-FETs source structure and the drain structure, and the n-FETs gate structure includes a gate metal 12 deposited on the P-type heavily doped GaN layer 06.

[0028] In the CMOS device, the p-FETs source metal 07 is used as the high-level signal VDD terminal of the CMOS circuit, the n-FETs source metal 11 is used as the ground or low-level signal GND terminal of the CMOS circuit, the p-FETs drain metal 08 and the n-FETs drain metal 10 are connected together as the output level signal terminal of the CMOS circuit, and the p-FETs gate metal 09 and the n-FETs gate metal 12 are connected together as the input level signal terminal of the CMOS circuit. Figure 5 shown.

[0029] The working principle of a GaN-based epitaxial structure and a monolithic integrated CMOS circuit proposed by the present invention is:

[0030] The current commercial enhancement mode p-GaN gate HEMTs epitaxial structure has problems such as poor conduction characteristics of p-FETs, high current mismatch of p- / n-FETs, large device area difference, poor P / N channel coordinated regulation capability and compatibility. Figure 4 This is a schematic diagram of the device structure of the present invention. The 3DHG brought by the linear gradient AlGaN barrier layer makes the distribution of the P channel not only at the 2DHG at the heterojunction interface of the GaN channel layer and the linear gradient AlGaN barrier layer, but also distributed in the 3DHG across the linear gradient AlGaN barrier layer. Starting from improving the overall hole carrier concentration and the P channel width, an enhanced p-FETs device with high on-current density is realized. In n-FETs based on the p-GaN gate structure, the linear gradient AlGaN helps to deplete the 2DEG concentration of the N channel below the p-GaN gate, increasing the gate control ability and threshold voltage of n-FETs. Etch away part of the linear gradient AlGaN barrier layer in the gate-drain / gate-source region of n-FETs. Since the Al component of the linear gradient AlGaN barrier layer decreases linearly from bottom to top, the retained part of the high Al component helps to restore the 2DEG concentration and realize the adjustable N channel transport capacity. Thus, a CMOS inverter with small current mismatch of p- / n-FETs and high P / N channel compatibility can be realized by monolithically integrating them on the same epitaxial structure.

Claims

1. A GaN-based monolithic integrated CMOS circuit, characterized in that: The invention comprises p-FETs and n-FETs, wherein the common structure of the p-FETs and the n-FETs is a substrate (01), a group III nitride buffer layer (02), a GaN channel layer (03) and an AlGaN barrier layer (04) which are stacked in sequence in a vertical direction, wherein the Al component in the AlGaN barrier layer (04) is linearly gradient, and the gradient mode is gradually reduced from bottom to top, and the AlGaN barrier layer of the p-FETs and the AlGaN barrier layer of the n-FETs are isolated from each other; The AlGaN barrier layer of the p-FETs has a polarization-induced 3DHG distributed across it due to a gradual change in polarization intensity, a GaN channel layer (05) is provided on the upper surface of the AlGaN barrier layer, a 2DEG is formed at the interface between the AlGaN barrier layer of the p-FETs and the GaN channel layer (05), and a P-type heavily doped GaN layer (06) is provided on the upper surface of the GaN channel layer (05); the upper surfaces of the P-type heavily doped GaN layer (06) have a p-FETs source ohmic metal (07) and a p-FETs drain ohmic metal (08) at both ends of the upper surface, wherein The p-FETs drain ohmic metal (08) is located on the side close to the n-FETs; a groove gate structure is provided between the p-FETs source ohmic metal (07) and the p-FETs drain ohmic metal (08), the groove gate structure comprising a gate dielectric (13) and a first gate metal (09), the gate dielectric (13) is located in a groove formed on the upper surface of the P-type heavily doped GaN layer (06), wraps the lower part of the first gate metal (09) and contacts the p-FETs source ohmic metal (07) and the p-FETs drain ohmic metal (08) on both sides respectively; The AlGaN barrier layer structure of the n-FETs also has a GaN channel layer (05) on its upper surface, and a P-type heavily doped GaN layer (06) on its upper surface; unlike p-FETs, part of the upper layer of the AlGaN barrier layer, the GaN channel layer (05) and both sides of the P-type heavily doped GaN layer (06) of the n-FETs are etched away, leaving only a portion of the middle gate region; a 2DEG is formed at the interface between the AlGaN barrier layer and the GaN channel layer (03) of the n-FETs, and both sides of the upper surface of the AlGaN barrier layer of the n-FETs have an n-FETs drain ohmic metal (10) and an n-FETs source ohmic metal (11), wherein the n-FETs drain ohmic metal (10) is located on the side close to the p-FETs; a second gate metal (12) is provided on the upper surface of the P-type heavily doped GaN layer (06) of the n-FETs to form a planar gate; The p-FETs source ohmic metal (07) is a high-level signal port of the CMOS circuit, the n-FETs source ohmic metal (11) is a low-level signal port of the CMOS circuit, the first gate metal (09) and the second gate metal (12) are connected to form an input-level signal port of the CMOS circuit, and the p-FETs drain ohmic metal (8) and the n-FETs drain ohmic metal (10) are connected to form an output-level signal port of the CMOS circuit.

2. The GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that: The material used for the substrate (01) is one of Si, sapphire and SiC.

3. The GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that: The material used for the p-FETs source ohmic metal (07) and the p-FETs drain ohmic metal (08) is any one of Pd / Au / Ni, Ni / Au and Pd / Ni.

4. The GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that: The material used for the first gate metal (09) is any one of Ti / Au, W / Au, Ni / Au, Mo / Au and Ru.

5. The GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that: The gate dielectric (13) is any one of an oxide layer and an insulating layer.

6. The GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that: The material used for the n-FETs drain ohmic metal (10) and the n-FETs source ohmic metal (11) is any one of Ti / Au, Ti / Al / Ni / Au and Ti / Al.

7. The GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that: The contact between the second gate metal (12) and the P-type heavily doped GaN layer (06) is an ohmic contact, and the material used for the second gate metal (12) is Ni / Au.

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