Display panel and display device

Abstract

The invention relates to a display panel and a display device, and relates to the technical field of display, the display panel comprises a plurality of sub-pixels and a pixel circuit electrically connected with the sub-pixels, and the pixel circuit comprises a driving transistor, a first transistor and a second transistor; the brightness sensitivity of the first color sub-pixels is greater than that of the second color sub-pixels; the width-to-length ratio of the channel region of the first transistor corresponding to the first color sub-pixel is N1, and the width-to-length ratio of the channel region of the first transistor corresponding to the second color sub-pixel is N2, N1lt; n2; and / or, the width-to-length ratio of the channel region of the second transistor corresponding to the first color sub-pixel is M1, and the width-to-length ratio of the channel region of the second transistor corresponding to the second color sub-pixel is M2, M1lt; and M2, the brightness of the sub-pixels with different brightness sensitivities can be regulated to be approximately the same, and screen body flicker is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] An Organic Light Emitting Diode (OLED) display is an active light-emitting display device, which has the advantages of simple manufacturing process, low cost, high contrast ratio, wide viewing angle, low power consumption, etc., and has been widely used in digital products and is one of the main new display technologies. The OLED display technology uses a very thin organic material coating and a glass substrate, and the organic material is excited to emit light by electric energy, and the magnitude of the output current is controlled by a TFT (Thin Film Transistor), so as to display different brightness levels.

[0003] At present, how to improve the display brightness uniformity of display products and improve the screen flicker phenomenon has become one of the technical problems to be solved urgently. Summary of the Invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device for improving the display brightness uniformity of display products and improving screen flicker.

[0005] In a first aspect, the present disclosure provides a display panel, including: a plurality of sub-pixels and a pixel circuit electrically connected to the sub-pixels, the pixel circuit including a driving transistor, a first transistor, and a second transistor, a gate of the driving transistor being connected to a first node, a first pole being connected to a second node, and a second pole being connected to a third node; the first transistor being connected in series between a reset signal terminal and the first node, and the second transistor being connected in series between the first node and the third node;

[0006] The plurality of sub-pixels at least include a first color sub-pixel and a second color sub-pixel, and the brightness sensitivity of the first color sub-pixel is greater than that of the second color sub-pixel;

[0007] A width-to-length ratio of a channel region of the first transistor corresponding to the first color sub-pixel is N1, and a width-to-length ratio of a channel region of the first transistor corresponding to the second color sub-pixel is N2, where N1 < N2; and / or,

[0008] A width-to-length ratio of a channel region of the second transistor corresponding to the first color sub-pixel is M1, and a width-to-length ratio of a channel region of the second transistor corresponding to the second color sub-pixel is M2, where M1 < M2.

[0009] In a second aspect, the present disclosure provides a display device including the display panel as described in the first aspect.

[0010] The technical solution provided by the embodiments of the present disclosure has the following advantages compared with the prior art: by setting the width-to-length ratio of the transistor channel region in the pixel circuit corresponding to the sub-pixel with high brightness sensitivity to be smaller than the width-to-length ratio of the transistor channel region in the pixel circuit corresponding to the sub-pixel with low brightness sensitivity, the charge leakage amount of the transistor channel region corresponding to the sub-pixel with high brightness sensitivity can be relatively increased, and the charge leakage amount of the transistor channel region corresponding to the sub-pixel with high brightness sensitivity can be relatively reduced under the objective leakage state of the transistor, which is beneficial for adjusting the brightness of sub-pixels with different brightness sensitivities to be approximately the same, thereby reducing screen flicker. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0012] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0013] Figure 1 Shown is a connection schematic diagram of a driving circuit in the prior art;

[0014] Figure 2 Shown is a schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0015] Figure 3 FIG. 1 is a schematic diagram of a driving circuit provided by an embodiment of the present disclosure;

[0016] Figure 4 Shown is a circuit layout provided by an embodiment of the present disclosure;

[0017] Figure 5 Shown is a circuit layout provided by an embodiment of the present disclosure;

[0018] Figure 6 FIG. 1 is a schematic diagram of a driving circuit provided by an embodiment of the present disclosure;

[0019] Figure 7 Shown is a circuit layout provided by an embodiment of the present disclosure;

[0020] Figure 8 FIG. 1 is a schematic diagram of a transistor channel width trend provided by an embodiment of the present disclosure;

[0021] Fig. 9FIG. 1 is a schematic diagram of a transistor channel width trend provided by an embodiment of the present disclosure;

[0022] Fig.10 Shown is a schematic diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0024] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0025] Figure 1 The figure shows a connection diagram of a driving circuit in the prior art. Figure 1 The driving circuit 20' is used to drive the light-emitting element 00' to emit light. The driving circuit 20' includes a reset transistor T1', a compensation transistor T2' and a driving transistor DT'. When the reset transistor T1' is turned on, the reset signal Vref' can be transmitted to the first node D1' through the first path J1'. When the compensation transistor T2' is turned on, the compensation signal can be transmitted to the first node D1' through the second path J2'. The first node D1' and the gate of the driving transistor DT' have the same potential. Due to the characteristics of the transistor itself, leakage current will inevitably be generated after the transistor is turned off. The leakage current has a great influence on the stability of the first node D1' in the driving circuit 20'. The sub-pixels with different brightness sensitivities have different brightness changes under the same leakage current state, which can easily cause screen flickering.

[0026] A display panel usually includes multiple color sub-pixels, such as red sub-pixels, green sub-pixels and blue sub-pixels, among which the brightness sensitivity of the green sub-pixels is greater than that of the red sub-pixels, and the brightness sensitivity of the red sub-pixels is greater than that of the blue sub-pixels; the higher the brightness of the color, the more sensitive the human eye is to the brightness change (screen flicker) caused by the leakage current change.

[0027] In response to the above problems, Figure 2 FIG. 1 is a schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 3 FIG. 1 is a schematic diagram of a driving circuit provided by an embodiment of the present disclosure. Figure 4 The circuit diagram shown in FIG. Figures 2 to 4, the present disclosure provides a display panel 100, including: a plurality of sub-pixels 10 and a pixel circuit 20 electrically connected to the sub-pixels 10. The pixel circuit 20 includes a driving transistor DT, a first transistor T1, and a second transistor T2. The gate of the driving transistor DT is connected to a first node D1, the first pole is connected to a second node D2, and the second pole is connected to a third node D3; the first transistor T1 is connected in series between a reset signal terminal Vref and the first node D1, and the second transistor T2 is connected in series between the first node D1 and the third node D3;

[0028] The plurality of sub-pixels 10 at least includes a first color sub-pixel 11 and a second color sub-pixel 12, and the brightness sensitivity of the first color sub-pixel 11 is greater than that of the second color sub-pixel 12;

[0029] The aspect ratio of the channel region of the first transistor T11 corresponding to the first color sub-pixel 11 is N1, and the aspect ratio of the channel region of the first transistor T12 corresponding to the second color sub-pixel 12 is N2, where N1 < N2; and / or,

[0030] The aspect ratio of the channel region of the second transistor T21 corresponding to the first color sub-pixel 11 is M1, and the aspect ratio of the channel region of the second transistor T22 corresponding to the second color sub-pixel 12 is M2, where M1 < M2.

[0031] Specifically, the display panel 100 includes a plurality of sub-pixels 10 and a pixel circuit 20 connected to the sub-pixels 10 in a one-to-one correspondence, the pixel circuit 20 is used to drive the sub-pixels 10 to emit light; the pixel circuit 20 includes a driving transistor DT, the driving transistor DT is used to turn on and off the light-emitting element in the sub-pixel 10, the driving transistor DT includes a gate, a first electrode and a second electrode, wherein the gate of the driving transistor DT is connected to the first node D1, the first electrode of the driving transistor DT is connected to the second node D2, the second node D2 is also connected to the power supply voltage terminal PVDD, and the second electrode of the driving transistor DT is connected to the third node D3; the pixel circuit 20 also includes a first transistor T1 and a second transistor T2, the first electrode of the first transistor T1 is connected to the reset signal terminal Vref, the second electrode of the first transistor T1 is connected to the first node D1, the first transistor T1 is used to reset the first node D1, when the first transistor T1 is turned on, current flows through the first transistor T1, a flow of charge is generated in the conductive channel of the first transistor T1, and the reset signal of the reset signal terminal Vref is written to the first node D1 through the flow of charge. The second electrode of the second transistor T2 is connected to the first node D1, and the first electrode of the second transistor T2 is connected to the third node D3. The second transistor T2 is used to compensate the first node D1. When the second transistor T2 is turned on, current flows through the second transistor T2, and charge flows in the conductive channel of the second transistor T2. The voltage signal of the third node D3 is written to the first node D1 through the charge flow. The larger the width-to-length ratio of the first transistor T1 and the second transistor T2, the larger the charge leakage in the channel region of the first transistor T1 and the second transistor T2 per unit time, the larger the gate voltage change of the driving transistor DT in the same time, and the greater the brightness difference when the sub-pixels 10 of different colors emit light.

[0032] Optionally, the display panel provided in this embodiment can be a display panel using organic light emitting diode display technology, that is, an OLED display panel. The basic structure of the light emitting element of the OLED display panel includes an anode, a light emitting material and a cathode. When the power supply supplies an appropriate voltage, the holes of the anode and the electrons of the cathode will combine in the light emitting material to generate bright light. In the present disclosure, the plurality of sub-pixels 10 may include at least two sub-pixels 10 of different colors. Exemplarily, the plurality of sub-pixels 10 may include a first color sub-pixel 11 and a second color sub-pixel 12. The sub-pixel 10 may include a light-emitting element, the light-emitting element includes the aforementioned light-emitting material, and the brightness sensitivity of the light-emitting materials of the different color sub-pixels 10 may be different, wherein the brightness sensitivity of the first color sub-pixel 11 is greater than the brightness sensitivity of the second color sub-pixel 12. Exemplarily, the first color sub-pixel 11 may be a green sub-pixel, the second color sub-pixel 12 may be a red sub-pixel, and the brightness sensitivity of the green sub-pixel is greater than the brightness sensitivity of the red sub-pixel, or the first color sub-pixel 11 may be a red sub-pixel, the second color sub-pixel 12 may be a blue sub-pixel, and the brightness sensitivity of the red sub-pixel is greater than the brightness sensitivity of the blue sub-pixel, or the first color sub-pixel 11 may be a green sub-pixel, the second color sub-pixel 12 may be a blue sub-pixel, and the brightness sensitivity of the green sub-pixel is greater than the brightness sensitivity of the blue sub-pixel.

[0033] In an optional embodiment provided by the present disclosure, the width-to-length ratio of the channel region of the first transistor T1 and the second transistor T2 of the pixel circuit 20 is negatively correlated with the brightness sensitivity of the sub-pixel 10 corresponding to the pixel circuit 20, that is, the higher the brightness sensitivity of the sub-pixel 10, the smaller the width-to-length ratio of the channel region of the first transistor T1 in the pixel circuit 20 electrically connected to the sub-pixel 10, and the smaller the width-to-length ratio of the channel region of the second transistor T2 in the pixel circuit 20 electrically connected to the sub-pixel 10; the lower the brightness sensitivity of the sub-pixel 10, the larger the width-to-length ratio of the channel region of the first transistor T1 in the pixel circuit 20 electrically connected to the sub-pixel 10, and the larger the width-to-length ratio of the channel region of the second transistor T2 in the pixel circuit 20 electrically connected to the sub-pixel 10; in an optional embodiment provided by the present disclosure, for a first color sub-pixel 11 and a second color sub-pixel 12 with different brightness sensitivities, wherein the brightness sensitivity of the first color sub-pixel 11 is greater than the brightness sensitivity of the second color sub-pixel 12, the first color sub-pixel 11 is greater than the brightness sensitivity of the second color sub-pixel 12, The width-to-length ratio N1 of the channel region of the first transistor T11 corresponding to the color sub-pixel 11 is smaller than the width-to-length ratio N2 of the channel region of the first transistor T12 corresponding to the second color sub-pixel 12; in another optional embodiment provided in the present disclosure, for the first color sub-pixel 11 and the second color sub-pixel 12 with different brightness sensitivities, the width-to-length ratio M1 of the channel region of the second transistor T21 corresponding to the first color sub-pixel 11 is smaller than the width-to-length ratio M2 of the channel region of the second transistor T22 corresponding to the second color sub-pixel 12; in another optional embodiment provided in the present disclosure, for the first color sub-pixel 11 and the second color sub-pixel 12 with different brightness sensitivities, the width-to-length ratio N1 of the channel region of the first transistor T11 corresponding to the first color sub-pixel 11 is smaller than the width-to-length ratio N2 of the channel region of the first transistor T12 corresponding to the second color sub-pixel 12, and the width-to-length ratio M1 of the channel region of the second transistor T21 corresponding to the first color sub-pixel 11 is smaller than the width-to-length ratio M2 of the channel region of the second transistor T22 corresponding to the second color sub-pixel 12.

[0034] The brightness sensitivity of the first color sub-pixel 11 is greater than that of the second color sub-pixel 12. The amount of electric charge flowing through the channel region of the first transistor T11 in the pixel circuit 20 corresponding to the first color sub-pixel 11 per unit time is less than the amount of electric charge flowing through the channel region of the first transistor T12 in the pixel circuit 20 corresponding to the second color sub-pixel 12 per unit time. That is, the charge leakage amount of the channel region of the first transistor T11 in the pixel circuit 20 corresponding to the first color sub-pixel 11 is less than the charge leakage amount of the channel region of the first transistor T12 in the pixel circuit 20 corresponding to the second color sub-pixel 12, making the brightness of the first color sub-pixel 11 approximately the same as that of the second color sub-pixel 12 and reducing screen flicker. Similarly, the amount of electric charge flowing through the channel region of the second transistor T21 in the pixel circuit 20 corresponding to the first color sub-pixel 11 per unit time is less than the amount of electric charge flowing through the channel region of the second transistor T22 in the pixel circuit 20 corresponding to the second color sub-pixel 12 per unit time. That is, the charge leakage amount of the channel region of the second transistor T21 in the pixel circuit 20 corresponding to the first color sub-pixel 11 is less than the charge leakage amount of the channel region of the second transistor T22 in the pixel circuit 20 corresponding to the second color sub-pixel 12, making the brightness of the first color sub-pixel 11 approximately the same as that of the second color sub-pixel 12 and reducing screen flicker.

[0035] For a display panel 100 provided by the present disclosure, the aspect ratio N1 of the channel region of the first transistor T11 corresponding to the first color sub-pixel 11 is equal to the aspect ratio M1 of the channel region of the second transistor T21 corresponding to the first color sub-pixel 11; the aspect ratio N2 of the channel region of the first transistor T12 corresponding to the second color sub-pixel 12 is equal to the aspect ratio M2 of the channel region of the second transistor T22 corresponding to the second color sub-pixel 12, where N1 < N2; and / or, M1 < M2.

[0036] Specifically, in an optional embodiment provided by the present disclosure, the aspect ratio N1 of the channel region of the first transistor T11 corresponding to the first color sub-pixel 11 is less than the aspect ratio N2 of the channel region of the first transistor T12 corresponding to the second color sub-pixel 12, and the aspect ratio M1 of the channel region of the second transistor T21 corresponding to the first color sub-pixel 11 is less than the aspect ratio M2 of the channel region of the second transistor T22 corresponding to the second color sub-pixel 12. Wherein, the aspect ratio N1 of the channel region of the first transistor T11 corresponding to the first color sub-pixel 11 is equal to the aspect ratio M1 of the channel region of the second transistor T21 corresponding to the first color sub-pixel 11, and the aspect ratio N2 of the channel region of the first transistor T12 corresponding to the second color sub-pixel 12 is equal to the aspect ratio M2 of the channel region of the second transistor T22 corresponding to the second color sub-pixel 12.

[0037] That is to say, the aspect ratios of the channel regions of the first transistors T1 in the sub-pixels 10 of different colors are different, and the aspect ratios of the channel regions of the second transistors T2 in the sub-pixels 10 of different colors are different. That is, the aspect ratio of the channel region of the transistor in the sub-pixel 10 with high brightness sensitivity is smaller than the aspect ratio of the channel region of the transistor in the sub-pixel 10 with low brightness sensitivity. The aspect ratio of the channel region of the first transistor T1 in the sub-pixel 10 of the same color may be the same as the aspect ratio of the channel region of the second transistor T2, that is, the aspect ratio of the channel region of the first transistor T1 in the sub-pixel 10 with the same brightness sensitivity may be equal to the aspect ratio of the channel region of the second transistor T2. In this way, on the premise that the aspect ratio of the channel region of the transistor in the sub-pixel 10 with high brightness sensitivity is smaller than the aspect ratio of the channel region of the transistor in the sub-pixel 10 with low brightness sensitivity, the aspect ratio of the channel region of the first transistor T1 corresponding to the same sub-pixel 10 can be designed to be equal to the aspect ratio of the channel region of the second transistor T2 corresponding to the same sub-pixel 10, providing an alternative design solution for making the brightness of the sub-pixels 10 of different colors as identical as possible under the objective leakage current state.

[0038] A display panel 100 provided by the present disclosure, the aspect ratio N1 of the channel region of the first transistor T11 corresponding to the first color sub-pixel 11 is not equal to the aspect ratio M1 of the channel region of the second transistor T21 corresponding to the first color sub-pixel 11; the aspect ratio N2 of the channel region of the first transistor T12 corresponding to the second color sub-pixel 12 is not equal to the aspect ratio M2 of the channel region of the second transistor T22 corresponding to the second color sub-pixel 12, where N1 < N2; and / or, M1 < M2.

[0039] Specifically, in an optional embodiment provided by the present disclosure, the aspect ratio N1 of the channel region of the first transistor T11 corresponding to the first color sub-pixel 11 is smaller than the aspect ratio N2 of the channel region of the first transistor T12 corresponding to the second color sub-pixel 12, and the aspect ratio M1 of the channel region of the second transistor T21 corresponding to the first color sub-pixel 11 is smaller than the aspect ratio M2 of the channel region of the second transistor T22 corresponding to the second color sub-pixel 12, where N1 ≠ M1, and N2 may be equal to M2.

[0040] In another optional embodiment provided by the present disclosure, the aspect ratio N1 of the channel region of the first transistor T11 corresponding to the first color sub-pixel 11 is smaller than the aspect ratio N2 of the channel region of the first transistor T12 corresponding to the second color sub-pixel 12, and the aspect ratio M1 of the channel region of the second transistor T21 corresponding to the first color sub-pixel 11 is smaller than the aspect ratio M2 of the channel region of the second transistor T22 corresponding to the second color sub-pixel 12, where N2 ≠ M2, and N1 may be equal to M1.

[0041] In another optional embodiment provided in the present disclosure, a width-to-length ratio N1 of a channel region of a first transistor T11 corresponding to a first color sub-pixel 11 is smaller than a width-to-length ratio N2 of a channel region of a first transistor T12 corresponding to a second color sub-pixel 12, and a width-to-length ratio M1 of a channel region of a second transistor T21 corresponding to a first color sub-pixel 11 is smaller than a width-to-length ratio M2 of a channel region of a second transistor T22 corresponding to a second color sub-pixel 12, wherein N1≠M1, and N2≠M2.

[0042] That is, the width-to-length ratio of the channel region of the first transistor T1 corresponding to the sub-pixel 10 with high brightness sensitivity is smaller than the width-to-length ratio of the channel region of the first transistor T1 corresponding to the sub-pixel 10 with low brightness sensitivity, and the width-to-length ratio of the channel region of the second transistor T2 corresponding to the sub-pixel 10 with high brightness sensitivity is smaller than the width-to-length ratio of the channel region of the second transistor T2 corresponding to the sub-pixel 10 with low brightness sensitivity. The width-to-length ratio of the channel region of the first transistor T1 and the width-to-length ratio of the channel region of the second transistor T2 in the sub-pixel 10 of the same color may be different. That is, the width-to-length ratio of the channel region of the first transistor T1 corresponding to the sub-pixel 10 with the same brightness sensitivity may be smaller than the width-to-length ratio of the channel region of the second transistor T2. The width-to-length ratio of the channel region may be unequal to the width-to-length ratio of the channel region of the corresponding second transistor T2 in the sub-pixel 10 of the same brightness sensitivity. Thus, under the premise that the width-to-length ratio of the transistor channel region in the sub-pixel 10 with high brightness sensitivity is smaller than the width-to-length ratio of the transistor channel region in the sub-pixel 10 with low brightness sensitivity, the width-to-length ratio of the channel region of the first transistor T1 corresponding to the same sub-pixel 10 is designed to be unequal to the width-to-length ratio of the channel region of the corresponding second transistor T2 in the same sub-pixel 10, thereby providing a variety of design options for achieving as close as possible brightness of sub-pixels 10 of different colors under an objective leakage current state.

[0043] Figure 5 The following is a circuit diagram provided by an embodiment of the present disclosure. Figures 1 to 5 The present disclosure provides a display panel 100 , wherein at least one of the first transistor T1 and the second transistor T2 includes a channel region of a non-rectangular structure.

[0044] Specifically, the first transistor T1 includes a channel region with a non-rectangular structure, and the second transistor T2 includes a channel region with a rectangular structure, or the first transistor T1 includes a channel region with a rectangular structure, and the second transistor T2 includes a channel region with a non-rectangular structure, or both the first transistor T1 and the second transistor T2 include a channel region with a non-rectangular structure, wherein the channel region with a non-rectangular structure means that the width of the channel region along the current direction is not a fixed value. In this way, by setting a channel region with a non-rectangular structure, the amount of charge flowing through the channel region of the transistor can be changed, thereby changing the charge leakage amount of the transistor, so as to facilitate adjusting the brightness of sub-pixels 10 with different brightness sensitivities to be approximately the same.

[0045] Please continue to refer to Figures 1 to 5 In a display panel 100 provided by the present disclosure, the length of the channel region of the first transistor T1 is equal to the length of the channel region of the second transistor T2; the width of the channel region of the first transistor T1 tends to decrease along the current direction; and / or the width of the channel region of the second transistor T2 tends to decrease along the current direction.

[0046] For more information, see Figure 5 and Figure 8 , the width-to-length ratio of the channel region of the first transistor T1 in the sub-pixels 10 of different brightness sensitivities is different, the width-to-length ratio of the channel region of the second transistor T2 in the sub-pixels 10 of different brightness sensitivities is different, and the width-to-length ratio of the channel region of the first transistor T1 and the second transistor T2 in the sub-pixels 10 of the same brightness sensitivity may be the same or different. In an optional embodiment provided by the present disclosure, when the width-to-length ratio of the channel region of the first transistor T1 and the second transistor T2 in the sub-pixels 10 of the same brightness sensitivity is the same, the length of the channel region of the first transistor T1 and the length of the channel region of the second transistor T2 in the sub-pixels 10 of the same brightness sensitivity are equal, that is, the width of the channel region of the first transistor T1 and the channel region of the second transistor T2 in the sub-pixels 10 of the same brightness sensitivity are equal. The widths of the first transistor T1 and the second transistor T2 are equal. At this time, the width of the channel region of the first transistor T1 shows a decreasing trend along the current direction (the direction of the one-way arrow in the figure is the current direction), and the width of the channel region of the second transistor T2 shows a decreasing trend along the current direction. The decreasing trend of the width of the channel region of the first transistor T1 is the same as the decreasing trend of the width of the channel region of the second transistor T2. In this way, when the width-to-length ratios of the transistor channel regions at the same position in sub-pixels of different colors are the same, the leakage currents of the first transistor T1 and the second transistor T2 in sub-pixels of different colors can be reduced by setting the channel region width of the first transistor T1 to a decreasing trend and setting the channel region width of the second transistor T2 to a decreasing trend, thereby reducing the influence on the stability of the first node D1 and improving the brightness uniformity of the display panel 100.

[0047] In another optional embodiment provided by the present disclosure, when the width-to-length ratios of the channel regions of the first transistor T1 and the second transistor T2 in the sub-pixel 10 of the same brightness sensitivity are different, the length of the channel region of the first transistor T1 and the length of the channel region of the second transistor T2 in the sub-pixel 10 of the same brightness sensitivity are equal, and the width of the channel region of the first transistor T1 and the width of the channel region of the second transistor T2 in the sub-pixel 10 of the same brightness sensitivity are not equal. At this time, the width of the channel region of the first transistor T1 tends to decrease along the current direction, the amount of charge flowing through the channel region of the first transistor T1 decreases, and the first transistor T1 decreases. The charge leakage of the transistor T1 is reduced, the width of the channel region of the second transistor T2 remains unchanged along the current direction, the amount of charge flowing through the channel region of the second transistor T2 remains unchanged, and the charge leakage of the second transistor T2 remains unchanged. In this way, when the width-to-length ratios of the transistor channel regions at the same position in sub-pixels of different colors are different, the channel region width of the first transistor T1 can be set to a decreasing trend, and the channel region width of the second transistor T2 can be set to a constant value to reduce the leakage of the first transistor T1 in sub-pixels of different colors 10, thereby reducing the impact on the stability of the first node D1 and improving the brightness uniformity of the display panel 100.

[0048] In another optional embodiment provided by the present disclosure, when the width-to-length ratios of the channel regions of the first transistor T1 and the second transistor T2 in the sub-pixel 10 of the same brightness sensitivity are different, the length of the channel region of the first transistor T1 and the length of the channel region of the second transistor T2 in the sub-pixel 10 of the same brightness sensitivity are equal, and the width of the channel region of the first transistor T1 and the width of the channel region of the second transistor T2 in the sub-pixel 10 of the same brightness sensitivity are not equal. At this time, the width of the channel region of the first transistor T1 tends to decrease along the current direction, the amount of charge flowing through the channel region of the first transistor T1 decreases, and the charge leakage of the first transistor T1 increases. As the flow rate decreases, the width of the channel region of the second transistor T2 tends to decrease along the current direction, the amount of charge flowing through the channel region of the second transistor T2 decreases, and the charge leakage of the second transistor T2 decreases. In this way, when the width-to-length ratios of the transistor channel regions at the same position in sub-pixels of different colors are different, the leakage currents of the first transistor T1 and the second transistor T2 in sub-pixels 10 of different colors can be reduced by setting the channel region width of the first transistor T1 to a decreasing trend and setting the channel region width of the second transistor T2 to a decreasing trend, thereby reducing the influence on the stability of the first node D1 and improving the brightness uniformity of the display panel 100.

[0049] Thus, by setting the width variation trend of the channel regions of the first transistor T1 and the second transistor T2, the leakage current of the first transistor T1 and the second transistor T2 can be flexibly adjusted, which is beneficial for adjusting the brightness of sub-pixels 10 with different brightness sensitivities to be approximately the same.

[0050] Please continue to refer to Figures 1 to 5 In a display panel 100 provided by the present disclosure, at least one of the first transistor T1 and the second transistor T2 is a dual-gate transistor, and the dual-gate transistor is a low-temperature polysilicon thin-film transistor.

[0051] It should be noted that Figure 5 Only the case where the first transistor T1 and the second transistor T2 are both dual-gate transistors is shown, which does not represent the number and arrangement of dual-gate transistors in the actual circuit layout. It can be understood that the first transistor T1 can be set as a dual-gate transistor and the second transistor T2 can be a non-dual-gate transistor, or the first transistor T1 can be set as a non-dual-gate transistor and the second transistor T2 can be a dual-gate transistor. The specific setting can be based on actual needs and will not be listed here. It should be noted that Figures 3 to 5 The transistor represented is a planar dual-gate structure, that is, the two gates of the transistor do not overlap. Compared with a single-gate transistor, a dual-gate transistor has more channel regions, more areas where the width-to-length ratio of the channel region can be adjusted, smaller leakage current, and less impact on the stability of the first node D1. In this way, when the first transistor T1 or the second transistor T2 adopts a dual-gate transistor, the width-to-length ratio of the dual-gate transistor channel region in sub-pixels of different colors is relatively designed, which is conducive to fine-tuning the transistor leakage and improving the uniformity of the panel display.

[0052] Please refer to Figure 5 The present disclosure provides a display panel 100. Optionally, when the first transistor T1 is a dual-gate transistor, the first transistor T1 includes a first channel region Q1 and a second channel region Q2 arranged along a current direction. Along the current direction (the direction of the unidirectional arrow in the figure), a width H2 of the second channel region Q2 is less than or equal to a width H1 of the first channel region Q1, and the width H1 of the first channel region Q1 tends to decrease; the width H2 of the second channel region Q2 is consistent, or the width H2 of the second channel region Q2 tends to decrease.

[0053] Specifically, in an optional embodiment provided by the present disclosure, along the current direction, the width H1 of the first channel region Q1 shows a decreasing trend, and the width H2 of the second channel region Q2 remains unchanged. At this time, the width H2 of the second channel region Q2 may be less than the minimum width of the first channel region Q1, or the width H2 of the second channel region Q2 may be equal to the minimum width of the first channel region Q1; in another optional embodiment provided by the present disclosure, along the current direction, the width H1 of the first channel region Q1 shows a decreasing trend, and the width H2 of the second channel region Q2 shows a decreasing trend. At this time, the maximum width of the second channel region Q2 may be less than the minimum width of the first channel region Q1, or the maximum width of the first channel region Q2 may be equal to the minimum width of the first channel region Q1. In this way, by setting the relative relationship and change trend of the widths of the two channel regions of the dual-gate transistor, the leakage current of the dual-gate transistor can be reduced, so that the brightness of the sub-pixels 10 with different brightness sensitivities can be adjusted to be approximately the same, thereby reducing the occurrence of screen flickering.

[0054] Optionally, when the second transistor T2 is a dual-gate transistor, the second transistor T2 includes a third channel region Q3 and a fourth channel region Q4 arranged along the current direction, and along the current direction (the direction of the unidirectional arrow in the figure), the width H4 of the fourth channel region Q4 is less than or equal to the width H3 of the third channel region Q3, and the width H3 of the third channel region Q3 tends to decrease; the width H4 of the fourth channel region Q4 is consistent, or the width H4 of the fourth channel region Q4 tends to decrease.

[0055] Specifically, in an optional embodiment provided by the present disclosure, along the current direction, the width H3 of the third channel region Q3 shows a decreasing trend, and the width H4 of the fourth channel region Q4 remains unchanged. At this time, the width H4 of the fourth channel region Q4 can be less than the minimum width of the third channel region Q3, or the width H4 of the fourth channel region Q4 can be equal to the minimum width of the third channel region Q3; in another optional embodiment provided by the present disclosure, along the current direction, the width H3 of the third channel region Q3 shows a decreasing trend, and the width H4 of the fourth channel region Q4 shows a decreasing trend. At this time, the maximum width of the fourth channel region Q4 can be less than the minimum width of the third channel region Q3, or the maximum width of the fourth channel region Q4 can be equal to the minimum width of the third channel region Q3. In this way, by setting the relative relationship and change trend of the widths of the two channel regions of the dual-gate transistor, the leakage current of the dual-gate transistor can be reduced, so that the brightness of the sub-pixels 10 with different brightness sensitivities can be adjusted to be approximately the same, thereby reducing the occurrence of screen flickering.

[0056] It should be noted that Figure 5Only the case where the width H1 of the first channel region Q1 and the width H2 of the second channel region Q2 in the first transistor T1 both show a decreasing trend, and the case where the width H3 of the third channel region Q3 and the width H4 of the fourth channel region Q4 in the second transistor T2 both show a decreasing trend are shown. It can be understood that the width H1 of the first channel region Q1 in the first transistor T1 can also be set to show a decreasing trend, and the width H2 of the second channel region Q2 remains unchanged, and the width H3 of the third channel region Q3 in the second transistor T2 can also be set to show a decreasing trend, and the width H4 of the fourth channel region Q4 remains unchanged.

[0057] Figure 6 FIG. 1 is a schematic diagram of a driving circuit provided by an embodiment of the present disclosure. Figure 7 FIG. 1 is a circuit diagram provided by an embodiment of the present disclosure. Figure 8 FIG. 1 is a schematic diagram of a transistor channel width trend provided by an embodiment of the present disclosure. Figures 1 to 8 In a display panel 100 provided by the present disclosure, at least one of the first transistor T1 and the second transistor T2 is a dual-gate transistor, and the dual-gate transistor is an indium gallium zinc oxide thin film transistor.

[0058] Specifically, in an optional embodiment provided by the present disclosure, the first transistor T1 is an indium gallium zinc oxide thin film transistor, which is a dual-gate transistor, and the second transistor T2 is a non-indium gallium zinc oxide thin film transistor; in another optional embodiment provided by the present disclosure, the first transistor T1 and the second transistor T2 are both indium gallium zinc oxide thin film transistors, which are dual-gate transistors. It should be noted that Figures 6 to 8 The dual-gate transistor shown in the figure is a vertical dual-gate structure, that is, the dual-gate transistor shown in the figure includes a top gate and a bottom gate, and the top gate and the bottom gate are respectively located on both sides of the active layer of the transistor, and overlap with the active layer to form a channel; thus, the indium gallium zinc oxide thin film transistor includes two channel regions. Compared with ordinary single-gate transistors, the adjustable area of ​​the channel region width-to-length ratio is more, and the adjustable accuracy of the transistor leakage is greater, which is conducive to fine-tuning the transistor leakage and is beneficial to improving the uniformity of the panel display.

[0059] The present disclosure provides a display panel 100 , in which the width of the channel region of the dual-gate transistor decreases along the current direction.

[0060] Optionally, when the first transistor T1 is an indium gallium zinc oxide thin film transistor, the first transistor T1 includes a fifth channel region Q5 and a seventh channel region Q7. The fifth channel region Q5 and the seventh channel region Q7 overlap in a direction perpendicular to the active layer. Along the current direction, the width H5 of the fifth channel region Q5 and the seventh channel region Q7 shows a decreasing trend. Optionally, when the second transistor T2 is an indium gallium zinc oxide thin film transistor, the second transistor T2 includes a sixth channel region Q6 and an eighth channel region Q8. The sixth channel region Q6 and the eighth channel region Q8 overlap in a direction perpendicular to the active layer. Along the current direction, the width H6 of the sixth channel region Q6 and the eighth channel region Q8 shows a decreasing trend. In this way, by setting the variation trend of the widths of the dual-gate transistor channel regions, the leakage current of the dual-gate transistor can be reduced, facilitating the adjustment of the brightness of the sub-pixels 10 with different brightness sensitivities to be approximately the same and reducing the occurrence of the flash screen phenomenon.

[0061] It should be noted that Figure 8 only shows the case where the widths H5 of the fifth channel region Q5 and the seventh channel region Q7 in the first transistor T1 and the widths H6 of the sixth channel region Q6 and the eighth channel region Q8 in the second transistor T2 both show a decreasing trend. It can be understood that the width H5 of the fifth channel region Q5 and the seventh channel region Q7 in the first transistor T1 can be set to show a decreasing trend, and the width H6 of the sixth channel region Q6 and the eighth channel region Q8 in the second transistor T2 can be set to a fixed value, specifically according to actual needs.

[0062] Please continue to refer to Figures 1 to 8 , a display panel 100 provided by the present disclosure, at least one of the first transistor T1 and the second transistor T2 includes a channel region with a rectangular structure, at least one of the first transistor T1 and the second transistor T2 is a dual-gate transistor, and the dual-gate transistor includes a first channel region and a second channel region.

[0063] Specifically, the aspect ratio of the width to length of the channel region of the first transistor T1 corresponding to the first color sub-pixel 11 is N1, and the aspect ratio of the width to length of the channel region of the first transistor T1 corresponding to the second color sub-pixel 12 is N2, where N1 < N2; the aspect ratio of the width to length of the channel region of the second transistor T2 corresponding to the first color sub-pixel 11 is M1, and the aspect ratio of the width to length of the channel region of the second transistor T2 corresponding to the second color sub-pixel is M2, where M1 < M2. The brightness sensitivity of the first color sub-pixel 11 is greater than the brightness sensitivity of the second color sub-pixel 12.

[0064] In an optional embodiment provided by the present disclosure, the first transistor T1 is a dual-gate transistor, and the second transistor T2 is a non-dual-gate transistor, wherein the first transistor T1 includes a channel region of a rectangular structure, and the second transistor T2 includes a channel region of a non-rectangular structure; or, the first transistor T1 includes a channel region of a non-rectangular structure, and the second transistor T2 includes a channel region of a rectangular structure; or, the first transistor T1 includes a channel region of a rectangular structure, and the second transistor T2 includes a channel region of a rectangular structure.

[0065] In another optional embodiment provided by the present disclosure, the first transistor T1 is a non-dual-gate transistor, and the second transistor T2 is a dual-gate transistor, wherein the first transistor T1 includes a channel region of a non-rectangular structure, and the second transistor T2 includes a channel region of a rectangular structure; or, the first transistor T1 includes a channel region of a rectangular structure, and the second transistor T2 includes a channel region of a non-rectangular structure; or, the first transistor T1 includes a channel region of a rectangular structure, and the second transistor T2 includes a channel region of a rectangular structure.

[0066] In another optional embodiment provided in the present disclosure, the first transistor T1 and the second transistor T2 are both dual-gate transistors, wherein the first transistor T1 includes a channel region of a rectangular structure, and the second transistor T2 includes a channel region of a non-rectangular structure; or, the first transistor T1 includes a channel region of a non-rectangular structure, and the second transistor T2 includes a channel region of a rectangular structure; or, the first transistor T1 includes a channel region of a rectangular structure, and the second transistor T2 includes a channel region of a rectangular structure.

[0067] In this way, by differentially designing the width-to-length ratio of the channel region of transistors in sub-pixels of different colors, the first transistor T1 and the second transistor T2 are differentially designed according to the type of transistor and the shape of the channel region, providing a variety of design options for reducing screen flicker.

[0068] Fig. 9 FIG. 1 is a schematic diagram of a transistor channel width trend provided by an embodiment of the present disclosure. Please refer to FIG. Fig. 9 In a display panel 100 provided by the present disclosure, in the same color sub-pixel 10, the width H7 of the first channel region Q9 in the first transistor T1 is different from the width H8 of the second channel region Q10, and / or the width H9 of the first channel region Q11 in the second transistor T2 is different from the width H10 of the second channel region Q12.

[0069] Specifically, in an optional embodiment provided by the present disclosure, when the first transistor T1 in the same color sub-pixel 10 is a dual-gate transistor and the second transistor T2 is a non-dual-gate transistor, the width H7 of the first channel region Q9 in the first transistor T1 is different from the width H8 of the second channel region Q10.

[0070] In another optional embodiment provided by the present disclosure, when the first transistor T1 in the same color sub-pixel 10 is a non-dual-gate transistor and the second transistor T2 is a dual-gate transistor, the width H9 of the first channel region Q11 in the second transistor T2 is different from the width H10 of the second channel region Q12.

[0071] In another optional embodiment provided by the present disclosure, when the first transistor T1 in the same color sub-pixel 10 is a dual-gate transistor and the second transistor T2 is a dual-gate transistor, the width H7 of the first channel region Q9 in the first transistor T1 is different from the width H8 of the second channel region Q10, and the width H9 of the first channel region Q11 in the second transistor T2 is different from the width H10 of the second channel region Q12.

[0072] In this way, on the basis of the differentiated design of the transistor channel area width-to-length ratio corresponding to sub-pixels with different brightness sensitivities, the channel area width of the transistor in the same color sub-pixel can be further differentiated, providing more options in transistor process manufacturing to reduce screen flicker and reduce leakage.

[0073] It should be noted that Fig. 9 It is only shown that the first transistor T1 and the second transistor T2 are both dual-gate transistors. It can be understood that the first transistor T1 can also be a non-dual-gate transistor and the second transistor T2 can be a dual-gate transistor, or the first transistor T1 can be a dual-gate transistor and the second transistor T2 can be a non-dual-gate transistor. These are not listed here one by one.

[0074] Please continue to refer to Fig. 9 In a display panel 100 provided by the present disclosure, in a same color sub-pixel 10, a first transistor T1 and a second transistor T2 are both dual-gate transistors, and a difference in width between a first channel region and a second channel region in the dual-gate transistor close to a first node D1 is greater than a difference in width between the first channel region and the second channel region in the dual-gate transistor far from the first node D1.

[0075] For more information, see Fig. 9In an optional embodiment provided by the present disclosure, in the same color sub-pixel 10, the first transistor T1 and the second transistor T2 are both dual-gate transistors, the first transistor T1 is close to the first node D1 relative to the second transistor T2, and the second transistor T2 is far away from the first node D1 relative to the first transistor T1, the first channel region Q9 and the second channel region Q10 of the first transistor T1 are rectangular structures, the width H7 of the first channel region Q9 of the first transistor T1 is different from the width H8 of the second channel region Q10, the first channel region Q11 and the second channel region Q12 of the second transistor T2 are rectangular structures, the width H9 of the first channel region Q11 of the second transistor T2 is different from the width H10 of the second channel region Q12, wherein the difference |H7-H8| between the width H7 of the first channel region Q9 and the width H8 of the second channel region Q10 in the first transistor T1 is greater than the difference |H9-H10| between the width H9 of the first channel region Q11 and the width H10 of the second channel region Q12 in the second transistor T2.

[0076] In another optional embodiment provided by the present disclosure, in the same color sub-pixel 10, the first transistor T1 and the second transistor T2 are both dual-gate transistors, the first transistor T1 is far away from the first node D1 relative to the second transistor T2, and the second transistor T2 is close to the first node D1 relative to the first transistor T1, the first channel region Q9 and the second channel region Q10 of the first transistor T1 are rectangular structures, the width H7 of the first channel region Q9 of the first transistor T1 is different from the width H8 of the second channel region Q10, the first channel region Q11 and the second channel region Q12 of the second transistor T2 are rectangular structures, the width H9 of the first channel region Q11 of the second transistor T2 is different from the width H10 of the second channel region Q12, wherein the difference |H7-H8| between the width H7 of the first channel region Q9 and the width H8 of the second channel region Q10 in the first transistor T1 is smaller than the difference |H9-H10| between the width H9 of the first channel region Q11 and the width H10 of the second channel region Q12 in the second transistor T2.

[0077] In this way, in the same color sub-pixel 10, by setting the width difference of the channel region in the dual-gate transistor relatively close to the first node D1 to be larger, the effects of the charge leakage of the first transistor T1 and the second transistor T2 on the first node D1 can be made as similar as possible, thereby improving the stability of the first node D1 and reducing screen flicker.

[0078] Fig.10The figure shows a schematic diagram of a display device provided by an embodiment of the present disclosure. The present disclosure provides a display device 200, including the display panel 100 as described in the above embodiment. The display device 200 provided by the embodiment of the present disclosure can be any electronic device with a display function, such as a touch screen, a mobile phone, a tablet computer, a laptop computer, an e-book, or a television. The display device 200 provided by the embodiment of the present disclosure has the beneficial effects of the display panel provided by the embodiment of the present disclosure. For details, please refer to the specific description of the display panel in the above embodiments, which will not be repeated in this embodiment.

[0079] Understandably, Fig.10 Only a rounded rectangular structure is used as an example to illustrate one shape of the display device 200. In some other embodiments of the present disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and the present disclosure does not specifically limit this.

[0080] In summary, the present disclosure provides a display panel and a display device. By setting the width-to-length ratio of the transistor channel region in the pixel circuit corresponding to the sub-pixel with high brightness sensitivity to be smaller than the width-to-length ratio of the transistor channel region in the pixel circuit corresponding to the sub-pixel with low brightness sensitivity, the charge leakage amount of the channel region of the first transistor in the pixel circuit corresponding to the first sub-pixel is smaller than the charge leakage amount of the channel region of the first transistor in the pixel circuit corresponding to the second sub-pixel, which is beneficial for adjusting the brightness of the first sub-pixel and the brightness of the second sub-pixel to be approximately the same, thereby reducing screen flicker. By designing the width-to-length ratio of the channel region of the first transistor corresponding to the same sub-pixel to be the same as the width-to-length ratio of the channel region of the second transistor corresponding to the same sub-pixel, on the premise that the width-to-length ratio of the channel region of the transistor in the sub-pixel with high brightness sensitivity is smaller than the width-to-length ratio of the channel region of the transistor in the sub-pixel with low brightness sensitivity, The width-to-length ratio of the body transistor channel region is equal or unequal, which can provide a variety of optional design schemes to make the brightness of sub-pixels of different colors as similar as possible under the objective leakage state of the transistor; by setting the channel region of the non-rectangular structure, the amount of charge flowing through the channel region of the transistor can be changed, thereby changing the charge leakage amount of the transistor, which is convenient for adjusting the brightness of sub-pixels with different brightness sensitivities to be approximately the same; by setting the width change trend of the channel region of the first transistor and the second transistor, the leakage current of the first transistor and the second transistor can be flexibly adjusted, which is conducive to adjusting the brightness of sub-pixels with different brightness sensitivities to be approximately the same; by setting the relative relationship and change trend of the width of the channel region of the dual-gate transistor, the leakage current of the dual-gate transistor can be reduced, which is convenient for adjusting the brightness of sub-pixels with different brightness sensitivities to be approximately the same, thereby reducing the occurrence of screen flickering.

[0081] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0082] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: Comprising: A plurality of sub-pixels and a pixel circuit electrically connected to the sub-pixels. The pixel circuit includes a driving transistor, a first transistor, and a second transistor. The gate of the driving transistor is connected to a first node, the first pole is connected to a second node, and the second pole is connected to a third node; the first transistor is connected in series between a reset signal terminal and the first node, and the second transistor is connected in series between the first node and the third node; A plurality of the sub-pixels at least include a first color sub-pixel and a second color sub-pixel, and the brightness sensitivity of the first color sub-pixel is greater than that of the second color sub-pixel; The width-to-length ratio of the channel region of the first transistor corresponding to the first color sub-pixel is N1, and the width-to-length ratio of the channel region of the first transistor corresponding to the second color sub-pixel is N2, where N1 < N2; and / or, The width-to-length ratio of the channel region of the second transistor corresponding to the first color sub-pixel is M1, and the width-to-length ratio of the channel region of the second transistor corresponding to the second color sub-pixel is M2, where M1 < M2.

2. The display panel according to claim 1, characterized in that: The width-to-length ratio N1 of the channel region of the first transistor corresponding to the first color sub-pixel is equal to the width-to-length ratio M1 of the channel region of the second transistor corresponding to the first color sub-pixel; the width-to-length ratio N2 of the channel region of the first transistor corresponding to the second color sub-pixel is equal to the width-to-length ratio M2 of the channel region of the second transistor corresponding to the second color sub-pixel, where N1 < N2; and / or, M1 < M2.

3. The display panel according to claim 1, characterized in that: The width-to-length ratio N1 of the channel region of the first transistor corresponding to the first color sub-pixel is not equal to the width-to-length ratio M1 of the channel region of the second transistor corresponding to the first color sub-pixel; the width-to-length ratio N2 of the channel region of the first transistor corresponding to the second color sub-pixel is not equal to the width-to-length ratio M2 of the channel region of the second transistor corresponding to the second color sub-pixel, where N1 < N2; and / or, M1 < M2.

4. The display panel according to claim 1, characterized in that: At least one of the first transistor and the second transistor includes a channel region with a non-rectangular structure.

5. The display panel according to claim 1, characterized in that: The length of the channel region of the first transistor is equal to the length of the channel region of the second transistor; the width of the channel region of the first transistor shows a decreasing trend along the current direction; and / or, the width of the channel region of the second transistor shows a decreasing trend along the current direction.

6. The display panel according to claim 5, characterized in that: At least one of the first transistor and the second transistor is a double-gate transistor, and the double-gate transistor is a low-temperature polycrystalline silicon thin-film transistor.

7. The display panel according to claim 6, characterized in that: The double-gate transistor includes a first channel region and a second channel region arranged along the current direction. Along the current direction, the width of the second channel region is less than or equal to the width of the first channel region, and the width of the first channel region shows a decreasing trend; the width of the second channel region is consistent, or the width of the second channel region shows a decreasing trend.

8. The display panel according to claim 5, characterized in that: At least one of the first transistor and the second transistor is a double-gate transistor, and the double-gate transistor is an indium gallium zinc oxide thin-film transistor.

9. The display panel according to claim 8, characterized in that: The width of the channel region of the double-gate transistor shows a decreasing trend along the current direction.

10. The display panel according to claim 1, characterized in that: At least one of the first transistor and the second transistor includes a channel region of a rectangular structure, and at least one of the first transistor and the second transistor is a dual-gate transistor including a first channel region and a second channel region.

11. The display panel according to claim 10, characterized in that: In the same color sub-pixel, the width of the first channel region in the first transistor is different from the width of the second channel region, and / or the width of the first channel region in the second transistor is different from the width of the second channel region.

12. The display panel according to claim 11, characterized in that: The first transistor and the second transistor are both dual-gate transistors, and the difference in width between the first channel region and the second channel region in the dual-gate transistor close to the first node is greater than the difference in width between the first channel region and the second channel region in the dual-gate transistor far from the first node.

13. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-12.

Images