Method for etching indium-based semiconductor material

Abstract

A method of etching into an indium-based semiconductor material. In one embodiment, a method includes mounting a substrate comprising an indium-based semiconductor material directly on a substrate support structure in a plasma processing chamber, where the indium-based semiconductor material forms a surface of the substrate carrying a patterned mask and disposed away from the substrate support structure. The plasma processing chamber contains solid silicon arranged to be exposed to a plasma generated within the plasma processing chamber, the exposed surface area of the solid silicon being at least one time the area of the surface of the substrate carrying the patterned mask that is not covered by the patterned mask. The method further includes establishing an inflow of an etch gas mixture to the plasma processing chamber, the etch gas mixture including an inert gas and a chlorine-containing gas configured to release chlorine radicals when present in a plasma generated by the etch gas mixture; and generating a plasma from the etch gas mixture within the plasma processing chamber such that the solid silicon is exposed to the plasma, thereby generating a silicon-containing species from the solid silicon in the plasma and concurrently applying a radio frequency (RF) bias to the substrate support structure, whereby a portion of the surface carrying the patterned mask that is not covered by the patterned mask is etched by a plasma comprising the generated silicon-containing species to form one or more etched features in the indium-based semiconductor material.

Description

Technical Field

[0001] The present invention relates to a method of etching into indium-based semiconductor materials, especially indium phosphide and its alloys. Background Art

[0002] Indium-based semiconductor materials find application in a range of semiconductor devices such as optoelectronic devices (e.g., lasers and photodiodes), transceivers, and photovoltaic devices. In the present specification, "indium-based semiconductor materials" refers to compound semiconductors containing indium. Indium phosphide (InP) is a notable example of an indium-based semiconductor material. Other examples of indium-based semiconductor materials include alloys of indium phosphide, including ternary alloys (e.g., indium gallium phosphide InGaP) and quaternary alloys (e.g., indium gallium arsenic phosphide InGaAsP), and indium antimonide (InSb). In contrast, semiconductor materials containing only trace levels of indium (e.g., where indium is present only as a dopant) are not indium-based semiconductors because indium does not appear in the compound formulas of these materials. For example, indium-doped silicon (Si) is not an indium-based semiconductor. Indium typically forms at least 5% by weight of the indium-based semiconductor material. Plasma etching processes for etching indium-based semiconductor materials typically employ a gas mixture comprising a chlorine-containing gas (e.g., molecular chlorine Cl2 or boron trichloride BCl3), which releases chlorine radicals into the generated plasma. The chlorinated species in the plasma aid in etching of the indium-based semiconductor material by chemically interacting with the indium-based semiconductor material.

[0003] As mentioned above, InP is a prominent indium-based semiconductor material and is by far the most commonly used material of this type in industrial processes for manufacturing semiconductor devices. Devices made of indium-based semiconductor materials (e.g., InP) are typically manufactured by etching into a substrate using plasma, wherein the indium-based semiconductor material forms a layer (e.g., an epitaxial layer) or forms an entire substrate (e.g., in the form of a wafer made of indium-based semiconductor material). Processes suitable for etching indium-based semiconductor materials on an industrial scale generally use an etching gas mixture containing a chlorine-containing gas (i.e., a gas configured to release chlorine-containing free radicals when present in a plasma) to generate a plasma.

[0004] To date, devices formed from indium-based semiconductor materials have been successfully manufactured in "carrier-based" processes, in which the substrate to be etched is placed on a separate carrier wafer, typically made of silicon, on which the substrate is located during etching. However, the applicability of these processes to industrial-scale production is severely limited by practical considerations. For example, in such systems preferred by industrial-scale production requiring high throughput, particularly cassette-based systems, it is extremely difficult to transport the carrier wafer and the substrate to be etched under vacuum. In cassette-based systems, multiple substrates to be etched (e.g., wafers) are typically loaded into a "cassette" inside a load lock (i.e., a second chamber that is connected to the main plasma processing chamber but can be separately sealed and pressurized). In addition, the presence of the carrier wafer makes it difficult to accurately control certain physical conditions near the wafer being etched, which can lead to inconsistencies between devices manufactured from one iteration to the next.

[0005] Attempts to provide industrial-scale processes for etching into InP and other indium-based semiconductor materials have generally been unsuccessful in producing the consistent and high-quality devices required for commercial production.Therefore, there is a need for a process for etching into indium-based semiconductor materials that can produce consistent, functional devices at high yields. Summary of the invention

[0006] The present invention provides a method for etching into an indium-based semiconductor material, the method comprising:

[0007] mounting a substrate comprising the indium-based semiconductor material directly on a substrate support structure in a plasma processing chamber, wherein the indium-based semiconductor material forms a surface of the substrate, the surface carrying a patterned mask and arranged away from the substrate support structure,

[0008] The plasma processing chamber comprises solid silicon, the solid silicon is arranged to be exposed to the plasma generated in the plasma processing chamber, and the exposed surface area of ​​the solid silicon is at least 1 times the area of ​​the surface of the substrate bearing the patterned mask that is not covered by the patterned mask; the method further comprises:

[0009] establishing a flow of an etching gas mixture into the plasma processing chamber, the etching gas mixture comprising an inert gas and a chlorine-containing gas configured to release chlorine radicals when present in a plasma generated by the etching gas mixture; and

[0010] A plasma is generated from the etching gas mixture in the plasma processing chamber, so that the solid silicon is exposed to the plasma, thereby generating silicon-containing substances from the solid silicon in the plasma, and a radio frequency (RF) bias is simultaneously applied to the substrate support structure, whereby portions of the surface carrying the patterned mask that are not covered by the patterned mask are etched by the plasma including the generated silicon-containing substances to form one or more etched features in the indium-based semiconductor material.

[0011] As described above, the phrase "indium-based semiconductor material" in this specification refers to a compound semiconductor including indium. The indium-based semiconductor material may be doped. In the method of the present invention, a substrate including an indium-based semiconductor material (which forms the surface of the substrate to be etched) is directly mounted on a substrate support structure. The indium-based semiconductor material forms the surface of the substrate to be etched, which is the surface on which the patterned mask is carried. In some embodiments, the substrate may be a wafer in which the indium-based semiconductor material is an epitaxial layer grown on another material (e.g., silicon), or a wafer whose main body is formed of an indium-based semiconductor material. In many embodiments, the substrate will have a substantially circular perimeter, for example, where the substrate is formed as a disk-shaped wafer. In these cases, the perimeter may not be a precise circle, for example, the wafer may have a circular shape in which one or more segments are removed along a portion of its perimeter to define a corresponding number of "planes".

[0012] The substrate may be a substantially flat portion of the perimeter that can be used to orient the substrate and / or convey information about the composition of the substrate.

[0013] "Substrate support structure" refers here to a device inside a plasma processing chamber that supports and restrains a substrate mounted thereon during processing. An example of a substrate support structure suitable for this situation is an electrostatic clamp (also called an electrostatic chuck), which includes a substrate table to which a direct current (DC) bias is applied, at least when the substrate is being etched. The bias polarizes the substrate on the substrate table, resulting in electrostatic attraction between the substrate and the table that restrains the substrate during processing. "Direct mounting" means that the substrate is directly in contact with and restrained by the substrate support structure. This is in contrast to carrier-based processes of the type described above, in which a carrier wafer on which the substrate to be etched is located is typically mounted on a substrate support structure (e.g., a mechanical clamp), while the substrate itself is located on the carrier wafer and is not restrained. In production-scale processes, it is very desirable to mount the substrate directly on the substrate support structure because, as described above, this allows the substrate to be automatically mounted and removed under vacuum, which allows multiple substrates to be etched in sequence without delaying the process by breaking vacuum conditions and then restoring vacuum conditions (e.g., the vacuum in a load lock used to introduce the substrate into the chamber) between each etching as is typically required in carrier-based processes. Furthermore, in processes where the substrate is mounted directly (rather than on a carrier wafer), physical conditions in the vicinity of the substrate, particularly substrate temperature, can be more reliably and accurately controlled, which makes these processes particularly suitable for production-scale processes where consistency of manufactured devices is an important consideration. As will be described below with reference to examples, the substrate support structure (particularly where the substrate support structure is an electrostatic clamp) may include a raised portion that is raised relative to the surrounding surface of the substrate support structure, and the substrate is disposed on the raised portion when the substrate is mounted on the substrate support structure. The raised portion may be integral to the surrounding surface of the substrate support structure, or may be formed by a separate support element (sometimes referred to as a "positioning plate") placed on the surface. Importantly, the support element or positioning plate still forms part of the substrate support structure, as the substrate disposed thereon is still constrained by the substrate support structure, for example, in the case of an electrostatic clamp, the positioning plate may be biased to provide an electrostatic force that constrains the substrate mounted directly thereon.

[0014] When etching indium-based semiconductor materials in a process that does not use a carrier wafer, a particular problem that has been encountered is that the resulting device typically contains deep microgrooves at the base of etched vertical features (e.g., the walls of grooves and terraces). The term "microgrooves" refers to grooves that appear at the bottom of the walls of the etched features and extend deeper into the substrate than the imaginary bottom of the etched features: an example of a prominent microgroove is shown in Figure 4(b), which will be described below. The presence of microgrooves typically prevents devices in which microgrooves appear from functioning fully. However, these defects do not typically occur in comparable carrier-based methods. The inventors have recognized that the presence of silicon in the above-mentioned carrier-based process promotes the desired characteristics of the profile of the features etched into the indium-based semiconductor material. Without wishing to be bound by theory, it is believed that silicon-containing species (e.g., silicon-containing radicals and ions) produced by the chemical interaction of the etchant (e.g., chlorine) in the plasma with the silicon carrier wafer help to passivate and reduce the microgrooves.

[0015] In the method of the present invention, a directly mounted substrate is etched inside a plasma processing chamber containing solid silicon exposed to a plasma. The solid silicon interacts with the plasma generated within the chamber to produce gaseous silicon-containing species, which aids in passivation and prevention of microgrooving. The inventors have discovered that devices of at least equal quality to those previously available only through carrier-based processes can be manufactured, wherein the surface area of ​​the solid silicon exposed to the plasma ("exposed surface area" as defined above) is at least 1 times the surface area of ​​the portion of the substrate surface to be etched that is not covered by the patterned mask (which forms the area of ​​the surface to be etched that will be exposed to the generated plasma). The portion of the surface that is not covered by the patterned mask typically varies depending on the nature of the device being manufactured, but is typically between 10% and 90%. Thus, the present invention enables consistent, production-scale manufacturing of devices from indium-based semiconductor materials.

[0016] "Solid silicon" refers to elemental silicon (Si) in a solid state. Solid silicon can be provided in a variety of forms, such as one or more wafers, slices or fragments, or preferably as replaceable elements designed for embodiments of the present invention, examples of which will be discussed below. Preferred forms of solid silicon contained in a plasma processing chamber will be described below. It should be understood that the "exposed surface area" of solid silicon defined above does not have to be a single continuous area, but may include multiple discrete areas. For example, solid silicon can be provided as several non-connected portions spaced apart from each other. The "exposed surface" in this example may include all portions of the surface of several fragments that are exposed to the plasma generated in the plasma processing chamber.

[0017] Several repetitions of the steps of the above method may be performed while continuously maintaining a vacuum or partial vacuum (e.g., a pressure in the range of 1 mTorr to 10 mTorr) within the plasma processing chamber. In these processes, after etching the substrate, the plasma is quenched and the substrate is removed. A new substrate is then mounted on the substrate support structure in the next repetition of the "mounting" step. After mounting the new substrate, the steps of establishing the inflow of the etching gas mixture into the chamber and generating the plasma are repeated while the new substrate is mounted on the substrate support structure. Mounting the substrate or each substrate may include transferring the substrate from a cassette in a load lock adjacent to the plasma processing chamber to the substrate support structure.

[0018] In a preferred embodiment, the exposed surface area of ​​the solid silicon is at least 3 times, preferably at least 6.5 times, and more preferably at least 13 times, the area of ​​the surface of the substrate bearing the patterned mask that is not covered by the patterned mask. As described above, it is believed that the beneficial effect of the solid silicon inside the chamber is the result of silicon-containing species generated by the interaction of the plasma with the solid silicon. The rate of generation of such species increases in proportion to the exposed surface area of ​​the solid silicon, so it is preferred that the exposed area is large relative to the exposed area of ​​the surface to be etched.

[0019] As described above, the exposed surface area of ​​the solid silicon is at least 1 times the area of ​​the surface to be etched that is not covered by the mask, which achieves a rate of silicon-containing species sufficient to prevent the formation of microgrooves. An increase in the rate of generation of silicon-containing species can be achieved by selecting the exposed surface area of ​​the solid silicon to be at least 1 times the area of ​​the surface carrying the mask (rather than only at least 1 times the area of ​​the portion of the surface that is not covered by the mask), preferably at least 3 times, and more preferably at least 6.5 times.

[0020] Advantageously, the solid silicon may be disposed on or laterally adjacent to the substrate support structure. For example, if the substrate support structure is an electrostatic clamp comprising a substrate table, on which the substrate is placed in use, the solid silicon may be disposed on the substrate table adjacent to the substrate (in which case the solid silicon will be disposed on the substrate support structure). Alternatively, the solid silicon may be maintained in a position laterally adjacent to the substrate support structure by a separate structure suitable for the purpose. The "lateral" arrangement of the solid silicon refers here to the positioning of the solid silicon in a plane parallel to the surface of the substrate carrying the mask. Positioning the solid silicon on the substrate support structure, or at least laterally adjacent to it, helps to ensure that the exposed area of ​​the solid silicon is relatively close to the substrate, and thereby promotes the production of silicon-containing material near the surface to be etched.

[0021] The solid silicon preferably has a thickness of at least 1 mm, preferably at least 3 mm, in a direction perpendicular to the surface of the substrate, which carries the mask when the substrate is mounted on a substrate support structure. The silicon will be plasma etched (because silicon-containing substances are generated therefrom), so choosing a suitable minimum thickness of silicon in the direction in which etching mainly occurs (i.e. perpendicular to the surface to be etched) ensures that the silicon does not need to be replaced frequently. In some embodiments, the temperature of the solid silicon can be controlled, for example by mounting the solid silicon on a substrate support structure (in the case where the substrate support structure is temperature controlled) or by providing a separate temperature control device for the solid silicon. The rate of generation of silicon-containing substances can be increased by applying a bias (e.g., an RF bias) to the solid silicon during etching, and / or mitigated by placing an electrically insulating material between the solid silicon and the substrate support structure (thereby reducing the bias to which the solid silicon is subjected, particularly in the case where the solid silicon is disposed on a substrate support structure).

[0022] In a preferred embodiment, the solid silicon laterally surrounds at least a portion, preferably all, of the perimeter of the surface of the substrate that carries the patterned mask. For example, if the solid silicon is shaped as a ring (e.g., a disk having a circular central opening through its center) and is arranged so that the substrate is laterally inside the central opening of the ring, the solid silicon will laterally surround the entire perimeter of the surface that carries the mask. If the solid silicon is in the form of a segment of such a ring (e.g., having a generally "C" shape), it will laterally surround a portion of the perimeter of the surface of the substrate that carries the patterned mask. Arranging the solid silicon to laterally surround (at least a portion of) the perimeter of the surface to be etched promotes uniformity in the concentration of silicon-containing material on the surface to be etched, thereby promoting consistent formation of features without microgrooves across the entire surface.

[0023] Preferably, the solid silicon is shaped to define an opening through the solid silicon, wherein the substrate mounted on the substrate support structure is laterally inside the opening. The example of the ring described above will provide this feature, wherein the substrate is laterally arranged in the central opening of the ring. Therefore, as described above, the solid silicon is preferably formed into a ring, preferably an annular disk, which defines the opening. Solid silicon having an annular form is particularly suitable for situations where the substrate to be etched has a circular shape, in which case the size of the annular solid silicon can be selected so as to minimize the lateral spacing between the surface carrying the mask and the edge of the inner opening of the ring. The annular disk is a particularly preferred form.

[0024] In some particularly preferred embodiments, the solid silicon is electrically isolated from the substrate support structure, and when the substrate is mounted on the substrate support structure, the solid silicon is electrically isolated from the substrate. This provides a very significant advantage because it reduces the coupling of the RF bias applied to the substrate support structure into the solid silicon, which ensures that the RF bias signal is concentrated in the substrate region. This in turn ensures that the power density of the RF bias signal is concentrated in the substrate region, thereby promoting a high etching rate. Preferably, electrical isolation is provided by an electrically insulating element arranged between the solid silicon and the substrate support structure so as to space the solid silicon from the substrate support structure and the substrate when the substrate is mounted on the substrate support structure. The electrically insulating element arranged in this manner ensures that the solid silicon is not in contact with the substrate support structure or the substrate, which reduces the RF bias signal transmitted to the solid silicon.

[0025] In the presence of the above-mentioned electrically insulating element, preferably, the electrically insulating element and the solid silicon are arranged so that the surface of the solid silicon exposed to the plasma is at a height of 0 mm to 5 mm, preferably 0 mm to 3 mm, more preferably 1.5 mm to 2 mm above the surface of the substrate on which the patterned mask is carried in a direction perpendicular to said surface of the substrate. It has been found that this can achieve good electrical isolation of the solid silicon while keeping the solid silicon close to the wafer and achieving uniform etching of the wafer.

[0026] Advantageously, the electrically insulating element is disposed on the substrate support structure so that when the substrate is mounted on the substrate support structure, the electrically insulating element is laterally adjacent to the substrate, and wherein the solid silicon is supported by the electrically insulating element. For example, the electrically insulating element may be formed by a ring of electrically insulating material having a sufficient diameter so that it can be disposed on a substrate support structure concentric with the substrate. The solid silicon can then be supported on the electrically insulating element, whereby it will be spaced apart from the substrate support structure. Therefore, preferably, the solid silicon has a central hole, which is arranged to be concentric with the substrate when the substrate is mounted on the substrate support structure; and wherein the electrically insulating element is arranged to prevent plasma from entering the space between the solid silicon and the substrate support structure via the central hole. In these embodiments, the electrically insulating element may have the above-mentioned annular shape (alternatively, more generally, an annular form), and therefore preferably, the electrically insulating element has an annular form and is arranged to be concentric with the substrate when the substrate is mounted on the substrate support structure.

[0027] The electrically insulating element is preferably made of a dielectric material, preferably quartz. However, the electrically insulating element may be made of any material(s) arranged to provide the required electrical isolation of the solid silicon.

[0028] As described above, it is advantageous to ensure that the exposed solid silicon is in close proximity to the surface to be etched. Therefore, preferably, each portion of the perimeter of the surface carrying the mask is laterally spaced no more than 5 mm, preferably no more than 1 mm from the exposed surface of the solid silicon. As described above and as described below, in some particularly preferred embodiments, the solid silicon and the substrate may laterally overlap each other, wherein the substrate overhangs an edge of a raised portion of a substrate support structure, on which the substrate is disposed when the substrate is mounted on the substrate support structure. In these embodiments, since the perimeter of the substrate laterally overlaps the solid silicon, the lateral spacing between the perimeter of the substrate and the solid silicon is zero.

[0029] In a preferred embodiment, the solid silicon forms a substantially flat surface that is exposed to the generated plasma. The substantially flat surface may form a portion or substantially all of the exposed surface area of ​​the solid silicon. Arranging the exposed surface in a planar form promotes uniform, predictable transport of the generated silicon-containing species away from the exposed surface because it limits the effect of the surface shape on the dynamic behavior of the plasma in its vicinity. The solid silicon may also or alternatively define a textured surface that is exposed to the plasma. Such a textured surface may be provided so as to increase the exposed surface area formed by the silicon within a given perimeter.

[0030] Preferably, the solid silicon forms a surface which is oriented substantially parallel to the surface of the substrate carrying the patterned mask and exposed to the generated plasma. This promotes uniform delivery of the generated silicon-containing species to the surface to be etched. This feature is particularly advantageous in the case where the solid silicon is disposed on or laterally adjacent to a substrate support structure and / or where the substrate is laterally located within an opening in the solid silicon as above.

[0031] The solid silicon may form a surface that is substantially arranged in the plane of the surface of the substrate bearing the mask and exposed to the generated plasma. For example, if the substrate is arranged laterally in an opening in the solid silicon as described above, this feature may be provided by positioning the silicon in a direction parallel to the surface of the substrate to be etched so that at least a portion of the exposed surface of the solid silicon is in the same plane as the surface of the substrate. Alternatively, the exposed silicon surface may be arranged so that it does not meet or intersect the plane of the surface bearing the mask - this may be the case in some preferred embodiments described below, in which the substrate support structure includes a raised portion on which the substrate is disposed when the substrate is mounted on the substrate support structure.

[0032] In a preferred embodiment, the surface of the substrate that carries the mask has a minimum lateral dimension of at least 50 millimeters (mm), preferably at least 100 mm. As described above, the surface that carries the mask is a surface formed of an indium-based semiconductor material. "Minimum lateral dimension" refers to the smallest dimension of the surface along any direction. In many cases, the surface that carries the mask will have a circular perimeter, in which case its minimum lateral dimension is simply the diameter. If the perimeter of the surface is elliptical, the minimum lateral direction will be the minor axis of the ellipse. If it is rectangular, the minimum lateral dimension will be the shorter side length of the rectangle.

[0033] Preferably, the surface of the substrate bearing the mask has an area of ​​at least 2000 square millimeters (mm 2 ) surface area, preferably at least 4000mm 2 For example, the surface formed by one side of a circular wafer having a diameter of 76 mm would have a diameter of approximately 4536.5 mm. 2 Substrates providing surfaces with areas within these ranges are particularly preferred for industrial-scale production.

[0034] Processes for etching indium-based semiconductor materials, particularly InP, are typically carried out as "thermal" processes, in which the material being etched is intentionally heated above ambient temperature (and typically very significantly above ambient temperature, e.g., to tens or hundreds of degrees Celsius). Although the plasma exposing the substrate typically causes it to heat up, it may be advantageous to supply additional heat by heating the substrate support structure to which the substrate is mounted. Accordingly, the method may advantageously include controlling the temperature of the substrate support structure during etching, preferably such that the temperature of the substrate is maintained in the range of 100 to 300 degrees Celsius, preferably in the range of 150 to 250 degrees Celsius, and more preferably in the range of 180 to 220 degrees Celsius during etching. In the present method, the substrate is mounted directly on the substrate support structure, which allows the substrate to be heated faster, more efficiently and with greater reliability than in processes in which a carrier wafer is present between the substrate and the support structure. A significant advantage of the present invention over carrier-based processes derives from the fact that the substrate is mounted directly on the substrate support structure. This direct mounting means that the substrate can be heated by the substrate support structure independently of the silicon, whereas in carrier-based processes where solid silicon is located between the substrate support structure and the substrate being etched, heating the substrate inevitably requires heating the silicon. Although it is desirable that the substrate support structure and substrate not be heated above the upper limit of the above range (particularly electrostatic chucks to which overheating may cause damage), it may be desirable for the solid silicon to reach higher temperatures in order to promote efficient production of silicon-containing species. The present invention allows the temperature of the solid silicon to be decoupled from the temperature of the substrate and substrate support structure, as the silicon can be allowed to be heated to high temperatures by the plasma while controlling the temperature of the substrate support structure to be within the desired range.

[0035] In a particularly preferred embodiment, the method comprises supplying a heat transfer gas, preferably helium, between the substrate and the substrate support during etching in order to control the temperature of the substrate. The heat transfer gas may transfer heat from the substrate support to the substrate and prevent overheating of the substrate by removing heat therefrom when the substrate is heated by the plasma above the temperature of the substrate support. This is particularly advantageous where the substrate support is an electrostatic chuck, because while heating the substrate is advantageous for the reasons described above, such chucks may be damaged when subjected to excessively high temperatures for extended periods of time.

[0036] When a heat transfer gas is used as described above, it is preferred that the pressure of the heat transfer gas in contact with the substrate is in the range of 1 Torr to 20 Torr, preferably in the range of 3 Torr to 15 Torr, and more preferably in the range of 5 Torr to 10 Torr. These ranges have been found to provide suitable heat transfer rates into and out of the substrate.

[0037] Preferably, the substrate support structure is an electrostatic clamp. As mentioned above, electrostatic clamps are particularly preferred because they are able to support and hold the substrate in place without covering any part of the surface carrying the mask, thereby maximizing the available area of ​​the substrate surface. An example of an alternative substrate support structure is a mechanical clamp.

[0038] The substrate support structure may include a raised portion that is raised relative to the surrounding surface of the substrate support structure, wherein when the substrate is mounted on the substrate support structure, the substrate is disposed on the raised portion. As described above, the raised portion may be integral with the surrounding surface of the substrate support structure, or formed by a separate support element (e.g., a "positioning plate") that allows the substrate to be directly mounted (e.g., by being configured to electrostatically clamp the substrate through features such as electrodes incorporated into the support element) so as to be supported and restrained on the raised portion. The separate support element is typically made of the same (one or more) materials as the surrounding surface. It should be understood that the support element and other parts of the substrate support structure cannot be made of materials that are easily etched by plasma (e.g., silicon and other semiconductors) because these materials will degrade rapidly if exposed to the plasma. Preferably, the substrate is suspended above the periphery of the raised portion, for example, where the lateral dimensions of the substrate are greater than the lateral dimensions of the raised portion. Advantageously, in the case where the substrate is located on the raised portion as described above, solid silicon can be disposed on the surrounding surface of the substrate support structure, preferably laterally overlapping the suspended portion of the substrate. This lateral overlap between the substrate and the solid silicon is advantageous because in this configuration the silicon and substrate can be arranged so that no part of the surface of the raised portion of the surrounding surface is exposed to the plasma during etching. This helps prevent damage to the substrate support structure (particularly if it is an electrostatic chuck), thereby extending its operating life.

[0039] Preferably, the indium-based semiconductor material comprises at least 5% by weight of indium. In a preferred embodiment, the indium-based semiconductor material is indium phosphide or a ternary or quaternary alloy thereof. As previously mentioned, indium phosphide is particularly suitable for a wide range of applications, and the process described herein is particularly suitable for making devices from this material. However, the presence of indium in other indium-based semiconductor materials causes these materials to have properties similar to indium phosphide (e.g., their interaction with substances in the plasma and the dependence of their behavior on the physical conditions to which they are subjected during etching), and therefore, the preferred features of the method described throughout this specification apply to the class of indium-based semiconductor materials.

[0040] The mask may include one or more of silicon dioxide, silicon nitride, and a metal such as chromium.

[0041] The inert gas is preferably a rare gas, preferably argon (Ar). Helium (He) and xenon (Xe) are examples of other suitable rare gases. In some embodiments, more than one inert gas may be present in the etching gas mixture, so the etching gas mixture may include two or more of helium, xenon and argon.

[0042] Preferably, the chlorine-containing gas is molecular chlorine Cl2, boron trichloride BCl3 or silicon tetrachloride SiCl4. Each of these compounds is suitable for etching into InP and producing silicon-containing species in the method according to the invention.

[0043] In some particularly preferred embodiments: the chlorine-containing gas flows into the plasma processing chamber at a rate in the range of 2 sccm to 20 sccm, preferably in the range of 4 sccm to 20 sccm, and more preferably in the range of 5 sccm to 15 sccm, and / or the inert gas flows into the plasma processing chamber at a rate in the range of 5 sccm to 50 sccm, preferably in the range of 20 sccm to 50 sccm, and more preferably in the range of 20 sccm to 30 sccm. It has been found that flow rates within these ranges, especially combined flow rates, can achieve reasonable etching rates while producing features that are substantially free of microgrooves and exhibit highly vertical sidewalls. These preferred values ​​are particularly suitable for substrates with lateral dimensions (e.g., diameter) up to 100 mm. In some embodiments, higher flow rates may be selected for substrates with larger lateral dimensions.

[0044] Preferably, the ratio of the inert gas to the chlorine-containing gas in the etching gas mixture is in the range of 1: 1 to 13: 1, preferably in the range of 1: 1 to 5: 1, preferably in the range of 2: 1 to 3: 1. Furthermore, it has been found that etching gas mixtures having these compositions achieve reasonable etch rates while producing features that are substantially free of micro-trenching and exhibit highly vertical sidewalls.

[0045] The etching gas mixture may also include hydrogen, wherein preferably the volume proportion of hydrogen in the etching gas mixture is not more than 25%, preferably not more than 20%. It has been found that the presence of hydrogen in the etching gas mixture moderates the rate of plasma etching solid silicon. Therefore, the addition of hydrogen makes the rate of silicon-containing species generation controllable and therefore optimal for the specific substrate and process parameters used.

[0046] In a preferred embodiment, the RF bias has a power in the range of 50 Watts (W) to 250 W, preferably 100 W to 200 W. These preferred values ​​are particularly applicable to substrates with lateral dimensions (e.g., diameter) up to 100 mm. In some embodiments, higher power values ​​can be selected for substrates with larger lateral dimensions in order to achieve a power density across the substrate that is similar to the power density across the substrate achieved by applying the above preferred values ​​to substrates with lateral dimensions below 100 mm.

[0047] Preferably, the pressure in the plasma chamber during etching is in the range of 1 mTorr to 10 mTorr, preferably in the range of 1 mTorr to 4 mTorr. These pressure conditions may be established before the substrate is etched and maintained after the substrate is etched.

[0048] The plasma is preferably generated by an inductively coupled plasma source. Other types of plasma sources may also be used, such as capacitively coupled plasma sources and microwave plasma sources.

[0049] In a preferred embodiment, the plasma generation power is in the range of 500 W to 2500 W, preferably in the range of 750 W to 1250 W. Preferably, the amplitude of the RF bias is in the range of 100 volts (V) to 250 V, preferably in the range of 150 V to 200 V.

[0050] In some particularly preferred embodiments of the present invention, the indium-based semiconductor material is InP; the solid silicon is disposed on a substrate support structure, the substrate support structure is an electrostatic chuck; and the exposed surface area of ​​the solid silicon is at least 13 times the area of ​​the surface of the substrate bearing the mask that is not covered by the patterned mask. Preferably, in these embodiments, the chlorine-containing gas is Cl2 flowing into the plasma processing chamber at a rate in the range of 5sccm to 15sccm; the inert gas is argon flowing into the plasma processing chamber at a flow rate of 20sccm to 30sccm; during etching, the pressure in the plasma processing chamber is in the range of 1mTorr to 4mTorr; the plasma is generated at a power in the range of 750W to 1500W; the amplitude of the RF bias is in the range of 150V to 200V; the power of the RF bias power supply is in the range of 100W to 200W; the temperature of the substrate support structure is controlled to be maintained in the range of 180°C to 220°C during etching; during etching, a heat transfer gas is provided between the substrate and the substrate support structure to control the temperature of the substrate. These processes, and particularly the preferred process parameters just mentioned, have been found to give excellent results, virtually eliminating micro-trenching while forming smooth vertical sidewalls at good etch rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] An example of a method according to an embodiment of the present invention will now be described with reference to the accompanying drawings, in which:

[0052] Figure 1 An example of an apparatus suitable for use in performing a method according to an embodiment of the present invention is shown;

[0053] Figure 2 Examples of suitable forms of solid silicon that may be used in methods according to embodiments of the present invention are shown;

[0054] Figure 3is a flow chart representing the steps of a method according to an embodiment of the present invention;

[0055] FIG4( a ) is an electron micrograph of a feature etched by a method according to an embodiment of the present invention;

[0056] FIG4( b ) is an electron micrograph of a feature etched according to a comparative example of a method that is not an embodiment of the present invention; and

[0057] FIG. 5( a ) shows a detailed view of an example of how solid silicon and a substrate may be arranged in some embodiments of the present invention;

[0058] FIG5( b ) shows a detailed view of an alternative arrangement to that of FIG5( a );

[0059] Figure 6 A detailed view showing an example of how solid silicon and a substrate may be arranged in another embodiment of the present invention;

[0060] Figure 7 is based on Figure 6 A photograph of a substrate support structure of an embodiment schematically shown in FIG.

[0061] 8(a) and 8(b) are electron micrographs showing features etched in a first experiment according to an embodiment of the present invention;

[0062] 9(a) and 9(b) are electron micrographs showing features etched according to a second experiment of an embodiment of the present invention;

[0063] 10( a) and 10( b) are electron micrographs showing features etched according to a third experiment of an embodiment of the present invention;

[0064] 11( a) and 11( b) are electron micrographs showing features etched according to a fourth experiment of an embodiment of the present invention;

[0065] 12(a) and 12(b) are electron micrographs showing features etched according to a fifth experiment of an embodiment of the present invention;

[0066] Fig.13 Shows Figure 6 Detailed view of an exemplary embodiment of the arrangement shown. DETAILED DESCRIPTION

[0067] Figure 1An example of a plasma processing tool suitable for implementing the disclosed method is shown. The plasma processing tool 1 includes a plasma processing chamber 2 in which a substrate 30 is placed during use. The substrate includes an indium-based semiconductor material, such as indium phosphide, forming a surface 30a of the substrate 30. For example, the indium-based semiconductor material can be an epitaxial layer on a substrate wafer. The surface 30a formed by the indium-based semiconductor material carries a patterned mask that covers portions of the surface 30a that define features to be etched into the indium-based semiconductor. Portions of the surface 30a that are not covered by the mask are exposed to a plasma generated in the chamber 2.

[0068] To perform etching, an etching gas mixture including an inert gas (e.g., argon Ar, helium He, or xenon Xe) and one or more chlorine-containing gases (e.g., chlorine molecular Cl2, silicon tetrachloride SiCl4, or boron trichloride BCl3) is introduced into the plasma processing chamber 2, and the conditions in the chamber 2 are controlled to achieve the desired etching mechanism. The process parameters in the chamber are controlled and can be adjusted by a set of at least one (but more typically a plurality of) devices, the example of which is shown in FIG. Figure 1 Schematically shown in . In this example, the tool 1 is equipped with two input gas sources 4 (a) and 4 (b) for supplying a first input gas G1 (e.g., Ar) and a second input gas G2 (e.g., Cl2) to the plasma processing chamber 2, respectively. Some embodiments of the present invention employ an etching gas mixture comprising more than two gases, and it will be understood that the plasma processing tool 1 may have any number of gas sources, each gas source being configured to supply a corresponding one of the component gases of the etching gas mixture. For example, the third gas source may be configured to supply hydrogen (H2). The entry of each gas into the chamber 2 is controlled by valves 6 (a) and 6 (b) and corresponding mass flow controllers (not shown). Furthermore, additional mass flow controllers may be provided, wherein the etching gas mixture comprises more than two gases. Exhaust gases including unreacted input gases and any reaction products are removed from the plasma processing chamber 2 via a conduit 7 and associated (one or more) pumps 8, which are typically capable of reducing the pressure in the chamber to near-vacuum conditions. The chamber pressure will be determined in the main part by the exhaust pump system, in particular by the pumping speed and the "conductivity" of the pumping line from the chamber to the pump (this is a factor related to the geometry of the pumping line). However, during processing, when plasma is generated and / or when etching occurs, gaseous species may be lost or generated in the chamber, which has an effect on the pressure. In order to adjust for such changes, an automatic pressure control valve 8a as known in the art is preferably provided. Valve 8a varies the conductivity of the pumping line so that the chamber pressure can be maintained substantially constantly at a desired level when plasma is struck and material is etched.

[0069] The plasma processing tool 1 is equipped with a plasma source for generating plasma in a plasma processing chamber by discharge. Here, the plasma source is described as an inductively coupled plasma source, which includes a coil 9 surrounding the plasma processing chamber 2, and the coil 9 is supplied with RF power from a power supply 10 via an RF matching unit 11. The RF matching unit 11 is configured to match the plasma impedance with the impedance of the RF power supply 10 to maximize the power transfer efficiency from the power supply to the plasma. Examples of suitable matching units are disclosed in WO-A-2010 / 073006. Other types of plasma sources may be used alternatively, such as capacitively coupled plasma (CCP) or a microwave plasma source.

[0070] The substrate 30 is mounted directly on the substrate support structure 14, which supports and restrains the substrate 30 in place during etching. The substrate support structure 14 is preferably an electrostatic clamp, but other substrate support structures, such as mechanical clamps, can be used. In the case of industrial-scale processes, the use of electrostatic clamps is particularly advantageous because these devices can hold the substrate firmly in place without covering any part of the surface to be etched, thereby maximizing the available area of ​​the substrate surface. The plasma processing chamber 2 may include a robotic tool (not shown) that is configured to install and remove substrates (e.g., wafers) from the substrate support structure 14 while maintaining a vacuum or partial vacuum in the plasma processing chamber 2. Providing such a tool allows multiple substrates to be processed in sequence without interruption, and then reestablishing vacuum conditions each time a new substrate is etched, thereby increasing the rate at which the substrate can be processed. The substrate retrieved by the robotic tool can be stored in a cassette, which can be located inside a load lock adjacent to the plasma processing chamber 2. Once the processed substrate is removed from the substrate support structure 14, it can be placed in a separate cassette by the robotic tool.

[0071] In use, a bias voltage is applied to the substrate 30. This is achieved by connecting a voltage source 12 to the substrate support structure 14. In this example, the bias voltage is a radio frequency (RF) voltage, which typically has a frequency of about 13.56 MHz. If an RF power source 12 is used, an automatic impedance matching unit (AMU) may preferably be provided to ensure good coupling of power from the power source 12 to the substrate support structure 14. In the case where the substrate support structure 14 is an electrostatic clamp, the bias voltage applied to generate an electrostatic force between the substrate 30 and the substrate support structure 14 is different from the RF bias, and a bias voltage applied to generate an electrostatic force between the substrate 30 and the substrate support structure 14 is provided in addition to the RF bias, the purpose of which is to promote anisotropic etching of indium-based semiconductor materials in a direction perpendicular to the etched surface.

[0072] The plasma processing chamber 2 contains solid silicon 50. As described above, "solid silicon" refers to elemental silicon Si in a solid state, which is generally in the form of one or more crystals that are machined or otherwise manufactured into a desired shape. In this example, the solid silicon 50 forms an annular element that is concentrically arranged on the substrate support structure 14 with the substrate 30. A portion of the surface of the solid silicon 50, including the side 50a away from the substrate support structure 14, is exposed to the plasma generated in the chamber. In this case, the surface 50b close to the substrate support structure 14 is not exposed to the generated plasma because the surface 50b is in contact with the substrate support structure 14 and the generated plasma cannot reach the surface. The effect of the solid silicon 50 on the etching of the substrate 30 will be discussed in more detail below.

[0073] In the method according to the invention, the exposed surface area of ​​the solid silicon is at least 1 times the area of ​​the surface of the substrate bearing the patterned mask that is not covered by the patterned mask. An example of calculating the exposure ratio of the exposed surface area of ​​the solid silicon to the area of ​​the surface bearing the mask (which is the surface to be etched) that is not covered by the mask will now be described. In this example, the substrate is formed as a circular wafer with a diameter of 76 mm, wherein the surface to be etched forms one side of the wafer and the patterned mask is carried on this side. The surface bearing the mask has π (0.5×76 mm) 2 =4536.5mm 2 The patterned mask covers 50% of the area of ​​the surface to be etched, so the area on the surface bearing the mask that is not covered by the mask is about 2268.2 mm 2 The solid silicon may be provided in the form of an annular disk as just described, having an outer diameter of 100 mm and an inner diameter (i.e. the diameter of the central opening) of about 76 mm, matching the diameter of the substrate. When placed on a substrate support structure (so that one side of the disk is exposed), the exposed surface area provided by the solid silicon in this form is approximately 3317 mm 2 Thus, in this example, the exposed area of ​​solid silicon is approximately 1.4 times the area of ​​the surface of the substrate bearing the mask that is not covered by the mask.

[0074] The tool 1 may also include a temperature control unit 16, such as a heater and / or cooling system, for regulating the processing temperature of the substrate support structure 14 (additional equipment for heating and / or cooling the plasma processing chamber and plasma source may be provided to assist in process control and / or maintain hardware stability). The temperature control unit 16 may be additionally configured to deliver a heat transfer gas (e.g., helium) to the substrate 30, for example, to a surface 30b of the substrate 30 proximate to the substrate support structure 14. The provision of a heat transfer gas improves control of substrate heating and cooling, and increases the rate of heat transfer between the substrate 30 and the substrate support structure 14.

[0075] The device operates according to instructions from a controller 20 (e.g., a programmable logic controller (PLC) or the like). In some cases, more than one controller may be provided, each of which controls one device or a subset of the devices. The controller is also connected to a user interface device, such as a computer workstation 25, for receiving input from a user and / or returning output.

[0076] exist Figure 1 In the figure, the data connections between various devices and the controller 20 are indicated by dotted lines. In practice, this can be implemented as a network such as a CANbus bridge, which has connections to each device as well as a user interface 25. The bus typically includes multiple network channels, which include one or more data channels, such as a serial data channel (e.g. RS485), and optionally, one or more power channels. The controller 20 issues commands via the bus, each command being addressed to one or more devices and including instructions for one or more process parameters to be implemented by the device in question. An example of a network protocol that can be used to issue commands for controlling devices is given in WO-A-2010 / 100425. Of course, as will be appreciated by those skilled in the art, many other network implementations are possible.

[0077] Figure 5(a) shows Figure 1 Detailed view of a substrate support structure 14 of FIG. The substrate 30 is arranged on a flat surface 14a of the substrate support structure and is coplanar with the silicon 50, which is arranged on the same surface laterally adjacent to the substrate (in this case concentric with it, as the silicon 50 has an annular form). In this example, there is a slight lateral spacing between the solid silicon 50 and the perimeter of the substrate 30, which is preferably less than 5 mm, and more preferably less than 1 mm.

[0078] FIG5( b) shows a detailed view of an alternative substrate support structure 140 on which the substrate 30 may be disposed in a preferred embodiment. The substrate support structure 140 includes a raised portion 141 on which the substrate 30 is disposed. The lateral extent of the raised portion 141 is less than the lateral extent of the substrate 30, so that the outer portion of the substrate 30 overhangs the perimeter of the raised portion 141. The solid silicon 501 has the same Figure 15(a) and is arranged concentrically with the substrate 30 and the raised portion on the surface of the substrate support structure 140 surrounding the raised portion. However, in this case, the diameter of the central opening of the annular solid silicon 501 is smaller than the lateral width of the substrate 30, so the suspended portion of the substrate 30 overlaps laterally with the portion of the solid silicon 501 near the raised portion 141. This arrangement is advantageous because the surface of the substrate support structure 140 is substantially completely covered by the substrate 30 and the solid silicon 501. In this example, the raised portion 141 is integral with the surrounding surface of the substrate support structure 140, but may alternatively be provided as a separate support element (e.g., a positioning plate).

[0079] Figure 2 An example of a suitable form in which solid silicon can be provided in an embodiment of the present invention is shown. The solid silicon includes two annular elements: an inner element 51 and an outer element 52, both of which are formed of solid silicon. The annular inner element 51 defines a central opening 51a and is preferably placed on a substrate support structure (such as the above-mentioned support structure 14) in use, which is concentrically arranged with a circular substrate in the direction shown. In a preferred embodiment of the method using the element, the diameter of the central opening 51a is such that all parts of the perimeter of the substrate surface to be etched are laterally spaced apart from the perimeter 51b of the central opening 51a by no more than 10mm, preferably no more than 5mm. For example, the substrate can be a circular wafer with a diameter of four inches, in which case the diameter of the central opening 51a can be no more than 10mm larger than four inches, preferably no more than 5mm. The inner element 51 has a stepped profile. The perimeter 51b of the central opening 51a is substantially circular, but defines a flat portion 51c, which corresponds in form to the removed portion of the circle.

[0080] The outer element 52 also has an annular shape with a central opening 52a. The perimeter 51b of the central opening 52a has a stepped profile, which is shaped to match the stepped profile of the inner element 51. When in use, the outer element 52 will be placed on the inner element 51 so that the stepped profile of the inner element 51 matches the profile of the central opening 52a of the outer element 52. The surface 52c shown is the lower surface of the element 52, and will therefore face the substrate support structure or other surface on which the inner element 51 is provided, and the opposite surface 52d (not visible) constitutes the upper surface of the element and is exposed to the plasma. The opposite surface has the same planar form as the lower surface 52c shown. In this case, most of the exposed surface area of ​​the solid silicon is constituted by the exposed surface of the outer element 52. Therefore, in an embodiment using this element, the opposite surface 52d preferably has a surface area that is at least 1 times the area of ​​the surface of the substrate that carries the mask and is not covered by the patterned mask. When the inner element 51 and the outer element 52 are placed concentrically with the substrate within their central openings 51a, 52a, the solid silicon laterally surrounds the perimeter of the substrate and the substrate is laterally located within the openings. Figure 1 When placed on a substrate support structure with a planar (eg, disk-shaped) substrate in the manner shown, the upper surface 52d of the outer element 52 constitutes a surface oriented parallel to the surface of the substrate carrying the patterned mask thereon and is exposed to the plasma generated in the plasma chamber.

[0081] Figure 3 is a flow chart showing the steps of a method according to an embodiment of the present invention. Figure 1 In step 303, the substrate is directly mounted on a substrate support structure (e.g., Figure 1 The electrostatic clamp described herein is placed on an electrostatic clamp (i.e., such that the substrate contacts and is restrained by a substrate support structure). The substrate comprises an indium-based semiconductor material, typically comprising at least 5% by weight of indium, which constitutes the surface of the substrate that carries the patterned mask, thereby defining the features to be etched. As previously described, examples of indium-based semiconductor materials include indium phosphide (InP) and its ternary and quaternary alloys. For example, the mask can be a layer of silicon dioxide (SiO2) deposited on the surface of the indium-based semiconductor material according to the desired pattern. Preferably, the surface on which the mask is carried has a minimum lateral dimension of at least 50 mm, more preferably at least 100 mm and / or at least 2000 mm 2 , preferably at least 4000mm 2 surface area.

[0082] Solid silicon is present inside the plasma processing chamber and is exposed to the plasma generated in the chamber, with the exposed surface area being at least 1 times the area of ​​the surface on which the mask is carried that is not covered by the patterned mask (but preferably, much larger than the area of ​​the portion of the surface on which the mask is carried, such as at least 3 times, 6.5 times, or 13 times). The solid silicon can be disposed on a substrate support structure, such as Figure 1 As shown, or laterally adjacent thereto, for example mounted in a separate fixture adjacent to the substrate support structure. Figure 2 The solid silicon element described is a suitable form of solid silicon and can be used as Figure 1 Shown is placed concentrically with the substrate.

[0083] In step 305, the etching gas mixture flows into the plasma treatment chamber. The etching gas mixture includes at least an inert gas (e.g., argon) and a chlorine-containing gas (e.g., chlorine molecule Cl2), which is configured to release chlorine radicals into the plasma generated from the etching gas mixture. Advantageously, the chlorine-containing gas flows into the plasma treatment chamber at a flow rate within the range of 2sccm to 20sccm, preferably within the range of 4sccm to 20sccm, and more preferably within the range of 5sccm to 15sccm, and the inert gas flows into the plasma treatment chamber at a flow rate within the range of 5sccm to 50sccm, preferably within the range of 20sccm to 50sccm, and more preferably within the range of 20sccm to 30sccm. The etching gas mixture may also include hydrogen, preferably, by volume, at a concentration not exceeding 25% of the etching gas mixture, and more preferably not exceeding 20%. As described above, the provision of hydrogen mitigates the rate at which solid silicon is etched, and therefore provides control of the rate of generation of silicon-containing substances in the plasma to be generated.

[0084] In step 307, a plasma is generated from the etching gas mixture, preferably at a power of 500W to 2500W, more preferably 750W to 1250W. When at least a portion of the surface of the solid silicon in the plasma processing chamber is exposed to the plasma, silicon-containing substances are generated from the solid silicon and enter the plasma. At the same time, a radio frequency (RF) bias with a power preferably in the range of 50W to 250W (more preferably in the range of 100W to 200W) is applied to the substrate support structure. The RF bias preferably has an amplitude in the range of 100V to 250V (preferably in the range of 150V to 200V). The plasma etches into the indium-based semiconductor material not covered by the patterned mask, thereby forming an etching feature in the indium-based semiconductor material. Preferably, during etching, the plasma processing chamber is under partial vacuum conditions, preferably with a pressure in the range of 1mTorr to 10mTorr (preferably in the range of 1mTorr to 4mTorr). At least during etching, the temperature of the substrate support structure is preferably controlled to be maintained in the range of 100 degrees Celsius (° C.) to 300° C., preferably in the range of 150° C. to 250° C., and more preferably in the range of 180° C. to 220° C. However, the temperature of solid silicon is generally not controlled and may reach temperatures above the upper limits of these ranges due to plasma heating. To control the temperature of the substrate, a heat transfer gas such as helium may be provided between the substrate support structure and the substrate, preferably such that the pressure of the heat transfer gas in contact with the substrate (commonly referred to as the "back pressure") is in the range of 1 Torr to 20 Torr, preferably in the range of 3 Torr to 15 Torr, and more preferably in the range of 5 Torr to 10 Torr. After etching is completed in step 307, the plasma may be quenched.

[0085] In some embodiments, particularly in embodiments where the method implements an industrial-scale production process, several substrates may be sequentially etched while continuously maintaining an internal (partial) vacuum in the plasma processing chamber. Thus, the method may include, at step 301, establishing a vacuum in the plasma processing chamber, and then, at step 303, mounting the substrate on a substrate support structure.

[0086] Then, after etching the substrate in step 307, the etched substrate can be removed from the substrate support structure in step 309, and in a further repetition of steps 303, 305 and 307, a new substrate is mounted on the substrate support structure and then etched. Additional repetitions of steps 301 and 309 and steps 303, 305 and 307 (one or more) are optional, as Figure 3 After etching is completed in each repetition of step 307, the plasma may be quenched before proceeding to step 309.

[0087] FIG. 4 (a) is an electron micrograph showing an indium phosphide 415 etched by a method according to an embodiment of the present invention. The etched indium phosphide is provided as a circular wafer having a diameter of about three inches (76 mm). The surface of the InP shown carries a patterned mask 411 of SiO2. In this example, the feature etched into the indium phosphide is a cylindrical mesa 401, 402, 403, 404, 405 defined by a silicon dioxide (SiO2) mask 411. In the region shown, the patterned mask forms a plurality of circular elements that define the lateral form of the etched mesa. The plasma used for etching is generated by an etching gas mixture containing chlorine molecules (Cl2) and argon (Ar). An inductively coupled plasma source is used to generate the plasma. The substrate with the etched InP shown in FIG. 4 (a) is directly mounted on a heated electrostatic fixture. During etching, an RF bias is applied to the surface of the electrostatic fixture on which the substrate is mounted. Helium is supplied to the surface of the substrate close to the electrostatic fixture to control the temperature of the substrate during etching. Solid silicon is provided on an electrostatic chuck adjacent to the wafer. The surface area of ​​the solid silicon exposed to the wafer is approximately 31,000 mm 2 , which is about 6.8 times the surface area of ​​the InP on which the mask 411 is carried before etching. About 50% of the surface on which the mask is carried is not covered by the mask, so in this example, the exposed area of ​​solid silicon is about 13.6 times the area of ​​the surface on which the mask is carried that is not covered by the mask.

[0088] FIG. 4( b) is an electron micrograph showing indium phosphide 435 etched by a method according to a comparative example of a method not within the scope of the present invention (due to the absence of solid silicon exposed to plasma), wherein the process parameters, etching gas composition, and mask 431 carried on the surface of the InP are the same as those for the method for etching indium phosphide shown in FIG. 4( a). Likewise, the InP is provided as a circular wafer having a diameter of 3 inches (76 mm), and the patterned SiO2 mask covers approximately 50% of the InP surface. The process for etching the material shown in FIG. 4( b) differs from the example of FIG. 4( a) in that the plasma processing chamber does not contain any solid silicon exposed to plasma. Instead of the silicon used in the example of FIG. 4( a), a quartz ring having a considerable surface area is placed on a substrate support structure adjacent to the substrate.

[0089] The process parameters for etching the substrates of FIG. 4( a) and FIG. 4( b) are listed in Table 1 below. The parameters listed are, in the order in which they appear in Table 1: the flow rate of Cl2, in standard cubic centimeters per minute (sccm); the flow rate of Ar, in sccm; the pressure in the plasma processing chamber, in millitorr (mTorr); the plasma source power, in watts (W); the RF bias voltage applied to the electrostatic chuck, in volts (V); the RF bias power, in W; the temperature to which the electrostatic chuck is heated, in degrees Celsius (°C); and the pressure of the heat transfer gas (helium) supplied to the substrate, in Torr.

[0090] Table 1

[0091]

[0092] Parameters related to the performance of the process for etching the substrate shown in Figures 4(a) and 4(b) and the physical properties of the resulting etched features were measured. These are listed in Table 2 below. The measurements listed are, in the order in which they appear in the table: the average vertical etch rate achieved during etching, in nanometers per minute (nm / min); the selectivity of the etching of InP relative to the SiO2 mask, which is given as the ratio of the InP etch rate to the SiO2 etch rate; the average angle of the sidewalls of the mesa relative to the imaginary bottom of the etched area, in degrees (°); the average depth of the microgrooves at the bottom of the wall of the etched mesa, in nanometers (nm); the average depth of the microgrooves relative to the height of the mesa, in percentage; the average height of the foot at the bottom of the etched feature relative to the height of the etched feature, in percentage; and the uniformity of the etch rate over the etched surface, which is determined by the variation of the etch rate over the substrate (given by the expression (R MAX -R MIN ) / 2σ, where R MAX is the maximum etch rate measured, R MIN is the minimum etch rate measured, and σ is the average etch rate) expressed as a percentage of the average etch rate.

[0093] It can be seen that the mesas 421, 422 formed in the example of FIG. 4(b) have deep microgrooves 421a, 422a at their bottom extending below the imaginary bottom 435 of the etched material. The relative depth of the microgrooves around the mesas in the wafer of FIG. 4(a) is more than 20 times smaller, which indicates that providing solid silicon exposed to plasma achieves an excellent reduction in microgrooves, wherein the microgrooves formed have a practically negligible relative depth. The results shown in Table 2 indicate that the presence of solid silicon exposed to plasma also improves the selectivity of the etching of InP relative to the SiO2 mask and the verticality of the sidewalls of the almost completely vertical mesas.

[0094] Table 2

[0095]

[0096]

[0097] Figure 6 Another example of how to arrange the substrate, substrate support structure and solid silicon in an embodiment of the present invention is shown. Here, the substrate support structure 160 includes an electrostatic clamp 161, on which the substrate 30 (which includes an indium-based semiconductor material) is placed. An electrically insulating element in the form of a quartz ring 62 is provided on the surface of the substrate support structure 160a adjacent to (and concentric with) the substrate 30. The solid silicon 60 has a planar, annular form, such as the example shown in Figures 5(a) and 5(b), with a central hole arranged concentrically with the substrate 30 and supported on the quartz ring 62. In this arrangement, the solid silicon 60 is separated from the substrate support structure 160 by a gap 63 (which will be a vacuum gap when the chamber is evacuated in use). In this arrangement, the solid silicon 60 is electrically isolated from the substrate support structure 160 and the substrate 30, so the power of the RF bias signal applied to the substrate 30 will be completely concentrated in the area of ​​the substrate 30. This promotes a high etching rate.

[0098] exist Figure 6 In the arrangement, preferably, the electrically insulating element 62 and the solid silicon disk 60 are arranged so that the upper surface of the solid silicon exposed to the plasma is at a height of 0 mm to 5 mm, preferably 0 mm to 3 mm, more preferably 1.5 mm to 2 mm above the surface 30a of the substrate 30 carrying the patterned mask and in a direction perpendicular to the surface of the substrate.

[0099] Figure 7 7 is a photograph of a substrate support structure 760 including an electrostatic chuck 761 on which a substrate may be placed when in use. The electrostatic chuck 762 is surrounded by a recess 762 which may accommodate a quartz ring or other annular electrically insulating element, such as a reference Figure 6 An electrically insulating element may support a solid silicon disk on a substrate support structure 760 and a substrate comprising an indium-based semiconductor material may be placed on an electrostatic chuck 761 in use.

[0100] Figure 8(a) to Figure 12(b) is a diagram showing the use of a method according to an embodiment of the present invention and using Figure 6Electron micrographs of the results of experiments conducted on an arrangement of solid silicon shown in . These experiments will now be described. In each pair of images (e.g., Figures 8(a) and 8(b)), the "(a)" figure (e.g., Figure 8(a)) shows multiple cylindrical features etched, while the "(b)" figure (e.g., Figure 8(b)) shows a close-up cross-sectional view of an etched feature. Although the parameters listed in Table 3 are the same for Figures 9(a) and 9(b) as for Figures 10(a) and 10(b), the substrate in the examples of Figures 9(a) and 9(b) has a larger exposed surface area (approximately 90%) than the substrate in the examples of Figures 10(a) and 10(b) where the exposed surface area is approximately 50%.

[0101] To produce Figure 8(a) to Figure 12(b) The etching parameters performed to show the results are listed in Table 3.

[0102] Table 3

[0103]

[0104] Figure 8(a) to Figure 12(b) The experimental results are shown in Table 4.

[0105] Table 4

[0106]

[0107]

[0108] From the results in Table 4, we can see that Figure 6 The arrangement shown achieves good etch rates with virtually no micro-trenching.

[0109] Fig.13 Shown in Figure 6 Detailed view of an arrangement of a substrate 1301, an electrically insulating element 1302, and a solid silicon disk 1303 that may be arranged in an embodiment of the device shown. The electrically insulating element has an upper surface 1302a that is located 0.675 mm above the upper surface 1301a of the substrate 1300 in a direction perpendicular to the plane of the substrate. The upper surface 1303a of the solid silicon disk 1303 is 1.825 mm in height relative to the upper surface 1301a of the substrate 1300.

Claims

1. A method of etching into an indium-based semiconductor material, the method comprising: mounting a substrate comprising the indium-based semiconductor material directly on a substrate support structure in a plasma processing chamber, wherein the indium-based semiconductor material forms a surface of the substrate, the surface carrying a patterned mask and arranged away from the substrate support structure, The plasma processing chamber comprises solid silicon, the solid silicon is arranged to be exposed to the plasma generated in the plasma processing chamber, and the exposed surface area of ​​the solid silicon is at least 1 times the area of ​​the surface of the substrate bearing the patterned mask that is not covered by the patterned mask; the method further comprises: establishing a flow of an etching gas mixture into the plasma processing chamber, the etching gas mixture comprising an inert gas and a chlorine-containing gas configured to release chlorine radicals when present in a plasma generated by the etching gas mixture; and A plasma is generated from the etching gas mixture in the plasma processing chamber, the solid silicon is exposed to the plasma, thereby generating silicon-containing species from the solid silicon in the plasma, and a radio frequency (RF) bias is simultaneously applied to the substrate support structure, whereby portions of the surface carrying the patterned mask that are not covered by the patterned mask are etched by the plasma including the generated silicon-containing species to form one or more etched features in the indium-based semiconductor material.

2. The method according to claim 1, wherein: The exposed surface area of ​​the solid silicon is at least 3 times, preferably at least 6.5 times, more preferably at least 13 times, the area of ​​the surface of the substrate carrying the patterned mask that is not covered by the patterned mask.

3. A method according to any one of the preceding claims, wherein: The solid silicon is disposed on or laterally adjacent to the substrate support structure.

4. A method according to any one of the preceding claims, wherein: The solid silicon laterally surrounds at least a portion of the perimeter of the surface of the substrate bearing the patterned mask, preferably the solid silicon laterally surrounds the entire perimeter of the surface of the substrate bearing the patterned mask.

5. A method according to any one of the preceding claims, wherein: The solid silicon is shaped to define an opening therethrough, wherein the substrate mounted on the substrate support structure is laterally located within the opening.

6. The method according to claim 5, wherein: The solid silicon forms a ring, preferably an annular disk, which defines the opening.

7. A method according to any one of the preceding claims, wherein: The solid silicon is electrically isolated from the substrate support structure and is electrically isolated from the substrate when the substrate is mounted on the substrate support structure.

8. The method according to claim 7, wherein: The electrical isolation is provided by an electrically insulating element arranged between the solid silicon and the substrate support structure so as to space the solid silicon apart from the substrate support structure and the substrate when mounted on the substrate support structure.

9. The method according to claim 8, wherein: The electrically insulating element is disposed on the substrate support structure such that the electrically insulating element is laterally adjacent to the substrate when the substrate is mounted on the substrate support structure, and wherein the solid silicon is supported by the electrically insulating element.

10. The method according to claim 8 or 9, wherein: The solid silicon has a central hole arranged concentrically with the substrate when the substrate is mounted on the substrate support structure; and wherein the electrically insulating element is arranged to prevent the plasma from entering the space between the solid silicon and the substrate support structure via the central hole.

11. The method according to any one of claims 8 to 10, wherein: The electrically insulating element has an annular form and is arranged concentrically with the substrate when the substrate is mounted on the substrate support structure.

12. The method according to any one of claims 8 to 11, wherein: The electrically insulating element is made of a dielectric material, preferably quartz.

13. A method according to any one of the preceding claims, wherein: Each portion of the perimeter of the surface on which the mask is carried is laterally spaced no more than 5 mm, preferably no more than 1 mm, from the exposed surface of the solid silicon.

14. A method according to any one of the preceding claims, wherein: The solid silicon forms a substantially planar surface that is exposed to the generated plasma.

15. A method according to any one of the preceding claims, wherein: The solid silicon forms a surface oriented substantially parallel to the surface of the substrate bearing the patterned mask and is exposed to the generated plasma.

16. A method according to any one of the preceding claims, wherein: The solid silicon forms a surface that is arranged substantially in the plane of the surface of the substrate carrying the mask and is exposed to the generated plasma.

17. A method according to any one of the preceding claims, wherein: The surface of the substrate carrying the mask has a smallest lateral dimension of at least 50 mm, preferably at least 100 mm.

18. A method according to any one of the preceding claims, wherein: The surface of the substrate carrying the mask has a surface area of ​​at least 2000 mm 2 , preferably at least 4000mm 2 surface area.

19. A method according to any one of the preceding claims, wherein: The method further comprises controlling the temperature of the substrate support structure during the etching, preferably such that the temperature of the substrate is maintained in the range of 100 degrees Celsius to 300 degrees Celsius, preferably in the range of 150 degrees Celsius to 250 degrees Celsius, more preferably in the range of 180 degrees Celsius to 220 degrees Celsius.

20. The method of claim 19, further comprising supplying a heat transfer gas between the substrate and a substrate support during the etching to control the temperature of the substrate, the heat transfer gas preferably being helium.

21. The method according to claim 20, wherein: The pressure of the heat transfer gas in contact with the substrate is in the range of 1 Torr to 20 Torr, preferably in the range of 3 Torr to 15 Torr, and more preferably in the range of 5 Torr to 10 Torr.

22. The method of any preceding claim, further comprising controlling the temperature of the solid silicon such that the temperature of the solid silicon remains above 150 degrees Celsius and / or below 250 degrees Celsius during the etching.

23. A method according to any one of the preceding claims, wherein: The substrate support structure is an electrostatic clamp.

24. A method according to any one of the preceding claims, wherein: The substrate support structure includes a raised portion that is raised relative to a surrounding surface of the substrate support structure, wherein the substrate is disposed on the raised portion when the substrate is mounted on the substrate support structure.

25. The method according to claim 24, wherein: The substrate overhangs a perimeter of the raised portion.

26. The method according to claim 25, wherein: The solid silicon is disposed on a peripheral surface of the substrate support structure, preferably laterally overlapping an overhanging portion of the substrate.

27. A method according to any one of the preceding claims, wherein: The indium-based semiconductor material includes at least 5% by weight of indium.

28. A method according to any one of the preceding claims, wherein: The indium-based semiconductor material is indium phosphide or a ternary alloy or a quaternary alloy thereof.

29. A method according to any one of the preceding claims, wherein: The mask includes one or more of silicon dioxide, silicon nitride and metal.

30. A method according to any one of the preceding claims, wherein: The inert gas is a rare gas, preferably argon (Ar).

31. A method according to any one of the preceding claims, wherein: The chlorine-containing gas is chlorine molecule (Cl2), boron trichloride (BCl3) or silicon tetrachloride (SiCl4).

32. A method according to any one of the preceding claims, wherein: The chlorine-containing gas flows into the plasma processing chamber at a rate in the range of 2 sccm to 20 sccm, preferably in the range of 4 sccm to 20 sccm, more preferably in the range of 5 sccm to 15 sccm, and / or The inert gas flows into the plasma processing chamber at a rate in a range of 5 sccm to 50 sccm, preferably in a range of 20 sccm to 50 sccm, and more preferably in a range of 20 sccm to 30 sccm.

33. A method according to any one of the preceding claims, wherein: The ratio of the inert gas to the chlorine-containing gas in the etching gas mixture is in the range of 1:1 to 13:1, preferably in the range of 1:1 to 5:1, preferably in the range of 2:1 to 3:

1.

34. A method according to any one of the preceding claims, wherein: The etching gas mixture comprises hydrogen, wherein preferably, the volume proportion of hydrogen in the etching gas mixture is not greater than 25%, preferably not greater than 20%.

35. A method according to any one of the preceding claims, wherein: The RF bias has a power in the range of 50W to 250W, preferably in the range of 100W to 200W.

36. A method according to any one of the preceding claims, wherein: During the etching, the pressure in the plasma chamber is in the range of 1 mTorr to 10 mTorr, preferably in the range of 1 mTorr to 4 mTorr.

37. A method according to any one of the preceding claims, wherein: The plasma is generated by an inductively coupled plasma source.

38. A method according to any one of the preceding claims, wherein: The plasma is generated at a power in the range of 500W to 2500W, preferably in the range of 750W to 1500W.

39. A method according to any one of the preceding claims, wherein: The amplitude of the RF bias voltage is in the range of 100V to 250V, preferably in the range of 150V to 200V.

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