Power semiconductor device with shallow conductive region

Abstract

A power transistor device includes a drift layer having a first conductivity type and a mesa on the drift layer. The mesa includes a channel region on the drift layer, a source layer on the channel region, and a gate region in the mesa adjacent to the channel region. The channel region and the source layer have a first conductivity type, and the gate region has a second conductivity type opposite the first conductivity type. The channel region includes a deep conductive region and a shallow conductive region between the deep conductive region and the gate region. The deep conductive region has a first doping concentration, and the shallow conductive region has a second doping concentration greater than the first doping concentration.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. In particular, the present disclosure relates to junction field effect transistor (JFET) power semiconductor devices. Background Art

[0002] A conventional n-channel vertical JFET structure 10 is shown in FIG. 1A . The vertical JFET structure 10 includes an n+ drain layer 26, and an n- drift layer 15 is formed on the n+ drain layer 26. An n-type channel region 24 is located on the drift layer 15, and an n+ source layer 16 is located on the channel region 14. An n++ source contact layer 38 is located on the n+ source layer. A drain ohmic contact 28 is located on the drain layer 26, and a source ohmic contact 40 is located on the source contact layer 38. The channel region 24, the source layer 16, and the source contact layer 38 are provided as part of the mesa 12 above the drift layer 15. A p+ gate region 18 is provided adjacent to the channel region 24 as part of the mesa 12. A p++ shielding region 32 is provided adjacent to the gate region 18, and a gate ohmic contact 36 is formed on the shielding region 32. A passivation layer 42 is located on the gate ohmic contact 36 and the shielding region 32 .

[0003] FIG. 1A illustrates half of a vertical JFET unit cell structure 10. The entire structure is symmetrical about an axis 30 and includes two gate regions 18 as part of a mesa 12 on opposite sides of a channel region 24. That is, only a half cross section of a JFET device is shown in FIG. 1A. The depicted portion can be mirrored around a vertical axis 30 to obtain the full pitch of the unit cell of the device. A full JFET device includes many such unit cells. For clarity, FIG. 1C illustrates the entire JFET unit cell 10, which includes half cells 10A, 10B sharing the same mesa 12.

[0004] Referring again to FIG. 1A , the channel of the vertical JFET structure 10 is formed within the mesa 12. The breadth of the channel in the n-type region is in the horizontal direction away from the pn junction between the gate region 18 and the channel region 24. The channel width is in the plane of FIG. 1A , and the channel length is in the vertical direction. Such a vertical JFET structure with a short channel length may also be referred to as a static induction transistor (SIT). In a SIT, the channel length is selected based on a tradeoff between low on-resistance (short channel) in the on state and resistance to drain induced barrier lowering (DIBL) in the off state. A conventional p-channel JFET may have a similar structure, but the conductivity type is inverted relative to that shown in FIG. 1A .

[0005] In operation, the conductivity between the source layer 16 and the drain layer 26 is modulated by applying a reverse bias to the gate region 18 relative to the source layer 16. To turn off an n-channel device such as the JFET structure 10, a negative gate-to-source voltage (or, simply, gate voltage (V GS )) is applied to the gate region 18. When no voltage is applied to the gate region 18, charge carriers are able to flow freely from the source layer 16 through the channel region 24 and the drift layer 15 to the drain layer 26. In contrast, referring to FIG. 1B , when a reverse bias is applied to the gate region 18, a depletion region 33 is formed at the interface between the gate region 18 and the surrounding n-type region (that is, the channel region 24 and the source layer 16). The depletion region 33 may extend into the drift layer 15. As the name implies, the depletion region 33 depletes charge carriers. When the magnitude of the reverse bias applied to the gate region 18 is large enough, the depletion region extends to cover the entire lateral width of the channel region 24, thereby pinching off the channel region 24 and hindering or blocking the flow of charge carriers between the source layer 16 and the drift layer 15. As indicated in FIG. 1A , in the mesa JFET structure 10, the “lateral width” of the channel region 24 is in the same direction as the width of the mesa 12. Therefore, the lateral width of the mesa 12 defines the lateral width of the channel region 24 .

[0006] The threshold voltage of a JFET device refers to the gate voltage at which the device begins to conduct. Because the pinch-off of the channel region 24 occurs when the gate voltage is large enough to allow the depletion region 33 to span the entire channel layer 24, the threshold voltage of the device is very sensitive to the lateral width of the channel region 24. As shown in the figure, in the conventional vertical JFET structure 10 shown in Figures 1A and 1B, the lateral width of the channel region 24 is determined by the width of the mesa 12. The width of the mesa 12 is determined by the manufacturing process (that is, masking and etching process) used to form the mesa 12. This manufacturing process is subject to various tolerances. Manufacturing variations within these tolerances can result in significant variations in the threshold voltage that vary from device to device, even within the same manufacturing batch. Summary of the invention

[0007] A power transistor device according to some embodiments includes a drift layer having a first conductivity type and a table on the drift layer. The table includes a channel region on the drift layer, a source layer on the channel region, and a gate region in the table adjacent to the channel region. The channel region and the source layer have a first conductivity type, and the gate region has a second conductivity type opposite to the first conductivity type. The channel region includes a deep conductive region and a shallow conductive region between the deep conductive region and the gate region. The deep conductive region has a first doping concentration, and the shallow conductive region has a second doping concentration greater than the first doping concentration.

[0008] In some embodiments, the shallow conductive region extends between the drift layer and the source layer in a vertical direction, and wherein the deep conductive region extends between the drift layer and the source layer in a vertical direction.

[0009] The channel region may include silicon carbide, and the shallow conductive region may have a conductivity greater than about 1E17 cm -3 The deep conductive region may have a doping concentration of less than about 1E17 cm -3 of doping concentration.

[0010] The channel region may include silicon carbide, and the shallow conductive region may have a thickness of approximately 3E17 cm -3 to about 5E18 cm -3 The deep conductive region may have a doping concentration of approximately 1E16 cm -3 to about 5E16 cm - 3 In some embodiments, the shallow conductive region may have a doping concentration of approximately 1E18 cm -3 The doping concentration of the deep conductive region may be approximately 1.5E16 cm -3 The shallow conductive region may have a doping concentration at least about 10 times greater than a doping concentration in the deep conductive region.

[0011] The shallow conductive region may have a graded doping profile that is graded in a lateral direction that is perpendicular to a direction in which carriers flow through the channel region when the vertical junction field effect device is in an on state.

[0012] The shallow conductive region may have a lateral width of about 0.1 to 0.3 micrometers in a lateral direction perpendicular to a direction in which carriers flow through the channel region when the vertical junction field effect device is in an on state.

[0013] The shallow conductive region may have a lateral width in a lateral direction perpendicular to the direction of carrier flow through the channel region when the vertical junction field effect device is in an on state, and the lateral width may be about one third of the half width of the mesa. The shallow conductive region may include an implanted region within the mesa.

[0014] The power transistor device may further include a breakdown adjustment region between the shallow conductive region and the gate region. The breakdown adjustment region may have a first conductivity type and may have a third doping concentration that is less than the second doping concentration of the shallow conductive region.

[0015] The vertical junction field effect device exhibits a variation in threshold voltage as a function of mesa width of less than 20 V / micron (in some embodiments less than 10 V / micron, and in some embodiments less than 5 V / micron).

[0016] The power transistor device may be a junction field effect transistor (JFET).The drift layer, the channel region and the gate region may include silicon carbide.

[0017] The lateral width of the shallow channel region in a lateral direction may be independent of the width of the mesa in a lateral direction, which may be perpendicular to the direction of current flow when the device may be in an on-state.

[0018] The lateral width of the deep channel region in a lateral direction may be proportional to the width of the mesa in a lateral direction that is perpendicular to the direction of current flow when the device is in an on-state.

[0019] The gate region may include a first gate region, and the shallow conductive region may include a first shallow conductive region, and the power transistor device may further include a second gate region opposite to the first gate region in the mesa, wherein the channel region is located between the first gate region and the second gate region. The device may include a second shallow conductive region located between the deep conductive region and the second gate region in the channel region. The second shallow conductive region may have a third doping concentration greater than the first doping concentration of the deep conductive region.

[0020] The first gate region may be surrounded by a breakdown adjustment region in the mesa so that the breakdown region is located above, below and on a side of the gate region adjacent to the channel region in the mesa. The breakdown adjustment region may have a first conductivity type and a third doping concentration, and the third doping concentration may be less than the second doping concentration of the shallow conductive region.

[0021] The deep conductive region and the channel region may be arranged on opposite sides of the shallow conductive region in a lateral direction, the lateral direction being perpendicular to a direction of current flow in the power transistor device.

[0022] A power transistor device according to some embodiments includes: a drift layer having a first conductivity type; a mesa located on the drift layer, the mesa including a channel region on the drift layer and a source layer on the channel region; and a gate region located on one side of the channel region in the mesa. The channel region and the source layer have a first conductivity type. The gate region has a second conductivity type opposite to the first conductivity type. The vertical junction field effect device exhibits a threshold voltage variation of less than 20 V / micrometer as a function of the mesa width.

[0023] A method for forming a power transistor device includes: providing a drift layer having a first conductivity type; forming a source layer having the first conductivity type on the drift layer; forming a mesa by selectively etching a portion of the source layer and the drift layer to form a trench, the trench extending into the drift layer and defining a mesa adjacent to the trench, the mesa having a mesa sidewall adjacent to the trench; forming a shallow conductive region extending between the drift layer and the source layer in the mesa; and forming a gate region having a second conductivity type in the mesa, wherein the gate region may be adjacent to a channel region in the mesa. The channel region includes a deep conductive region adjacent to the shallow conductive region, and the shallow conductive region may be located between the deep conductive region and the gate region, and the shallow conductive region may have a higher doping concentration than the deep conductive region.

[0024] Forming the shallow conductive region may include performing oblique angle ion implantation of first conductivity type dopant ions in a mesa sidewall at a first implantation energy to form the shallow conductive region in the mesa, wherein a portion of the drift layer in the mesa forms a deep conductive region adjacent to the shallow conductive region.

[0025] Forming a gate region may include: implanting second conductive type dopant ions into the sidewalls of the mesa at a second implantation energy that may be lower than the first implantation energy to form a gate region in the mesa, wherein a shallow conductive region may be located between the gate region and a deep conductive region, and wherein the second conductive type is opposite to the first conductive type.

[0026] Forming the mesa may include forming an etching mask on the source layer and etching the source layer and the drift layer to form the mesa in a region below the etching mask. Forming the shallow conductive region may include implanting first conductivity type dopant ions into the mesa sidewalls using the etching mask as an implantation mask.

[0027] The etching mask may include SiO 2 Etching mask and SiO 2 The method may further include: forming a second etching mask on the mesa and the groove; patterning the second etching mask to expose the mesa and the bottom surface of the groove adjacent to the mesa and expose one or more surface areas in the edge region of the device; and implanting the second conductive type dopant ions into the mesa sidewall and the junction termination region at a second implantation energy lower than the first implantation energy to form a gate region in the mesa and an edge termination region in the edge region. The shallow conductive region is located between the gate region and the deep conductive region, and the second conductive type is opposite to the first conductive type.

[0028] The second etching mask may include SiO 2 , and patterning the second etch mask may include selectively etching the second etch mask using the silicon nitride mask as an etch stop layer.

[0029] The power transistor device according to some embodiments includes: a drift layer having a first conductivity type; a mesa located on the drift layer, the mesa including a channel region on the drift layer and a source layer on the channel region, the channel region and the source layer having the first conductivity type; and a gate region adjacent to the channel region in the mesa, the gate region having a second conductivity type opposite to the first conductivity type. A breakdown adjustment region may be provided in the mesa between the channel region and the gate region, the breakdown adjustment region having the first conductivity type. The channel region may have a first doping concentration, and wherein the breakdown adjustment region may have a second doping concentration, the second doping concentration may be less than the first doping concentration.

[0030] The channel region may include a deep conductive region and a shallow conductive region between the deep conductive region and the breakdown adjustment region. The shallow conductive region may have a first doping concentration, and the deep conductive region may have a third doping concentration, which may be less than the first doping concentration. The breakdown adjustment region surrounds the gate region in the mesa. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are included to provide a further understanding of the present disclosure, are incorporated in and constitute a part of this specification, illustrate various aspects of the present disclosure, and together with the detailed description, serve to explain the principles of the present disclosure. No attempt is made to show the structural details of the present disclosure in more detail than may be necessary for a basic understanding of the present disclosure and the various ways in which the present disclosure may be implemented. In the drawings:

[0032] 1A, 1B and 1C illustrate conventional JFET device structures.

[0033] Figure 2A and 2B A JFET device structure according to some embodiments is illustrated.

[0034] Figure 2C A channel doping profile of a JFET device structure is illustrated in accordance with some embodiments.

[0035] Figure 3 Graphs illustrating the channel doping profile and associated electric field strength and electron energy of a JFET device structure according to some embodiments.

[0036] Figures 4A to 4I Operations for fabricating a JFET device structure are illustrated in accordance with some embodiments.

[0037] Figure 5A Operations for fabricating a JFET device structure are illustrated in accordance with further embodiments.

[0038] Figure 5B A JFET device structure according to another embodiment is shown.

[0039] Figure 5C , 5D and 5E diagram Figure 5B Some possible channel doping profiles for the JFET device structure.

[0040] Figure 6 An exemplary circuit including a JFET device is shown in accordance with some embodiments.

[0041] Figure 7 is a flow chart illustrating operations for processing a JFET device, according to some embodiments. DETAILED DESCRIPTION

[0042] Embodiments of the inventive concept are more fully explained with reference to the non-limiting aspects and examples described and / or illustrated in the accompanying drawings and detailed in the following description. It should be noted that, even if not explicitly noted herein, those skilled in the art will appreciate that the features illustrated in the drawings are not necessarily drawn to scale, and that the features of some embodiments may be adopted together with other aspects. Descriptions of known components and processing techniques may be omitted so as not to unnecessarily obscure the various aspects of the present disclosure. The examples used herein are intended only to facilitate an understanding of the manner in which the present disclosure may be implemented, and to further enable those skilled in the art to implement various aspects of the present disclosure. Therefore, the examples and aspects herein should not be interpreted as limiting the scope of the present disclosure, which is defined solely by the appended claims and applicable laws. In addition, it is noted that similar reference numerals always represent similar parts in several views of the accompanying drawings.

[0043] It will be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] It will be understood that when an element (such as a layer, region, or substrate) is referred to as being "on" or "extending onto" another element, it can be directly on or directly extending onto the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements. Similarly, it will be understood that when an element (such as a layer, region, or substrate) is referred to as being "on" or "extending over" another element, it can be directly on or directly extending over the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" or "extending directly over" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0045] Relative terms, such as, "below" or "above" or "up" or "lower" or "horizontal" or "vertical", may be used herein to describe the relationship of one element, layer or region to another element, layer or region, as shown in the figures. It will be understood that these terms and the terms discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0046] The terms used herein are only used for the purpose of describing specific aspects and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "include" and / or "comprise" when used herein specify the presence of stated features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art.

[0048] Although JFET devices are sometimes referred to as static induction transistors, the term JFET will be used in the following description. However, it will be understood that the embodiments described herein may be applied to any device that uses a depletion region to modulate the conductivity of a channel in a mesa.

[0049] Power electronic devices manufactured using silicon carbide (SiC) can have high blocking voltages. For power devices with blocking voltages in the range of 600V-1000V, SiC JFETs have one-half to one-third the chip area compared to SiC MOSFETs. SiC JFETs can also be manufactured using simpler manufacturing processes than MOSFETs, which can result in lower manufacturing costs. In addition, SiC JFET devices do not have SiO 2 -SiC interface. This can increase device reliability because the oxide layer can break down under high voltage operation. JFET devices have the disadvantage of being a normally-on device. However, in power applications (such as high reliability Si-SiC heterojunction integrated circuits), its advantages can outweigh its disadvantages.

[0050] In a vertical SiC JFET device optimized for low resistance, it is desirable for the device to have a predictable threshold voltage for circuit performance. However, as described above, the threshold voltage of a vertical JFET is highly sensitive to the width of the mesa of the device. Some embodiments described herein are based on the recognition that the sensitivity of the threshold voltage to the mesa width in a vertical JFET device is a function of the conductivity of the portion of the channel whose lateral width varies with the mesa width. By providing a stepped or graded doping profile in the channel region, some embodiments described herein can reduce the sensitivity of the threshold voltage to variations in the mesa width.

[0051] For example, in some embodiments, the channel is divided into a highly conductive shallow channel region near the gate region and a less conductive deep channel region. In some embodiments, the shallow channel can be self-aligned with the edge of the mesa, so that only the lateral width of the less conductive deep channel region is sensitive to the mesa width. This can reduce the sensitivity of the threshold voltage of the device to the mesa width. Since the conductivity of the channel is dominated by the highly conductive shallow channel region, the total median conductivity of the channel itself can remain constant or nearly constant. By appropriately selecting the doping concentrations of the shallow channel region and the deep channel region, some embodiments can reduce the sensitivity of the threshold voltage to the mesa width by more than an order of magnitude.

[0052] Thus, some embodiments may avoid the traditional tradeoff between the conductivity of the JFET channel and the sensitivity of the threshold voltage to mesa width variations. That is, in traditional structures, the more conductive the channel is made, the more sensitive it is to mesa width variations. Thus, some embodiments may allow the mesa width to be narrowed, and also allow the channel region to be more highly doped to increase the conductivity while reducing the sensitivity of the threshold voltage to the mesa width.

[0053] As shown in FIGS. 1A and 1B , the JFET channel of the conventional structure has a substantially constant doping to have a uniform conductivity regardless of the lateral width of the channel. According to some embodiments described herein, the JFET channel doping is graded so that the deeper portion of the JFET channel near the center of the mesa is more lightly doped, while the shallower portion of the JFET channel (closer to the gate junction) is more heavily doped. Additionally, in some embodiments, the doping of the shallower portion of the JFET channel may be self-aligned with the edge of the mesa. These aspects combine to make the threshold voltage of the JFET device insensitive to variations in the width of the mesa while not subjecting it to a tradeoff in channel conductivity.

[0054] Figure 2AAn n-channel vertical JFET structure 100 is illustrated in accordance with some embodiments. The vertical JFET structure 100 includes an n+ drain layer 26, and an n- drift layer 15 is formed on the n+ drain layer 26. An n-type channel region 114 is located on the drift layer 15, and an n+ source layer 16 is located on the channel region 114. An n++ source contact layer 38 is located on the n+ source layer. A drain ohmic contact 28 is located on the drain layer 26, and a source ohmic contact 40 is located on the source contact layer 38. The channel region 114, the source layer 16, and the source contact layer 38 are provided in the mesa 12 above the drift layer 15. A p+ gate region 18 is provided adjacent to the channel region 24 as part of the mesa 12. A p++ shielding region 32 is provided adjacent to the gate region 18, and a gate ohmic contact 36 is formed on the shielding region 32. Passivation layer 42 covers gate ohmic contact 36 and shielding region 32. Optional sidewall protection layer 61 is located on the exposed sidewalls of mesa 12. Sidewall protection layer 61 may have a thickness of, for example, 20 to 30 nm, 23 to 27 nm in some embodiments, and 25 nm in some embodiments.

[0055] In some embodiments, the doping concentration of the channel region 114 may be graded along the width of the mesa 12 (corresponding to the lateral width of the channel region 114 ) such that the channel region 114 has a lower doping concentration near the center of the mesa 12 and a higher doping concentration near the gate region 18 .

[0056] For example, in Figure 2A In the embodiment illustrated in FIG. 1 , the channel region 114 has a two-step graded profile so that it is divided into a deep conductive region 122 and a shallow conductive region 124 between the deep conductive region 122 and the gate region 18. The channel region 114 includes both the shallow conductive region 124 and the deep conductive region 122 adjacent to the gate region 18, and both the shallow conductive region 124 and the deep conductive region 122 may extend in a vertical direction between the drift layer 15 and the source layer 16. The shallow conductive region 124 extends in a vertical direction (e.g., in the y direction, or in the direction of carrier flow, such as Figure 2A 100) extends between the drift layer 15 and the source layer 16, and the deep conductive region 122 extends in a vertical direction between the drift layer 15 and the source layer 16. Therefore, the deep conductive region 122 and the channel region 18 are arranged on opposite sides of the shallow conductive region 124 in a lateral direction (e.g., x-direction), which is perpendicular to the direction of current flow in the device 100.

[0057] The deep conductive region 122 is provided near the center of the mesa 12 and has a doping concentration that is less than the doping concentration of the shallow conductive region 124. For example, the shallow conductive region 124 may have a doping concentration that is at least about 10 times greater than the doping concentration of the deep conductive region 122. In some cases, the shallow conductive region 124 may have a doping concentration that is at least about 20 times greater than the doping concentration of the deep conductive region 122, and in some cases, at least about 100 times greater than the doping concentration of the deep conductive region 122.

[0058] In some embodiments, the shallow conductive region 124 has a thickness of approximately 1E17 cm -3 or greater doping concentrations, such as about 1E17 cm -3 and 1E19 cm -3 In some embodiments, the shallow conductive region 124 has a doping concentration of approximately 3E17 cm -3 and 5E18 cm -3 In some embodiments, the shallow conductive region 124 has a doping concentration of approximately 1E18 cm -3 of doping concentration.

[0059] In some embodiments, the deep conductive region 122 has a thickness of approximately 5E15 cm -3 and 1E17 cm -3 In some embodiments, the deep conductive region 122 has a doping concentration of approximately 5E16 cm -3 or a smaller doping concentration, such as about 5E15 cm -3 and 5E16 cm -3 In some embodiments, the deep conductive region 122 has a doping concentration of approximately 1.5E16 cm -3 of doping concentration.

[0060] In some embodiments, the shallow conductive region has a doping concentration at least about 10 times greater than the doping concentration of the deep conductive region, and in some cases, at least about 100 times greater than the doping concentration of the deep conductive region.

[0061] Since the shallow conductive region 124 may be formed via ion implantation into a portion of an epitaxial layer forming the drift layer 15 , the deep conductive region 122 may have the same doping concentration as the drift layer 15 in some embodiments.

[0062] In some embodiments, the shallow conductive region 124 may be Figure 2A The vertical JFET 100 has a lateral width of about 0.1 to 0.3 microns in the x-direction shown in FIG. 1 , and a lateral direction perpendicular to the direction in which carriers flow through the channel region 114 when the vertical JFET 100 is in the on state ( Figure 2AIn some embodiments, the shallow conductive region has a lateral width in a lateral direction perpendicular to a direction in which carriers flow through the channel region when the vertical junction field effect device is in an on state, the lateral width being approximately one third of the half-width of the mesa.

[0063] Although illustrated as an n-channel device, it will be appreciated that the JFET device structure 100 can be formed as a p-channel device by switching the n-type layers to p-type, and vice versa.

[0064] In some embodiments, vertical JFET 100 according to some embodiments can exhibit a variation in threshold voltage as a function of mesa width of less than 20 V / micrometer. In some embodiments, vertical JFET 100 according to some embodiments can exhibit a variation in threshold voltage as a function of mesa width of less than 10 V / micrometer (and in some embodiments less than 5 V / micrometer).

[0065] Although the two-step graded doping profile is shown in Figure 2A , but the channel region 114 may have other doping profiles. For example, various possible doping profiles are shown in Figure 2C middle, Figure 2C A graph including various channel doping profiles across the entire mesa width according to some embodiments. Figure 2C , the total channel width is 2W. Therefore, each channel region 114 in one half of the mesa has a width W.

[0066] Figure 2C (a) illustrates a two-step doping profile, where each half of the mesa includes a more heavily doped shallow conductive region 124 and a more lightly doped deep conductive region 122 . Figure 2C (b) illustrates a three-step doping profile in the channel region 114 . Figure 2C (c) illustrates a doping profile in which the interface between the shallow conductive region 124 and the deep conductive region 122 grades from a higher doping concentration to a lower doping concentration. Figure 2C The doping profiles illustrated in are exemplary and many other doping profiles are possible within the scope of the inventive concept.

[0067] like Figure 2A As shown in FIG. 1 , the shallow conductive region 124 extends between the drift layer 15 and the source layer 16 in the vertical direction, and the deep conductive region 122 extends between the drift layer 15 and the source layer 16 in the vertical direction.

[0068] In some embodiments, the shallow conductive region has a graded doping profile that is graded in a lateral direction that is perpendicular to a direction in which carriers flow through the channel region when the vertical junction field effect device is in an on state.

[0069] As a function of the position along the horizontal direction of the channel of the conventional JFET structure 10, Figure 3 (a) is the graph of doping concentration, Figure 3 (b) is a graph of the electric field strength, and Figure 3 (c) is a graph of electron energy. Similarly, as a function of position along the horizontal direction of the channel of the JFET structure 100 according to some embodiments, and Figure 3 (d) is the graph of doping concentration, Figure 3 (e) is a graph of the electric field strength, and Figure 3 (f) is a graph of electron energy.

[0070] like Figure 3 As shown in (a), in the conventional structure, the channel region has a constant doping concentration N ch In contrast, Figure 3 As shown in (d), in the structure according to some embodiments, the channel region has a step-graded doping profile, which includes a doping concentration N away from the p-type gate region (the p-type gate region has a doping concentration N of the opposite type to that in the channel region). g ) in the deep conductive region with a low doping concentration N d and a high doping concentration N in the shallow conductive region near the p-type gate region h In some embodiments, the shallow conductive region may have a width δ of approximately 0.2 microns.

[0071] like Figure 3 As shown in (b) and 3(e), the peak electric field (E m ) is higher in the JFET structure 100 because the junction is formed by a more highly doped n-channel region than in the conventional structure 10, while the built-in voltage is the same in both cases. The gate-source breakdown voltage is determined by the junction between the gate region 18 and the source layer 16, as long as the n+ doping N h It is sufficient to be lower than the n+ doping concentration of the source layer 16. Therefore, compared with the conventional JFET structure 10, the JFET structure 100 should not have a lower gate-source breakdown voltage.

[0072] Solving the Poisson equation for electrostatics, we obtain the traditional constant doping structure and Figure 2A The threshold voltage (V T ) and V T Sensitivity to mesa width. In the embodiments described herein, V T The sensitivity is lower because N d (The doping in the center of the channel) is lower than N ch (Doping of the channel in the conventional structure).

[0073] For N ch Constant doping channel, V T is calculated as:

[0074]

[0075] V as a function of mesa width W T The change is calculated as:

[0076]

[0077] For N h and N d The two-step doping channel, V T is calculated as:

[0078]

[0079] V as a function of mesa width W T The change is calculated as:

[0080]

[0081] Although the V T To N ch sensitive, but some embodiments of V T For much lower values ​​of N d sensitive.

[0082] Simulations were performed to compare the performance of conventional structures with structures according to some embodiments. T As the gate voltage, this gate voltage will create a 1.5V barrier (V barrier The simulations used a mesa width of 1.2 microns, a mesa width variation of + / - 0.2 microns, a p+ implant depth of 0.2 microns in the mesa on each side, an n+ implant depth of 0.2 microns in the trench of the new structure, and an 8E16 cm -3 N ch 、1E16 cm -3 N d and 3E17 cm -3 N h Using these conditions, the above analytical model gives the V shown in Table 1 T and V T As shown in Table 1, when the width of the mesa varies by + / -0.2μm, the V T from -5.0 V to -16.6 V. In contrast, for the structure formed as described herein, when the width of the mesa varies by + / - 0.2 microns, V TIt only changes from -9.3V to -10.4V.

[0083] Therefore, when the structure described herein is used, the V T The variation is shown to be reduced to less than 1 / 10.

[0084] Table 1 - V with table width T Changes

[0085]

[0086] In some embodiments, the vertical junction field effect device may exhibit a variation in threshold voltage as a function of mesa width of less than 20 V / micron. In some embodiments, the vertical junction field effect device exhibits a variation in threshold voltage as a function of mesa width of less than 10 V / micron (and in some embodiments, less than 5 V / micron). In some embodiments, the vertical junction field effect device exhibits a variation in threshold voltage as a function of mesa width of between 5 V / micron and 20 V / micron.

[0087] A process flow for forming a JFET structure according to some embodiments is illustrated in Figures 4A-4I In. Figures 4A-4I In the drawings, the relative sizes of various layers and regions are exaggerated and not drawn on scale for clarity. Figures 4A-4I The process flow shown in is for producing an n-channel JFET device. For a p-channel JFET device, the conductivity type of the layers / regions of the device will be reversed from n-type to p-type and vice versa.

[0088] Reference Figure 4A , an n+SiC substrate 26 having a thickness of about 350 microns is provided. The substrate 26 may have a 2H, 4H, 6H or 3C polymorph, and may have an on-axis or off-axis orientation. The n+ substrate 26 will form the drain layer 26 of the completed JFET device.

[0089] An n-epitaxial layer 15 having a thickness of about 8 microns is formed on the substrate 26. This epitaxial layer thickness is suitable for devices with a blocking voltage of 600-800 V. For higher voltage ratings, the n-epitaxial layer 15 will be thicker. The n-epitaxial layer 15 may have a thickness of about 5E15 cm -3 and 1E17cm -3 and in some embodiments have a doping concentration of approximately 1E16 cm -3 and 5E16cm -3 In a specific embodiment, the n-epitaxial layer 15 may have a doping concentration of about 1.5E16 cm -3The thickness and / or doping of the n-epitaxial layer 15 forming the drift layer of the device may be selected to provide the device with a desired on-state resistance and / or off-state voltage blocking capability.

[0090] Reference Figure 4B By implanting n-type ions (such as silicon) into the epitaxial layer 15 according to the dose and implantation energy, an n+ source layer 16 and an n++ source contact layer are formed. The n+ source layer 16 may have a thickness of about 0.5 microns and a thickness of about 1E18 cm -3 The n+ source contact layer 38 may have a thickness of approximately 0.5 microns and may be degenerately doped to allow for the formation of a source ohmic contact thereto.

[0091] Reference Figure 4C , a mask 46 is formed on the upper surface of the structure. The mask 46 is formed to have a thickness of about 1 micrometer and is formed by depositing SiO 2 The structure is then etched to form trenches 48 defining the mesas 12. Figure 2A-2B As in FIG. 4 , for ease of understanding, only half of the structure located to the right of axis 30 is shown. Trench 48 has a width of approximately 1.2 microns, and the mesa has a total width of approximately 1.2 microns. Trench 48 may be etched in n-epitaxial layer 15 to a depth of approximately 2 microns.

[0092] After the trench forming operation, mask 46 may have a remaining thickness of approximately 0.7 microns. Figure 4D With mask 46 in place, angled ion implantation 50 is performed to implant n+ shallow channel regions 124 into the sidewalls of mesas 12. Using sufficient ion implantation to obtain approximately 1E17 cm -3 to 1E19 cm -3 (and in some cases, about 3E17 cm -3 to 5E18 cm -3 ) doping concentration, the n+ shallow channel region 124 is implanted. At a maximum implantation energy of about 700 to 800 keV, the n+ shallow channel region 124 can be implanted to obtain a desired implantation depth. At a high temperature and an inclination angle of 35 to 40 degrees relative to the normal, the implantation can be performed multiple times to ensure that the bottom of the trench sidewall is not shielded. The implantation can be performed at four twist angles separated by 90 degrees from each other.

[0093] Reference Figure 4E , the second SiO 2Layer 48 is deposited on the structure and patterned to form openings 49 in edge termination regions 57 of the structure. The pattern etch conditions are selected to use the underlying silicon nitride layer 46B as an etch stop layer so that when the second SiO 2 When layer 48 is patterned, mask 46 is not removed. An inclined ion implantation 52 is performed to implant p+ gate region 18 into the sidewalls of mesa 12 and simultaneously implant edge termination region 55 into edge termination region 57. A sufficient ion implantation is performed to obtain approximately 1E18 cm -3 to 1E19 cm -3 The p+ gate region 18 is implanted at a doping concentration of about 100 keV. The p+ gate region 18 may be implanted at a maximum implant energy of about 300-400 keV to obtain a desired implant depth. The implantation may be performed multiple times at a high temperature and a tilt angle of 35 to 40 degrees relative to the normal to ensure that the bottom of the trench sidewall is not shaded. The implantation may be performed at four twist angles separated by 90 degrees from each other.

[0094] Reference Figure 4F , an ion implantation operation 54 is performed to implant the p++ shielding region 32 into the surface of the trench 48. In the ion implantation operation 54, p-type ions may be implanted into the surface of the trench at a maximum implantation energy of about 350 keV. After the ion implantation operation 54, a junction termination extension (JTE) region (not shown) may be formed in the edge termination region 57 by ion implantation. All implanted dopants may then be activated by annealing at 1550C for 30 minutes using a carbon cap.

[0095] Reference Figure 4G , SiO 2 Layers may then be deposited over the structure using PECVD, and isotropically etched, for example, using inductively coupled plasma (ICP) etching, to form sidewall protection layer 61 on the exposed sidewalls of mesas 12 adjacent trenches 48. Sidewall protection layer 61 may have a thickness of, for example, 20 to 30 nm, in some embodiments 23 to 27 nm, and in some embodiments 25 nm.

[0096] Reference Figure 4H , a Ni layer 63 having a thickness of 100 nm may be deposited on the structure and annealed at 750°C to form silicide at the bottom of the trench 48. The unreacted Ni may then be etched away, and the structure annealed at 1000°C or less to form a gate ohmic contact 36 on the p+ shielding region 32 in the gate pad region and a source ohmic contact 40 on the source contact layer 38. Additional conventional processing, such as trench filling 72, planarization, metallization 74, backside metallization 76, and laser annealing, may then be performed to complete the device processing, such as Fig. 4I as shown in .

[0097] Figure 5A The operations for processing a JFET device structure according to another embodiment are shown. Figure 5A As shown in FIG. 1 , in some embodiments, the n-type implant 50 ( Figure 4D ) and a p-type implant 52 ( Figure 4E ) can be selected so that after implantation and annealing, the n-breakdown adjustment region 202 remains around the gate region 18, including between the shallow conductive region 124 and the gate region 18 and between the source region 16 and the gate region 18. The shallow conductive region 124 is located between the deep conductive region 122 and the breakdown adjustment region 202. The breakdown adjustment region 202 may have a thickness of approximately 5E15 cm -3 to about 1E17 cm -3 (In some embodiments, approximately 1E16 cm -3 to about 5E16 cm -3 , and in certain embodiments approximately 1.5E16 cm -3 The breakdown adjustment region 202 may have a doping concentration that is similar to, but not necessarily equal to, the doping concentration of the deep conductive region 122 .

[0098] The breakdown adjustment region 202 is provided so that the gate-source PN junction is formed by the p+ gate region 18 and the n- region. This can increase the gate-source breakdown voltage. The n- breakdown adjustment region 202 surrounding the p+ gate region 18 is also self-aligned with the edge of the mesa 12 and can be formed using tilted implantation by adding a lower energy n implant in some embodiments.

[0099] Figure 5B The JFET device structure 200 is shown including an n-breakdown adjustment region 202 between the shallow conductive region 124 and the gate region 18, and Figure 5C , 5D and 5E diagram Figure 5B Some possible channel doping profiles for the JFET device structure. Figure 5C As can be seen in FIG. 1 , the breakdown adjustment region 202 has a doping concentration N b , doping concentration N b is less than the doping concentration N of the shallow conductive region 124 h .

[0100] Doping concentration N b The doping concentration N of the deep conductive region 122 may be greater than, less than, or equal to d For example, in Figure 5C In the embodiment, the breakdown adjustment region 202 has a doping concentration N b, doping concentration N b is approximately equal to the doping concentration N of the deep conductive region 122 d . Figure 5D The doping profile is shown in FIG. 1 , where the doping concentration N of the breakdown adjustment region 202 is b Higher than the doping concentration N of the deep conductive region 122 d ,and Figure 5E The doping profile is shown in FIG. 1 , where the doping concentration N of the breakdown adjustment region 202 is b is less than the doping concentration N of the deep conductive region 122 d .

[0101] Although illustrated as an n-channel device, it will be appreciated that the JFET device structure 200 can be formed as a p-channel device by switching the n-type layer to p-type, and vice versa.

[0102] SiC JFET devices according to some embodiments may provide improved yield due to reduced threshold voltage sensitivity to mesa width. Alternatively or additionally, such devices may be able to maintain yield while allowing for tighter designs (eg, narrower mesas) that improve performance.

[0103] Figure 6 FIG. 2 shows an exemplary circuit including a JFET device according to some embodiments. Figure 6 As shown in , a vertical SiC JFET 100 according to some embodiments can be connected with a silicon MOSFET 150 in a modified stacked topology, where the SiC JFET gate is driven directly and where very low variation in the SiC JFET threshold voltage is desired.

[0104] The JFET devices as described herein may also be beneficially used in other SiC JFET applications, such as for use as normally-on SiC JFET switches in solid-state circuit breakers.

[0105] More generally, some embodiments described herein can be used in any vertical channel junction field effect device having mesa / trench features where an important property of the device is sensitive to mesa width and where reducing the sensitivity of that property to mesa width is of interest.

[0106] Figure 7A method for forming a vertical junction field effect transistor is shown. The method includes providing a drift layer having a first conductivity type (box 702), forming a source layer having the first conductivity type on the drift layer (box 704), and forming a mesa by selectively etching a portion of the source layer and the drift layer to form a groove, the groove extending into the drift layer and defining a mesa adjacent to the groove (box 706). There is a mesa sidewall adjacent to the groove. The method also includes forming a shallow conductive region extending between the drift layer and the source layer in the mesa (box 708), and forming a gate region having a second conductivity type in the mesa (box 710). The gate region is adjacent to a channel region in the mesa, and the channel region includes a deep conductive region adjacent to the shallow conductive region, so that the shallow conductive region is located between the deep conductive region and the gate region. The shallow conductive region has a higher doping concentration than the deep conductive region.

[0107] Forming the shallow conductive region may include performing oblique angle ion implantation of first conductivity type dopant ions in a mesa sidewall at a first implantation energy to form the shallow conductive region in the mesa, wherein a portion of the drift layer in the mesa forms a deep conductive region adjacent to the shallow conductive region.

[0108] Forming the gate region may include: implanting second conductivity type dopant ions into the sidewalls of the mesa at a second implantation energy lower than the first implantation energy to form a gate region in the mesa, wherein a shallow conductive region is located between the gate region and a deep conductive region, and wherein the second conductivity type is opposite to the first conductivity type.

[0109] In some embodiments, forming the mesa includes: forming an etching mask on the source layer, and etching the source layer and the drift layer to form the mesa in the region below the etching mask. Forming the shallow conductive region may include: using the etching mask as an implantation mask to implant first conductivity type dopant ions into the mesa sidewalls.

[0110] The etching mask may include SiO 2 Etching mask and SiO 2 The method may further include: forming a second etching mask on the mesa and the groove; patterning the second etching mask to expose the mesa and the bottom surface of the groove adjacent to the mesa, and to expose one or more surface areas in the edge region of the device; and implanting second conductivity type dopant ions into the mesa sidewall and the junction termination region at a second implantation energy lower than the first implantation energy to form a gate region in the mesa and an edge termination region in the edge region. The shallow conductive region is located between the gate region and the deep conductive region, and the second conductivity type is opposite to the first conductivity type.

[0111] The second etching mask may include SiO 2 , and patterning the second etch mask includes selectively etching the second etch mask using the silicon nitride mask as an etch stop layer.

[0112] Although embodiments of the inventive concept have been described in considerable detail with reference to certain configurations of the embodiments of the inventive concept, other versions are possible. The field plate and gate can also have many different shapes and can be connected to the source contact in many different ways. Therefore, the spirit and scope of the present invention should not be limited to the specific embodiments described above.

Claims

1. A power transistor device, comprising: A drift layer (15) having a first conductivity type; A mesa (12) located on the drift layer, the mesa comprising a channel region (114) on the drift layer and a source layer (16) on the channel region, the channel region and the source layer having the first conductivity type; and A gate region (18), located in the mesa and adjacent to the channel region, the gate region having a second conductivity type opposite to the first conductivity type; The channel region includes a deep conductive region (122) and a shallow conductive region (124) between the deep conductive region and the gate region; The deep conductive region has a first doping concentration, and the shallow conductive region has a second doping concentration greater than the first doping concentration. 2 . The power transistor device of claim 1 , wherein the shallow conductive region extends between the drift layer and the source layer in a vertical direction, and wherein the deep conductive region extends between the drift layer and the source layer in a vertical direction.

3. The power transistor device of claim 1 , wherein the channel region comprises silicon carbide, and wherein the shallow conductive region has a relative width greater than about 1E17 cm -3 The doping concentration of the deep conductive region is less than about 1E17 cm -3 of doping concentration.

4. The power transistor device of claim 1 , wherein the channel region comprises silicon carbide, and wherein the shallow conductive region has a -3 and about 5E18 cm -3 and the deep conductive region has a doping concentration of approximately 1E16 cm -3 to about 5E16 cm -3 of doping concentration.

5. The power transistor device of claim 4, wherein the shallow conductive region has a width of approximately 1E18 cm -3 The doping concentration of the deep conductive region is about 1.5E16 cm -3 of doping concentration. 6 . The power transistor device of claim 1 , wherein the shallow conduction region has a doping concentration at least about 10 times greater than a doping concentration of the deep conduction region.

7. The power transistor device of claim 1, wherein the shallow conductive region has a graded doping profile that is graded in a lateral direction that is perpendicular to a direction of carrier flow through the channel region when the VJFETD is in an on-state.

8. The power transistor device of claim 1, wherein the shallow conductive region has a lateral width of approximately 0.1 to 0.3 microns in a lateral direction perpendicular to a direction in which carriers flow through the channel region when the VJFETD is in an on state.

9. A power transistor device as described in claim 1, wherein the shallow conductive region has a lateral width in a lateral direction, the lateral direction being perpendicular to the direction of carrier flow through the channel region when the vertical junction field effect device is in an on state, and the lateral width is approximately one third of the half-width of the mesa.

10. The power transistor device of claim 1, wherein the shallow conductive region comprises an implanted region within the mesa.

11. The power transistor device of claim 1 , further comprising: A breakdown adjustment region is located between the shallow conductive region and the gate region, wherein the breakdown adjustment region has the first conductivity type and has a third doping concentration that is less than the second doping concentration of the shallow conductive region.

12. The power transistor device of claim 1, wherein the channel region comprises silicon carbide, and wherein the vertical junction field effect device exhibits a threshold voltage variation as a function of mesa width of less than 20 V / micron.

13. The power transistor device of claim 1, wherein the channel region comprises silicon carbide, and wherein the vertical junction field effect device exhibits a threshold voltage variation as a function of mesa width of less than 10 V / micron.

14. The power transistor device of claim 1, wherein the channel region comprises silicon carbide, and wherein the vertical junction field effect device exhibits a threshold voltage variation as a function of mesa width of less than 5 V / micron.

15. The power transistor device of claim 1, wherein the channel region comprises silicon carbide, and wherein the vertical junction field effect device exhibits a variation in threshold voltage as a function of mesa width of between 5 V / micron and 20 V / micron.

16. The power transistor device of claim 1, wherein the power transistor device comprises a junction field effect transistor (JFET). 17 . The power transistor device of claim 1 , wherein the drift layer, the channel region, and the gate region comprise silicon carbide.

18. The power transistor device of claim 1, wherein a lateral width of the shallow channel region in a lateral direction is independent of a width of the mesa in the lateral direction, the lateral direction being perpendicular to a direction of current flow when the device is in an on state.

19. The power transistor device of claim 1, wherein a lateral width of the deep channel region in a lateral direction is proportional to a width of the mesa in the lateral direction, the lateral direction being perpendicular to a direction of current flow when the device is in an on state.

20. The power transistor device of claim 1, wherein the gate region comprises a first gate region and the shallow conductive region comprises a first shallow conductive region, the power transistor device further comprising: a second gate region located in the mesa and opposite to the first gate region, wherein the channel region is located between the first gate region and the second gate region; and a second shallow conductive region, located in the channel region and between the deep conductive region and the second gate region; The second shallow conductive region has a third doping concentration greater than the first doping concentration of the deep conductive region. 21 . The power transistor device of claim 20 , wherein the first gate region is surrounded by a breakdown adjustment region in the mesa, the breakdown adjustment region having the first conductivity type and having a third doping concentration less than the second doping concentration of the shallow conductive region.

22. The power transistor device of claim 1, wherein the deep conductive region and the channel region are arranged on opposite sides of the shallow conductive region in a lateral direction, the lateral direction being perpendicular to a direction of current flow in the power transistor device.

23. A power transistor device comprising: A drift layer (10) having a first conductivity type; A mesa (12) located on the drift layer, the mesa comprising a channel region (14) on the drift layer and a source layer (16) on the channel region, the channel region and the source layer having the first conductivity type; and A gate region (18) located on one side of the channel region in the mesa, the gate region having a second conductivity type opposite to the first conductivity type; The vertical junction field effect device exhibits a threshold voltage variation as a function of mesa width of less than 20 V / micron.

24. The power transistor device of claim 23, wherein the channel region comprises silicon carbide, and wherein the vertical junction field effect device exhibits a threshold voltage variation as a function of mesa width of less than 10 V / micron.

25. The power transistor device of claim 23, wherein the channel region comprises silicon carbide, and wherein the vertical junction field effect device exhibits a threshold voltage variation as a function of mesa width of less than 5 V / micron.

26. The power transistor device of claim 23, wherein the channel region comprises silicon carbide, and wherein the vertical junction field effect device exhibits a variation in threshold voltage as a function of mesa width of between 5 V / micron and 20 V / micron.

27. The power transistor device of claim 23, wherein the channel region comprises a deep conductive region (122) and a shallow conductive region (124) between the deep conductive region and the gate region; The deep conductive region has a first doping concentration, and the shallow conductive region has a second doping concentration greater than the first doping concentration. 28 . The power transistor device of claim 27 , wherein the shallow conductive region extends in a vertical direction between the drift layer and the source layer, and wherein the deep conductive region extends in a vertical direction between the drift layer and the source layer.

29. The power transistor device of claim 27, wherein the channel region comprises silicon carbide, and wherein the shallow conductive region has a relative width greater than about 1E17 cm -3 The doping concentration of the deep conductive region is less than about 1E17 cm -3 of doping concentration.

30. The power transistor device of claim 27, wherein the shallow conductive region has a graded doping profile that is graded in a lateral direction that is perpendicular to a direction of carrier flow through the channel region when the VJFETD is in an on-state.

31. A power transistor device as described in claim 27, wherein the shallow conductive region has a lateral width in a lateral direction, the lateral direction being perpendicular to the direction of carrier flow through the channel region when the vertical junction field effect device is in an on state, and the lateral width is approximately one-third of the half-width of the mesa.

32. The power transistor device of claim 27, further comprising: A breakdown adjustment region is located between the shallow conductive region and the gate region, wherein the breakdown adjustment region has the first conductivity type and has a third doping concentration that is less than the second doping concentration of the shallow conductive region.

33. A method of forming a power transistor device, comprising: providing (702) a drift layer having a first conductivity type; forming (704) a source layer having the first conductivity type on the drift layer; forming (706) a mesa by selectively etching a portion of the source layer and the drift layer to form a trench extending into the drift layer and defining the mesa adjacent to the trench, the mesa having a mesa sidewall adjacent to the trench; forming (708) a shallow conductive region in the mesa extending between the drift layer and the source layer; and forming (710) a gate region having a second conductivity type in the mesa, wherein the gate region is adjacent to a channel region in the mesa, wherein the channel region includes a deep conductive region adjacent to the shallow conductive region, and the shallow conductive region is located between the deep conductive region and the gate region; Compared with the deep conductive region, the shallow conductive region has a higher doping concentration.

34. The method of claim 33, wherein forming the shallow conductive region comprises: An oblique ion implantation of first conductivity type dopant ions is performed in the mesa sidewalls at a first implantation energy to form the shallow conductive region in the mesa, wherein a portion of the drift layer in the mesa forms the deep conductive region adjacent to the shallow conductive region.

35. The method of claim 34, wherein forming the gate region comprises: Second conductivity type dopant ions are implanted into the sidewalls of the mesa at a second implantation energy lower than the first implantation energy to form the gate region in the mesa, wherein the shallow conductive region is located between the gate region and the deep conductive region, and wherein the second conductivity type is opposite to the first conductivity type.

36. The method of claim 34, wherein forming the mesa comprises: forming an etching mask on the source layer; and The source layer and the drift layer are etched to form the mesa in a region below the etch mask, wherein forming the shallow conductive region includes implanting the first conductivity type dopant ions into sidewalls of the mesa using the etch mask as an implantation mask.

37. The method of claim 36, wherein the etching mask comprises a SiO2 etching mask on the source layer and a silicon nitride mask on the SiO2 mask, the method further comprising: forming a second etching mask on the mesa and the trench; patterning the second etch mask to expose the mesas and bottom surfaces of the trenches adjacent to the mesas and to expose one or more surface regions in an edge region of the device; and Second conductive type dopant ions are implanted into the sidewalls of the mesa and the junction termination region at a second implantation energy lower than the first implantation energy to form the gate region in the mesa and an edge termination region in the edge region, wherein the shallow conductive region is located between the gate region and the deep conductive region, and wherein the second conductive type is opposite to the first conductive type.

38. The method of claim 37, wherein the second etch mask comprises SiO2, and wherein patterning the second etch mask comprises selectively etching the second etch mask using the silicon nitride mask as an etch stop layer.

39. A power transistor device comprising: A drift layer (10) having a first conductivity type; A mesa (12) located on the drift layer, the mesa comprising a channel region (114) on the drift layer and a source layer (16) on the channel region, the channel region and the source layer having the first conductivity type; and A gate region (18), located in the mesa and adjacent to the channel region, the gate region having a second conductivity type opposite to the first conductivity type; A breakdown adjustment region (202), located in the mesa and between the channel region and the gate region, the breakdown adjustment region having the first conductivity type; Wherein the channel region has a first doping concentration, and wherein the breakdown adjustment region has a second doping concentration that is less than the first doping concentration.

40. The power transistor device of claim 39, wherein the channel region comprises a deep conductive region (122) and a shallow conductive region (124) between the deep conductive region and the breakdown adjustment region; The shallow conductive region has the first doping concentration, and the deep conductive region has a third doping concentration that is less than the first doping concentration.

41. The power transistor device of claim 39, wherein the breakdown adjustment region is located above and below the gate region in the mesa and is located on a side of the gate region adjacent to the channel region in the mesa.

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