Semiconductor test structure and semiconductor test method

Abstract

The invention relates to a semiconductor test structure and a semiconductor test method. The semiconductor test method comprises the following steps: accessing a test piece; the test piece comprises a to-be-tested circuit; the circuit to be detected and a sensing amplification circuit in the chip have the same structure; inputting a test signal to the circuit to be tested; the test signal simulates an input signal of the sensing amplification circuit in a working state; receiving a test result signal by the circuit to be tested; the test result signal is generated after the circuit to be tested senses and amplifies the voltage difference between the bit line signal and the complementary bit line signal; and analyzing the test result signal to determine the state of the circuit to be tested. Therefore, the parasitic parameters of the metal wiring in the circuit to be tested are similar to those of the metal wiring in the chip, so that the parameters of the device in the test piece can reflect the parameters of the corresponding device in the chip more accurately, and the accuracy of the test result is further improved. The test piece can simulate the working state of the sensing amplification circuit for testing, the test process can be simplified, and the test time can be saved.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and in particular to a semiconductor test structure and a semiconductor test method. Background Art

[0002] In order to test the electrical performance of the devices in the chip, a test element group (TEG) is usually set in the saw path area of ​​the wafer. The test element and the semiconductor chip usually have the same devices and are made by the same process. Therefore, the reliability, stability, process margin and other performance of the semiconductor chip can be evaluated through the test results of the test element.

[0003] In the related art, each device under test (DUT) of the test piece requires a repeated test structure, and each DUT needs to be tested separately, resulting in low test efficiency and poor accuracy of test results. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure provide a semiconductor test structure and a semiconductor test method to improve the test efficiency and the accuracy of the test results.

[0005] The technical solution of the present invention is achieved in this way:

[0006] The disclosed embodiment provides a semiconductor testing method, comprising: accessing a test piece; the test piece comprises a circuit to be tested; the circuit to be tested has the same structure as a sensing amplifier circuit in a chip; inputting a test signal to the circuit to be tested; the test signal simulates an input signal of the sensing amplifier circuit in a working state; the circuit to be tested receives a test result signal; the test result signal is generated after the circuit to be tested senses and amplifies a voltage difference between a bit line signal and a complementary bit line signal; and analyzing the test result signal to determine a state of the circuit to be tested.

[0007] In the above scheme, the test result signal is analyzed to determine the state of the circuit to be tested, including: comparing the test result signal with a pre-stored standard output curve; the standard output curve simulates the output signal of the sensing amplifier circuit in the working state; if the test result signal fits the standard output curve, it is determined that the state of the circuit to be tested is normal.

[0008] In the above solution, the test signal also includes: a power signal and a control signal; wherein the control signal simulates a read / write operation enable signal received by the sense amplifier circuit; and the power signal simulates a voltage connected to the sense amplifier circuit.

[0009] In the above scheme, the circuit to be tested includes multiple transistors; the test result signal is analyzed to determine the state of the circuit to be tested, and it also includes: for any transistor, the corresponding test signal and the corresponding test result signal are analyzed to determine the electrical performance of the transistor.

[0010] In the above scheme, the control signal includes: a first test signal, a second test signal and a third test signal; the read / write operation enable signal includes: an equalization signal, a first offset control signal, a second offset control signal, a data transmission signal and a column selection signal; wherein the first test signal simulates the equalization signal; the second test signal simulates the isolation control signal; and the third test signal simulates the offset control signal.

[0011] In the above scheme, the control signal also includes: a fourth test signal and a fifth test signal; the read / write operation enable signal also includes: a data transmission signal and a column selection signal; wherein the fourth test signal simulates the data transmission signal; and the fifth test signal simulates the column selection signal.

[0012] In the above scheme, for any transistor, the corresponding test signal and the corresponding test result signal are analyzed to determine the electrical performance of the transistor, including: connecting the source, drain and gate of any transistor to the corresponding test signal to provide the corresponding test voltage to the transistor; monitoring the test current generated by the source, drain and gate of the transistor; and determining the electrical performance of the transistor based on the fitting state of the test current change curve and the standard output curve.

[0013] In the above scheme, the source, drain and gate of any transistor are connected to the corresponding test signal to provide the transistor with a corresponding test voltage, including: connecting the source, drain and gate of any transistor to the corresponding test signal so that the test voltage connected to the transistor simulates the working voltage of the corresponding transistor in the sensing amplifier circuit when it is in an on state; and / or connecting the source, drain and gate of any transistor to the corresponding test signal so that the test voltage connected to the transistor simulates the working voltage of the corresponding transistor in the sensing amplifier circuit when it is in an off state.

[0014] In the above scheme, the source and gate of any transistor are connected to the corresponding test signal, and the corresponding test voltage is provided to the transistor, including: when testing the off state of the transistor, a first test voltage is provided to the gate of the transistor, a second test voltage is provided to the source of the transistor, and a third test voltage is provided to the drain of the transistor; the second test voltage and / or the third test voltage are both greater than the first test voltage.

[0015] In the above scheme, the source and gate of any transistor are connected to the corresponding test signal, and the corresponding test voltage is provided to the transistor, and it also includes: if the transistor is connected to any one of the bit line, complementary bit line, read bit line and complementary read bit line, a fourth test voltage and a fifth test voltage are provided to the source or drain of the transistor; the fourth test voltage and the fifth test voltage have different values; the fourth test voltage and the fifth test voltage respectively simulate different level states of the bit line signal, complementary bit line signal, read bit line signal and complementary read bit line signal in the sensing amplifier circuit.

[0016] In the above scheme, for any transistor, the corresponding test signal and the corresponding test result signal are analyzed to determine the electrical performance of the transistor, and it also includes: connecting the body terminal of any transistor to the corresponding test signal and providing a sixth test voltage to the body terminal of the transistor; wherein, if the transistor is a P-type transistor, the sixth test voltage connected to its body terminal is positive; or, if the transistor is an N-type transistor, the sixth test voltage connected to its body terminal is negative.

[0017] The present disclosure also provides a semiconductor test structure, including: a test piece; the test piece includes a circuit to be tested; the circuit to be tested has the same structure as the sensing amplifier circuit in the chip; the test piece is connected to the test equipment and is configured to receive a test signal from the test equipment; and generates and outputs a test result signal; the test signal simulates the input signal of the sensing amplifier circuit in a working state; the test result signal is generated after the circuit to be tested senses and amplifies the voltage difference between the bit line signal and the complementary bit line signal.

[0018] In the above scheme, the test piece also includes multiple test lines and multiple pads; the multiple test lines and multiple pads are used to transmit test signals and test result signals; wherein the first end of each test line is correspondingly connected to the circuit to be tested; the second end of each test line is correspondingly connected to a pad.

[0019] In the above scheme, the circuit to be tested includes a plurality of transistors; the source, drain and gate of each transistor are respectively connected to different pads.

[0020] In the above solution, the test piece and the chip are located on the same wafer; the test piece is located in the dicing area between adjacent chips.

[0021] The embodiment of the present disclosure provides a semiconductor testing method, including: accessing a test piece; the test piece includes a circuit to be tested; the circuit to be tested has the same structure as the sensing amplifier circuit in the chip; inputting a test signal to the circuit to be tested; the test signal simulates the input signal of the sensing amplifier circuit in the working state; the circuit to be tested receives a test result signal; the test result signal is generated by the circuit to be tested after sensing and amplifying the voltage difference between the bit line signal and the complementary bit line signal; analyzing the test result signal to determine the state of the circuit to be tested. In the embodiment of the present disclosure, the circuit to be tested and the sensing amplifier circuit have the same metal wiring, and the parasitic parameters of the metal wiring in the circuit to be tested are similar to the parasitic parameters of the metal wiring in the sensing amplifier circuit, thereby avoiding the interference of the parasitic parameter difference of the metal wiring on the test result, so that the parameters of the devices such as transistors in the test piece can more accurately reflect the parameters of the corresponding devices in the chip, further improving the accuracy of the test result. At the same time, in the embodiment of the present disclosure, the test piece can simulate the working state of the sensing amplifier circuit for testing. Compared with the test method of testing each transistor separately in the related art, the test piece can simulate the working state of the chip and test multiple transistors at the same time, further simplifying the test process and saving test time. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of a semiconductor testing method provided by an embodiment of the present disclosure Figure 1 ;

[0023] Figure 2 A schematic diagram of the structure of a test piece provided in an embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of the structure of a circuit to be tested provided by an embodiment of the present disclosure;

[0025] Figure 4 A waveform diagram of a test signal provided by an embodiment of the present disclosure;

[0026] Figure 5 A schematic diagram of a semiconductor testing method provided by an embodiment of the present disclosure Figure 2 ;

[0027] Figure 6 A schematic diagram of the structure of a semiconductor test structure provided by an embodiment of the present disclosure;

[0028] Figure 7 A schematic diagram of the structure of a wafer provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0030] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0031] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0033] Figure 1 is an optional flow chart of the semiconductor testing method provided by the embodiment of the present disclosure, which will be combined with Figure 1 The steps shown are explained.

[0034] S101, connecting a test piece; the test piece includes a circuit to be tested; the circuit to be tested has the same structure as the sensing amplifier circuit in the chip.

[0035] Figure 2 It is a schematic diagram of the structure of an optional test piece provided in an embodiment of the present disclosure.

[0036] In the embodiments of the present disclosure, reference Figure 2 , the test piece 100 may include a circuit to be tested 10, a plurality of test lines 20 and a plurality of pads 30. The circuit to be tested 10 may include a plurality of transistors and metal wirings, and the plurality of transistors are interconnected through the metal wirings. The test equipment is connected to the test piece, that is, the plurality of transistors are connected to the test equipment through the corresponding test lines 20 and pads 30. Thus, the test equipment can input a test signal to the test piece.

[0037] In the disclosed embodiments, metal wiring generally has parasitic parameters such as parasitic capacitance and parasitic resistance. During chip operation, the parasitic parameters of metal wiring will generate signal noise, which may cause voltage fluctuations of signals in the circuit, or even cause signal distortion errors, affecting the normal operation of the circuit, and further affecting the performance of the devices in the circuit.

[0038] In the embodiments of the present disclosure, reference Figure 2 , the circuit to be tested 10 and the sensing amplifier circuit in the chip have the same structure, that is, the transistors in the circuit to be tested 10 and the transistors in the sensing amplifier circuit in the chip have the same structure, and the metal wiring in the circuit to be tested 10 and the metal wiring in the sensing amplifier circuit in the chip have the same structure. In other words, the parasitic parameters of the metal wiring in the circuit to be tested 10 are similar to the parasitic parameters of the metal wiring of the sensing amplifier circuit. In this way, the circuit to be tested of the present disclosure has the same metal wiring as the sensing amplifier circuit in the chip, and the test piece can simulate the parasitic parameters of the sensing amplifier circuit in the actual operation process during the test, so that the parameters of the devices such as transistors in the test piece can more accurately reflect the parameters of the corresponding devices in the chip, further improving the accuracy of the test results.

[0039] S102 , inputting a test signal to the circuit under test; the test signal simulates an input signal of the sensing amplifier circuit in a working state.

[0040] Figure 3 It is a schematic diagram of the structure of an optional circuit to be tested provided by an embodiment of the present disclosure.

[0041] In the present disclosure, Figure 2 and Figure 3 The sensing amplifier circuit usually has multiple working states such as precharge, charge share, sensing amplifier, etc. The test signal simulates the input signal of the sensing amplifier circuit in the working state. Therefore, the test equipment can output the test signal to the test piece 100, simulate the working state of the sensing amplifier circuit in the test piece 100, and test the circuit 10 to be tested. For example, the test equipment can be based on Figure 4The waveforms of the first test signal EQ', the second test signal ISO', the third test signal NcEn', the fourth test signal IO', the fifth test signal CSL', the sixth test signal ION', the fourth power signal PCS' and the fifth power signal NCS' output different test voltages to the circuit under test 10 at different stages, and the first power signal PW', the second power signal NW' and the third power signal Vad2' also provide corresponding test voltages to the circuit under test 10 at corresponding different stages, so that the circuit under test 10 simulates various working states of the sensing amplifier circuit, such as pre-charging, charge sharing, sensing amplification, etc., to test the circuit under test 10.

[0042] S103, the circuit under test receives a test result signal; the test result signal is generated by the circuit under test sensing and amplifying a voltage difference between a bit line signal and a complementary bit line signal.

[0043] S104: Analyze the test result signal to determine the state of the circuit to be tested.

[0044] Figure 4 is a waveform diagram of an optional test signal and a test result signal provided by an embodiment of the present disclosure. It should be noted that: Figure 4 The unit of the vertical axis is V. Figure 4 The waveforms in the figure are only used as examples. The corresponding waveforms can also be set according to the actual working conditions of the sensing amplifier circuit in the chip, and there is no limitation here. Figure 4 Among them, Q1 is the pre-charging working state of the analog sensing amplifier circuit, Q2 is the charge sharing working state of the analog sensing amplifier circuit, and Q3 is the sensing amplification working state of the analog sensing amplifier circuit.

[0045] In the present disclosure, in combination Figure 3 and Figure 4 , the main function of the sense amplifier circuit is to sense and amplify the voltage difference of the signal on the bit line and the complementary bit line. The test equipment simulates the sense amplifier working state of the sense amplifier circuit in the test piece 100, outputs the corresponding test signal to the circuit under test 10, and the sense amplifier SA (Sense Amplifier) ​​in the circuit under test 10 will amplify the voltage difference of the signal on the bit line 111 and the complementary bit line 112. In this way, the test equipment can monitor the voltage changes of the bit line 111 and the complementary bit line 112 in the circuit under test 10 through the pad 30, and generate the first test result signal Bla' and the second test result signal Blb'. Therefore, the test equipment can determine the state of the circuit under test 10 based on whether the first test result signal Bla' and the second test result signal Blb' fit the standard output curve of the corresponding bit line signal Bla and the standard output curve of the complementary bit line signal Blb.

[0046] For example, combined with Figure 3 and Figure 4 , the test equipment simulates the sense amplifier working state of the sense amplifier circuit in the test piece 100, and outputs the corresponding test signal to the circuit under test 10. The fourth power signal PCS' simulates the first internal power PCS in the sense amplifier circuit, and is input to the transistor M10 and the transistor M11 of the sense amplifier SA, and the fifth power signal NCS' simulates the second internal power NCS in the sense amplifier circuit, and is input to the transistor M8 and the transistor M9 of the sense amplifier SA. Thus, the voltage of the read bit line 113 is pulled down or increased, so that the voltage on the bit line 111 is further reduced or increased. Thus, the test equipment can compare the first test result signal Bla' with the standard output curve of the bit line signal Bla, and compare the second test result signal Blb' with the standard output curve of the bit line signal Blb. If the first test result signal Bla' fits the standard output curve of the bit line signal Bla, and the second test result signal Blb' fits the standard output curve of the bit line signal Blb, it is determined that the state of the circuit under test 10 is normal. Otherwise, it means that the state of the circuit under test 10 is abnormal.

[0047] In the embodiments of the present disclosure, reference Figure 3In the process of testing the test piece 100 in the working state of the analog sensing amplifier circuit, the gate, drain, source and body of the transistor in the circuit to be tested 10 input test signals or output test result signals. Thus, the test equipment can analyze the test signal and the corresponding test result signal corresponding to each transistor to determine the electrical performance of the transistor. For example, the test equipment can output the corresponding test signal to the circuit to be tested 10, and provide the corresponding test voltage to each port of the transistor in the circuit to be tested 10. Then, the test equipment can monitor the test current generated by the source and drain of the transistor and generate a test current change curve. Thus, the test equipment can compare the test current change curve of the transistor with the standard output curve to determine the electrical performance of the transistor. In the sensing amplification working state of the test piece 100 simulating the sensing amplification circuit, the drain of the transistor M8 in the sense amplifier SA is connected to the sense bit line 113, the source of the transistor M8 is connected to the test voltage provided by the fifth power signal NCS', the gate of the transistor M8 is connected to the test voltage provided by the complementary sense bit line 114, and the body of the transistor M8 is connected to the test voltage provided by the first power signal PW'. The test equipment can monitor the test current of the drain of the transistor M8 in the sense amplifier SA through the pad 30 corresponding to the sense bit line 113 to generate a third test result signal SaBla'. Thus, the test equipment determines the state of the transistor M8 in the sense amplifier SA according to the fitting degree of the test current change curve of the third test result signal SaBla' and the standard output curve. In this way, compared with the test method of testing each transistor separately in the related art, the embodiment of the present disclosure can test multiple transistors at the same time by using the working conditions of the chip, thereby further simplifying the test process and saving test time.

[0048] It can be understood that the circuit to be tested of the test piece in the embodiment of the present disclosure has the same structure as the sensing amplifier circuit in the chip. In this way, the circuit to be tested and the sensing amplifier circuit have the same metal wiring, and the parasitic parameters of the metal wiring in the circuit to be tested are similar to the parasitic parameters of the metal wiring in the sensing amplifier circuit, thereby avoiding the interference of the parasitic parameter differences of the metal wiring on the test results, so that the parameters of devices such as transistors in the test piece can more accurately reflect the parameters of the corresponding devices in the chip, further improving the accuracy of the test results. At the same time, the test piece in the embodiment of the present disclosure can simulate the working state of the sensing amplifier circuit for testing. Compared with the test method of testing each transistor separately in the related art, the test piece can simulate the working state of the chip and test multiple transistors at the same time, further simplifying the test process and saving test time.

[0049] In some embodiments of the present disclosure, S201 can be used to implement Figure 1 S104 shown will be described in conjunction with each step.

[0050] S201, comparing the test result signal with a pre-stored standard output curve; if the test result signal fits the standard output curve, it is determined that the state of the circuit to be tested is normal.

[0051] In the present disclosure, Figure 2 and Figure 4 The standard output curve may include a standard output curve of a bit line signal Bla in the sense amplifier circuit and a standard output curve of a complementary bit line signal Blb. The test equipment may be configured as follows: Figure 4 The test device 100 outputs the waveforms corresponding to the multiple test signals, outputs the corresponding test voltage to the circuit under test, so as to simulate the multiple working states of the sensing amplifier circuit in the test device 100, and outputs the first test result signal Bla' and the second test result signal Blb'. The test device can compare the first test result signal Bla' with the standard output curve of the bit line signal Bla, and compare the second test result signal Blb' with the standard output curve of the bit line signal Blb. If the first test result signal Bla' fits the standard output curve of the bit line signal Bla, and the second test result signal Blb' fits the standard output curve of the complementary bit line signal Blb, it is determined that the state of the circuit under test 10 is normal. Otherwise, it means that the state of the circuit under test 10 is abnormal.

[0052] In some embodiments of the present disclosure, the test signal further includes: a power signal and a control signal; wherein the control signal simulates a read / write operation enable signal received by the sense amplifier circuit; and the power signal simulates a voltage connected to the sense amplifier circuit.

[0053] In the present disclosure, Figure 2 and Figure 3 , the test signal also includes a power signal and a control signal. The power signal simulates the voltage connected to the sense amplifier circuit. For example, the power signal includes a first power signal PW'. The first power signal PW' simulates the first voltage PW, and provides a voltage to the body (Body) of the N-type transistor (Negative channel Metal Oxide Semiconductor) in the circuit under test 10. The control signal simulates the read / write operation enable signal received by the sense amplifier circuit. For example, the control signal includes a first test signal EQ', and the read / write operation enable signal includes an equalization signal EQ. The first test signal EQ' simulates the equalization signal EQ, and provides a test voltage to the gate of the equalization transistor M7.

[0054] In some embodiments of the present disclosure, S301 can be used to implement Figure 1 S104 shown will be described in conjunction with each step.

[0055] S301 , for any transistor, analyzing a corresponding test signal and a corresponding test result signal.

[0056] In the present disclosure, Figure 2 and Figure 3 , the gate, drain, source and body of each transistor in the circuit to be tested 10 can be led to the pad 30 through the test line 20. For any transistor, the test equipment can also input test signals to the gate, source, drain and body of the transistor respectively to generate a test result signal. Thus, the test equipment can analyze the corresponding test signal and the corresponding test result signal to determine the electrical performance of the transistor. For example, the test equipment outputs test signals to the gate, source, drain and body of the balancing transistor M7, and then the test equipment can determine whether the state of the balancing transistor M7 is normal according to the change curve of the test current of the drain of the balancing transistor M7.

[0057] In some embodiments of the present disclosure, reference Figure 2 The test piece 100 further includes a plurality of test lines 20 and a plurality of pads 30. The plurality of test lines 20 and the plurality of pads 30 are used to transmit test signals and test result signals. The first end of each test line 20 is connected to the circuit to be tested 10. The second end of each test line 20 is connected to a pad 30.

[0058] In the present disclosure, Figure 2 and Figure 3 , multiple test lines 20 and multiple pads 30 are used to transmit test signals and test result signals. For example, the gate of the first selection transistor M1 receives a fifth test signal CSL' that is analogous to the column selection signal CSL, and the test line 20 and pad 30 corresponding to the fifth test signal CSL' are used to input the fifth test signal CSL', and output the test current generated by the gate of the first selection transistor M1.

[0059] In some embodiments of the present disclosure, Figure 2 and Figure 3 , the control signal includes a first test signal EQ', a second test signal ISO' and a third test signal NcEn'. The read / write operation enable signal includes: an equalization signal EQ, an isolation control signal ISO and an offset control signal NcEn. Among them, the first test signal EQ' is simulated by the equalization signal EQ; the second test signal ISO' is simulated by the isolation control signal ISO; and the third test signal NcEn' is simulated by the offset control signal NcEn.

[0060] In the present disclosure, Figure 2 and Figure 3, the test signal also includes a power signal and a control signal. The power signal includes a first power signal PW', a second power signal NW', a third power signal Vad2', a fourth power signal PCS' and a fifth power signal NCS'. The first selection transistor M1, the second selection transistor M2, the first isolation transistor M3, the second isolation transistor M4, the third isolation transistor M5, the fourth isolation transistor M6, the equalization transistor M7, the transistor M8 in the sense amplifier SA and the transistor M9 in the sense amplifier SA are all N-type transistors, and the transistor M10 in the sense amplifier SA and the transistor M11 in the sense amplifier SA are all P-type transistors (Positive channel Metal Oxide Semiconductor). The power signal simulates the voltage connected to the sensing amplifier circuit. The first power signal PW' simulates the first voltage PW and provides a voltage to the body terminal of the N-type transistor in the circuit to be tested 10. The second power signal NW' simulates the second voltage NW connected to the sensing amplifier circuit and provides a voltage to the body terminal of the P-type transistor in the circuit to be tested 10. The third power signal Vad2' simulates the third voltage Vad2 connected to the sense amplifier circuit, and provides a voltage to the drain of the equalizing transistor M7 in the circuit under test 10. The fourth power signal PCS' simulates the first internal power PCS in the sense amplifier circuit. The fifth power signal NCS' simulates the second internal power NCS in the sense amplifier circuit.

[0061] In the present disclosure, in combination Figure 2 and Figure 3 , the control signal includes: a first test signal EQ', a second test signal ISO', and a third test signal NcEn'. The read / write operation enable signal includes: an equalization signal EQ, an isolation control signal ISO, and an offset control signal NcEn. The control signal simulates the read / write operation enable signal received by the sense amplifier circuit. Among them, the first test signal EQ' simulates the equalization signal EQ, and provides a test voltage to the gate of the equalization transistor M7; the second test signal ISO' simulates the isolation control signal ISO, and provides a test voltage to the gate of the first isolation transistor M3 and the second isolation transistor M4. The third test signal NcEn' simulates the offset control signal NcEn, and provides a test voltage to the gate of the third isolation transistor M5 and the fourth isolation transistor M6.

[0062] In some embodiments of the present disclosure, Figure 2 and Figure 3 The control signal also includes: a fourth test signal IO' and a fifth test signal CSL'. The read / write operation enable signal also includes: a data transmission signal IO and a column selection signal CSL. Among them, the fourth test signal IO' simulates the data transmission signal IO; the fifth test signal CSL' simulates the column selection signal CSL.

[0063] It should be noted that, combined with Figure 2 and Figure 3 The read / write operation enable signal also includes a complementary data transmission signal ION corresponding to the data transmission signal IO. The control signal includes a sixth test signal ION' which simulates the complementary data transmission signal ION and provides a test voltage to the source of the second selection transistor M2.

[0064] In the present disclosure, in combination Figure 2 and Figure 3 , the fourth test signal IO' simulates the data transmission signal IO, and provides a test voltage to the source of the first selection transistor M1; the fifth test signal CSL' simulates the column selection signal CSL, and provides a test voltage to the gate of the first selection transistor M1 or the second selection transistor M2. During the write operation, the fourth test signal IO' or the sixth test signal ION' provides a test voltage to the source of the corresponding first selection transistor M1 and the second selection transistor M2, and the fifth test signal CSL' provides a test voltage to the gate of the first selection transistor M1 or the second selection transistor M2, so that the corresponding first selection transistor M1 or the second selection transistor M2 is turned on, and the data is written into the storage unit. During the read operation, the fifth test signal CSL' turns on the corresponding first selection transistor M1 and the second selection transistor M2, so that the test current on the bit line 111 or the complementary bit line 112 is output.

[0065] In some embodiments of the present disclosure, Figure 5 S401 to S403 are shown to implement S301, and will be described in conjunction with each step.

[0066] S401 , connecting the source, drain and gate of any transistor to a corresponding test signal, and providing a corresponding test voltage to the transistor.

[0067] In the present disclosure, in combination Figure 2 and Figure 3 The test equipment can simulate the working state of the sense amplifier circuit in the test piece 100, input a corresponding test signal to the transistor in the circuit under test 10, and provide a corresponding test voltage to the transistor to test the transistor.

[0068] In the present disclosure, in combination Figure 2 and Figure 3The test device can also separately provide corresponding test voltages to the source, drain and gate of any transistor in the circuit under test 10 to test the transistor. For example, the test device inputs the fifth test signal CSL' to the gate of the first selection transistor M1, inputs the fourth test signal IO' to the source of the first selection transistor M1, inputs the first power supply signal PW' to the body terminal of the first selection transistor M1, and then provides corresponding test voltages to the gate, source and body terminal of the first selection transistor M1.

[0069] S402 , monitoring the test current generated by the source, drain and gate of the transistor.

[0070] In the present disclosure, Figure 2 and Figure 3 After the test equipment inputs the test signal to the transistor, the transistor will generate a test current. Then, the test equipment can monitor the test current generated by the source, drain and gate of the transistor and record the change curve of the test current.

[0071] S403 : Determine the electrical performance of the transistor based on the fitting state between the test current variation curve and the standard output curve.

[0072] It should be noted that the standard output curve may include the output characteristic curve of the transistor and the transfer characteristic curve of the transistor. The output characteristic curve of the transistor is used to characterize: when the source current is constant, the relationship between the drain current Id and Uds; wherein Uds is the voltage difference between the source and drain of the transistor. The transfer characteristic curve of the transistor is used to characterize: when Uds is constant, the relationship between the drain current Id and Ugs of the transistor; wherein Ugs is the voltage difference between the gate and source of the transistor.

[0073] In the embodiments of the present disclosure, reference Figure 3 , the test equipment can determine the electrical performance of the transistor based on the fitting state of the test current change curve and the standard output curve. For example, the test equipment generates the output characteristic curve and transfer characteristic curve corresponding to the first selection transistor M1 based on the test current generated by the drain of the first selection transistor M1 and the test voltage connected to the first selection transistor M1, that is, generates the test current change curve. Thus, the test equipment compares the output characteristic curve and transfer characteristic curve corresponding to the first selection transistor M1 with the corresponding standard output curve. If the test current change curve of the first selection transistor M1 fits the corresponding standard output curve, it means that the state of the first selection transistor M1 is normal.

[0074] In some embodiments of the present disclosure, S501 and / or S502 can be used to implement Figure 5 S401 in the embodiment will be described in combination with each step.

[0075] S501 , connecting the source, drain and gate of any transistor to the corresponding test signal, so that the test voltage connected to the transistor simulates the working voltage when the corresponding transistor in the sensing amplifier circuit is in an on state.

[0076]

[0077] Table 1

[0078] It should be noted that Table 1 illustrates an optional test condition for a transistor. The test condition for a transistor can also be set according to actual needs and is not limited here.

[0079] In the present disclosure, combined with Table 1 and Figure 3 , the transistors in the sensing amplifier circuit in the chip are used as switches, and correspondingly, the test equipment needs to test the open state of the transistors in the circuit to be tested 10. For example, when testing the open state of the balancing transistor M7, the test equipment provides a 1V test voltage to the source of the balancing transistor M7, a 1.35V test voltage to the gate of the balancing transistor M7, a -0.7V test voltage to the body of the balancing transistor M7, and a 0.5V test voltage to the drain of the balancing transistor M7. Thus, the test equipment can determine whether the open state of the balancing transistor M7 is normal based on the degree of fit between the test current change curve of the drain of the balancing transistor M7 and the output characteristic curve of the transistor. If the test current change curve of the drain of the balancing transistor M7 has the same saturation region as the output characteristic curve of the transistor, it means that the open state of the balancing transistor M7 is normal.

[0080] S502 , connecting the source, drain and gate of any transistor to the corresponding test signal, so that the test voltage connected to the transistor simulates the working voltage when the corresponding transistor in the sensing amplifier circuit is in a turned-off state.

[0081] In the present disclosure, combined with Table 1 and Figure 3, the transistors in the sensing amplifier circuit in the chip are used as switches, and the test equipment needs to test the closed state of the transistors in the circuit to be tested 10. For example, when testing the closed state of the balancing transistor M7, the test equipment provides a test voltage of 0.5V to the source of the balancing transistor M7, a test voltage of 0V to the gate of the balancing transistor M7, a test voltage of -0.7V to the body of the balancing transistor M7, and a test voltage of 0.5V to the drain of the balancing transistor M7. Thus, the test equipment determines whether the closed state of the balancing transistor M7 is normal based on the degree of fit between the test current change curve of the drain of the balancing transistor M7 and the output characteristic curve of the transistor. If the test current change curve of the drain of the balancing transistor M7 and the output characteristic curve of the transistor have the same cut-off region, it means that the closed state of the balancing transistor M7 is normal.

[0082] In some embodiments of the present disclosure, S601 can be used to implement Figure 5 S401 in the embodiment will be described in combination with each step.

[0083] S601. When testing the off state of the transistor, a first test voltage is provided to the gate of the transistor, a second test voltage is provided to the source of the transistor, and a third test voltage is provided to the drain of the transistor; the second test voltage and / or the third test voltage are both greater than the first test voltage.

[0084] It should be noted that in the embodiment of the present disclosure, when the N-type transistor in the sensing amplifier circuit is in the off state, the source / drain voltage of the N-type transistor is greater than the gate voltage. Since the transistor will be turned on when the gate voltage of the N-type transistor is greater than its source / drain voltage, when the transistor is in the off state, setting the source / drain voltage of the transistor to be greater than the gate voltage can prevent the transistor from being turned on by mistake due to gate voltage fluctuations.

[0085] Further, in the embodiment of the present disclosure, combined with Table 1 and Figure 3When testing the transistor in the circuit to be tested, a second test voltage and a third test voltage are provided to the source / drain of the N-type transistor, and both the second test voltage and the third test voltage are greater than the first test voltage provided to the gate of the N-type transistor, so that the test equipment can more accurately simulate the voltage condition of the transistor in the sense amplifier circuit when it is in the off state. For example, the second test voltage provided by the test equipment to the source of the first selection transistor M1 can be 0.5V, the third test voltage provided to the drain of the first selection transistor M1 can be 0.5V, and the first test voltage provided to the gate of the first selection transistor M1 can be 0V. The test equipment determines whether the state of the first selection transistor M1 is normal based on whether the change curve of the test current of the drain of the first selection transistor M1 is in the cut-off region of the standard output characteristic curve. In this way, the parameters of the devices such as transistors in the test piece can more accurately reflect the parameters of the corresponding devices in the chip, further improving the accuracy of the test results.

[0086] In some embodiments of the present disclosure, S701 can be used to implement Figure 5 S401 in the embodiment will be described in combination with each step.

[0087] S701. If the transistor is connected to any one of the bit line, the complementary bit line, the read bit line and the complementary read bit line, a fourth test voltage and a fifth test voltage are provided to the source or drain of the transistor; the fourth test voltage and the fifth test voltage have different values; the fourth test voltage and the fifth test voltage respectively simulate different level states of the bit line signal, the complementary bit line signal, the read bit line signal and the complementary read bit line signal in the sensing amplifier circuit.

[0088] In the embodiment of the present disclosure, the signals on the bit line, complementary bit line, read bit line and complementary read bit line in the sense amplifier circuit have different level states. Figure 3 If the transistor in the circuit to be tested 10 is connected to any one of the bit line 111, the complementary bit line 112, the read bit line 113 and the complementary read bit line 114, the test equipment needs to provide a fifth test voltage and a sixth test voltage with different voltage values ​​in the test of the open state (or closed state) of the transistor to simulate the different level states of the transistor in the actual operation of the sensing amplifier circuit to test the transistor. For example, the source of the equalizing transistor M7 is connected to the read bit line 113. When the test equipment tests the open state of the equalizing transistor M7, the test equipment provides 0V and 1V test voltages to the source of the equalizing transistor M7 to simulate the low level and high level states on the read bit line 113 to test the equalizing transistor M7. In this way, the parameters of the transistors and other devices in the test piece can more accurately reflect the parameters of the corresponding devices in the chip, further improving the accuracy of the test results.

[0089] In some embodiments of the present disclosure, S801 can be used to implement Figure 5 S401 in the embodiment will be described in combination with each step.

[0090] S801. Connect the body terminal of any transistor to the corresponding test signal to provide the transistor with a corresponding test voltage; wherein, if the transistor is a P-type transistor, the sixth test voltage connected to its body terminal is positive; or, if the transistor is an N-type transistor, the sixth test voltage connected to its body terminal is negative.

[0091] In the present disclosure, combined with Table 1 and Figure 3 When testing the transistor, in order to prevent the transistor from parasitic conduction, it is necessary to provide a corresponding test voltage to the body terminal of the transistor. If the transistor is a P-type transistor, the sixth test voltage connected to its body terminal is positive; or, if the transistor is an N-type transistor, the sixth test voltage connected to its body terminal is negative. For example, the balancing transistor M7 is an N-type transistor, and the test equipment provides a test voltage of -0.7V to the body terminal of the balancing transistor M7. The transistor M10 in the readout amplifier SA is a P-type transistor, and the test equipment provides a test voltage of 3V to the body terminal of the transistor M10.

[0092] Figure 6 It is a structural schematic diagram of an optional semiconductor test structure provided by an embodiment of the present disclosure.

[0093] The present disclosure also provides a semiconductor test structure, referring to Figure 6 , the semiconductor test structure 400 includes a test piece 100. The test piece 100 includes a circuit to be tested 10. The circuit to be tested 10 has the same structure as the sensing amplifier circuit in the chip. The test piece 100 is connected to a test device 500 and is configured to receive a test signal from the test device; and, generate and output a test result signal. The test signal simulates the input signal of the sensing amplifier circuit in a working state; the test result signal is generated by the circuit to be tested 10 sensing and amplifying the voltage difference between the bit line signal and the complementary bit line signal.

[0094] In the embodiments of the present disclosure, reference Figure 6, the circuit to be tested 10 of the test piece 100 has the same structure as the sensing amplifier circuit in the chip. In this way, the circuit to be tested and the sensing amplifier circuit have the same metal wiring, and the parasitic parameters of the metal wiring in the circuit to be tested are similar to the parasitic parameters of the metal wiring in the sensing amplifier circuit, thereby avoiding the interference of the parasitic parameter differences of the metal wiring on the test results. Therefore, the parameters of devices such as transistors in the test piece can more accurately reflect the parameters of the corresponding devices in the chip, further improving the accuracy of the test results. At the same time, the test piece in the embodiment of the present disclosure can simulate the working state of the sensing amplifier circuit for testing. Compared with the test method of testing each transistor separately in the related art, the test piece can simulate the working state of the chip and test multiple transistors at the same time, further simplifying the test process and saving test time.

[0095] In some embodiments of the present disclosure, Figure 2 and Figure 6 The test piece 100 further includes a plurality of test lines 20 and a plurality of pads 30. The plurality of test lines 20 and the plurality of pads 30 are used to transmit test signals and test result signals. The first end of each test line 20 is connected to the circuit to be tested 10. The second end of each test line 20 is connected to a pad 30.

[0096] In some embodiments of the present disclosure, reference Figure 6 The circuit under test 10 includes a plurality of transistors; the source, drain and gate of each transistor are respectively connected to different pads.

[0097] In the present disclosure, in combination Figure 3 and Figure 6 , the gate, drain, source and body of each transistor in the circuit to be tested 10 can be led to the pad 30 through the test line 20. For example, the gate of the equalizing transistor M7 receives the first test signal EQ' that simulates the equalizing signal EQ in the sense amplifier circuit, and the gate of the equalizing transistor M7 can be led to the pad 30 through the test line 20 corresponding to the first test signal EQ'. The source of the equalizing transistor M7 is connected to the readout bit line 113, and the source of the equalizing transistor M7 can be led to the pad 30 through the test line 20 corresponding to the third test result signal. The drain of the equalizing transistor M7 simulates the third power signal Vad2' of the third voltage Vad2 connected to the sense amplifier circuit, and the drain of the equalizing transistor M7 can be led to the pad 30 through the test line 20 corresponding to the third power signal Vad2'. The body of the equalizing transistor M7 receives the first power signal PW' that simulates the first voltage PW connected to the sense amplifier circuit, and the body of the equalizing transistor M7 can be led to the pad 30 through the test line 20 corresponding to the first power signal PW'.

[0098] Figure 7It is a schematic diagram of the structure of an optional wafer provided in an embodiment of the present disclosure.

[0099] In some embodiments of the present disclosure, reference Figure 7 The test piece 100 and the chips 200 are located on the same wafer 300 . The test piece 100 is located in the scribe line area 310 between adjacent chips 200 .

[0100] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0101] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0102] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor testing method, characterized in that: include: Access the test piece; The test piece includes a circuit to be tested; The circuit to be tested has the same structure as the sensing amplifier circuit in the chip; Inputting a test signal to the circuit under test; the test signal simulates the input signal of the sensing amplifier circuit in a working state; Receiving a test result signal from the circuit to be tested; The test result signal is generated by the circuit under test sensing and amplifying the voltage difference between the bit line signal and the complementary bit line signal; The test result signal is analyzed to determine the state of the circuit to be tested.

2. The semiconductor testing method according to claim 1, characterized in that: Analyzing the test result signal to determine the state of the circuit to be tested includes: Comparing the test result signal with a pre-stored standard output curve; If the test result signal fits the standard output curve, it is determined that the state of the circuit to be tested is normal.

3. The semiconductor testing method according to claim 1, characterized in that: The test signal further includes: a power signal and a control signal; wherein the control signal simulates a read / write operation enable signal received by the sensing amplifier circuit; and the power signal simulates a voltage connected to the sensing amplifier circuit.

4. The semiconductor testing method according to claim 3, characterized in that: The circuit to be tested includes a plurality of transistors; Analyzing the test result signal to determine the state of the circuit to be tested also includes: For any of the transistors, the corresponding test signal and the corresponding test result signal are analyzed to determine the electrical performance of the transistor.

5. The semiconductor testing method according to claim 3, characterized in that: The control signal includes: a first test signal, a second test signal and a third test signal; the read / write operation enable signal includes: an equalization signal, an isolation control signal and an offset control signal; wherein, The first test signal simulates the equalization signal; the second test signal simulates the isolation control signal; and the third test signal simulates the offset control signal.

6. The semiconductor testing method according to claim 3, characterized in that: The control signal further includes: a fourth test signal and a fifth test signal; the read / write operation enable signal further includes: a data transmission signal and a column selection signal; wherein the fourth test signal simulates the data transmission signal; and the fifth test signal simulates the column selection signal.

7. The semiconductor testing method according to claim 4, characterized in that: For any of the transistors, analyzing the corresponding test signal and the corresponding test result signal to determine the electrical performance of the transistor includes: Connecting the source, drain and gate of any of the transistors to the corresponding test signal to provide the transistor with a corresponding test voltage; monitoring a test current generated by a source, a drain and a gate of the transistor; The electrical performance of the transistor is determined based on the fitting state of the test current variation curve and the standard output curve.

8. The semiconductor testing method according to claim 7, characterized in that: The step of connecting the source, drain and gate of any of the transistors to the corresponding test signal and providing the transistor with the corresponding test voltage comprises: Connecting the source, drain and gate of any of the transistors to the corresponding test signal, so that the test voltage connected to the transistor simulates the working voltage of the corresponding transistor in the sensing amplifier circuit when it is in an on state; and / or, The source, drain and gate of any of the transistors are connected to a corresponding test signal, so that the test voltage connected to the transistor simulates the working voltage when the corresponding transistor in the sensing amplifier circuit is in a closed state.

9. The semiconductor testing method according to claim 8, characterized in that: The step of connecting the source, drain and gate of any of the transistors to the corresponding test signal and providing the transistor with the corresponding test voltage comprises: When testing the off state of the transistor, a first test voltage is provided to the gate of the transistor, a second test voltage is provided to the source of the transistor, and a third test voltage is provided to the drain of the transistor; the second test voltage and / or the third test voltage are both greater than the first test voltage.

10. The semiconductor testing method according to claim 8, characterized in that: The step of connecting the source and gate of any of the transistors to a corresponding test signal to provide a corresponding test voltage to the transistor further includes: If the transistor is connected to any one of the bit line, the complementary bit line, the read bit line and the complementary read bit line, a fourth test voltage and a fifth test voltage are provided to the source or drain of the transistor; the fourth test voltage and the fifth test voltage have different values; the fourth test voltage and the fifth test voltage respectively simulate different level states of the bit line signal, the complementary bit line signal, the read bit line signal and the complementary read bit line signal in the sensing amplifier circuit.

11. The semiconductor testing method according to claim 7, characterized in that: For any of the transistors, the corresponding test signal and the corresponding test result signal are analyzed to determine the electrical performance of the transistor, further comprising: Connect the body terminal of any of the transistors to the corresponding test signal and provide a sixth test voltage to the body terminal of the transistor; wherein, if the transistor is a P-type transistor, the sixth test voltage connected to its body terminal is positive; or, if the transistor is an N-type transistor, the sixth test voltage connected to its body terminal is negative.

12. A semiconductor test structure, characterized in that: include: Test piece; The test piece includes a circuit to be tested; The circuit to be tested has the same structure as the sensing amplifier circuit in the chip; The test piece is connected to the test equipment and is configured to receive a test signal from the test equipment; and generate and output a test result signal; the test signal simulates the input signal of the sensing amplifier circuit in a working state; the test result signal is generated after the circuit under test senses and amplifies the voltage difference between the bit line signal and the complementary bit line signal.

13. The semiconductor test structure according to claim 12, characterized in that: The test piece also includes a plurality of test lines and a plurality of pads; The plurality of test lines and the plurality of pads are used to transmit the test signal and the test result signal; wherein, The first end of each of the test lines is correspondingly connected to the circuit to be tested; the second end of each of the test lines is correspondingly connected to one of the pads.

14. The semiconductor test structure according to claim 13, characterized in that: The circuit to be tested includes a plurality of transistors; a source, a drain and a gate of each of the transistors are respectively connected to different pads.

15. The semiconductor test structure according to claim 12, characterized in that: The test piece and the chip are located on the same wafer; The test piece is located in a dicing street area between adjacent chips.

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