Semiconductor test method and semiconductor test structure
By designing test pieces with the same structure as the chip word line driving circuit in semiconductor testing, and simulating the working state for testing, the problems of low testing efficiency and poor accuracy in the prior art are solved, and efficient and accurate semiconductor testing is achieved.
Patent Information
- Application Number
- CN202310814921.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-03
- Publication Date
- 2025-01-10
AI Technical Summary
The existing semiconductor testing methods are inefficient and have poor accuracy in test results. They need to conduct separate tests on each device to be tested, resulting in insufficient time consumption and accuracy.
By designing the test piece, its circuit to be tested has the same structure as the word line driving circuit in the chip, it simulates the working state of the word line driving circuit, inputs the test signal to the circuit to be tested and analyzes the test result signal to determine the circuit to be tested and the transistor to be tested and the circuit to be tested and the transistor to be tested is determined. The state of the metal wiring is to avoid interference with different parasitic parameters, and to achieve simultaneous testing of multiple transistors.
Improves testing efficiency and accuracy, simplifies the testing process, saves test time, and can more accurately reflect device parameters in the chip.
Smart Images
Figure CN119291424A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the semiconductor field, and in particular to a semiconductor testing method and a semiconductor testing structure. Background Art
[0002] In order to test the electrical performance of the devices in the chip, a test element group (TEG) is usually set in the saw path area of the wafer. The test element and the semiconductor chip usually have the same devices and are made by the same process. Therefore, the reliability, stability, process margin and other performance of the semiconductor chip can be evaluated through the test results of the test element.
[0003] In the related art, each device under test (DUT) of the test piece requires a repeated test structure, and each DUT needs to be tested separately, resulting in low test efficiency and poor accuracy of test results. Summary of the invention
[0004] In view of this, the embodiments of the present disclosure provide a semiconductor testing method and a semiconductor testing structure to improve the testing efficiency and the accuracy of the testing results.
[0005] The technical solution of the present invention is achieved in this way:
[0006] The disclosed embodiment provides a semiconductor testing method, comprising: accessing a test piece; the test piece comprises a circuit to be tested; the circuit to be tested has the same structure as a word line driving circuit in a chip; inputting a test signal to the circuit to be tested; the test signal simulates an input signal of the word line driving circuit in a working state; the circuit to be tested receives a test result signal; and analyzing the test result signal to determine a state of the circuit to be tested.
[0007] In the above scheme, the test signal includes: a power signal and a control signal; wherein the control signal simulates the read / write operation enable signal received by the word line driving circuit; the power signal simulates the power supply terminal connected to the word line driving circuit; the test result signal includes: a word line level; the word line level simulates the word line driving signal output by the word line driving circuit.
[0008] In the above scheme, the test result signal is analyzed to determine the state of the circuit to be tested, including: comparing the test result signal with a pre-stored standard output curve; if the test result signal fits the standard output curve, it is determined that the state of the circuit to be tested is normal.
[0009] In the above scheme, the circuit to be tested includes multiple transistors; the first end of each transistor serves as an input end of the circuit to be tested; the second end of each transistor serves as an output end of the circuit to be tested; the test result signal is analyzed to determine the state of the circuit to be tested, and it also includes: for any transistor, the corresponding test signal and the corresponding test result signal are analyzed to determine the electrical performance of the transistor.
[0010] In the above scheme, for any transistor, the corresponding test signal and the corresponding test result signal are analyzed to determine the electrical performance of the transistor, including: connecting the source, drain and gate of any transistor to the corresponding test signal to provide the corresponding test voltage to the transistor; monitoring the test current generated by the source, drain and gate of the transistor; and determining the electrical performance of the transistor based on the fitting state of the test current change curve and the standard output curve.
[0011] In the above scheme, the source, drain and gate of any transistor are connected to the corresponding test signal to provide the transistor with a corresponding test voltage, including: connecting the source, drain and gate of any transistor to the corresponding test signal so that the test voltage connected to the transistor simulates the working voltage of the corresponding transistor in the word line driving circuit when it is in an open state; and / or connecting the source, drain and gate of any transistor to the corresponding test signal so that the test voltage connected to the transistor simulates the working voltage of the corresponding transistor in the word line driving circuit when it is in a closed state.
[0012] In the above scheme, the control signal includes: a first test signal, a second test signal and a third test signal; the read / write operation enable signal includes: a first address decoding signal, a second address decoding signal and a third address decoding signal; wherein the first test signal simulates the first address decoding signal of the word line driving circuit; the second test signal simulates the second address decoding signal of the word line driving circuit; and the third test signal simulates the third address decoding signal of the word line driving circuit. The disclosed embodiment also discloses a semiconductor test structure, which includes: a test piece; the test piece includes a circuit to be tested; the circuit to be tested has the same structure as the word line driving circuit in the chip; the test piece is connected to the test equipment and is configured to receive a test signal from the test equipment; and generates and outputs a test result signal; the test signal simulates the input signal of the word line driving circuit in a working state.
[0013] In the above scheme, the test piece also includes multiple test lines and multiple pads; the multiple test lines and multiple pads are used to transmit test signals and test result signals; wherein the first end of each test line is correspondingly connected to the input end or the output end of the circuit to be tested; the second end of each test line is correspondingly connected to a pad.
[0014] In the above scheme, the circuit to be tested includes a plurality of transistors; the source, drain and gate of each transistor are respectively connected to different pads.
[0015] In the above solution, the test piece and the chip are located on the same wafer; the test piece is located in the dicing area between adjacent chips.
[0016] In the embodiment of the present disclosure, a test piece is connected; the test piece includes a circuit to be tested; the circuit to be tested has the same structure as the word line driving circuit in the chip; a test signal is input to the input end of the circuit to be tested; the test signal simulates the input signal of the word line driving circuit in the working state; the test result signal is received by the output end of the circuit to be tested; the test result signal is analyzed to determine the state of the circuit to be tested. In the embodiment of the present disclosure, the circuit to be tested and the word line driving circuit have the same metal wiring, and the parasitic parameters of the metal wiring in the circuit to be tested are similar to the parasitic parameters of the metal wiring in the word line driving circuit, which avoids the parasitic parameter difference of the metal wiring from interfering with the test result, so that the parameters of the devices such as transistors in the test piece can more accurately reflect the parameters of the corresponding devices in the chip, further improving the accuracy of the test result. At the same time, in the embodiment of the present disclosure, the test piece can simulate the working state of the word line driving circuit for testing. Compared with the test method of testing each transistor separately in the related art, the test piece can simulate the working state of the chip and test multiple transistors at the same time, further simplifying the test process and saving test time. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A schematic diagram of a semiconductor testing method provided by an embodiment of the present disclosure Figure 1 ;
[0018] Figure 2 A schematic diagram of the structure of a test piece provided in an embodiment of the present disclosure;
[0019] Figure 3 A schematic diagram of the structure of a circuit to be tested provided by an embodiment of the present disclosure;
[0020] Figure 4 A waveform diagram of a test signal provided by an embodiment of the present disclosure;
[0021] Figure 5 A schematic diagram of a semiconductor testing method provided by an embodiment of the present disclosure Figure 2 ;
[0022] Figure 6 A schematic diagram of the structure of a semiconductor test structure provided by an embodiment of the present disclosure;
[0023] Figure 7 A schematic diagram of the structure of a wafer provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0024] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.
[0025] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.
[0026] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.
[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.
[0028] Figure 1 is an optional flow chart of the semiconductor testing method provided by the embodiment of the present disclosure, which will be combined with Figure 1 The steps shown are explained.
[0029] S101, connecting a test piece; the test piece includes a circuit to be tested; the circuit to be tested has the same structure as a word line driving circuit in a chip.
[0030] Figure 2 It is a schematic diagram of the structure of an optional test piece provided in an embodiment of the present disclosure.
[0031] In the embodiments of the present disclosure, reference Figure 2 , the test piece 100 may include a circuit to be tested 10, a plurality of test lines 20 and a plurality of pads 30. The circuit to be tested 10 may include a plurality of transistors and metal wirings, and the plurality of transistors are interconnected through the metal wirings. The test equipment is connected to the test piece, that is, the plurality of transistors are connected to the test equipment through the corresponding test lines 20 and pads 30. Thus, the test equipment can input a test signal to the test piece.
[0032] In the embodiments of the present disclosure, reference Figure 2In the embodiments of the present disclosure, metal wiring generally has parasitic parameters such as parasitic capacitance and parasitic resistance. During the operation of the chip, the parasitic parameters of the metal wiring will generate signal noise, which may cause voltage fluctuations of the signal in the circuit, or even cause signal distortion errors, affecting the normal operation of the circuit, and further affecting the performance of the devices in the circuit.
[0033] In the embodiments of the present disclosure, reference Figure 2 , the circuit to be tested 10 and the word line driving circuit in the chip have the same structure, that is, the transistors in the circuit to be tested 10 and the transistors in the word line driving circuit in the chip have the same structure, and the metal wiring in the circuit to be tested 10 and the metal wiring in the word line driving circuit in the chip have the same structure. In other words, the parasitic parameters of the metal wiring in the circuit to be tested 10 are similar to the parasitic parameters of the metal wiring of the word line driving circuit. In this way, the circuit to be tested of the present disclosure has the same metal wiring as the word line driving circuit in the chip, and the test piece can simulate the parasitic parameters of the word line driving circuit in the actual operation process during the test, so that the parameters of the devices such as transistors in the test piece can more accurately reflect the parameters of the corresponding devices in the chip, further improving the accuracy of the test results.
[0034] S102, inputting a test signal to the circuit to be tested; the test signal simulates the input signal of the word line driving circuit in a working state.
[0035] Figure 3 is a schematic diagram of an optional circuit to be tested provided by an embodiment of the present disclosure. It should be noted that: Figure 3 The circuit under test 10 shown only illustrates one driving sub-circuit 110 , and the circuit under test 10 may also include multiple driving sub-circuits 110 , and the multiple driving sub-circuits 110 are connected to one word line 101 , which is not limited here. Figure 3 The second test signal PhDec' in the word line driving circuit simulates the second address decoding signal PhDec (not shown in the figure); Figure 3 The circuit under test 10 and its corresponding word line driving circuit only include one driving sub-circuit 110 . Since one driving sub-circuit 110 drives eight word lines, the second address decoding signal PhDec may be PhDec<0:2>.
[0036] It should also be noted that Figure 2 In the example, the circuit under test 10 includes two driving sub-circuits. Therefore, Figure 2 The second address decoding signal PhDec (not shown in the figure) simulated by the second test signal PhDec' may be PhDec<0:3>. Figure 3 The first test signal GrDecN' in Figure 2In the figure, the first test signal GrDecN'-a and the first test signal GrDecN'-b are used to represent the first test signal GrDecN'-a and the second test signal GrDecN'-b. Figure 3 The word line level WL' in the word line driving circuit is simulated by the word line driving signal WL (not shown in the figure), Figure 3 The word line level WL' in Figure 2 The first test signal GrDecN'-a provides a test voltage to a corresponding driving sub-circuit in the circuit under test 10, and the corresponding test result signal generated is WL'-a. The first test signal GrDecN'-b provides a test voltage to another corresponding driving sub-circuit in the circuit under test 10, and the corresponding test result signal generated is WL'-b.
[0037] In the embodiments of the present disclosure, reference Figure 3 , the test signal can simulate the input signal of the word line driving circuit in the working state. Therefore, the test equipment outputs the test signal to the test piece, and can simulate the working state of the word line driving circuit in the test piece to test the circuit under test 10. For example, the test equipment inputs the first test signal GrDecN' to the gate of the first transistor under test M1 and the second transistor under test M2 in the circuit under test 10, inputs the second test signal PhDec' to the source of the first transistor under test M1 in the circuit under test 10, and inputs the third test signal PhDecN' to the gate of the third transistor under test M3, so that the circuit under test 10 simulates the working state of the word line driving circuit to run. Among them, the first test signal GrDecN' simulates the first address decoding signal GrDecN of the word line driving circuit; the second test signal PhDec' simulates the second address decoding signal PhDec of the word line driving circuit; the third test signal PhDecN' simulates the third address decoding signal PhDecN of the word line driving circuit.
[0038] S103: The circuit to be tested receives a test result signal.
[0039] S104: Analyze the test result signal to determine the state of the circuit to be tested.
[0040] Figure 4 is an optional signal waveform diagram of the test signal and the test result signal provided by the embodiment of the present disclosure. It should be noted that: Figure 4 The unit of the vertical axis is V. Figure 4 The waveforms in the figure are only used as examples. The corresponding waveforms can also be set according to the actual working conditions of the word line driving circuit in the chip, and there is no limitation here. Figure 4 Among them, Q1 is the working state of the activated word line of the analog word line driving circuit, and Q2 is the working state of the closed word line of the analog word line driving circuit.
[0041] In the present disclosure, Figure 3 and Figure 4 The main function of the word line driving circuit is to output a high level or low level word line driving signal to the word line corresponding to the address decoding signal based on the address decoding signal. Correspondingly, during the process of simulating the word line driving circuit in the test piece 100 for testing, the level of the word line in the circuit under test 10 will change. Therefore, the test equipment can be based on Figure 4 The waveform in the test circuit 10 is used to input a corresponding test signal to simulate the working state of the word line driving circuit, and the voltage change of the word line 101 in the test circuit 10 is monitored to generate a corresponding test result signal, that is, the word line level WL'. Thus, the test equipment can determine the state of the test circuit 10 based on whether the word line level WL' fits the word line driving signal WL.
[0042] by Figure 4 Take the Q1 stage as an example to illustrate: Figure 3 and Figure 4 The test device inputs a first test signal GrDecN' that simulates the first address decoding signal GrDecN to the gates of the first transistor M1 and the second transistor M2, inputs a third test signal PhDecN' that simulates the third address decoding signal PhDecN to the gate of the third transistor M3, and inputs a second test signal PhDec' that simulates the second address decoding signal PhDec to the source of the first transistor M1. Thus, the test device can simulate the working state of the activated word line of the word line driving circuit in the circuit 10 under test.
[0043] It should be noted that the sources of the second transistor M2 to be tested and the third transistor M3 to be tested are both connected to the test signal VWLN'. The test signal VWLN' can always maintain a low level during the test.
[0044] When the test starts, the third test signal PhDecN' is at a high level. If the third transistor M3 is in a normal state, the third transistor M3 will be in an open state. The first test signal GrDecN' is at a high level. If the first transistor M1 and the second transistor M2 are in a normal state, the first transistor M1 will be in an off state and the second transistor M2 will be in an open state; and the voltage of the word line level WL' is kept at a low level.
[0045] Then, the third test signal PhDecN' changes from a high level to a low level. If the state of the third transistor M3 to be tested is normal, the third transistor M3 to be tested will be in a closed state. The second test signal PhDec changes from a low level to a high level, and the first test signal GrDecN' changes from a high level to a low level. If the states of the first transistor M1 to be tested and the second transistor M2 to be tested are normal, the first transistor M1 to be tested will be in an open state, and the second transistor M2 to be tested will be in a closed state; and the voltage of the word line level WL' will gradually rise. Thus, the test equipment can determine the state of the circuit 10 to be tested based on whether the word line level WL' fits the word line drive signal WL in the Q1 stage.
[0046] In the embodiments of the present disclosure, reference Figure 3 In the process of testing the test piece in the working state of the simulated word line driving circuit, the gate, drain, source and body of the transistor in the circuit to be tested 10 input the test signal or output the test result signal. Thus, the test equipment can analyze the test signal and the corresponding test result signal corresponding to each transistor to determine the electrical performance of the transistor. For example, the test equipment can output the corresponding test signal to the circuit to be tested 10, and provide the corresponding test voltage to the transistor in the circuit to be tested 10. Then, the test equipment can monitor the test current generated by the source, drain and gate of the transistor, and generate a test current change curve. Thus, the test equipment can compare the test current change curve of the transistor with the standard output curve to determine the electrical performance of the transistor. In the process of simulating the working state of the word line driving circuit in the test piece 100, the test equipment inputs the second test signal PhDec' to the source of the first transistor M1 to be tested, inputs the first test signal GrDecN' to the gate of the first transistor M1 to be tested, inputs the first power supply signal NW' to the body of the first transistor M1 to be tested, and the drain of the first transistor M1 to be tested is connected to the word line 101. The test equipment can monitor the test current of the drain of the first transistor M1 to be tested by monitoring the pad 30 corresponding to the word line 101. Thus, the test equipment determines the state of the first transistor M1 to be tested according to the fitting degree of the test current change curve of the drain of the first transistor M1 to be tested and the standard output curve. In this way, compared with the test method of testing each transistor separately in the related art, the embodiment of the present disclosure can use the working conditions of the chip to test multiple transistors at the same time, thereby further simplifying the test process and saving test time.
[0047] It can be understood that the circuit to be tested of the test piece in the embodiment of the present disclosure has the same structure as the word line driving circuit in the chip. In this way, the circuit to be tested and the word line driving circuit have the same metal wiring, and the parasitic parameters of the metal wiring in the circuit to be tested are similar to the parasitic parameters of the metal wiring in the word line driving circuit, thereby avoiding the interference of the parasitic parameter differences of the metal wiring on the test results, so that the parameters of devices such as transistors in the test piece can more accurately reflect the parameters of the corresponding devices in the chip, further improving the accuracy of the test results. At the same time, the test piece in the embodiment of the present disclosure can simulate the working state of the word line driving circuit for testing. Compared with the test method of testing each transistor separately in the related art, the test piece can simulate the working state of the chip and test multiple transistors at the same time, further simplifying the test process and saving test time.
[0048] In some embodiments of the present disclosure, the test signal includes: a power signal and a control signal. The control signal simulates the read / write operation enable signal received by the word line drive circuit; the power signal simulates the power supply terminal connected to the word line drive circuit. The test result signal includes: a word line level; the word line level simulates the word line drive signal output by the word line drive circuit.
[0049] In the embodiments of the present disclosure, reference Figure 3 The test signal includes a power signal and a control signal. The control signal simulates the read / write operation enable signal received by the word line driving circuit. For example, the control signal includes a first test signal GrDecN', the read / write operation enable signal includes a first address decoding signal GrDecN, and the test device outputs the first test signal GrDecN' that simulates the first address decoding signal GrDecN to the gate of the first transistor M1 to be tested.
[0050] In the present disclosure, Figure 2 and Figure 3, the power signal simulates the power supply terminal connected to the word line driving circuit. For example, the power signal includes a first power supply signal NW', a second power supply signal PW' and a third power supply signal VWLN', and the power supply terminal connected to the word line driving circuit includes a first power supply terminal NW, a second power supply terminal PW and a third power supply terminal VWLN. The test equipment can input a first power supply signal NW' simulated at the first power supply terminal NW to the body terminal of the first transistor to be tested M1, and connect the body terminal of the first transistor to be tested M1 to the corresponding voltage. The test equipment can input a third power supply signal VWLN' simulated at the third power supply terminal VWLN to the source electrodes of the second transistor to be tested M2 and the third transistor to be tested M3, and connect the sources of the second transistor to be tested M2 and the third transistor to be tested M3 to the corresponding voltage. The test equipment can input a second power supply signal PW' simulated at the second power supply terminal PW to the body terminals of the second transistor to be tested M2 and the third transistor to be tested M3, and connect the body terminals of the second transistor to be tested M2 and the third transistor to be tested M3 to the corresponding voltage.
[0051] In some embodiments of the present disclosure, S201 can be used to implement Figure 1 S104 shown will be described in conjunction with each step.
[0052] S201, comparing the test result signal with a pre-stored standard output curve; if the test result signal fits the standard output curve, it is determined that the state of the circuit to be tested is normal.
[0053] In the present disclosure, Figure 2 and Figure 4 The standard output curve may include a standard output curve of the word line drive signal WL. The test equipment may be configured as follows: Figure 4 The waveforms of the first test signal GrDecN', the second test signal PhDec' and the third test signal PhDecN' in the test device 100 output the corresponding test signals, simulate the working state of the word line driving circuit in the test device 100, and output the word line level WL'. The test equipment can compare the word line level WL' with the standard output curve of the pre-stored word line driving signal WL. If the word line level WL' fits the standard output curve of the pre-stored word line driving signal WL, it is determined that the state of the circuit under test 10 is normal. Otherwise, it means that the state of the circuit under test 10 is abnormal.
[0054] In some embodiments of the present disclosure, S301 can be used to implement Figure 1 S104 shown will be described in conjunction with each step.
[0055] S301 . For any transistor, analyze a corresponding test signal and a corresponding test result signal to determine the electrical performance of the transistor.
[0056] In the present disclosure, Figure 2 and Figure 3 , the gate, drain, source and body of each transistor in the circuit to be tested 10 can be led to the pad 30 through the test line 20. For any transistor, the test equipment can also output test signals to the gate, source, drain and body of the transistor respectively to generate a test result signal. Thus, the test equipment can analyze the corresponding test signal and the corresponding test result signal to determine the electrical performance of the transistor. For example, the test equipment outputs test signals to the gate, source, drain and body of the first transistor to be tested M1, and then the test equipment can determine whether the state of the first transistor to be tested M1 is normal according to whether the change curve of the test current of the drain of the first transistor to be tested M1 fits the standard output curve.
[0057] In some embodiments of the present disclosure, Figure 5 S401 to S403 are shown to implement S301, and will be described in conjunction with each step.
[0058] S401 , connecting the source, drain and gate of any transistor to a corresponding test signal, and providing a corresponding test voltage to the transistor.
[0059] In the present disclosure, Figure 2 and Figure 3 The test equipment can simulate the working state of the word line driving circuit in the test piece 100, input a corresponding test signal to the transistor in the circuit under test 10, and provide a corresponding test voltage to the transistor to test the transistor.
[0060] In the present disclosure, Figure 2 and Figure 3 The test device can also separately provide corresponding test voltages to the source, drain and gate of any transistor in the circuit under test 10 to test the transistor. For example, the test device inputs a first test signal GrDecN' to the gate of the first transistor under test M1, inputs a second test signal PhDec' to the source of the first transistor under test M1, inputs a first power signal NW' to the body of the first transistor under test M1, and then provides corresponding test voltages to the gate, source and body of the first transistor under test M1.
[0061] S402 , monitoring the test current generated by the source, drain and gate of the transistor.
[0062] In the present disclosure, Figure 2 and Figure 3 After the test equipment inputs the test signal to the transistor, the transistor will generate a test current. Then, the test equipment can monitor the test current generated by the source, drain and gate of the transistor and record the change curve of the test current.
[0063] S403 : Determine the electrical performance of the transistor based on the fitting state between the test current variation curve and the standard output curve.
[0064] It should be noted that the standard output curve may include the output characteristic curve of the transistor and the transfer characteristic curve of the transistor. The output characteristic curve of the transistor is used to characterize: when the source current is constant, the relationship between the drain current Id and Uds; wherein Uds is the voltage difference between the source and drain of the transistor. The transfer characteristic curve of the transistor is used to characterize: when Uds is constant, the relationship between the drain current Id and Ugs of the transistor; wherein Ugs is the voltage difference between the gate and source of the transistor.
[0065] In the embodiments of the present disclosure, reference Figure 3 , the test equipment can determine the electrical performance of the transistor based on the fitting state of the test current change curve and the standard output curve. For example, the test equipment generates the output characteristic curve and transfer characteristic curve corresponding to the first transistor M1 to be tested based on the test current generated by the drain of the first transistor M1 to be tested and the test voltage connected to the first transistor M1 to be tested, that is, generates the test current change curve. Thus, the test equipment compares the output characteristic curve and transfer characteristic curve corresponding to the first transistor M1 to be tested with the corresponding standard output curve. If the corresponding output characteristic curve and transfer characteristic curve of the first transistor M1 to be tested fit the corresponding standard output curve, it means that the state of the first transistor M1 to be tested is normal.
[0066] In some embodiments of the present disclosure, S401 may be implemented through S501 and / or S502, which will be described in conjunction with each step.
[0067] S501 , connecting the source, drain and gate of any transistor to the corresponding test signal, so that the test voltage connected to the transistor simulates the working voltage when the corresponding transistor in the word line driving circuit is in an on state.
[0068]
[0069] Table 1
[0070] It should be noted that Table 1 illustrates an optional test condition for a transistor. The test condition for a transistor can also be set according to actual needs and is not limited here.
[0071] In the present disclosure, combined with Table 1 and Figure 3When testing a transistor, in order to prevent the transistor from leaking electricity, it is necessary to provide a corresponding test voltage to the body terminal of the transistor. If the transistor is a P-type transistor, the test voltage connected to its body terminal is positive; or, if the transistor is an N-type transistor, the test voltage connected to its body terminal is negative. For example, the first transistor to be tested M1 is a P-type transistor, and the test equipment provides a 3V test voltage to the body terminal of the first transistor to be tested M1. The second transistor to be tested M2 and the third transistor to be tested M3 are both N-type transistors, and the test equipment provides a -0.7V test voltage to the body terminals of the second transistor to be tested M2 and the third transistor to be tested M3.
[0072] In the present disclosure, combined with Table 1 and Figure 3 , the transistors in the word line driving circuit in the chip are used as switches, and correspondingly, the test equipment needs to test the open state of the transistors in the circuit to be tested 10. For example, when testing the open state of the second transistor to be tested M2, the test equipment provides a test voltage of -0.2V to the source of the second transistor to be tested M2, a test voltage of 3V to the gate of the second transistor to be tested M2, a test voltage of 3V to the drain of the second transistor to be tested M2, and a test voltage of -0.7V to the body of the second transistor to be tested M2. Thus, the test equipment can determine whether the open state of the second transistor to be tested M2 is normal based on the degree of fit between the test current change curve of the drain of the second transistor to be tested M2 and the output characteristic curve of the transistor. If the test current change curve of the drain of the second transistor to be tested M2 has the same saturation region as the output characteristic curve of the transistor, it means that the open state of the second transistor to be tested M2 is normal.
[0073] S502, connecting the source, drain and gate of any transistor to the corresponding test signal, so that the test voltage connected to the transistor simulates the working voltage when the corresponding transistor in the word line driving circuit is in the off state.
[0074] In the present disclosure, combined with Table 1 and Figure 3, the transistors in the word line driving circuit in the chip are used as switches, and correspondingly, the test equipment needs to test the closed state of the transistors in the circuit to be tested 10. For example, when testing the closed state of the second transistor to be tested M2, the test equipment provides a test voltage of -0.2V to the source of the second transistor to be tested M2, a test voltage of 0V to the gate of the second transistor to be tested M2, a test voltage of 3V to the drain of the second transistor to be tested M2, and a test voltage of -0.7V to the body of the second transistor to be tested M2. Thus, the test equipment can determine whether the closed state of the second transistor to be tested M2 is normal based on the degree of fit between the test current change curve of the drain of the second transistor to be tested M2 and the output characteristic curve of the transistor. If the test current change curve of the drain of the second transistor to be tested M2 has the same cut-off region as the output characteristic curve of the transistor, it means that the closed state of the second transistor to be tested M2 is normal.
[0075] In some embodiments of the present disclosure, S401 may be implemented through S601, which will be described in conjunction with each step.
[0076] S601. When testing the on state of the first transistor to be tested, a first test voltage is provided to the gate of the first transistor to be tested, and a second test voltage is provided to the source of the transistor; the second test voltage is greater than the first test voltage; when testing the off state of the first transistor to be tested, the second test voltage is provided to the gate of the first transistor to be tested, and the first test voltage is provided to the source of the transistor.
[0077] It should be noted that, in the embodiment of the present disclosure, for the transistor in the word line driving circuit that receives the first address decoding signal GrDecN and the second address decoding signal PhDec, the voltage of the second address decoding signal PhDec connected to its source will switch between a high level and a low level. When the second address decoding signal PhDec is at a high level, the first address decoding signal GrDecN is at a low level, so that Figure 3 The first test transistor M1 in the word line driving circuit is turned on to output a high-level word line driving signal. When the second address decoding signal PhDec is at a low level, the first address decoding signal GrDecN is at a high level, so that Figure 3 The corresponding transistors of the second test transistor M2 and the third test transistor M3 in the word line driving circuit are turned on to output a low level word line driving signal.
[0078] Further, in the embodiment of the present disclosure, combined with Table 1 and Figure 3, the circuit to be tested 10 includes a first transistor to be tested M1. The first transistor to be tested M1 corresponds to a transistor in the word line driving circuit for receiving a first address decoding signal GrDecN and a second address decoding signal PhDec. When the test equipment tests the on state of the first transistor to be tested M1, the first test signal GrDecN' input to the gate of the first transistor to be tested M1 provides a first test voltage, and the second test signal PhDec' input to the source of the first transistor to be tested M1 provides a second test voltage, and the second test voltage is greater than the first test voltage. When the test equipment tests the off state of the first transistor to be tested M1, the first test signal GrDecN' input to the gate of the first transistor to be tested M1 provides a second test voltage, and the second test signal PhDec' input to the source of the first transistor to be tested M1 provides a first test voltage. For example, the first test voltage is 0V, and the second test voltage is 3V. Thus, the test equipment can more accurately simulate the voltage conditions of the corresponding transistor in the word line driving circuit when it is in the off and on states. In this way, the parameters of devices such as transistors in the test piece can more accurately reflect the parameters of corresponding devices in the chip, further improving the accuracy of the test results.
[0079] In some embodiments of the present disclosure, reference Figure 2 The test piece 100 further includes a plurality of test lines 20 and a plurality of pads 30. The first end of each test line 20 is correspondingly connected to the input end or the output end of the circuit to be tested 10; the second end of each test line 20 is correspondingly connected to a pad 30. The plurality of test lines 20 and the plurality of pads 30 are used to transmit test signals and test result signals.
[0080] In the present disclosure, Figure 2 and Figure 3 , multiple test lines 20 and multiple pads 30 are used to transmit test signals and test result signals. For example, the gate of the first transistor M1 to be tested receives the first test signal GrDecN' that simulates the first address decoding signal GrDecN. The test line 20 and pad 30 connected to the gate of the first transistor M1 to be tested are used to input the first test signal GrDecN', and output the test current generated by the gate of the first transistor M1 to be tested.
[0081] In some embodiments of the present disclosure, Figure 2 and Figure 3, the control signal includes: a first test signal GrDecN', a second test signal PhDec' and a third test signal PhDecN'. The read / write operation enable signal includes: a first address decoding signal GrDecN, a second address decoding signal PhDec and a third address decoding signal PhDecN. Among them, the first test signal GrDecN' simulates the first address decoding signal GrDecN of the word line driving circuit; the second test signal PhDec' simulates the second address decoding signal PhDec of the word line driving circuit; the third test signal PhDecN' simulates the third address decoding signal PhDecN of the word line driving circuit.
[0082] In the present disclosure, Figure 2 and Figure 3 , the test device can input the first test signal GrDecN' into the circuit under test 10, and provide a test voltage to the gates of the first transistor under test M1 and the second transistor under test M2. The test device can input the second test signal PhDec' into the circuit under test 10, and provide a test voltage to the source of the first transistor under test M1. The test device can input the third test signal PhDecN' into the circuit under test 10, and provide a test voltage to the gate of the third transistor under test M3. Thus, the test device can make the circuit under test 10 simulate the working state of the word line driving circuit to run.
[0083] Figure 6 It is a structural schematic diagram of an optional semiconductor test structure provided by an embodiment of the present disclosure.
[0084] The present disclosure also discloses a semiconductor test structure, referring to Figure 6 The semiconductor test structure 400 includes a test piece 100. The test piece 100 includes a circuit to be tested 10. The circuit to be tested 10 has the same structure as the word line driving circuit in the chip. The test piece 100 is connected to a test device 500 and is configured to receive a test signal from the test device 500; and to generate and output a test result signal. The test signal simulates an input signal of the word line driving circuit in a working state.
[0085] In the embodiments of the present disclosure, reference Figure 6, the circuit to be tested 10 of the test piece 100 has the same structure as the word line driving circuit in the chip. In this way, the circuit to be tested and the word line driving circuit have the same metal wiring, and the parasitic parameters of the metal wiring in the circuit to be tested are similar to the parasitic parameters of the metal wiring in the word line driving circuit, which avoids the interference of the parasitic parameter differences of the metal wiring on the test results. Therefore, the parameters of devices such as transistors in the test piece can more accurately reflect the parameters of the corresponding devices in the chip, further improving the accuracy of the test results. At the same time, the test piece in the embodiment of the present disclosure can simulate the working state of the word line driving circuit for testing. Compared with the test method of testing each transistor separately in the related art, the test piece can simulate the working state of the chip and test multiple transistors at the same time, further simplifying the test process and saving test time.
[0086] In some embodiments of the present disclosure, Figure 2 and Figure 6 The test piece 100 further includes a plurality of test lines 20 and a plurality of pads 30. The plurality of test lines 20 and the plurality of pads 30 are used to transmit test signals and test result signals. The first end of each test line 20 is correspondingly connected to the input end or the output end of the circuit to be tested 10; the second end of each test line 20 is correspondingly connected to a pad 30.
[0087] In some embodiments of the present disclosure, reference Figure 6 The circuit under test 10 includes a plurality of transistors; the source, drain and gate of each transistor are respectively connected to different pads.
[0088] In the present disclosure, Figure 2 and Figure 3 , the gate, drain, source and body of each transistor in the circuit under test 10 can be led out to the pad 30 through the test line 20. For example, the gate of the first transistor under test M1 receives the first test signal GrDecN' which simulates the first address decoding signal GrDecN in the word line driving circuit, and the gate of the first transistor under test M1 can be led out to the pad 30 through the test line 20 corresponding to the first test signal GrDecN'. The source of the first transistor under test M1 receives the second test signal PhDec' which simulates the second address decoding signal PhDec in the word line driving circuit, and the source of the first transistor under test M1 can be led out to the pad 30 through the test line 20 corresponding to the second test signal PhDec'. The drain of the first transistor under test M1 is connected to the word line 101, and the drain of the first transistor under test M1 can be led out to the pad 30 through the test line 20 corresponding to the word line level WL'. The body terminal of the first transistor M1 to be tested receives a first power signal NW′ simulating the first power terminal NW connected to the word line driving circuit. The body terminal of the first transistor M1 to be tested can be led out to the pad 30 through the test line 20 corresponding to the first power signal NW′.
[0089] In some embodiments of the present disclosure, reference Figure 7 , the test piece 100 and the chips 200 are located on the same wafer 300 ; the test piece 100 is located in the dicing street area 310 between adjacent chips 200 .
[0090] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.
[0091] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.
[0092] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. A semiconductor testing method, characterized in that: include: Access the test piece; The test piece includes a circuit to be tested; The circuit to be tested has the same structure as the word line driving circuit in the chip; Inputting a test signal to the circuit to be tested; the test signal simulates an input signal of the word line driving circuit in a working state; Receiving a test result signal from the circuit to be tested; The test result signal is analyzed to determine the state of the circuit to be tested.
2. The semiconductor testing method according to claim 1, characterized in that: The test signal includes: a power signal and a control signal; wherein the control signal simulates a read / write operation enable signal received by the word line driving circuit; and the power signal simulates a power supply terminal connected to the word line driving circuit; The test result signal includes: a word line level; the word line level simulates a word line driving signal output by the word line driving circuit.
3. The semiconductor testing method according to claim 1, characterized in that: Analyzing the test result signal to determine the state of the circuit to be tested includes: Comparing the test result signal with a pre-stored standard output curve; If the test result signal fits the standard output curve, it is determined that the state of the circuit to be tested is normal.
4. The semiconductor testing method according to claim 1, characterized in that: The circuit to be tested comprises a plurality of transistors; the first end of each of the transistors serves as an input end of the circuit to be tested; the second end of each of the transistors serves as an output end of the circuit to be tested; Analyzing the test result signal to determine the state of the circuit to be tested also includes: For any of the transistors, the corresponding test signal and the corresponding test result signal are analyzed to determine the electrical performance of the transistor.
5. The semiconductor testing method according to claim 4, characterized in that: For any of the transistors, analyzing the corresponding test signal and the corresponding test result signal to determine the electrical performance of the transistor includes: Connecting the source, drain and gate of any of the transistors to the corresponding test signal to provide the transistor with a corresponding test voltage; monitoring a test current generated by a source, a drain and a gate of the transistor; The electrical performance of the transistor is determined based on the fitting state of the test current variation curve and the standard output curve.
6. The semiconductor testing method according to claim 5, characterized in that: The step of connecting the source, drain and gate of any of the transistors to the corresponding test signal and providing the transistor with the corresponding test voltage comprises: Connecting the source, drain and gate of any of the transistors to the corresponding test signal, so that the test voltage connected to the transistor simulates the working voltage of the corresponding transistor in the word line driving circuit when it is in an on state; and / or, The source, drain and gate of any of the transistors are connected to the corresponding test signal, so that the test voltage connected to the transistor simulates the working voltage when the corresponding transistor in the word line driving circuit is in a closed state.
7. The semiconductor testing method according to claim 2, characterized in that: The control signal includes: a first test signal, a second test signal and a third test signal; the read / write operation enable signal includes: a first address decoding signal, a second address decoding signal and a third address decoding signal; wherein, The first test signal simulates a first address decoding signal of the word line driving circuit; the second test signal simulates a second address decoding signal of the word line driving circuit; and the third test signal simulates a third address decoding signal of the word line driving circuit.
8. A semiconductor test structure, characterized in that: include: Test piece; The test piece includes a circuit to be tested; The circuit to be tested has the same structure as the word line driving circuit in the chip; The test piece is connected to the test equipment and is configured to receive a test signal from the test equipment; and generate and output a test result signal; the test signal simulates an input signal of the word line driving circuit in a working state.
9. The semiconductor test structure according to claim 8, characterized in that: The test piece also includes a plurality of test lines and a plurality of pads; The plurality of test lines and the plurality of pads are used to transmit the test signal and the test result signal; wherein, The first end of each of the test lines is correspondingly connected to the input end or the output end of the circuit to be tested; the second end of each of the test lines is correspondingly connected to one of the pads.
10. The semiconductor test structure according to claim 9, characterized in that: The circuit to be tested includes a plurality of transistors; a source, a drain and a gate of each of the transistors are respectively connected to different pads.
11. The semiconductor test structure according to claim 8, characterized in that: The test piece and the chip are located on the same wafer; The test piece is located in a dicing street area between adjacent chips.