Method and system for boundary scan test and effective positioning of short circuit fault

Abstract

The invention discloses a method and a system for boundary scan testing and effective positioning of a short circuit fault. The method comprises the following steps: acquiring first data corresponding to a short circuit fault to be subjected to boundary scan testing and positioning in real time; wherein the first data is a connection relationship of a to-be-tested connection network; based on the first data, respectively generating second data and third data corresponding to a to-be-tested connection network; according to the second data and the third data and in combination with the first data, performing binary processing on level data sent in the to-be-tested connection network; according to the transmission state of the level data in the to-be-tested connection network, fourth data corresponding to the to-be-tested connection network is generated; wherein the fourth data is short-circuit fault data of the to-be-tested connection network; according to the method, the system and the platform corresponding to the method, the short-circuit faults can be clearly checked among the connected networks, and the short-circuit fault checking efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of boundary scan test processing, and in particular relates to a method and a system for boundary scan testing and effectively locating short circuit faults. Background Art

[0002] In the field of boundary scan test fixtures, it is necessary to test the internal signals of the board under test (DUT) and the open and short circuit faults between the signals. Since there are many types and models of boundary scan chips inside the DUT, such as CPU, FPGA, CPLD, BMC, PCH, etc., the test of the boundary scan chip of the DUT to the connector requires the support of the analog test card. The analog test card also has boundary scan chips, such as FPGA, ARM, etc. The transceiver connections between the pins of these boundary scan chips (BS chips) form a testable connection network. Each connection network consists of BS chip pins and connection lines that can communicate signals. During the boundary scan test process , the signal is sent and received in the same connection network, and the data reception result is used to determine whether each connection network has an open circuit fault. The open circuit fault occurs in a known connection network, and the open circuit fault can be detected by measuring the connectivity in the connection network. The open circuit fault is relatively easy to detect, while the short circuit fault occurs between different connection networks. The existing method can report the connection network that failed the test (fail) and print out the test vector data corresponding to each connection network that failed the test. When a short circuit occurs between different connection networks, it can be detected that a fault has occurred, but it is impossible to distinguish whether the connection network that failed the test is caused by an open circuit fault or a short circuit fault. The troubleshooting of short circuit faults is relatively complicated, because the short circuit fault occurs between at least two connection networks, and the connection networks with short circuit faults need to be associated in the algorithm to help troubleshoot the short circuit fault. The existing test method has obvious defects in solving this problem. For the customer's on-site maintenance personnel, they lack the ability to eliminate short-circuit faults between different connection networks of the DUT. They are unable to comprehensively analyze the connection networks and test vector data of failed tests and determine which pins (at least 2) have short-circuited. Once a problem that cannot be repaired occurs, they contact engineers. However, it is not easy for engineers to handle short-circuit faults. They often need to eliminate various possibilities of failure and even go to the customer's site to handle it, which makes maintenance extremely inconvenient. Further research and analysis show that the existing algorithm needs to consider two defects. First, when a short-circuit fault occurs, it is often the case that only one connection network fault is reported, while other connection networks that are short-circuited with this connection network cannot be reported. The test algorithm has obvious defects and does not support the ability to effectively locate short-circuit faults. Second, even if short-circuit faults between connection networks can be reported in the form of test fails, the connection networks of these fails are relatively scattered. In the algorithm, the vector data of short-circuit faults between any connection networks are not associated and integrated, and short-circuit fault prompts between connection networks cannot be performed. Customer on-site maintenance personnel cannot clearly know whether a short-circuit fault has occurred, do not know which connection networks have short-circuit faults, and do not know whether the short-circuit faults need to be checked.

[0003] Therefore, in view of the above short-circuit faults occurring between different connection networks, which are difficult to troubleshoot technical problems and defects, it is urgent to design and develop a method and system for boundary scan testing that can effectively locate short-circuit faults. Summary of the invention

[0004] In order to overcome the deficiencies and difficulties of the above-mentioned prior art, the present invention provides a method, system and platform for boundary scan testing and effective positioning of short-circuit faults, which can clearly identify between which connection networks short-circuit faults are to be detected, thereby improving the efficiency of short-circuit fault detection.

[0005] The first object of the present invention is to provide a method for boundary scan testing and effectively locating short-circuit faults; the second object of the present invention is to provide a system for boundary scan testing and effectively locating short-circuit faults; the third object of the present invention is to provide a platform for boundary scan testing and effectively locating short-circuit faults.

[0006] The first object of the present invention is achieved in that the method comprises the following steps:

[0007] Acquire in real time first data corresponding to a short circuit fault to be tested by boundary scan and located; wherein the first data is a connection relationship of a connection network to be tested;

[0008] Based on the first data, second data and third data corresponding to the connection network to be tested are respectively generated; wherein the second data is only output pin data in the connection network to be tested; and the third data is only receiving pin data in the connection network to be tested;

[0009] According to the second data and the third data, and in combination with the first data, binary processing is performed on the level data sent in the connection network to be tested;

[0010] According to the transmission state of the level data in the connection network to be tested, fourth data corresponding to the connection network to be tested is generated; wherein the fourth data is short circuit fault data of the connection network to be tested.

[0011] Further, the generating, based on the first data, second data and third data corresponding to the connection network to be tested, respectively, further includes:

[0012] Generate and obtain fifth data corresponding to the connection network to be tested; wherein the fifth data is a link. Further, based on the first data, respectively generate second data and third data corresponding to the connection network to be tested, and also include:

[0013] According to the arrangement order of the boundary register units from the data input signal end to the data output signal end, sequentially searching for the register units with only output capability;

[0014] Based on the register unit with only output capability, corresponding sixth data is transmitted in real time at the data output signal terminal; wherein the sixth data is level form data corresponding to 0 or 1.

[0015] Further, the binary processing of the level data sent in the tested connection network according to the second data and the third data and in combination with the first data also includes:

[0016] Determine in real time whether the first data is an integer, if so, execute the next step; otherwise, add 1 to the first data and then execute the next step;

[0017] Processing the first data in two equal parts, sending high-level data in real time in one of the data, and sending low-level data in real time in the other data;

[0018] Get all the data after the binary division, and repeat the above two steps until the binary data is 1.

[0019] Further, the binary processing of the level data sent in the tested connection network according to the second data and the third data and in combination with the first data also includes:

[0020] Determine in real time whether the first data is an integer, if so, execute the next step; otherwise, add 1 to the first data and then execute the next step;

[0021] Processing the first data in two equal parts, sending low-level data in real time in one of the data, and sending high-level data in real time in the other data;

[0022] Get all the data after the binary division, and repeat the above two steps until the binary data is 1.

[0023] Furthermore, the step of generating fourth data corresponding to the connection network to be tested according to the transmission state of the level data in the connection network to be tested further includes:

[0024] Generate and obtain a plurality of fourth data, associate and process the plurality of fourth data, and generate seventh data corresponding to the plurality of fourth data; wherein the seventh data is prompt data indicating a possible short circuit fault.

[0025] The second object of the present invention is achieved in this way: the system is applied to the method for boundary scan testing and effectively locating short circuit faults, and the system comprises:

[0026] A data acquisition unit, used for acquiring in real time first data corresponding to a short-circuit fault to be tested by boundary scan and located; wherein the first data is a connection relationship of a connection network to be tested;

[0027] A first data generating unit, configured to generate second data and third data corresponding to the connection network to be tested, respectively, based on the first data; wherein the second data is only output pin data in the connection network to be tested; and the third data is only receiving pin data in the connection network to be tested;

[0028] A data binary processing unit, configured to binary process the level data sent from the connection network to be tested according to the second data and the third data and in combination with the first data;

[0029] The second data generating unit is used to generate fourth data corresponding to the connection network to be tested according to the transmission status of the level data in the connection network to be tested; wherein the fourth data is short circuit fault data of the connection network to be tested.

[0030] Furthermore, the first data generating unit further includes:

[0031] A first generating module is used to generate and obtain fifth data corresponding to the connection network to be tested; wherein the fifth data is pin data of a link that has only a sending capability but no receiving capability;

[0032] And / or, the data binary processing unit further includes:

[0033] A first determination module, used for determining in real time whether the first data is an integer;

[0034] A first processing module, used for processing the first data in two equal parts, and sending high-level data in real time in one of the data, and sending low-level data in real time in the other data;

[0035] The second processing module is used to obtain all the data after the bisection process, and repeat the bisection process until the bisection data is 1;

[0036] And / or, the second data generating unit further includes:

[0037] The third processing module is used to generate and obtain a plurality of fourth data, and associate and process the plurality of fourth data, and generate seventh data corresponding to the plurality of fourth data; wherein the seventh data is prompt data of a possible short circuit fault.

[0038] Furthermore, the first data generating unit further includes:

[0039] A first search module is used to sequentially search for register units with only output capability according to the arrangement order of boundary register units from the data input signal end to the data output signal end;

[0040] A data transmission module, configured to transmit corresponding sixth data in real time at the data output signal terminal based on the register unit having only output capability; wherein the sixth data is level data corresponding to 0 or 1;

[0041] And / or, the data binary processing unit further includes:

[0042] A second determination module is used to determine in real time whether the first data is an integer, and if so, execute the next step; otherwise, add one to the first data and then execute the next step;

[0043] a fourth processing module, configured to divide the first data into two equal parts, and send high-level data in real time in one of the data, and send low-level data in real time in the other data;

[0044] The fifth processing module is used to obtain all the data after the binary division process, and repeat the above two steps until the binary division data is 1.

[0045] The third object of the present invention is achieved as follows: it includes a processor, a memory, and a platform control program for boundary scan testing and effectively locating short-circuit faults; wherein the platform control program for boundary scan testing and effectively locating short-circuit faults is executed on the processor, the platform control program for boundary scan testing and effectively locating short-circuit faults is stored in the memory, and the platform control program for boundary scan testing and effectively locating short-circuit faults implements the method for boundary scan testing and effectively locating short-circuit faults.

[0046] The present invention uses a method to obtain in real time first data corresponding to a short-circuit fault to be tested by boundary scanning and to be located; wherein the first data is a connection relationship of a connection network to be tested; based on the first data, second data and third data corresponding to the connection network to be tested are respectively generated; wherein the second data is only output pin data in the connection network to be tested; and the third data is only receiving pin data in the connection network to be tested; according to the second data and the third data, and in combination with the first data, the level data sent in the connection network to be tested is binary processed; according to the transmission state of the level data in the connection network to be tested, fourth data corresponding to the connection network to be tested is generated; wherein the fourth data is short-circuit fault data of the connection network to be tested; and a system and platform corresponding to the method can clearly identify between which connection networks short-circuit faults are to be checked, thereby improving the efficiency of short-circuit fault troubleshooting. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 A schematic flow chart of a method for boundary scan testing and effectively locating short circuit faults according to the present invention;

[0049] Figure 2 A schematic diagram of a hardware framework for simulating seven connection networks to be tested according to an embodiment of a method for boundary scan testing and effectively locating short circuit faults of the present invention;

[0050] Figure 3 A schematic diagram of a data transmission framework for simulating seven connected networks to be tested in an embodiment of a method for boundary scan testing and effectively locating short circuit faults according to the present invention;

[0051] Figure 4 A schematic diagram of a system architecture for boundary scan testing and effectively locating short circuit faults according to the present invention;

[0052] Figure 5 The present invention is a schematic diagram of a platform architecture for boundary scan testing and effectively locating short circuit faults. DETAILED DESCRIPTION

[0053] In order to better understand the purpose, technical solutions and advantages of the present invention, the present invention is further described below in conjunction with the accompanying drawings and specific implementation methods. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0054] The present invention may also be implemented or applied through other different specific examples, and the details in this specification may also be modified and changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0056] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. Secondly, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0057] Preferably, the method for boundary scan testing and effectively locating short circuit faults of the present invention is applied in one or more terminals or servers. The terminal is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application specific integrated circuits (ASIC), field programmable gate arrays (FPGA), digital signal processors (DSP), embedded devices, etc.

[0058] The terminal can be a computing device such as a desktop computer, a notebook, a PDA, a cloud server, etc. The terminal can interact with the client through a keyboard, a mouse, a remote control, a touch pad, or a voice control device.

[0059] The present invention is to realize a method, system and platform for boundary scan testing and effectively locating short circuit faults.

[0060] like Figure 1 , which is a flow chart of a method for boundary scan testing and effectively locating short circuit faults provided by an embodiment of the present invention. In this embodiment, the method for boundary scan testing and effectively locating short circuit faults can be applied to a terminal or a fixed terminal with a display function, and the terminal is not limited to a personal computer, a smart phone, a tablet computer, a desktop computer or an all-in-one computer equipped with a camera, etc.

[0061] The method for boundary scan testing and effectively locating short circuit faults can also be applied to a hardware environment consisting of a terminal and a server connected to the terminal via a network. The network includes but is not limited to: a wide area network, a metropolitan area network, or a local area network. The method for boundary scan testing and effectively locating short circuit faults in the embodiment of the present invention can be executed by a server, can be executed by a terminal, or can be executed by both a server and a terminal.

[0062] For example, for a terminal that needs to be used for boundary scan testing and effectively locate short-circuit faults, the function of boundary scan testing and effectively locating short-circuit faults provided by the method of the present invention can be directly integrated on the terminal, or a client for implementing the method of the present invention can be installed. For another example, the method provided by the present invention can also be run on a server or other device in the form of a software development kit (Software Development Kit, SDK), and an interface for the function of boundary scan testing and effectively locating short-circuit faults is provided in the form of SDK. The terminal or other device can implement the function of boundary scan testing and effectively locating short-circuit faults through the provided interface. The present invention is further described below in conjunction with the accompanying drawings.

[0063] like Figure 1 As shown, the present invention provides a method for boundary scan testing and effectively locating short circuit faults, wherein the method comprises the following steps:

[0064] S1. Acquire in real time first data corresponding to a short circuit fault to be tested by boundary scan and located; wherein the first data is a connection relationship of a connection network to be tested;

[0065] S2. Based on the first data, respectively generate second data and third data corresponding to the connection network to be tested; wherein the second data is only output pin data in the connection network to be tested; and the third data is only receiving pin data in the connection network to be tested;

[0066] S3, according to the second data and the third data, and in combination with the first data, binary processing of the level data sent in the tested connection network;

[0067] S4. Generate fourth data corresponding to the connection network to be tested according to the transmission state of the level data in the connection network to be tested; wherein the fourth data is short-circuit fault data of the connection network to be tested.

[0068] The generating, based on the first data, second data and third data corresponding to the connection network to be tested respectively, further includes:

[0069] S21. Generate and obtain fifth data corresponding to the connection network to be tested; wherein the fifth data is pin data of a link that has only a sending capability but no receiving capability.

[0070] The generating, based on the first data, second data and third data corresponding to the connection network to be tested respectively, further includes:

[0071] S22, searching for register units with only output capability in sequence according to the arrangement order of the boundary register units from the data input signal end to the data output signal end;

[0072] S23. Based on the register unit with only output capability, corresponding sixth data is transmitted in real time at the data output signal terminal; wherein the sixth data is level form data corresponding to 0 or 1.

[0073] The binary processing of the level data sent from the tested connection network according to the second data and the third data and in combination with the first data also includes:

[0074] S31, determining in real time whether the first data is an integer, if so, executing the next step; otherwise, adding 1 to the first data and then executing the next step;

[0075] S32, dividing the first data into two equal parts, and sending high-level data in real time in one of the data, and sending low-level data in real time in the other data;

[0076] S33, obtain all the data after the binary division process, and repeat the above two steps until the binary data is 1.

[0077] The binary processing of the level data sent from the tested connection network according to the second data and the third data and in combination with the first data also includes:

[0078] S34, determining in real time whether the first data is an integer, if so, executing the next step; otherwise, adding 1 to the first data and then executing the next step;

[0079] S35, dividing the first data into two equal parts, and sending low-level data in real time in one of the data, and sending high-level data in real time in the other data;

[0080] S36, obtain all the data after the binary division process, and repeat the above two steps until the binary data is 1.

[0081] The step of generating fourth data corresponding to the connection network to be tested according to the transmission state of the level data in the connection network to be tested further includes:

[0082] S41, generating and acquiring a plurality of fourth data, and associatively processing the plurality of fourth data, and generating seventh data corresponding to the plurality of fourth data; wherein the seventh data is prompt data indicating a possible short circuit fault.

[0083] Specifically, in an embodiment of the present invention, in order to make the short-circuit fault location method applicable to general DUTs, the algorithm needs to consider the short-circuit faults that may exist between any two connection networks, and summarize the specific connection networks between which the short-circuit faults occur, so as to facilitate on-site maintenance by customers.

[0084] For each connection network, at least two or more pins form a transceiver relationship, so that open and short circuit testing can be performed. For any connection network, it is necessary to determine that one of the pins is an output (drive) pin that can output high and low levels, and the other pins are input (receive) pins that can receive data output from the drive pins on the same connection network.

[0085] For each pin on the connection network, two outputs are not allowed at the same time. After each connection network determines the unique drive pin, the other pins are receive pins, which can complete the transmission and reception test of one output to one or more inputs.

[0086] In order to effectively locate the short-circuit fault, assume that any two connection networks are named connection network A1 and connection network A2. At the same time, assume that the drive pin output of connection network A1 is 0 and the drive pin output of connection network A2 is 1. When connection network A1 and connection network A2 are short-circuited, the 0 and 1 levels of connection network A1 and connection network A2 conflict, and the receive pin of connection network A2 will receive 0 (output 0 means that the signal is pulled to GND, so when 0 and 1 conflict, the high level 1 driven is pulled to the low level 0), which is inconsistent with the expected value 1. At this time, connection network A2 will report a fault, while the data received by connection network A1 is 0, which is the same as the expected value, and no fault can be reported.

[0087] Therefore, even if any two networks meet the short-circuit test of outputting 0 and 1 at the same time, at most one of the connected networks can be detected to have a fault, while the other connected network that is short-circuited with it cannot report a fault, and there is no way to distinguish whether it is an open circuit or a short circuit fault.

[0088] In order to report all connection network faults when a short circuit occurs, the following method is used. Assuming that any two connection networks are connection network A1 and connection network A2, the drive pin output of connection network A1 is 0, and the drive pin output of connection network A2 is 1. After the connection network A2 fault is detected, the drive pin output of connection network A1 is 1, and the drive pin output of connection network A2 is 0. The connection network A1 fault is detected, that is, the connection network A1 and the connection network A2 output 0 and 1 and 1 and 0 signals respectively at the same time. This can ensure that any two connection networks can report faults when a short circuit occurs.

[0089] With the existing method, even if any two connection networks have a short-circuit fault, the test fail caused by the short-circuit fault is the same as the test fail of the open circuit, both of which are based on a single connection network. The reported fail information is scattered, and it is impossible to know between which two connection networks the short-circuit fault occurs. Therefore, while ensuring that all connection network faults can be reported, it is also necessary to be able to associate the short-circuit faults between multiple connection networks together, so as to provide users with more accurate short-circuit fault positioning and facilitate the elimination of short-circuit faults.

[0090] In order to achieve the above technical objectives, from an algorithmic point of view, it is necessary to ensure that any two connection networks, namely connection network A1 and connection network A2, are tested by outputting 0 and 1 from their respective drive pins once, and 0 and 1 are reversed, and 1 and 0 are output for the second test, so that the faults of any two connection networks can be reported. On this basis, combined with the two tests before and after the drive pin data is flipped, the results of the two tests are associated, which can prompt the customer's on-site maintenance personnel which two connection networks have a short circuit fault. The customer's on-site maintenance personnel can specifically troubleshoot the short circuit fault and improve the efficiency of short circuit fault troubleshooting. It can be seen that if any two connection networks have the test capability of outputting 0 and 1 and 1 and 0 twice simultaneously, the short circuit fault can be effectively located.

[0091] It is known that after the unique drive pin on a connection network is determined, the other receive pins are also determined accordingly, and then extended to the boundary register cell (cell) of the boundary scan, the drive pin corresponds to the output, and the configuration register cell is filled with a non-safe value (the non-safe value may be 0 or 1, determined by the standard BSDL file definition of the boundary scan chip) to ensure that the drive pin can update the output, the receive pin corresponds to the input, and the configuration register cell has a safe value (the safe value may be 0 or 1, also determined by the standard BSDL file definition of the boundary scan chip) to ensure that the receive pin only receives. In short, after the unique drive pin on each connection network is determined, the data of the configuration register of the BS chip is also determined. Therefore, in order to achieve the effect of effectively locating short-circuit faults between connection networks, it is only necessary to consider how the drive pin sends data to achieve it.

[0092] The BSDL file defines the cell order of the boundary register unit of the boundary scan chip, including control cell, input cell, output cell, and INOUT cell, which is used as both input and output. IN, OUT and IN OUT cells all have corresponding control cell controls, such as:

[0093] When a control cell is an unsafe value, the data of the corresponding OUT or INOUT cell will be updated to the output pin in the form of the corresponding level. At this time, the pin is the drive pin. On the contrary, when the control cell is a safe value, the corresponding pin is the receive pin. The receive pin does not update data. It receives the data updated by the drive pin on the same connection network to form a send-receive relationship, so that the test can be completed. In addition, there are internal cells in BSDL, which do not participate in the actual sending and receiving of data, and will not be elaborated here.

[0094] Each connection network has a unique drive pin and multiple receive pins. The drive pin is determined in the boundary scan test as follows:

[0095] In the boundary register, the control cell, IN cell, OUT cell or INOUT cell, and internal cell form the boundary scan register cell order is fixed.

[0096] According to the order of the boundary register cells, each control cell is searched for the situation where it only controls the OUT cell. The pin corresponding to this OUT cell has only output capability. The pin corresponding to the first OUT cell with only output capability found in each connection network is configured as a drive pin. This is because in the same connection network, if other pins are defined as drive pins, the pin with only output capability will not be able to receive data, thus losing test coverage, which is not allowed by the customer.

[0097] After the drive pins with output capability on each connection network are determined, the control cell corresponding to the first OUT cell or INOUT cell with drive capability on each remaining connection network is configured as a non-safe value in the order of the boundary register cells. The pins corresponding to these OUT cells or INOUT cells are drive pins that can update output data.

[0098] In this way, the drive pins of all connected networks are determined. In addition, other IN or INOUT cells on each connected network are configured as safe values, and the corresponding chip pins are receive pins, which can receive the data updated by the drive pins in the same connected network.

[0099] To effectively locate the short-circuit fault, a binary drive algorithm is used. Specifically, assuming that there are m connected networks with measurable send-receive relationships, the m connected networks correspond to m drive pins respectively.

[0100] when When it is an integer, in the first step, the drive pins corresponding to the m connected networks are sent in sequence 1 and 0, when the short circuit fault is here The drive pin of 1 and When a 0 is generated between the connection networks corresponding to the drive pins, only test data The receive pin corresponding to the 1 will receive the wrong data. In the second step, the data divided in the first step is further divided into two parts, and each time the first half of the data is kept unchanged. 1 is divided into two 1 and 0, 0 is divided into two 0 and 1, that is, the drive pins corresponding to the m connected networks are sent in sequence 1, 0, 0, 1, and so on, continue to divide by two, until all the binary data units are 1 and cannot be divided any further; When is an integer, assume that the m drive data cannot be divided further in step a.

[0101] when If it is a decimal, it cannot be In the case of integers, the m data are divided into two parts continuously. At this time, the following processing is required. First, determine The integer part of Indicates that, since the number of drive pins is greater than So each step sends Not enough data, and send The data is redundant.

[0102] In this case, the algorithm is based on the number of drive pins. Perform binary division, the method of binary division is the same as described above When it is an integer, the number of drive pins is an integer. The corresponding binary data,

[0103] Due to the number of drive pins You just need to delete the redundant test vectors and then test again.

[0104] Specifically, in the first step, the algorithm follows Perform binary search, assuming there is The drive pins corresponding to the connected networks are sent in sequence. 1 and 0, but the number of drive pins Therefore, the data sent in the first step needs to delete the following bit data, i.e. delete The last 0 part 0, and finally the drive pins corresponding to the m connected networks are sent in sequence 1 and 0, when the short circuit fault occurs The drive pin of 1 and When a 0 occurs between the connected networks corresponding to the drive pins, only the test data The receive pin corresponding to a 1 will receive wrong data;

[0105] The second step is the first half of the first step after the binary division. 1, because is an integer, this part is normally divided into two parts 1 and 0, when the short circuit fault occurs 1 and When a connection network corresponding to 0 is generated, only The receive pin corresponding to 1 will receive the wrong data; the second half after the first step of binary division is different from the first half, and the number of drive pins in the second half is insufficient But still according to The binary algorithm is executed, but when the algorithm is finally executed, the data behind each step of the algorithm is deleted. bit data, that is, to delete redundant test vectors, to ensure that only data with m drive pins is sent in one step.

[0106] And so on, continue to execute until the number of units of all binary data is 1 and can no longer be binary divided. When it is a decimal, the total is two points step.

[0107] The above binary drive algorithm can only report that a fault has occurred, but cannot accurately report which two connected networks have a short circuit fault. In order to achieve this goal, it is necessary to improve the above binary drive algorithm. The method is as follows:

[0108] Similarly, the above binary drive algorithm still needs to be executed, but after executing each step of the above binary drive algorithm, the data sent in each step is flipped and sent again.

[0109] Specific examples are as follows: When it is an integer, in the first step, the drive pins corresponding to the m connected networks are sent in sequence 1 and 0, when the short circuit fault is here The drive pins of 1 and When a 0 is generated between the drive pins corresponding to the connection network, the front The receive pin corresponding to the m 1 will receive the wrong data, and the corresponding connection network will report a fault; the second step is to flip the data and send it again, that is, the drive pins corresponding to the m connection networks will send the data in sequence. 0 and 1, when the short circuit fault is here The drive pins of the 0 and When a 1 is generated between the drive pins corresponding to the connection network, The receive pin corresponding to a 1 will receive incorrect data, and the corresponding connection network will report a fault.

[0110] Combining the first step and the second step after flipping,

[0111] current The number of connected networks reporting test failures for each 1 test data is 1. When the number of connected networks reporting a test fail is also 1 for each test data, it will effectively indicate that there is a short circuit fault between the two connected networks.

[0112] current The number of connected networks reporting test failures for each 1 test data item appears to be 1 or more. When the number of connected networks reporting test fail for each test data is also 1 or several, it will effectively prompt that there may be a short circuit fault between 1 or several connected networks before the binary division and 1 or several connected networks after the binary division. In practical applications, there will not be too many short circuit faults, so it is effective.

[0113] Similarly, the second step of the binary drive algorithm is still executed according to the above method.

[0114] While the algorithm can effectively locate short-circuit faults, it also has an advantage that the test vectors corresponding to each connection network have changes between 0 and 1, which can take into account open and short circuit tests at the same time.

[0115] In the actual boundary scan test at the customer site, comprehensive judgment and location of short-circuit faults will waste more time. Short-circuit faults may only occur when a fail occurs, and once the DUT test fixture is debugged and stabilized, the number of connection networks that fail in each DUT test will not be too many. We set it to judge whether there is a short-circuit fault between p failed connection networks at most. p is a fixed value, indicating that at most p failed connection networks are supported for further comprehensive location of short-circuit faults. Users can flexibly set values ​​from 1 to p through the host computer, and flexibly set q value through the host computer. Set it to q, at this time 1≤q≤p, it will prompt whether there are related short-circuit faults between q failed connection networks at most according to the order of the boundary scan register cells.

[0116] For the short-circuit fault problem of q failed connection networks, it is only necessary to find the test fail data and the connection network associated with the short-circuit test fail according to the binary drive algorithm. If the connection network associated with the failed connection network passes the test, it means that the failed connection network is not caused by a short-circuit fault. If the connection network associated with the short-circuit fails the test, it means that a short circuit may occur between the failed connection network and the connection network associated with the short-circuit. At this time, a short-circuit fault prompt is reported, and the customer's on-site maintenance personnel will check whether the two connection networks are normal and have short-circuit faults. At the same time, they will also check the open circuit situation together, and finally the short-circuit fault can be quickly determined.

[0117] As long as the short-circuit fault is not completely eliminated, there will definitely be reports of related failed connection networks. An effective short-circuit fault positioning and troubleshooting mechanism will be able to guide the troubleshooting of all short-circuit faults.

[0118] like Figure 2 As shown, it is a hardware block diagram of simulating the test of 7 connection networks to be tested according to an embodiment of the present invention, which includes a host computer, a boundary scan controller, a JTAG bus, and BS chip 1 and BS chip 2, and 7 connection networks to be tested between BS chip 1 and BS chip 2, which are connection network 1 to connection network 7. Data are sent from pins 1.1, 1.3, 1.4, 1.5, 1.6, and 1.7 of BS chip 1 and pin 2.2 of BS chip 2, and then received by pins 2.1, 2.3, 2.4, 2.5, and 2.6 of BS chip 2, pin 2.7 of BS chip 2 on the same connection network, pin 1.8 of BS chip 1, and pin 1.2 of BS chip 1. By sending and receiving data in respective connection networks, open circuit tests in connection networks and short circuit tests between connection networks are completed. By designing a test algorithm and processing the data of the execution algorithm, short circuit faults between different connection networks can be effectively located, which facilitates on-site short circuit fault troubleshooting.

[0119] like Figure 3 As shown, it is a data transmission block diagram of simulating 7 connected networks to be tested according to an embodiment of the present invention, combined with Figure 2 and Figure 3 As shown, the 2.2 pin of BS chip 2 on connection network 2 has only the ability to send data but not receive data, while the 1.2 pin of BS chip 1 has the ability to send and receive data. At this time, we can only consider sending data from the 2.2 pin of BS chip 2 and receiving data from the 1.2 pin of BS chip 1, and connection network 2 can complete the test. If the 1.2 pin of BS chip 1 is set as the drive pin, and the 2.2 pin of BS chip 2 cannot receive the data sent by the drive pin, connection network 2 cannot complete the test. Based on the above analysis, in order to obtain a better coverage test effect, it is necessary to determine the pin on the link that has only the ability to send but not receive as the only drive pin on the connection network.

[0120] The specific steps to determine the unique drive pin on each connection network on the link from TDI to TDO are as follows:

[0121] first step, Figure 3 BS chips 1 and 2, respectively, define the arrangement order of boundary register cells in their respective standard BSDL files. According to the arrangement order of boundary register cells from the JTAG data input signal TDI end to the data output signal TDO end, the register cells whose chip pins have only drive capabilities defined in the BSDL file are searched in turn, and the pins corresponding to such cells are determined as drive pins, thereby determining the 2.2 pin of BS chip 2 as a drive pin, corresponding to connection network 2.

[0122] In the second step, still according to the arrangement order of the boundary register units from the TDI end to the TDO end, search for the register cells with drive capabilities defined in the BSDL file (except the drive pins determined in the first step) in turn, and determine the pin corresponding to the first register cell with drive capabilities found on each connection network as the drive pin.

[0123] Combining the first and second steps, that is, determining the unique drive pins on all connected networks of the link, determine Figure 3The boundary register cells D1 to D7 correspond to pin 1.1 of BS chip 1, pin 2.2 of BS chip 2, and pins 1.3 to 1.7 of BS chip 1, respectively. After the drive pin is determined, the pins corresponding to the cells of other boundary registers on each connection network are receive pins, which are BS chip 2 pin 2.1, BS chip 1 pin 1.2, BS chip 2 pins 2.3 to 2.6, BS chip 2 pin 2.7 and BS chip 1 pin 1.8 on the same connection network. The cell corresponding to the drive pin is OUT or INOUT cell, which is filled with 0 or 1 as determined by the algorithm. The corresponding control cell should be filled with the non-safe value 0 (determined by the BS chip). In this way, the data sent by the drive pin will be updated to the corresponding connection network in the form of the corresponding level. The cell corresponding to the receive pin is IN or INOUT cell, and the corresponding control cell should be filled with the safe value 1 (determined by the BS chip), which will be able to receive the data sent by the drive pin on the same connection network.

[0124] You only need to determine how the drive pin sends data, that is, determine what data the drive algorithm needs to send for each transaction, and the data that all register cells from TDI to TDO need to send will also be determined accordingly.

[0125] Table 1 Algorithm for reporting faults in 8 connected networks under short circuit conditions

[0126]

[0127] Table 1 is an algorithm for reporting faults of 8 connection networks in a short circuit situation according to an embodiment of the present invention. A binary drive algorithm is used. Specifically, it is assumed that there are 8 connection networks with a measurable transceiver relationship, and the 8 connection networks correspond to 8 drive pins respectively.

[0128] is an integer. The first step is to send the first data. The drive pins corresponding to the 8 connection networks send 4 1s and 4 0s in sequence, that is, 11110000. When a short circuit fault occurs between the connection networks corresponding to the drive pins with 4 1s and the drive pins with 4 0s, the receive pins corresponding to the 4 1 test data receive incorrect data and report a fault. The second step is to send the second data. The data divided in the first step is further divided in two. Each time the first half of the data is kept unchanged, 4 1s are changed into 2 1s and 2 0s, and 4 0s are changed into 2 0s and 2 1s. That is, the drive pins corresponding to the 8 connection networks send 2 1s, 2 0s, 2 0s, and 2 1s in sequence, that is, 11000011. The third step is to send the third data. The data divided in the second step is further divided in two according to the above method. The drive pins corresponding to the 8 connection networks send 10010110 in sequence. At this time, the unit of the quantity of all binary data is 1 and cannot be divided any further.

[0129] is an integer, the number of steps for binary division of 8 drive data is 3, and the data unit is 1. The more specific implementation process will be further explained in detail in conjunction with the algorithm in Table 2.

[0130] Table 2 Algorithms for reporting faults in 7 connected networks under short circuit conditions

[0131]

[0132] Table 2 is an algorithm for reporting faults of 7 connected networks in the case of a short circuit according to an embodiment of the present invention.

[0133] Compared with the drive algorithm in Table 1, the drive algorithm in Table 2 deletes the test vector 8 to ensure that each piece of data has 7 bits and corresponds to 7 drive pins one by one.

[0134] Combination Figure 3 As shown in Table 2, it is assumed that there are 7 measurable connection networks with a transmit-receive relationship, and the 7 connection networks correspond to 7 drive pins respectively. At this time, is a decimal and cannot be In the case of integers, the 7 data are divided into two parts continuously. At this time, the following processing is required. First, determine The integer part of Indicates that the value is 2, because the number of drive pins is greater than Therefore, sending 4 data is not enough, and sending 8 data is redundant.

[0135] In this case, the algorithm is based on the number of drive pins. Perform binary division, the method of binary division is the same as described above When the drive pin number is an integer, the binary data corresponding to the integer 8 is obtained.

[0136] The actual number of drive pins is 4<m<8. You only need to delete the redundant test vectors in the algorithm and then perform the test.

[0137] Specifically, in the first step, the algorithm follows Perform binary search, assuming there is The drive pins corresponding to the connected networks are sent in sequence. 1 and 0, that is, 11110000, but the number of drive pins Therefore, the first step of sending data is to delete the following bit data, i.e. delete The last 0 part 0, and finally the drive pins corresponding to the 7 connected networks send 4 1s and 3 0s in sequence, that is, 1111000.

[0138] According to the order of the boundary register cells, they correspond to the 1.1, 1.3 to 1.7 pins of BS chip 1 and the 2.2 pin of BS chip 2. These pins are drive pins. The connection networks corresponding to these drive pins are connection network 1, connection networks 3 to 7, and connection network 2. The corresponding receive pins are 2.1, 2.3 to 2.6 pins of BS chip 2, 2.7 of BS chip 2 and 1.8 pins of BS chip 1 on the same connection network (both are receiving), and 1.2 pin of BS chip 1. The test vectors are named vector 1 to vector 7 in the order of the drive pins. The above is a detailed explanation of the correspondence between the algorithm and the hardware.

[0139] When a short circuit occurs between any two connection networks corresponding to the 4 drive pins of 1 and the 3 drive pins of 0, only the receive pins on the connection networks 1 and 3 to 5 corresponding to vectors 1 to 4 can receive incorrect data, resulting in a fail, while the receive pins on the connection networks 6, 7, and 2 corresponding to vectors 5 to 7 receive correct data. This is because there is a short circuit between the two connection networks, causing a conflict between the 0 and 1 levels, resulting in the receive pins on BS chips 1 and 2 that should have received 1 receiving 0. Since the data of the drive pins of each connection network will be the expected value received by the receive pins on each connection network, ultimately only the receive pins corresponding to vectors 1 to 4 will have a mismatch between the received value and the expectation. Therefore, when a short circuit fault occurs, the connection network corresponding to the vector part with drive data of 0 cannot report a fault.

[0140] The first step is to divide all the connection networks into two parts, and determine whether there is a fault caused by a short circuit between the two parts of the connection network. However, for each part of the connection network after the division, whether there is a fault caused by a short circuit between the two parts needs to be further divided into two parts, and the method of reporting the fault is the same as the first step.

[0141] In the second step, the data sent in the first half after the first step is divided into two parts: 1, because is an integer, this part is normally divided into two parts 1 and 0, that is, 1100. When a short circuit fault occurs, similarly, only the connection network corresponding to the vector part with drive data of 1 will report a fault, while the connection network corresponding to the vector part with drive data of 0 will not report a fault; the second half after the first step of binary division is slightly different from the first half. The number of drive pins in the second half is insufficient But still according to The binary algorithm is executed, but the last bit of data is not sent, that is, 1100001 is sent. Compared with the algorithm in Table 1, the last bit of the algorithm data is deleted after each step. The method of reporting faults is the same as the first step. Only the connection network corresponding to the vector part with drive data of 1 will report a fault, while the connection network corresponding to the vector part with drive data of 0 will not report a fault.

[0142] The third step is to further divide the data into two parts based on the second step. The number sent is 1001011. The method of reporting the fault is the same as the first step. The connection network corresponding to the vector part where the drive data is 0 still cannot report the fault. At this time, the unit of all binary data quantities is 1 and cannot be divided any further.

[0143] above Figure 3 The drive algorithm considered in Table 2 can only report a fault when a short circuit fault occurs. It can only report a part of the short circuit fault and cannot comprehensively and accurately report the short circuit fault between any two connected networks.

[0144] In order to effectively report short-circuit faults between different connected networks, the above binary drive algorithm needs to be optimized;

[0145] Table 3 Algorithm for reporting all faults in 8 connected networks under short circuit conditions

[0146]

[0147]

[0148] Table 3 is an algorithm for reporting all faults of 8 connected networks in the case of a short circuit according to an embodiment of the present invention. Combining Table 3 with Table 1, the algorithm optimizes the binary drive algorithm of Table 1, with the purpose of ensuring that all connected network faults can be reported in the case of a short circuit, and the combined algorithm can effectively locate the short circuit fault between connected networks. It is only necessary to flip the data sent in each step of Table 1 and send it again, and insert a piece of data opposite to the previous piece after the first, second, and third pieces of data in Table 1, respectively, to obtain Table 3.

[0149] The optimized drive algorithm makes up for the defect that the fault cannot be reported when the connection network corresponding to the vector part where the drive data is 0 fails. When a short circuit fault occurs, all connection network faults can be reported, and a comprehensive analysis can be performed to effectively locate the short circuit fault between different connection networks. The more specific implementation process will be further explained in detail in combination with the algorithm in Table 4.

[0150] Table 4 Algorithm for reporting all faults in 7 connected networks under short circuit conditions

[0151]

[0152] Table 4 is an algorithm for reporting all faults of 7 connection networks under short circuit conditions according to an embodiment of the present invention. Compared with the drive algorithm of Table 4, the drive algorithm of Table 3 also deletes test vector 8, and the number of test vectors remains consistent with the number of connection networks to be tested.

[0153] Combine Table 4 with Table 2, and flip the data sent in each step of Table 2 and send it again, that is, insert a piece of data opposite to the previous one after the 1st, 2nd, and 3rd data in Table 2.

[0154] This algorithm essentially optimizes the binary drive algorithm in Table 2 and combines Figure 3 As shown in Table 4,

[0155] Assumptions Figure 3 There are two connection networks, as shown by the dotted line between connection network 2 and connection network 4, a short circuit fault occurs between connection network 2 and connection network 4. Combined with the algorithm, all connection network faults are reported according to the following steps, and the short circuit fault between any connection networks is effectively located.

[0156] In the first step, the first data 1111000 is sent according to Table 4, which corresponds to 7 connection networks respectively. The first step is to determine whether there is a fault reported due to a short circuit between the 4 connection networks corresponding to 1111 and the three connection networks corresponding to 000. According to the corresponding relationship determined by the arrangement of the boundary scan register as described above, it can be known that the drive pin of the connection network 2 corresponds to vector 7, that is, the 7th bit data 0, and the drive pin of the connection network 4 corresponds to vector 4, that is, the 4th bit data 1, so the drive data corresponding to the connection network 2 is 0, and the drive data corresponding to the connection network 4 is 1. When a short circuit fault occurs between the connection network 2 and the connection network 4, the receive pin corresponding to the connection network 4 will receive 0. The data 0 received by the receive pin of the connection network 4 does not match the expected data of the drive of the connection network 1. The connection network 4 will report a fault, while the expectation of the connection network 2 itself is 0, and no fault will be reported.

[0157] In the second step, data 0000111, which is opposite to the second data, is sent according to Table 4, corresponding to 7 connection networks respectively. The second step is to determine whether there is a fault reported due to a short circuit between the 4 connection networks corresponding to 0000 and the three connection networks corresponding to 111. According to the corresponding relationship determined by the arrangement of the boundary scan register as described above, it can be known that the drive pin of the connection network 2 corresponds to vector 7, that is, the 7th bit data 1, and the drive pin of the connection network 4 corresponds to vector 4, that is, the 4th bit data 0, so the drive data corresponding to the connection network 2 is 1, and the drive data corresponding to the connection network 4 is 0. When a short circuit fault occurs between the connection network 2 and the connection network 4, the receive pin corresponding to the connection network 2 will receive 0. The data 0 received by the receive pin of the connection network 2 does not match the expected data of the drive of the connection network 1. The connection network 2 will report a fault, while the expectation of the connection network 4 itself is 0, and no fault will be reported.

[0158] Combining the first and second steps, it can be seen that the first step reports the connection network 4 fault, and the second step reports the connection network 2 fault. These two steps report faults through completely opposite data, and both faults occur between the connection network 2 and the connection network 4 corresponding to the test vector 7 and the test vector 4. After executing these two steps of the algorithm, a short-circuit fault prompt is given, such as: consider the short-circuit fault between the connection network 2 and the connection network 4; in this way, the on-site maintenance personnel will consider troubleshooting the short-circuit fault between the connection network 2 and the connection network 4, otherwise it will take a lot of time because the short-circuit fault is difficult to troubleshoot;

[0159] When a short circuit occurs at the four 1 drive pins and the three 0 drive pins, and several failures occur, all these failures are associated and a possible short circuit failure is prompted.

[0160] Assumptions Figure 3 For any two connection networks, as shown by the dotted line between connection network 5 and connection network 7, a short circuit fault also occurs between connection network 5 and connection network 7. Continuing to execute the third and fourth steps will be able to troubleshoot the short circuit fault.

[0161] The third step is to send the third data 1100001 according to Table 4, which corresponds to 7 connection networks respectively. The third step is to judge whether there is a fault reported due to a short circuit between the two connection networks corresponding to 11 and the two connection networks corresponding to 00, and between the two connection networks corresponding to 00 and the one connection network corresponding to 1. According to the corresponding relationship determined by the arrangement of the boundary scan register as described above, it can be known that the drive pin of the connection network 5 corresponds to vector 5, that is, the 5th bit data 0, and the drive pin of the connection network 7 corresponds to vector 7, that is, the 7th bit data 1, so the drive data corresponding to the connection network 5 is 0, and the drive data corresponding to the connection network 7 is 1. When a short circuit fault occurs between the connection network 5 and the connection network 7, the receive pin corresponding to the connection network 7 will receive 0. The data 0 received by the receive pin of the connection network 7 does not match the expected data of the drive of the connection network 1. The connection network 7 will report a fault, while the expectation of the connection network 5 itself is 0, and no fault will be reported.

[0162] In the fourth step, data 0011110 opposite to the third data is sent according to Table 4, corresponding to 7 connection networks respectively. The fourth step is to judge whether there is a fault reported due to a short circuit between the two connection networks corresponding to 00 and the two connection networks corresponding to 11, and between the two connection networks corresponding to 11 and the one connection network corresponding to 0. According to the corresponding relationship determined by the arrangement of the boundary scan register as described above, it can be known that the drive pin of the connection network 5 corresponds to vector 5, that is, the fifth bit data 1, and the drive pin of the connection network 7 corresponds to vector 7, that is, the seventh bit data 0, so the drive data corresponding to the connection network 5 is 1, and the drive data corresponding to the connection network 7 is 0. When a short circuit fault occurs between the connection network 5 and the connection network 7, the receive pin corresponding to the connection network 5 will receive 0. The data 0 received by the receive pin of the connection network 5 does not match the expected data that the drive of the connection network is 1. The connection network 5 will report a fault, while the expectation of the connection network 7 itself is 0, and no fault will be reported.

[0163] Combining the third and fourth steps, it can be seen that the third step reports a connection network 7 fault, and the fourth step reports a connection network 5 fault. These two steps also report faults through completely opposite data, and both faults occur between the connection network 5 and the connection network 7 corresponding to the test vector 5 and the test vector 7. After executing these two steps of the algorithm, a short-circuit fault prompt is given, such as: consider the short-circuit fault between the connection network 5 and the connection network 7; in this way, the on-site maintenance personnel will consider troubleshooting the short-circuit fault between the connection network 5 and the connection network 7;

[0164] By the same token, executing the algorithm 1001011 in the fifth step and the opposite algorithm data 0110100 in the sixth step will be able to report the short circuit fault between the further divided connecting networks, until the divided data is 1 and cannot be divided any further, which will effectively report the short circuit fault prompt between the connecting networks.

[0165] The present invention only considers the algorithm of 7 test vectors, which is completed after executing the sixth step of the algorithm. In practical applications, the number of binary divisions may be greater, and all are implemented according to the method of the present invention.

[0166] The optimized drive algorithm makes up for the defect that the fault cannot be reported when the connection network corresponding to the vector part where the drive data is 0 fails. When a short circuit fault occurs, all connection network faults can be reported, and comprehensive analysis can be performed to give prompts for short circuit faults between connection networks.

[0167] By using the above optimized binary short-circuit fault test algorithm, the short-circuit test is clearly classified, which is convenient for data extraction and comparative analysis, the correspondence between data and connection networks, and effective fault location prompts.

[0168] In the process of implementing the algorithm, in addition to the algorithm, it is necessary to send one more data of all 1s in the end to remove the status of the last algorithm execution. The boundary scan controller will be able to receive all the data of the algorithm execution and perform a comprehensive analysis to effectively locate the short-circuit fault.

[0169] This algorithm can not only support the location of short-circuit faults, but also has an advantage that the test vectors corresponding to each connection network have changes between 0 and 1, and can take into account open and short circuit tests at the same time. It is a relatively complete boundary scan test algorithm.

[0170] When any two connection networks are open, the data of open circuit fail may coincide with the test data of the associated short circuit, that is, there is a certain probability that the prompt of short circuit fault is caused by the possibility of open circuit fault. Despite this, the prompt of short circuit fault is still very important for the troubleshooting of open and short circuit faults. The analysis is as follows: when a short circuit fault prompt is given, if you first check whether there is an open circuit fault inside the two connection networks, and then check whether there is a short circuit fault between the two connection networks, or first check whether there is a short circuit fault between the two connection networks, and then check whether there is a short circuit fault between the two connection networks, you can quickly troubleshoot the fault problem; on the contrary, if the short circuit fault actually occurs, no prompt is given as to which two connection networks may have a short circuit. After checking the open circuit fault inside the connection network of the fail, you know that it may be caused by a short circuit fault, but you don’t know which two connection networks have a short circuit fault. At this time, it is difficult to troubleshoot the short circuit fault, even for engineers, which will waste a lot of time. Therefore, although the prompt of short circuit fault is not 100% accurate, it solves the problem that it is difficult to troubleshoot the actual short circuit fault, and effectively improves the troubleshooting efficiency.

[0171] The short-circuit fault between the connected networks needs to be checked together with the open-circuit fault of the connected network. The combination of the two can quickly troubleshoot all faults and effectively solve the problem of short-circuit faults being difficult to troubleshoot.

[0172] In the actual customer site of boundary scan testing, comprehensive judgment and location of short-circuit faults will waste more time. Short-circuit faults may only occur when fail occurs, and once the DUT test fixture is debugged and stabilized, the number of connection networks that fail in each DUT test will not be too many. We set a maximum of p=10 failed connection networks to determine whether there are short-circuit faults. p=10 is a fixed value, indicating that a maximum of p=10 failed connection networks are supported to further comprehensively locate short-circuit faults. Users can flexibly set values ​​from 1 to p=10 through the host computer, and flexibly set q value through the host computer, set to q=6, at this time 1≤q=6≤p=10, it will prompt whether there are related short-circuit faults between up to q=6 failed connection networks according to the order of boundary scan register cells.

[0173] The present invention derives a general boundary scan test algorithm for effectively locating short-circuit faults from the test content. In the implementation steps, a fault scenario in which short circuits occur in seven connection networks to be tested is simulated, and the key steps and analysis process of implementing the binary drive algorithm are described in detail. In fact, the number of connection networks to be tested on a boundary scan chain from TDI to TDO is far less than seven, and the same implementation method can be used.

[0174] To achieve the above object, the present invention also provides a system for boundary scan testing and effectively locating short circuit faults, wherein the system is applied to the method for boundary scan testing and effectively locating short circuit faults, such as Figure 4 As shown, the system includes:

[0175] A data acquisition unit, used for acquiring in real time first data corresponding to a short-circuit fault to be tested by boundary scan and located; wherein the first data is a connection relationship of a connection network to be tested;

[0176] A first data generating unit, configured to generate second data and third data corresponding to the connection network to be tested, respectively, based on the first data; wherein the second data is only output pin data in the connection network to be tested; and the third data is only receiving pin data in the connection network to be tested;

[0177] A data binary processing unit, configured to binary process the level data sent from the connection network to be tested according to the second data and the third data and in combination with the first data;

[0178] The second data generating unit is used to generate fourth data corresponding to the connection network to be tested according to the transmission status of the level data in the connection network to be tested; wherein the fourth data is short circuit fault data of the connection network to be tested.

[0179] Furthermore, the first data generating unit further includes:

[0180] A first generating module is used to generate and obtain fifth data corresponding to the connection network to be tested; wherein the fifth data is pin data of a link that has only a sending capability but no receiving capability;

[0181] And / or, the data binary processing unit further includes:

[0182] A first determination module, used for determining in real time whether the first data is an integer;

[0183] A first processing module, used for processing the first data in two equal parts, and sending high-level data in real time in one of the data, and sending low-level data in real time in the other data;

[0184] The second processing module is used to obtain all the data after the bisection process, and repeat the bisection process until the bisection data is 1;

[0185] And / or, the second data generating unit further includes:

[0186] The third processing module is used to generate and obtain a plurality of fourth data, and associate and process the plurality of fourth data, and generate seventh data corresponding to the plurality of fourth data; wherein the seventh data is prompt data of a possible short circuit fault.

[0187] Furthermore, the first data generating unit further includes:

[0188] A first search module is used to sequentially search for register units with only output capability according to the arrangement order of boundary register units from the data input signal end to the data output signal end;

[0189] A data transmission module, configured to transmit corresponding sixth data in real time at the data output signal terminal based on the register unit having only output capability; wherein the sixth data is level data corresponding to 0 or 1;

[0190] And / or, the data binary processing unit further includes:

[0191] A second determination module is used to determine in real time whether the first data is an integer, and if so, execute the next step; otherwise, add one to the first data and then execute the next step;

[0192] a fourth processing module, configured to divide the first data into two equal parts, and send high-level data in real time in one of the data, and send low-level data in real time in the other data;

[0193] The fifth processing module is used to obtain all the data after the binary division process, and repeat the above two steps until the binary division data is 1.

[0194] In the system solution embodiment of the present invention, the specific details of the method steps involved in the boundary scan test and effective positioning of short circuit faults have been described above, that is, the functional modules in the system are used to implement the steps or sub-steps in the above method embodiment, which will not be repeated here.

[0195] To achieve the above object, the present invention also provides a platform for boundary scan testing and effectively locating short circuit faults, such as Figure 5 As shown, it includes a processor, a memory, and a platform control program for boundary scan testing and effectively locating short-circuit faults; wherein, the platform control program for boundary scan testing and effectively locating short-circuit faults is executed by the processor, the platform control program for boundary scan testing and effectively locating short-circuit faults is stored in the memory, and the platform control program for boundary scan testing and effectively locating short-circuit faults implements the method steps for boundary scan testing and effectively locating short-circuit faults. For example:

[0196] S1. Acquire in real time first data corresponding to a short circuit fault to be tested by boundary scan and located; wherein the first data is a connection relationship of a connection network to be tested;

[0197] S2. Based on the first data, respectively generate second data and third data corresponding to the connection network to be tested; wherein the second data is only output pin data in the connection network to be tested; and the third data is only receiving pin data in the connection network to be tested;

[0198] S3, according to the second data and the third data, and in combination with the first data, binary processing of the level data sent in the tested connection network;

[0199] S4. Generate fourth data corresponding to the connection network to be tested according to the transmission state of the level data in the connection network to be tested; wherein the fourth data is short-circuit fault data of the connection network to be tested.

[0200] The specific details of the steps have been explained above and will not be repeated here.

[0201] In the embodiment of the present invention, the platform built-in processor for boundary scan testing and effectively locating short-circuit faults can be composed of integrated circuits, such as a single packaged integrated circuit, or a plurality of integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips. The processor uses various interfaces and lines to connect various components, and executes or executes programs or units stored in the memory, and calls data stored in the memory to perform various functions and process data for boundary scan testing and effectively locating short-circuit faults;

[0202] The memory is used to store program codes and various data. It is installed in a platform used for boundary scan testing and effective positioning of short-circuit faults, and realizes high-speed and automatic access to programs or data during operation.

[0203] The memory includes read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electronically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0204] The present invention uses a method to obtain in real time first data corresponding to a short-circuit fault to be tested by boundary scanning and to be located; wherein the first data is a connection relationship of a connection network to be tested; based on the first data, second data and third data corresponding to the connection network to be tested are respectively generated; wherein the second data is only output pin data in the connection network to be tested; and the third data is only receiving pin data in the connection network to be tested; according to the second data and the third data, and in combination with the first data, the level data sent in the connection network to be tested is binary processed; according to the transmission state of the level data in the connection network to be tested, fourth data corresponding to the connection network to be tested is generated; wherein the fourth data is short-circuit fault data of the connection network to be tested; and a system and platform corresponding to the method can clearly identify between which connection networks short-circuit faults are to be checked, thereby improving the efficiency of short-circuit fault troubleshooting.

[0205] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for effectively locating short circuit faults for boundary scan testing, characterized in that: The method comprises the following steps: Acquire in real time first data corresponding to a short circuit fault to be tested by boundary scan and located; wherein the first data is a connection relationship of a connection network to be tested; Based on the first data, second data and third data corresponding to the connection network to be tested are respectively generated; wherein the second data is only output pin data in the connection network to be tested; and the third data is only receiving pin data in the connection network to be tested; According to the second data and the third data, and in combination with the first data, binary processing is performed on the level data sent in the connection network to be tested; According to the transmission state of the level data in the connection network to be tested, fourth data corresponding to the connection network to be tested is generated; wherein the fourth data is short circuit fault data of the connection network to be tested.

2. A method for boundary scan testing and effectively locating short circuit faults according to claim 1, characterized in that: The generating, based on the first data, second data and third data corresponding to the connection network to be tested respectively, further includes: Generate and obtain fifth data corresponding to the connection network to be tested; wherein the fifth data is pin data of a link that has only a sending capability but no receiving capability.

3. A method for boundary scan testing and effectively locating short circuit faults according to claim 1 or 2, characterized in that: The generating, based on the first data, second data and third data corresponding to the connection network to be tested respectively, further includes: According to the arrangement order of the boundary register units from the data input signal end to the data output signal end, sequentially searching for the register units with only output capability; Based on the register unit with only output capability, corresponding sixth data is transmitted in real time at the data output signal terminal; wherein the sixth data is level form data corresponding to 0 or 1.

4. A method for boundary scan testing and effectively locating short circuit faults according to claim 1, characterized in that: The binary processing of the level data sent from the tested connection network according to the second data and the third data and in combination with the first data also includes: Determine in real time whether the first data is an integer, if so, execute the next step; otherwise, add 1 to the first data and then execute the next step; Processing the first data in two equal parts, sending high-level data in real time in one of the data, and sending low-level data in real time in the other data; Get all the data after the binary division, and repeat the above two steps until the binary data is 1.

5. A method for boundary scan testing and effectively locating short circuit faults according to claim 1 or 4, characterized in that: The binary processing of the level data sent from the tested connection network according to the second data and the third data and in combination with the first data also includes: Determine in real time whether the first data is an integer, if so, execute the next step; otherwise, add 1 to the first data and then execute the next step; Processing the first data in two equal parts, sending low-level data in real time in one of the data, and sending high-level data in real time in the other data; Get all the data after the binary division, and repeat the above two steps until the binary data is 1.

6. A method for boundary scan testing and effectively locating short circuit faults according to claim 1, characterized in that: The step of generating fourth data corresponding to the connection network to be tested according to the transmission state of the level data in the connection network to be tested further includes: Generate and obtain a plurality of fourth data, associate and process the plurality of fourth data, and generate seventh data corresponding to the plurality of fourth data; wherein the seventh data is prompt data indicating a possible short circuit fault.

7. A system for boundary scan testing and effectively locating short circuit faults, characterized in that: The system is applied to the method for boundary scan testing and effectively locating short circuit faults according to any one of claims 1 to 6, and the system comprises: A data acquisition unit, used for acquiring in real time first data corresponding to a short-circuit fault to be tested by boundary scan and located; wherein the first data is a connection relationship of a connection network to be tested; A first data generating unit, configured to generate second data and third data corresponding to the connection network to be tested, respectively, based on the first data; wherein the second data is only output pin data in the connection network to be tested; and the third data is only receiving pin data in the connection network to be tested; A data binary processing unit, configured to binary process the level data sent from the connection network to be tested according to the second data and the third data and in combination with the first data; The second data generating unit is used to generate fourth data corresponding to the connection network to be tested according to the transmission status of the level data in the connection network to be tested; wherein the fourth data is short circuit fault data of the connection network to be tested.

8. A system for boundary scan testing and effectively locating short circuit faults according to claim 7, characterized in that: The first data generating unit further includes: A first generating module is used to generate and obtain fifth data corresponding to the connection network to be tested; wherein the fifth data is pin data of a link that has only a sending capability but no receiving capability; And / or, the data binary processing unit further includes: A first determination module, used for determining in real time whether the first data is an integer; A first processing module, used for processing the first data in two equal parts, and sending high-level data in real time in one of the data, and sending low-level data in real time in the other data; The second processing module is used to obtain all the data after the bisection process, and repeat the bisection process until the bisection data is 1; And / or, the second data generating unit further includes: The third processing module is used to generate and obtain a plurality of fourth data, and associate and process the plurality of fourth data, and generate seventh data corresponding to the plurality of fourth data; wherein the seventh data is prompt data of a possible short circuit fault.

9. A system for boundary scan testing and effectively locating short circuit faults according to claim 7 or 8, characterized in that: The first data generating unit further includes: A first search module is used to sequentially search for register units with only output capability according to the arrangement order of boundary register units from the data input signal end to the data output signal end; A data transmission module, configured to transmit corresponding sixth data in real time at the data output signal terminal based on the register unit having only output capability; wherein the sixth data is level data corresponding to 0 or 1; And / or, the data binary processing unit further includes: A second determination module is used to determine in real time whether the first data is an integer, and if so, execute the next step; otherwise, add one to the first data and then execute the next step; a fourth processing module, configured to divide the first data into two equal parts, and send high-level data in real time in one of the data, and send low-level data in real time in the other data; The fifth processing module is used to obtain all the data after the binary division process, and repeat the above two steps until the binary division data is 1.

10. A platform for boundary scan testing and effectively locating short circuit faults, characterized in that: The invention comprises a processor, a memory and a platform control program for boundary scan testing and effectively locating short-circuit faults; wherein the platform control program for boundary scan testing and effectively locating short-circuit faults is executed on the processor, the platform control program for boundary scan testing and effectively locating short-circuit faults is stored in the memory, and the platform control program for boundary scan testing and effectively locating short-circuit faults implements the method for boundary scan testing and effectively locating short-circuit faults as described in any one of claims 1 to 6.

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