Method of forming semiconductor die

Abstract

A method of forming a semiconductor die includes forming a photoresist layer over a wafer; aligning a first photomask with a first region of the wafer; performing a first exposure process on a first part of the photoresist layer in the first region of the wafer; aligning a second photomask with a second region of the wafer, the alignment of the first photomask and the alignment of the second photomask being performed using an alignment mark in a bonding region of the wafer, the bonding region being an overlapping region of the first region and the second region; performing a second exposure process on a second part of the photoresist layer in the second region of the wafer; and performing a developing process to remove the first portion and the second portion of the photoresist layer.

Description

Technical Field

[0001] The present disclosure relates to a method of forming a semiconductor die. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advances. During the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a fabrication process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Summary of the invention

[0003] In some embodiments disclosed herein, a method for forming a semiconductor die includes: forming a photoresist layer above a wafer; aligning a first mask with a first area of ​​the wafer; performing a first exposure process on a first portion of the photoresist layer within the first area of ​​the wafer; aligning a second mask with a second area of ​​the wafer, wherein aligning the first mask and aligning the second mask are performed using alignment marks within a bonding area of ​​the wafer, the bonding area being an overlapping area of ​​the first area and the second area; performing a second exposure process on a second portion of the photoresist layer within the second area of ​​the wafer; and performing a development process to remove the first and second portions of the photoresist layer.

[0004] In some embodiments of the present disclosure, a method for forming a semiconductor die includes: forming a photoresist layer above a wafer; performing a first exposure process on a first portion and a second portion of the photoresist layer in a first region of the wafer via a first photomask, wherein the first photomask has an alignment mark pattern corresponding to the second portion of the photoresist layer; performing a second exposure process on a third portion of the photoresist layer in a second region of the wafer via a second photomask, wherein the second portion of the photoresist layer is in a bonding region of the wafer, the bonding region being an overlapping region of the first region and the second region; and performing a development process to remove the first portion, the second portion, and the third portion of the photoresist layer to form a patterned photoresist layer.

[0005] In some embodiments of the present disclosure, a method for forming a semiconductor die includes: forming a semiconductor device in a first device area and a second device area of ​​a substrate, and no semiconductor device exists in a non-device area of ​​the substrate, wherein the non-device area separates the first device area from the second device area; forming an alignment mark above the non-device area of ​​the substrate, wherein a portion of the alignment mark extends into the first device area of ​​the substrate; and using the alignment mark to form features above the first device area and the second device area. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram of a lithography system according to some embodiments of the present disclosure;

[0008] Figure 2 is a top view of a wafer according to some embodiments;

[0009] Figures 3A to 15 illustrates a semiconductor die at various stages of fabrication according to some embodiments of the present disclosure;

[0010] Fig.16A is a perspective view of a wafer according to some embodiments of the present disclosure;

[0011] Fig. 16B is a top view of a wafer according to some embodiments of the present disclosure;

[0012] Fig. 16C is a cross-sectional view of a wafer according to some embodiments of the present disclosure;

[0013] Fig.17A is a perspective view of a wafer according to some embodiments of the present disclosure;

[0014] Fig. 17B is a top view of a wafer according to some embodiments of the present disclosure;

[0015] Fig. 17C is a cross-sectional view of a wafer according to some embodiments of the present disclosure;

[0016] Fig.18 is a cross-sectional view of a wafer according to some embodiments of the present disclosure;

[0017] Fig.19 is a cross-sectional view of a wafer according to some embodiments of the present disclosure;

[0018] Fig. 20A and Fig. 20B is a top profile of an alignment mark according to some embodiments of the present disclosure;

[0019] Fig.21A and Fig.21B is a top profile of an alignment mark according to some embodiments of the present disclosure;

[0020] Fig.22A and Fig. 22Bis a top profile of an alignment mark according to some embodiments of the present disclosure;

[0021] FIG. 23A to FIG. 24C A semiconductor die is illustrated at various stages of fabrication according to some embodiments of the present disclosure.

[0022]

Explanation of symbols

[0023] 10: Die area / device area

[0024] 10A: First Area

[0025] 10B: Second Area

[0026] 10C: Joint area

[0027] 11: Semiconductor grains

[0028] 20: Back-end process structure / BEOL structure

[0029] 22, 24: Cutting Road

[0030] 102:Substrate

[0031] 103: Fins

[0032] 104: Installation

[0033] 104 G :Gate Structure

[0034] 104 GD :Gate dielectric layer

[0035] 104 GM :Gate Metal Layer

[0036] 104 SD : Source / Drain Region

[0037] 104 SP :Spacer

[0038] 105: Shallow trench isolation area / STI area

[0039] 110: Interlayer dielectric layer / ILD layer

[0040] 112: Contact

[0041] 200, 220, 240, 250: Intermetallic dielectric layer / IMD layer

[0042] 211, 214, 231, 234: Metal features

[0043] 212, 213, 215, 232, 233, 235, 500, 600, AM1, AM2, AM3, AM4, AM5, AM6: Alignment mark

[0044] 300:EUV lithography system

[0045] 310:Illuminator

[0046] 320: Mask carrier

[0047] 330: Mask

[0048] 340: Projection Optics Box / POB

[0049] 350: Substrate carrier

[0050] 400: Radiation source

[0051] 1001, 1002, 1011, 1021, 1022, 1023, 1024: Features

[0052] α: first angle

[0053] β: Second angle

[0054] CC:Line

[0055] E1, E2, E3, E4, E5, E6: Exposure process

[0056] E11, E12, E13, E21, E22, E31, E32, E33, E41, E42: Exposure area

[0057] EL:EUV light

[0058] G1, G3, G5: First grating

[0059] G2, G4, G6: Second grating

[0060] G7: The third grating

[0061] G8: The fourth grating

[0062] L1, L2, L3: Length

[0063] MA1, MA2, MA3, MA4, MA5, MA6: Photomask

[0064] O1, O2, O3, O4, O5, O6, O7: Open

[0065] P11, P21, P31, P41: Layout pattern

[0066] P12, P13, P22, P32, P33, P42: Alignment mark pattern

[0067] PH1, PH2: Fixed spacing

[0068] PH3, PH4, PH5, PH6, PH7, PH8: Spacing

[0069] PR1, PR2: Photoresist layer

[0070] S1: Feature Group

[0071] W: Wafer / Substrate

[0072] W1, W2, W3: Width DETAILED DESCRIPTION

[0073] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. The specific examples of the components and configurations described below are for simplifying the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0074] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0075] The advanced lithography processes, methods, and materials described in this disclosure can be used in many applications, including fin-type field effect transistors (FinFETs). For example, fins can be patterned to produce relatively tight spacing between features, and the above disclosure is particularly suitable for this situation. In addition, spacers used to form fins of FinFETs can be processed according to the above disclosure.

[0076] Figure 1Schematic diagram of a lithography system according to some embodiments of the present disclosure. In some embodiments, EUV lithography system 300 is designed to use EUV light (or EUV radiation) to expose a resist layer. The resist layer is a material that is sensitive to EUV light. EUV lithography system 300 uses a radiation source 400 to generate EUV light EL. Therefore, radiation source 400 is also referred to as EUV radiation source 400. EUV radiation source 400 can generate EUV radiation using a laser-produced plasma (LPP) mechanism, which will be further described later.

[0077] EUV lithography system 300 also employs illuminator 310. In some embodiments, illuminator 310 includes various reflective optics such as a single mirror or a mirror system having multiple mirrors to direct light EL from radiation source 400 onto mask 330 fixed on mask stage 320.

[0078] In some embodiments, the mask carrier 320 includes an electrostatic chuck (electronic chuck) for fixing the mask 330. In this context, the terms mask, reticle, and shrink reticle are used interchangeably. In the disclosed embodiment, the mask 330 is a reflective mask.

[0079] The EUV lithography system 300 also includes a projection optics module (or projection optics box (POB)) 340 for imaging the pattern of the mask 330 onto a semiconductor substrate W (e.g., a wafer) fixed on a substrate stage (e.g., a wafer stage) 350 of the EUV lithography system 300. In the disclosed embodiment, the POB 340 includes reflective optics. EUV light EL guided from the mask 330 and carrying an image of the pattern defined on the mask 330 is collected by the POB 340. The illuminator 310 and the POB 340 may be collectively referred to as an optical module of the EUV lithography system 300. In the disclosed embodiment, the semiconductor substrate W is a semiconductor wafer, such as a silicon wafer or other type of wafer to be patterned. In the disclosed embodiment, the semiconductor substrate W is coated with a resist layer sensitive to the EUV light EL. Various elements including the above elements are integrated together and are operable to perform an EUV lithography exposure process.

[0080] Figure 21 is a top view of a wafer according to some embodiments. Wafer W is shown. In some embodiments, wafer W may be a semiconductor wafer. Wafer W includes a plurality of die regions 10 (or chip regions). Wafer W includes a plurality of scribe lines 22 and 24, wherein each scribe line 22 extends along the X direction, and each scribe line 24 extends along the Y direction. Each of the die regions 10 of wafer W is surrounded by a pair of scribe lines 22 and a pair of scribe lines 24. After completing the semiconductor manufacturing process performed on wafer W, each of the die regions 10 can be singulated into individual die by slicing the wafer through scribe lines 22 and 24.

[0081] In the depicted embodiment, the lithography system (e.g. Figure 1 In the EUV lithography system 300, a mask (eg Figure 1 The wafer W is exposed to EUV radiation (light) using a mask 330 (such as a mask 330). Multiple exposures of the mask may be used to transfer the image of the mask to the wafer W multiple times. For example, the mask is used in multiple exposure processes to pattern the wafer W so that the pattern of the mask image area is transferred to each field (such as the die area 10) of the wafer W. Each field (such as the die area 10) may correspond to at least one semiconductor device (or at least one integrated circuit device). For example, an exposure tool (such as a stepper or a scanner) processes one field (such as exposing the die area 10 of the wafer W to the mask), then processes the next field (such as exposing another die area 10 of the wafer W to the mask), and so on. In the disclosed example, the wafer W may include a resist layer disposed above the substrate, wherein the pattern of the mask image area is transferred to the resist layer.

[0082] like Figure 2 As shown in , each of the die regions 10 may include a first region 10A and a second region 10B adjacent to the first region 10A. The first region 10A and the second region 10B may undergo a first exposure process and a second exposure process, respectively. For example, in the first exposure process, a first pattern of a first mask may be aligned with the first region 10A of the die region 10. Thereafter, the first exposure process is performed by exposing the first region 10A to the first pattern of the mask so as to transfer the first pattern of the first mask to a layer (e.g., photoresist) on the first region 10A of the die region 10. After the first exposure process is completed, a second pattern of a second mask may be aligned with the second region 10B of the die region 10. Then, a second exposure process is performed by exposing the second region 10B to the second pattern of the second mask so as to transfer the second pattern of the mask to a layer (e.g., photoresist) on the second region 10B of the die region 10. In some embodiments, the first pattern of the first mask may be different from the second pattern of the second mask. The first pattern and the second pattern may form a desired pattern (e.g., layout) together above the die region 10 of the wafer W.

[0083] Figures 3A to 15 A semiconductor die at various stages of fabrication according to some embodiments of the present disclosure is illustrated. Figures 3A to 15 , but it should be understood that Figures 3A to 15 The structure shown in is not limited to this method, but can be independent of this method. Figures 3A to 15 Described as a series of actions, it should be understood that these actions are not restrictive, because the order of actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions illustrated and / or described can be omitted in whole or in part.

[0084] References Figure 3A , Figure 3B and Figure 3C ,in Figure 3A A perspective view of the wafer. Figure 3B is a top view of the wafer, and Figure 3C is a cross-sectional view of a wafer. In more detail, Figure 3A and Figure 3B The view of FIG. 1 illustrates a single die region 10 of a wafer W, and Figure 3C For along Figure 3B It should be noted that Figure 3A , Figure 3B and Figure 3C Some parts of Figure 2 Parts described herein are identical and such parts are labeled identically.

[0085] like Figure 3A and Figure 3B As shown in , a die region 10 of a wafer W is shown. The die region 10 is surrounded by saw streets 22 and 24. The die region 10 includes a first area 10A and a second area 10B. The first area 10A and the second area 10B may also be referred to as a first mask area and a second mask area, respectively. The first area 10A and the second area 10B have an overlapping area, which may be referred to as a stitching zone 10C. This is because features (such as metal features) extending from the first area 10A and the second area 10B may be joined together in the stitching area 10C. In some embodiments, the stitching area 10C has a strip-shaped top view, which may include a uniform width. In some embodiments, the first area 10A and the second area 10B may have substantially the same size; but in other embodiments, their sizes or shapes may be different from each other. In some embodiments, the stitching area 10C is a strip-shaped area that extends continuously from one side of the die region 10 to the other side of the die region 10.

[0086] Next generation EUV tools pursue higher reduction ratios, especially when using high numerical aperture (NA) lens systems. However, higher reduction ratios may require the use of larger mask sizes or result in a reduction in the size of the printing field. On the one hand, making larger masks to compensate is undesirable due to manufacturing complexity, but on the other hand, smaller fields may result in the need to "join" or accept substantially reduced yields, thereby exacerbating the problems that already exist in EUV lithography. Therefore, large wafers such as wafers for graphics processing units (GPUs) may need to be joined together by two or more component patterns to form a complete composite pattern. Two or more component patterns typically require two or more masks, and changing masks during lithography can undesirably reduce EUVL yields.

[0087] The device region 10 of the wafer W may include active devices such as diodes, metal-oxide-semiconductor field effect transistors (MOSFET), complementary MOS (CMOS) transistors, bipolar junction transistors (BJT), laterally diffused MOS (LDMOS) transistors, high-power MOS transistors, fin-like field effect transistors (FinFET), other integrated circuit elements, or combinations thereof. In other embodiments, the device region 10 may include passive devices such as resistors, capacitors, inductors, or combinations thereof. In some embodiments, the dicing streets 22 and 24 and the bonding region 10C may not contain the above-mentioned active devices and passive devices.

[0088] exist Figure 3C, the wafer W includes a substrate 102. The substrate 102 may include, for example, doped or undoped bulk silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. In general, an SOI substrate includes a layer of a semiconductor material such as silicon formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is disposed on a substrate such as a silicon or glass substrate. Alternatively, the substrate 102 may include another elemental semiconductor such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof. Other substrates may also be used, such as multilayer or gradient substrates.

[0089] In some embodiments, one or more active and / or passive devices 104 are formed above the device region 10 of the substrate 102 of the wafer W (in Figure 3C In more detail, the device 104 may be formed in the first region 10A and the second region 10B of the die region 10. The one or more active and / or passive devices 104 may include various N-type metal-oxide semiconductors.

[0090] semiconductor, NMOS) and / or P-type metal-oxide semiconductor (P-type metal-oxide

[0091] The present invention relates to a semiconductor (PMOS) device such as a transistor, a capacitor, a resistor, a diode, a photodiode, a fuse and the like. It should be understood by those skilled in the art that the above examples are provided for illustrative purposes only and are not intended to limit the present disclosure in any way. For a given application, other circuit systems may also be formed as appropriate. In some embodiments, the cutting lanes 22 and 24 and the bonding area 10C may not contain one or more active and / or passive devices 104. Therefore, the first area 10A and the second area 10B may also be referred to as device areas, and the bonding area 10C may be referred to as a non-device area.

[0092] In the depicted embodiment, the device 104 is a fin field-effect transistor (FinFET), which is a three-dimensional MOSFET structure formed in a fin-shaped strip called a fin 103 on a semiconductor protrusion. Figure 3C The cross section shown in FIG. 1 is a cross section taken along the longitudinal axis of the fin at the junction of the source / drain region 104. SDThe fins 103 can be formed by patterning the substrate 102 using photolithography and etching techniques. For example, a spacer image transfer (SIT) patterning technique can be used. In this method, a sacrificial layer is formed over the substrate using a suitable photolithography and etching process and patterned to form a mandrel. A self-aligned process is used to form spacers next to the mandrel. The sacrificial layer is then removed by an appropriate selective etching process. Each remaining spacer can then be used as a hard mask to pattern individual fins 103 by etching trenches in the substrate 102 using, for example, reactive ion etching (RIE). In some other embodiments, the device 104 can also be a planar transistor or a gate-all-around (GAA) transistor.

[0093] Shallow trench isolation (STI) regions 105 formed on opposite sidewalls of the fin 103 are illustrated in FIG. Figure 3C The STI region 105 may be formed by depositing one or more dielectric materials, such as silicon oxide, to completely fill the trench around the fin and then recessing the top surface of the dielectric material. The dielectric material of the STI region 105 may be deposited using high density plasma chemical vapor deposition (HDP-CVD), low-pressure CVD (LPCVD), sub-atmospheric CVD (SACVD), flowable CVD (FCVD), spin coating, and / or the like, or a combination thereof. After deposition, an annealing process or a curing process may be performed. In some cases, the STI region 105 may include a liner, such as, for example, a thermal oxide liner grown by oxidizing a silicon surface. The recessing process may use, for example, a planarization process (e.g., chemical mechanical polishing (CMP)) followed by a selective etching process (e.g., wet etching or dry etching or a combination thereof), which may recess the top surface of the dielectric material in the STI region 105 so that the upper portion of the fin 103 protrudes from the surrounding insulating STI region 105. In some cases, the patterned hard mask used to form the fin 103 may also be removed by the planarization process.

[0094] In some embodiments, Figure 3C The gate structure 104 of the device 104 illustrated in GIt is a high-k metal gate (HKMG) gate structure, which can be formed using a gate-last process flow. In the gate-last process flow, a sacrificial dummy gate structure (not shown) is formed after forming the STI region 105. The dummy gate structure may include a dummy gate dielectric, a dummy gate electrode, and a hard mask. First, a dummy gate dielectric material (such as silicon oxide, silicon nitride, or the like) may be deposited. Next, a dummy gate material (such as amorphous silicon, polycrystalline silicon, or the like) may be deposited over the dummy gate dielectric and then planarized (such as by CMP). A hard mask layer (such as silicon nitride, silicon carbide, or the like) may be formed over the dummy gate material. A dummy gate structure is then formed by patterning the hard mask and transferring the pattern to the dummy gate dielectric and the dummy gate material using suitable photolithography and etching techniques. The dummy gate structure may extend along multiple sides of the protruding fins and extend between the fins above the surface of the STI region 105. As described in more detail below, the dummy gate structure may be Figure 3C The metal gate structure 104 described in G Alternatively, the material used to form the dummy gate structure and the hard mask may be deposited using any suitable method such as CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), or the like, or by thermal oxidation of a semiconductor surface, or a combination thereof.

[0095] exist Figure 3C , the source / drain region 104 of the device 104 SD and spacer 104 SP The spacer 104 may be formed, for example, to be self-aligned with the dummy gate structure. The spacer 104 may be formed by deposition of a spacer dielectric layer and anisotropic etching after the dummy gate patterning is completed. SP The spacer dielectric layer may include one or more dielectrics such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof. The anisotropic etching process removes the spacer dielectric layer from above the top of the dummy gate structure, thereby leaving spacers 104 extending laterally along the sidewalls of the dummy gate structure to a portion of the surface of the fin 103. SP .

[0096] Source / drain region 104 SD The source / drain region 104 is a semiconductor region that is in direct contact with the semiconductor fin 103. SD It may include a heavily doped region and a relatively lightly doped drain extension or LDD region.SP To separate the heavily doped region from the dummy gate structure, the LDD region can be formed by forming the spacer 104 SP is formed before, and thus the spacer 104 SP The LDD region extends below the fin 103 and, in some embodiments, further extends into a portion of the semiconductor fin 103 below the dummy gate structure. For example, the LDD region may be formed by implanting dopants (eg, As, P, B, In, or the like) using an ion implantation process.

[0097] Source / drain region 104 SD For example, after forming the LDD region, the spacer 104 may be formed. SP , and then, heavily doped source and drain regions may be formed adjacent to the spacers 104 by first etching the fins to form recesses, and then depositing a crystalline semiconductor material in the recesses by a selective epitaxial growth (SEG) process. SP The selective epitaxial growth process can fill the recesses and can further extend beyond the original surface of the fin 103 to form an elevated source / drain epitaxial structure. The crystalline semiconductor material can be an element (such as Si, or Ge, or the like) or an alloy (such as Si 1-x C x , or Si 1-x Ge x , or the like). The SEG process may use any suitable epitaxial growth method, such as, for example, vapor / solid / liquid phase epitaxy (VPE, SPE, LPE), or metal-organic CVD (MOCVD), or molecular beam epitaxy (MBE), or the like. A high dose (e.g., from about 10 14 cm -2 Up to 10 16 cm -2 ) can be introduced into the heavily doped source / drain regions 104 in situ during SEG, or by an ion implantation process performed after SEG, or by a combination thereof. SD middle.

[0098] Once the source / drain regions 104 are formed SD , a first interlayer dielectric (ILD) layer, such as a lower portion of the ILD layer 110, is deposited on the source / drain region 104 SDIn some embodiments, a contact etch stop layer (CESL) (not shown) of a suitable dielectric (e.g., silicon nitride, silicon carbide, or the like, or a combination thereof) may be deposited prior to depositing the ILD material. A planarization process (e.g., CMP) may be performed to remove excess ILD material and any remaining hard mask material from above the dummy gate, thereby forming a top surface, wherein the top surface of the dummy gate material is exposed and may be substantially coplanar with the top surface of the first ILD layer. The dummy gate structure may then be formed by first removing the dummy gate structure using one or more etching techniques. Figure 3C The metal gate structure 104 described in G , so that in each spacer 104 SP Next, a replacement gate dielectric layer 104 including one or more dielectrics is deposited. GD , followed by the deposition of a replacement gate metal layer 104 comprising one or more metals GM , to completely fill the groove. The gate dielectric layer 104 may be removed from above the top surface of the first ILD using, for example, a CMP process. GD and gate metal layer 104 GM The redundant part of Figure 3C As described in the example of FIG. 1 , the resulting structure may include a plurality of spacers 104 embedded in the respective spacers 104. SP The gate dielectric layer 104 between GD and gate metal layer 104 GM the remainder of .

[0099] Gate dielectric layer 104 GD The gate metal layer 104 may include, for example, a high-k dielectric material such as metal oxides and / or silicates (e.g., oxides and / or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, and other metals), silicon nitride, silicon oxide, and the like, or a combination thereof, or a multilayer thereof. In some embodiments, the gate metal layer 104 may include, for example, a high-k dielectric material such as metal oxides and / or silicates (e.g., oxides and / or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, and other metals), silicon nitride, silicon oxide, and the like, or a combination thereof, or a multilayer thereof. GM It may be a multi-layer metal gate stack, including a gate dielectric layer 104 formed in sequence GDThe barrier layer, work function layer and gate fill layer on top. Example materials for the barrier layer include TiN, TaN, Ti, Ta or the like, or multilayer combinations thereof. For p-type FETs, the work function layer may include TiN, TaN, Ru, Mo, Al, and for n-type FETs, the work function layer may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr. Other suitable work function materials or combinations or multilayers thereof may be used. The gate fill layer filling the remainder of the recess may include a metal such as Cu, Al, W, Co, Ru or the like, or combinations or multilayers thereof. The material used to form the gate structure may be deposited by any suitable method, such as CVD, PECVD, PVD, ALD, PEALD, electrochemical plating (ECP), electroless plating, and / or the like.

[0100] In forming the metal gate structure 104 G Afterwards, a second ILD layer is deposited on the first ILD layer, and these ILD layers are collectively referred to as ILD layer 110. Figure 3C In some embodiments, the insulating material used to form the first and second ILD layers may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), low dielectric constant (low-k) dielectrics such as fluorosilicate glass (FSG), silicon oxycarbide (SiOCH), carbon-doped oxide (CDO), flowable oxides or porous oxides (e.g., xerogel / aerogel), or the like, or combinations thereof. The dielectric material used to form the first and second ILD layers may be deposited using any suitable method such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, and / or the like, or combinations thereof.

[0101] like Figure 3C As shown in FIG. 1 , the contact 112 is formed to contact the metal gate structure 104 of the device 104. G and source / drain region 104 SDContacts 112 may be formed using photolithography, etching, and deposition techniques.

[0102] For example, a patterned mask may be formed over the ILD layer 110 and used to etch an opening extending through the ILD layer 110 to expose the gate structure 104. G and source / drain region 104 SD Afterwards, a conductive liner may be formed in the opening of the ILD layer 110. Subsequently, the opening is filled with a conductive fill material. The liner includes a barrier metal for reducing the diffusion of the conductive material from the contact 112 into the surrounding dielectric material. In some embodiments, the liner may include two barrier metal layers. The first barrier metal is connected to the source / drain region 104. SD and then may contact the source / drain region 104 SD The heavily doped semiconductor in the source / drain region 104 reacts chemically to form a low resistance ohmic contact, after which the unreacted metal can be removed. SD If the heavily doped semiconductor in the source / drain region 104 is silicon or a silicon-germanium alloy semiconductor, the first barrier metal may include Ti, Ni, Pt, Co, other suitable metals or alloys thereof, and may be connected to the source / drain region 104. SD Silicide is formed. The second barrier metal layer of the conductive liner may additionally include other metals (e.g., TiN, TaN, Ta or other suitable metals, or alloys thereof). Using any acceptable deposition technique (e.g., CVD, ALD, PEALD, PECVD, PVD, ECP, electroless plating or the like, or any combination thereof), a conductive fill material (e.g., W, Al, Cu, Ru, Ni, Co, alloys thereof, combinations thereof, and the like) may be deposited over the conductive liner layer to fill the contact opening. Next, a planarization process (e.g., CMP) may be used to remove any excess conductive material from over the surface of the ILD layer 110.

[0103] refer to Figure 4An inter-metal dielectric (IMD) layer 200 is formed over the ILD layer 110. In some embodiments, the IMD layer 200 may be made of, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, spin-on glass, spin-on polymer, silicon oxide, silicon oxynitride, combinations thereof, or the like, and may be formed by any suitable method such as spin coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or the like. In some embodiments, before forming the IMD layer, an etch stop layer (not shown) may be formed over the ILD layer 110. A photoresist layer PR1 is then formed over the IMD layer 200.

[0104] References Figure 5A , Figure 5B and Figure 5C ,in Figure 5A A perspective view of the wafer. Figure 5B is a top view of the wafer, and Figure 5C For along Figure 5B . An exposure process E1 is performed. During the exposure process E1, a first region 10A of the die region 10 is exposed using a mask MA1. In more detail, the first region 10A and the bonding region 10C are exposed using the mask MA1. In some embodiments, the raised region of the mask MA1 above the wafer W only covers the first region 10A and the bonding region 10C. That is, the raised region of the mask MA1 does not cover both the first region 10A and the second region 10B. In some embodiments, the raised region of the mask MA1 may also cover portions of the cutting lanes 22 and 24 adjacent to the first region 10A. In some embodiments, the second region 10B does not undergo the exposure process E1. Before performing the exposure process E1, the mask MA1 is appropriately aligned with the first region 10A.

[0105] In some embodiments, the mask MA1 may include a layout pattern P11, alignment mark patterns P12 and P13 (alignment marks). The layout pattern P11 and the alignment mark patterns P12 and P13 may be openings in the mask MA1, so that radiation can pass through the openings of the mask MA1 and expose the corresponding area of ​​the photoresist layer PR1 in the first area 10A. In more detail, the layout pattern P11 corresponds to the first area 10A of the die area 10 (for example, located above the first area 10A), the alignment mark pattern P12 corresponds to the cutting streets 22 and 24 (for example, located above the cutting streets 22 and 24), and the alignment mark pattern P13 corresponds to the bonding area 10C (for example, located above the bonding area 10C).

[0106] During the exposure process E1, the photoresist layer PR1 is exposed to radiation (e.g., EUV light) through the mask MA1 to form exposure areas E11, E12, and E13 in the photoresist layer PR1. The pattern of the exposure area E11 corresponds to the layout pattern P11, the pattern of the exposure area E12 corresponds to the alignment mark pattern P12, and the pattern of the exposure area E13 corresponds to the alignment mark pattern P13.

[0107] References Fig. 6A , Figure 6B and Figure 6C ,in Fig. 6A A perspective view of the wafer. Figure 6B is a top view of the wafer, and Figure 6C For along Figure 6B A cross-sectional view of line CC. FIG. 5A to FIG. 5C After the exposure process E1 discussed in the above is completed, the exposure process E2 is performed. During the exposure process E2, the second region 10B of the die region 10 is exposed using the mask MA2. In more detail, the second region 10B and the bonding region 10C are exposed using the mask MA2. In some embodiments, the raised area of ​​the mask MA2 only covers the second region 10B and the bonding region 10C. That is, the raised area of ​​the mask MA2 does not cover both the first region 10A and the second region 10B. In some embodiments, the raised area of ​​the mask MA2 may also cover the portions of the dicing streets 22 and 24 adjacent to the second region 10B. In some embodiments, the first region 10A does not undergo the exposure process E2.

[0108] In some embodiments, the mask MA2 may include a layout pattern P21 and an alignment mark pattern P22. The layout pattern P21 and the alignment mark pattern P22 may be openings in the mask MA2, so that radiation can pass through the openings of the mask MA2 and expose the corresponding area of ​​the photoresist layer PR1 in the second area 10B. In more detail, the layout pattern P21 corresponds to the second area 10B of the die area 10 (e.g., located above the second area 10B), and the alignment mark pattern P22 corresponds to the cutting streets 22 and 24 (e.g., located above the cutting streets 22 and 24).

[0109] During the exposure process E2, the photoresist layer PR1 is exposed to radiation (eg, EUV light) through the mask MA2 to form exposure areas E21 and E22 in the photoresist layer PR1. The pattern of the exposure area E21 corresponds to the layout pattern P21, and the pattern of the exposure area E22 corresponds to the alignment mark pattern P22.

[0110] like Figure 6B As shown in , the mask MA2 may include a protruding portion, wherein the raised area of ​​the protruding portion on the wafer may overlap the bonding area 10C. In some embodiments, one of the layout patterns P21 may extend into the protruding portion, and thus the corresponding exposure area E21 may extend into the bonding area 10C.

[0111] refer to Figure 7 After the exposure processes E1 and E2 are completed, a development process is performed to remove the exposed portion of the photoresist layer PR1. In more detail, the exposure regions E11, E12, E13, E21, and E22 in the photoresist layer PR1 are removed during the development process. Therefore, a plurality of openings corresponding to the patterns of the exposure regions E11, E12, E13, E21, and E22 are formed in the developed photoresist layer PR1. Therefore, the pattern of the mask MA1 and the pattern of the mask MA2 are transferred to the photoresist layer PR1.

[0112] The developed photoresist layer PR1 is then used as an etching mask to pattern the IMD layer 200. For example, an etching process is performed on the IMD layer 200 through the opening of the developed photoresist layer PR1. Therefore, the pattern of the mask MA1 and the pattern of the mask MA2 are transferred to the IMD layer 200 through the developed photoresist layer PR1.

[0113] exist Figure 7 , as a result of the etching process, openings O1, O2, O3, O4, and O5 are formed in the IMD layer 200. The pattern of the opening O1 may correspond to the layout pattern P11. The pattern of the opening O2 may correspond to the alignment mark pattern P12. The pattern of the opening O3 may correspond to the alignment mark pattern P13. The pattern of the opening O4 may correspond to the layout pattern P21. The pattern of the opening O5 may correspond to the alignment mark pattern P22.

[0114] References Fig. 8A , Figure 8B and Figure 8C ,in Fig. 8A A perspective view of the wafer. Figure 8B is a top view of the wafer, and Figure 8C For along Figure 8B . The photoresist layer PR1 is removed from the IMD layer 200 using a suitable process such as ashing or stripping. A conductive material such as a metal is formed in the openings O1, O2, O3, O4, and O5 of the IMD layer 200. Thereafter, a planarization process such as CMP is performed to remove excess conductive material until the IMD layer 200 is exposed. The conductive material may include a metal such as copper (Cu), aluminum (Al), tungsten (W), a combination thereof, or the like, and may be formed using a suitable deposition process.

[0115] The portions of the conductive material filled in the openings O1, O2, O3, O4 and O5 of the IMD layer 200 may be respectively referred to as metal features 211, alignment marks 212, alignment marks 213, metal features 214 and alignment marks 215. The patterns of the metal features 211, alignment marks 212, alignment marks 213, metal features 214 and alignment marks 215 may inherit the patterns of the layout pattern P11, alignment mark pattern P12, alignment mark pattern P13, layout pattern P21 and alignment mark pattern P22 described above.

[0116] In some embodiments, the metal feature 211 is electrically connected to the device 104 in the first region 10A of the die region 10 via the contact 112. On the other hand, the metal feature 214 is electrically connected to the device 104 in the second region 10B of the die region 10 via the contact 112. In some embodiments, the alignment marks 212, 213, and 215 are electrically isolated from the device 104. In some embodiments, the alignment mark 213 is only in the bonding region 10C and does not extend into the first region 10A and the second region 10B. In some embodiments, one of the metal features 214 may extend into the bonding region 10C.

[0117] refer to Fig. 9 An inter-metal dielectric (IMD) layer 220 is formed over the IMD layer 200. In some embodiments, the material and formation method of the IMD layer 220 may be similar to the material and formation method described with respect to the IMD layer 200, and thus, for the sake of brevity, the relevant details will not be repeated. A photoresist layer PR2 is then formed over the IMD layer 220.

[0118] References Fig. 10A , Fig. 10B and Fig. 10C ,in Fig. 10AA perspective view of the wafer. Fig. 10B is a top view of the wafer, and Fig. 10C For along Fig. 10B It should be noted that the alignment marks 212, 213 and 215 in the lower IMD layer 200 are Fig. 10A and Fig. 10B . The exposure process E3 is performed. During the exposure process E3, the first region 10A of the die region 10 is exposed using the mask MA3. In more detail, the first region 10A and the bonding region 10C are exposed using the mask MA1. In some embodiments, the raised region of the mask MA3 only covers the first region 10A and the bonding region 10C. That is, the raised region of the mask MA3 does not cover both the first region 10A and the second region 10B. In some embodiments, the raised region of the mask MA3 may also cover the portions of the cutting lanes 22 and 24 adjacent to the first region 10A. In some embodiments, the second region 10B does not undergo the exposure process E3.

[0119] In some embodiments, before performing the exposure process E3, the mask MA3 is aligned with the underlying metal features 211 of the IMD layer 200 in the first region 10A using the alignment marks 212 and / or 213 in the IMD layer 200. For example, the mask MA3 is aligned with the underlying metal features 211 of the IMD layer 200 in the first region 10A using the alignment marks 213 in the bonding region 10C. Once the mask MA3 is aligned with the metal features 211 of the IMD layer 200, the exposure process E3 can be performed.

[0120] In some embodiments, the mask MA3 may include a layout pattern P31, alignment mark patterns P32 and P33. The layout pattern P31 and the alignment mark patterns P32 and P33 may be openings in the mask MA1, so that radiation can pass through the openings of the mask MA3 and expose the corresponding area of ​​the photoresist layer PR2 in the first area 10A. In more detail, the layout pattern P31 corresponds to the first area 10A of the die area 10 (for example, located above the first area 10A), the alignment mark pattern P32 corresponds to the cutting streets 22 and 24 (for example, located above the cutting streets 22 and 24), and the alignment mark pattern P33 corresponds to the bonding area 10C (for example, located above the bonding area 10C).

[0121] During the exposure process E3, the photoresist layer PR2 is exposed to radiation (e.g., EUV light) through the mask MA3 to form exposure areas E31, E32, and E33 in the photoresist layer PR2. The pattern of the exposure area E31 corresponds to the layout pattern P31, the pattern of the exposure area E32 corresponds to the alignment mark pattern P32, and the pattern of the exposure area E13 corresponds to the alignment mark pattern P33.

[0122] In some embodiments, the exposure region E31 may overlap with the corresponding metal feature 211 in the IMD layer 200. Fig. 10C In the embodiment, at least the exposure region E31 vertically overlaps with the corresponding metal feature 211 in the IMD layer 200 .

[0123] On the other hand, the exposure areas E32 and E33 may not overlap with the alignment marks 212 and 213 in the IMD layer 200. For example, Fig. 10A and Fig. 10B As shown in FIG. 2 , the exposure area E33 does not overlap with the alignment mark 213 .

[0124] References Fig.11A , Fig. 11B and Fig. 11C ,in Fig.11A A perspective view of the wafer. Fig. 11B is a top view of the wafer, and Fig. 11C For along Fig. 11B A cross-sectional view of line CC. FIG. 10A to FIG. 10C After the exposure process E3 discussed in the above is completed, the exposure process E4 is performed. During the exposure process E4, the first region 10A of the die region 10 is exposed using the mask MA4. In more detail, the second region 10B and the bonding region 10C are exposed using the mask MA4. In some embodiments, the raised area of ​​the mask MA4 only covers the second region 10B and the bonding region 10C. That is, the raised area of ​​the mask MA4 does not cover both the first region 10A and the second region 10B. In some embodiments, the raised area of ​​the mask MA4 may also cover the portions of the dicing streets 22 and 24 adjacent to the second region 10B. In some embodiments, the first region 10A does not undergo the exposure process E4.

[0125] In some embodiments, before performing the exposure process E4, the mask MA4 is aligned with the underlying metal features 214 of the IMD layer 200 in the second region 10B using the alignment marks 213 and / or 215 in the IMD layer 200. For example, the mask MA4 is aligned with the underlying metal features 214 of the IMD layer 200 in the second region 10B using the alignment marks 213 in the bonding region 10C. Once the mask MA4 is aligned with the metal features 214 of the IMD layer 200, the exposure process E4 can be performed.

[0126] In some embodiments, the mask MA4 may include a layout pattern P41 and an alignment mark pattern P42. The layout pattern P41 and the alignment mark pattern P42 may be openings in the mask MA4, so that radiation can pass through the openings of the mask MA4 and expose the corresponding area of ​​the photoresist layer PR2 in the second area 10B. In more detail, the layout pattern P41 corresponds to the second area 10B of the die area 10 (for example, located above the second area 10B), and the alignment mark pattern P42 corresponds to the cutting streets 22 and 24 (for example, located above the cutting streets 22 and 24).

[0127] During the exposure process E4, the photoresist layer PR2 is exposed to radiation (eg, EUV light) through the mask MA4 to form exposure areas E41 and E42 in the photoresist layer PR2. The pattern of the exposure area E41 corresponds to the layout pattern P41, and the pattern of the exposure area E42 corresponds to the alignment mark pattern P42.

[0128] In some embodiments, the exposure region E41 may overlap with a corresponding metal feature 214 in the IMD layer 200. Fig. 11C In the embodiment, at least the exposure region E41 vertically overlaps with the corresponding metal feature 211 in the IMD layer 200 .

[0129] On the other hand, the exposure area E42 may not overlap with the alignment mark 215 in the IMD layer 200. For example, Fig.11A and Fig. 11B As shown in FIG. 2 , the exposure area E42 does not overlap with the alignment mark 215 .

[0130] refer to Fig.12 After the exposure processes E3 and E4 are completed, a development process is performed to remove the exposed portion of the photoresist layer PR2. In more detail, the exposure regions E31, E32, E33, E41, and E42 in the photoresist layer PR2 are removed during the development process. Therefore, a plurality of openings corresponding to the patterns of the exposure regions E31, E32, E33, E41, and E42 are formed in the developed photoresist layer PR2. Therefore, the pattern of the mask MA3 and the pattern of the mask MA4 are transferred to the photoresist layer PR2.

[0131] The developed photoresist layer PR2 is then used as an etching mask to pattern the IMD layer 220. For example, an etching process is performed on the IMD layer 220 through the opening of the developed photoresist layer PR2. Therefore, the pattern of the mask MA3 and the pattern of the mask MA4 are transferred to the IMD layer 220 through the developed photoresist layer PR2.

[0132] exist Fig.12 In the cross-sectional view of FIG. 1 , as a result of the etching process, openings O6 and O7 are formed in the IMD layer 220. The pattern of the opening O6 may correspond to the layout pattern P31. The pattern of the opening O7 may correspond to the layout pattern P41. Fig.12 Although not shown, openings corresponding to the alignment mark patterns P32, P33, and P42 may also be formed in the IMD layer 220.

[0133] References Fig.13A , Fig. 13B and Fig. 13C ,in Fig.13A A perspective view of the wafer. Fig. 13B is a top view of the wafer, and Fig. 13C For along Fig. 13B . The photoresist layer PR2 is removed from the IMD layer 220 using a suitable process such as ashing or stripping. A conductive material such as a metal is formed in the openings (e.g., openings O6 and O7) of the IMD layer 220. Thereafter, a planarization process such as CMP is performed to remove excess conductive material until the IMD layer 220 is exposed. The conductive material may include a metal such as copper (Cu), aluminum (Al), tungsten (W), a combination thereof, or the like, and may be formed using a suitable deposition process.

[0134] The portions of the conductive material filled in the openings of the IMD layer 220 may be respectively referred to as metal features 231, alignment marks 232, alignment marks 233, metal features 234, and alignment marks 235. The patterns of the metal features 231, alignment marks 232, alignment marks 233, metal features 234, and alignment marks 235 may inherit the patterns of the layout pattern P31, alignment mark pattern P32, alignment mark pattern P33, layout pattern P41, and alignment mark pattern P42 described above.

[0135] In some embodiments, the metal feature 231 contacts the corresponding metal feature 211 in the IMD layer 200. On the other hand, the metal feature 234 contacts the corresponding metal feature 214 in the IMD layer 200. That is, the metal features 231 and 234 can be electrically connected to the device 104 in the first region 10A and the second region 10B, respectively. In some embodiments, the alignment marks 232, 233, and 235 are electrically isolated from the device 104.

[0136] Furthermore, the alignment marks 232 and 233 may not overlap with the alignment marks 212 and 213 in the IMD layer 200. Similarly, the alignment mark 235 may not overlap with the alignment mark 215 in the IMD layer 200.

[0137] refer to Fig.14. Multiple IMD layers may be formed over IMD layer 220. For example, IMD layers 240 and 250 are shown formed over IMD layer 220. In some embodiments, each of IMD layers 240 and 250 may include metal features and alignment marks similar to those described with respect to IMD layers 200 and 220, and the methods of forming IMD layers 240 and 250 may also be similar to those described with respect to IMD layers 200 and 220. In some embodiments, although Fig.14 Although not shown, a plurality of IMD layers may be formed between the IMD layer 220 and the IMD layer 240. In some embodiments, the IMD layers such as the IMD layers 200, 220, 240, and 250 may be collectively referred to as a back-end-of-line (BEOL) structure 20. In some embodiments, the number of IMD layers (e.g., the IMD layers 200, 220, 240, and 250) is only for explanation and the present disclosure is not limited thereto. In other embodiments, more or fewer IMD layers may also be applied.

[0138] refer to Fig.15 For example, the wafer W is cut (or diced) via the dicing streets 22 and 24 (see Figure 2 ), so that each of the die regions 10 of the wafer W is singulated into individual semiconductor dies 11. During the die sawing process, the alignment marks within the sawing streets 22 and 24 (e.g., the alignment marks 212, 215, 232, and 235 described above) may be removed (or destroyed). Therefore, after the die sawing process, these alignment marks may not exist in the semiconductor die 11. On the other hand, after the die sawing process, the alignment marks within the bonding region 10C (e.g., the alignment marks 213 and 233 described above) may remain in the semiconductor die 11. Therefore, such alignment marks (e.g., the alignment marks 213 and 233) may be referred to as intra-die alignment marks or intra-wafer alignment marks.

[0139] Fig.16A is a perspective view of a wafer according to some embodiments of the present disclosure. Fig. 16B FIG. 4 is a top view of a wafer according to some embodiments of the present disclosure. Fig. 16C is a cross-sectional view of a wafer according to some embodiments of the present disclosure. In more detail, Fig. 16C For along Fig. 16B It should be noted that FIG. 16A to FIG. 16C Some parts of Figures 3A to 15 For components described in , such components are labeled as the same and the relevant details will not be repeated for the sake of brevity.

[0140] FIG. 16A to FIG. 16C The structure and Figures 3A to 15The structure discussed is different in that the alignment mark 213 may extend into the first region 10A of the die region 10. That is, the alignment mark 213 may overlap both the first region 10A and the bonding region 10C of the die region 10. In some embodiments, the alignment mark 213 does not extend into the second region 10B. Fig. 16C In the embodiment, the alignment mark 213 may vertically overlap with at least one device 104 in the first region 10A, while the alignment mark 213 does not overlap with the device 104 in the second region 10B.

[0141] The alignment mark 213 may be formed by, for example, designing the alignment mark pattern P13 of the mask MA1 so that Figure 5A The exposure area E13 of the photoresist layer PR1 overlaps both the first area 10A and the bonding area 10C of the die area 10. Therefore, the corresponding opening O3 formed in the IMD layer 200 will overlap both the first area 10A and the bonding area 10C of the die area 10, and the resulting pattern of the alignment mark 213 is shown in FIG. FIG. 16A to FIG. 16C .

[0142] Fig.17A is a perspective view of a wafer according to some embodiments of the present disclosure. Fig. 17B FIG. 4 is a top view of a wafer according to some embodiments of the present disclosure. Fig. 17C is a cross-sectional view of a wafer according to some embodiments of the present disclosure. In more detail, Fig. 17C For along Fig. 17B It should be noted that 17A to 17C Some parts of Figures 3A to 15 For components described in , such components are labeled as the same and the relevant details will not be repeated for the sake of brevity.

[0143] 17A to 17C The structure and Figures 3A to 15 The difference of the structure discussed is that the alignment mark 213 can extend into the first region 10A and the second region 10B of the die region 10. That is, the alignment mark 213 can overlap with the first region 10A, the second region 10B, and the bonding region 10C of the die region 10. Fig. 16C In the embodiment, the alignment mark 213 may vertically overlap at least one device 104 in the first region 10A, and may vertically overlap at least one device 104 in the second region 10B. The alignment mark 213 is formed in a portion of the first region 10A that does not contain a layout pattern (e.g., metal feature 211). This configuration can increase process flexibility.

[0144] Fig.18 is a cross-sectional view of a wafer according to some embodiments of the present disclosure. Fig.18 Similar to Fig. 13C , Fig.18and Fig. 13C The difference between Fig.18 The structure includes an alignment mark 500 within the bonding area 10C. In some embodiments, the alignment mark 500 can be formed in the same process as the formation of the fin 103. That is, the alignment mark 500 can be formed by patterning the substrate 102 using photolithography and etching techniques. Therefore, the alignment mark 500 can include the same material as the fin 103, and the top surface of the alignment mark 500 can be substantially flush with the top surface of the fin 103. In some embodiments, the alignment mark 500 can be used to align the mask (such as the masks MA1 to MA4 discussed above) during the exposure process. The alignment mark 213 is formed in the portion of the first area 10A and the second area 10B that does not contain the layout pattern (such as the metal features 211 and 214). This configuration can increase process flexibility.

[0145] Fig.19 is a cross-sectional view of a wafer according to some embodiments of the present disclosure. Fig.19 Similar to Fig. 13C , Fig.19 and Fig. 13C The difference between Fig.19 The structure includes an alignment mark 600 in the bonding region 10C. In some embodiments, the gate structure 104 may be formed G The alignment mark 600 is formed in the same process. In some embodiments, the alignment mark 600 may include a G The top surface of the alignment mark 600 may be the same as the gate structure 104. G The top surface of is substantially flush. In other embodiments, the alignment mark 600 may include polysilicon. In some embodiments, the alignment mark 600 may be used to align a mask (eg, the masks MA1 to MA4 discussed above) during an exposure process.

[0146] Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , Fig.22A and Fig. 22B It should be noted that the shapes of the alignment marks 212, 213, 215, 232, 233, 235, 500 and 600 discussed above are for explanation only, and the actual contours of the alignment marks 212, 213, 215, 232, 233, 235, 500 and 600 may vary with the embodiments. Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , Fig.22A and Fig. 22BPossible embodiments of alignment marks 212, 213, 215, 232, 233, 235, 500, and 600 as discussed above are illustrated.

[0147] Fig. 20A and Fig. 20B The first type of alignment mark is described below. Fig. 20A In FIG. 1 , an alignment mark AM1 having a longitudinal direction along the X direction is shown. Fig. 20B , an alignment mark AM2 having a longitudinal direction along the Y direction is shown. Each of the alignment marks AM1 and AM2 includes a first grating G1 of a feature 1001 and a second grating G2 of a feature 1002. The feature 1001 is a periodic structure extending in a first direction, the first direction making a first angle α relative to a center line between the first grating G1 and the second grating G2, wherein -20°<α<-65°. The feature 1002 is a periodic structure extending in a second direction, the first direction making a second angle β relative to a center line between the first grating G1 and the second grating G2, wherein 20°<β<65°. The alignment marks AM1 and AM2 each have a length L1 in the range of about 150 μm to about 170 μm and a width W1 in the range of about 5 μm to about 80 μm. The feature 1001 includes a fixed pitch PH1 in the range of about 2.0 μm to about 3.5 μm. Features 1002 include a fixed pitch PH2 in the range of about 2.0 μm to about 3.5 μm.

[0148] Fig.21A and Fig.21B The second type of alignment mark is described below. Fig.21A In FIG. 1 , an alignment mark AM3 having a longitudinal direction along the X direction is shown. Fig.21B , an alignment mark AM4 having a longitudinal direction along the Y direction is shown. Each of the alignment marks AM3 and AM4 includes a first grating G3 and a second grating G4. The first grating G3 may be similar to the second grating G4. For example, the first grating G3 and the second grating G4 each include a plurality of feature groups S1 that are periodically configured, and each feature group S1 includes a plurality of features 1011 that are periodically configured. The spacing PH3 between two adjacent feature groups S1 is in the range of about 10 μm to about 20 μm. The spacing PH4 between two adjacent features 1011 is smaller than the spacing PH3. The distance between the first grating G3 and the second grating G4 may be greater than the spacing PH3. The alignment marks AM3 and AM4 each have a length L2 in the range of about 300 μm to about 400 μm and a width W2 in the range of about 5 μm to about 80 μm.

[0149] Fig.22A and Fig. 22B A third type of alignment mark is described below. Fig.22AIn FIG. 1 , an alignment mark AM5 having a longitudinal direction along the X direction is shown. Fig. 22B , an alignment mark AM6 having a longitudinal direction along the Y direction is shown. Each of the alignment marks AM5 and AM6 includes a first grating G5, a second grating G6, a third grating G7, and a fourth grating G8. The first grating G5 includes a plurality of periodically configured features 1021, the second grating G6 includes a plurality of periodically configured features 1022, the third grating G7 includes a plurality of periodically configured features 1023, and the fourth grating G8 includes a plurality of periodically configured features 1024. A pitch PH5 between two adjacent features 1021 is in the range of about 1 μm to about 20 μm, a pitch PH6 between two adjacent features 1022 is in the range of about 1 μm to about 20 μm, a pitch PH7 between two adjacent features 1023 is in the range of about 1 μm to about 20 μm, and a pitch PH8 between two adjacent features 1024 is in the range of about 1 μm to about 20 μm. In some embodiments, pitch PH5 is equal to pitch PH8, and pitch PH6 is equal to pitch PH7, wherein pitches PH5 and PH8 are smaller than pitches PH6 and PH7. Alignment marks AM5 and AM6 each have a length L3 in a range of about 700 μm to about 800 μm and a width W3 in a range of about 5 μm to about 80 μm.

[0150] FIG. 23A to FIG. 24C A semiconductor die at various stages of manufacture according to some embodiments of the present disclosure is illustrated. It should be noted that FIG. 23A to FIG. 24C Some parts of Figures 3A to 15 Components described herein are labeled identically and the related details will not be repeated for the sake of brevity.

[0151] References Fig.23A , Fig. 23B and Fig.23C ,in Fig.23A A perspective view of the wafer. Fig. 23B is a top view of the wafer, and Fig.23C For along Fig. 23B Cross-sectional view of line CC. FIG. 23A to FIG. 23C This illustrates that a single exposure process E5 is used for the photoresist layer PR1 through the mask MA5. FIG. 5A to FIG. 6C In the process described in the above, the photoresist layer PR1 in the die region 10 is exposed in two steps (eg, two photomasks and two exposure processes). FIG. 23A to FIG. 23C In the embodiment, the photoresist layer PR1 in the entire die region 10 is exposed via a single mask MA5 in a single exposure process E5.

[0152] For example, the pattern of the mask MA5 may be transferred to the photoresist layer PR1 in the entire region of the die region 10. In more detail, the mask MA5 may include the layout pattern P11 and the alignment mark patterns P12 and P13 of the mask MA1 (see FIG. 5A to FIG. 5C ) and the layout pattern P21 and the alignment mark pattern P22 of the mask MA2 (see FIG. 6A to FIG. 6C ). Therefore, during the exposure process E5, exposure regions E11, E12, E13, E21, and E22 may be formed in the photoresist layer PR1. The structure may undergo the following steps: Figures 7 to 8C The process described in , and the resulting structure can be FIG. 8A to FIG. 8C The structure shown in is the same.

[0153] References Fig.24A , Fig. 24B and Fig.24C ,in Fig.24A A perspective view of the wafer. Fig. 24B is a top view of the wafer, and Fig.24C For along Fig. 24B Cross-sectional view of line CC. FIG. 24A to FIG. 24C This illustrates that a single exposure process E6 is used for the photoresist layer PR2 through the mask MA6. FIG. 10A to FIG. 11C In the process described in the above, the photoresist layer PR2 in the die region 10 is exposed in two steps (eg, two photomasks and two exposure processes). FIG. 24A to FIG. 24C In the embodiment, the photoresist layer PR2 in the entire region of the die region 10 is exposed via a single mask MA6 in a single exposure process E6.

[0154] For example, the pattern of the mask MA6 may be transferred to the photoresist layer PR2 in the entire region of the die region 10. In more detail, the mask MA6 may include the layout pattern P31 and the alignment mark patterns P32 and P33 of the mask MA3 (see FIG. 10A to FIG. 10C ) and the layout pattern P41 and alignment mark pattern P42 of the mask MA4 (see FIG. 11A to FIG. 11C ). Therefore, during the exposure process E6, exposure regions E31, E32, E33, E41, and E42 may be formed in the photoresist layer PR2. The structure may undergo the following steps: Figures 12 to 15 The process described in , and the resulting structure can be Fig.15 The structure shown in is the same.

[0155] Based on the foregoing embodiments, it can be seen that the present disclosure provides advantages in manufacturing integrated circuits. However, it should be understood that other embodiments may provide additional advantages, and not all advantages must be disclosed herein, and not all embodiments require specific advantages. Embodiments of the present disclosure provide wafer alignment marks in the bonding area to stabilize the stacking within the product. With this configuration, device stability can be improved.

[0156] In some embodiments of the present disclosure, a method includes: forming a photoresist layer above a wafer; aligning a first photomask with a first area of ​​the wafer; performing a first exposure process on a first portion of the photoresist layer within the first area of ​​the wafer; aligning a second photomask with a second area of ​​the wafer, wherein aligning the first photomask and aligning the second photomask are performed using alignment marks within a bonding area of ​​the wafer, the bonding area being an overlapping area of ​​the first area and the second area; performing a second exposure process on a second portion of the photoresist layer within the second area of ​​the wafer; and performing a development process to remove the first portion and the second portion of the photoresist layer.

[0157] In some embodiments, the alignment mark does not overlap with portions of the first region and the second region outside the bonding region.

[0158] In some embodiments, the method further includes performing a die-cutting process by cutting the wafer through scribe lines of the wafer to form semiconductor dies, wherein the alignment mark remains in the semiconductor die after the die-cutting process is completed.

[0159] In some embodiments, the alignment mark extends into the first region of the wafer.

[0160] In some embodiments, the alignment mark does not overlap with a portion of the second region outside the bonding area.

[0161] In some embodiments, the method further includes forming semiconductor devices over the first region and the second region of the wafer, and wherein the bonding region of the wafer is free of semiconductor devices.

[0162] In some embodiments, the alignment mark does not overlap the semiconductor device.

[0163] In some embodiments, the alignment mark overlaps at least one of the semiconductor devices.

[0164] In some embodiments of the present disclosure, a method includes: forming a photoresist layer above a wafer; performing a first exposure process on a first portion and a second portion of the photoresist layer in a first region of the wafer through a first photomask, wherein the first photomask has an alignment mark pattern corresponding to the second portion of the photoresist layer; performing a second exposure process on a third portion of the photoresist layer in a second region of the wafer through a second photomask, wherein the second portion of the photoresist layer is in a bonding region of the wafer, the bonding region being an overlapping region of the first region and the second region; and performing a development process to remove the first portion, the second portion, and the third portion of the photoresist layer to form a patterned photoresist layer.

[0165] In some embodiments, the method further includes: forming a dielectric layer above the wafer before forming the photoresist layer; performing an etching process on the dielectric layer through the patterned photoresist layer to form an opening in the dielectric layer, wherein the pattern of the opening in the bonding area of ​​the wafer corresponds to the alignment mark pattern of the first mask; and filling the opening of the dielectric layer with a material, wherein the material filled in the opening in the bonding area of ​​the wafer forms an alignment mark.

[0166] In some embodiments, the method further includes performing a die-cutting process by cutting the wafer through scribe lines of the wafer to form semiconductor dies, wherein the alignment mark remains in the semiconductor die after the die-cutting process is completed.

[0167] In some embodiments, the second portion of the photoresist layer extends into the first region of the wafer.

[0168] In some embodiments, the second portion of the photoresist layer does not overlap with the first region and the second region outside the bonding region.

[0169] In some embodiments, the method further includes forming semiconductor devices over the first region and the second region of the wafer, and wherein the bonding region of the wafer is free of semiconductor devices.

[0170] In some embodiments, the second portion of the photoresist layer does not overlap the semiconductor device.

[0171] In some embodiments of the present disclosure, a method includes: forming semiconductor devices in a first device area and a second device area of ​​a substrate, and no semiconductor devices are present in a non-device area of ​​the substrate, wherein the non-device area separates the first device area from the second device area; forming an alignment mark above the non-device area of ​​the substrate, wherein a portion of the alignment mark extends into the first device area of ​​the substrate; and using the alignment mark to form features above the first device area and the second device area.

[0172] In some embodiments, the non-device region is a stripe region extending continuously from one side of the substrate die to the other side of the substrate die.

[0173] In some embodiments, a portion of the alignment mark vertically overlaps at least one of the semiconductor devices.

[0174] In some embodiments, the method further includes forming a back-end-of-line (BEOL) structure above the semiconductor device, the BEOL structure including a dielectric layer and a metal feature in the dielectric layer, wherein the alignment mark is formed in the dielectric layer.

[0175] In some embodiments, the alignment marks include a periodic structured grating.

[0176] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor grain, characterized in that: The following steps are involved: forming a photoresist layer on a wafer; aligning a first photomask with a first area of ​​the wafer; Performing a first exposure process on a first portion of the photoresist layer in the first region of the wafer; Aligning a second photomask with a second area of ​​the wafer, wherein aligning the first photomask and aligning the second photomask are performed using an alignment mark in a bonding area of ​​the wafer, the bonding area being an overlap area of ​​the first area and the second area; Performing a second exposure process on a second portion of the photoresist layer in the second region of the wafer; and A developing process is performed to remove the first portion and the second portion of the photoresist layer.

2. The method according to claim 1, characterized in that The alignment mark does not overlap with portions of the first region and the second region outside the bonding region.

3. The method according to claim 1, characterized in that The alignment mark extends into the first area of ​​the wafer.

4. The method according to claim 3, characterized in that The alignment mark does not overlap with a portion of the second region outside the bonding region.

5. A method for forming a semiconductor grain, characterized in that: The following steps are involved: forming a photoresist layer on a wafer; Performing a first exposure process on a first portion and a second portion of the photoresist layer in a first region of the wafer through a first photomask, wherein the first photomask has an alignment mark pattern corresponding to the second portion of the photoresist layer; Performing a second exposure process on a third portion of the photoresist layer in a second region of the wafer through a second photomask, wherein the second portion of the photoresist layer is in a bonding region of the wafer, and the bonding region is an overlapping region of the first region and the second region; as well as A developing process is performed to remove the first portion, the second portion and the third portion of the photoresist layer to form a patterned photoresist layer.

6. The method according to claim 5, characterized in that Further comprising the steps of: forming a dielectric layer over the wafer before forming the photoresist layer; Performing an etching process on the dielectric layer through the patterned photoresist layer to form a plurality of openings in the dielectric layer, wherein a pattern of the plurality of openings in the bonding area of ​​the wafer corresponds to the alignment mark pattern of the first mask; and The plurality of openings of the dielectric layer are filled with a material, wherein the material filled in the plurality of openings in the bonding area of ​​the wafer forms an alignment mark.

7. The method according to claim 5, characterized in that Further comprising the steps of: A plurality of semiconductor devices are formed above the first region and the second region of the wafer, and wherein the bonding region of the wafer does not contain the plurality of semiconductor devices.

8. A method for forming a semiconductor grain, characterized in that: The following steps are involved: Forming a plurality of semiconductor devices in a first device region and a second device region of a substrate, and the plurality of semiconductor devices do not exist in a non-device region of the substrate, wherein the non-device region separates the first device region from the second device region; forming an alignment mark above the non-device area of ​​the substrate, wherein a portion of the alignment mark extends into the first device area of ​​the substrate; as well as Features are formed over the first device region and the second device region using the alignment mark.

9. The method according to claim 8, characterized in that The non-device area is a strip-shaped area extending continuously from one side of the substrate to the other side of the substrate.

10. The method according to claim 9, characterized in that The portion of the alignment mark vertically overlaps at least one of the plurality of semiconductor devices.

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