LDO chip without off-chip capacitor

Abstract

The invention relates to the technical field of semiconductor integrated circuits, and provides an off-chip capacitor-free LDO (Low Dropout Regulator) chip which comprises an error amplifier, a buffer circuit, an overshoot and undershoot suppression circuit, a power tube, a feedback circuit and a feed-forward circuit, the forward input end of the error amplifier is connected with the feedback end of the feedback circuit, the reverse input end of the error amplifier is connected with first reference voltage, the output end of the error amplifier is connected with the input end of the buffer circuit, and the output end of the buffer circuit is connected with the input end of the overshoot and undershoot suppression circuit, the output end of the feedforward circuit and the grid electrode of the power tube. The source electrode of the power tube is connected with an input power supply and the input end of the feedforward circuit, and the drain electrode of the power tube is connected with the output end of the overshoot and undershoot suppression circuit, the input end of the feedback circuit and the output end of the LDO chip. The performance of the LDO chip without the off-chip capacitor can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuits, and in particular to an LDO chip without an external capacitor. Background Art

[0002] Power management chips play a vital role in analog chips, digital chips, and mixed signal chips. These chips usually require multiple power systems of different types and voltage levels to ensure their normal operation and performance. Low Dropout Regulator (LDO) is a widely used power management integrated circuit that can provide a stable output voltage and remain relatively stable even when the input voltage and output load current change. LDO is favored for its advantages such as low noise, high efficiency, small area, and good load regulation. However, traditional LDO designs usually require a large external ceramic capacitor to ensure stability and reduce output noise. This external capacitor not only increases the material cost, but also increases the demand for circuit board space. Therefore, LDO without external capacitors has become a hot topic of research, but this design also brings new challenges, such as transient response performance, power supply ripple and output noise control. It can be seen that there is currently a problem of low performance of LDO chips without external capacitors. Summary of the invention

[0003] The present application provides an LDO chip without an external capacitor, which can solve the problem of low performance of the LDO chip without an external capacitor.

[0004] The present application provides an LDO chip without an external capacitor, the LDO chip comprising an error amplifier, a buffer circuit, an overshoot and undershoot suppression circuit, a power tube, a feedback circuit, and a feedforward circuit;

[0005] The positive input terminal of the error amplifier is connected to the feedback terminal of the feedback circuit, the reverse input terminal of the error amplifier is connected to the first reference voltage, the output terminal of the error amplifier is connected to the input terminal of the buffer circuit, the output terminal of the buffer circuit is respectively connected to the input terminal of the overshoot and undershoot suppression circuit, the output terminal of the feedforward circuit, and the gate of the power tube, the source of the power tube is respectively connected to the input power supply and the input terminal of the feedforward circuit, and the drain of the power tube is respectively connected to the output terminal of the overshoot and undershoot suppression circuit, the input terminal of the feedback circuit, and the output terminal of the LDO chip.

[0006] Optionally, the feedforward circuit includes an operational amplifier, a summing amplifier, an enhanced capacitor, and an enhanced resistor, wherein the first end of the enhanced capacitor is the input end of the feedforward circuit, and the output end of the summing amplifier is the output end of the feedforward circuit;

[0007] The first end of the enhancement resistor is connected to the second reference voltage, the second end of the enhancement resistor is respectively connected to the second end of the enhancement capacitor and the positive input end of the operational amplifier, and the output end of the operational amplifier is respectively connected to the reverse input end of the operational amplifier and the input end of the summing amplifier.

[0008] Optionally, the operational amplifier includes a first operational transistor, a second operational transistor, a third operational transistor, a fourth operational transistor, and a fifth operational transistor;

[0009] The gate of the third operational transistor is the positive input terminal of the operational amplifier, the gate of the fourth operational transistor is the negative input terminal of the operational amplifier, and the drain of the fourth operational transistor and the drain of the second operational transistor are both output terminals of the operational amplifier;

[0010] The source of the first operational transistor is connected to the source of the second operational transistor, the gate of the first operational transistor is respectively connected to the gate of the second operational transistor, the drain of the second operational transistor, and the drain of the third operational transistor, the source of the third operational transistor is respectively connected to the source of the fourth operational transistor and the drain of the fifth operational transistor, the source of the fifth operational transistor is connected to the ground terminal, and the gate of the fifth operational transistor is connected to the reverse control voltage;

[0011] The first operational transistor, the second operational transistor, the third operational transistor, the fourth operational transistor and the fifth operational transistor are all P-type MOS transistors.

[0012] Optionally, the overshoot and undershoot suppression circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, an initial transistor, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor;

[0013] The first end of the first capacitor, the second end of the second capacitor, the first end of the third capacitor, and the second end of the fourth capacitor are all output ends of the overshoot and undershoot suppression circuit, and the gate of the fourteenth transistor and the gate of the fifteenth transistor are all input ends of the overshoot and undershoot suppression circuit;

[0014] The second end of the first capacitor is respectively connected to the source of the initial transistor and the first end of the first resistor, the drain of the initial transistor is connected to the drain of the thirteenth transistor, the gate of the initial transistor is respectively connected to the gate of the sixth transistor, the drain of the fourteenth transistor, and the drain of the fifth transistor, the second end of the first resistor is respectively connected to the source of the first transistor, the source of the thirteenth transistor, and the source of the sixth transistor, the drain of the first transistor is respectively connected to the drain of the second transistor and the gate of the fifth transistor, the gate of the second transistor is connected to the gate of the fifth transistor, the source of the second transistor is respectively connected to the drain of the third transistor, the gate of the third transistor, the gate of the fourth transistor, and the second end of the third capacitor, the source of the third transistor is connected to the source of the fourth transistor, the drain of the fourth transistor is connected to the source of the fifth transistor, and the drain of the fifth transistor is connected to the drain of the sixth transistor;

[0015] The first end of the second capacitor is respectively connected to the gate of the ninth transistor and the gate of the tenth transistor, the source of the tenth transistor is connected to the source of the ninth transistor, the drain of the tenth transistor is connected to the source of the eleventh transistor, the drain of the ninth transistor is respectively connected to the gate of the ninth transistor and the source of the eighth transistor, the gate of the eighth transistor is respectively connected to the gate of the eleventh transistor, the drain of the seventh transistor and the drain of the eighth transistor, the drain of the tenth transistor is connected to the source of the eleventh transistor, the drain of the eleventh transistor is respectively connected to the gate of the thirteenth transistor, the drain of the twelfth transistor, the gate of the twelfth transistor and the drain of the fifteenth transistor, the source of the twelfth transistor is respectively connected to the source of the fifteenth transistor, the source of the seventh transistor and the first end of the second resistor, the first end of the second resistor is respectively connected to the source of the thirteenth transistor and the first end of the fourth capacitor, the gate of the seventh transistor is connected to the forward control voltage, and the gate of the first transistor is connected to the reverse control voltage.

[0016] Optionally, the initial transistor, the first transistor, the sixth transistor, the fourteenth transistor, the eleventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all P-type MOS transistors;

[0017] The second transistor, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, the twelfth transistor, the thirteenth transistor and the fifteenth transistor are all N-type MOS transistors.

[0018] Optionally, the feedback circuit includes a first feedback resistor, a second feedback resistor, and a feedback capacitor;

[0019] The first end of the first feedback resistor and the first end of the feedback capacitor are both input ends of the feedback circuit, the second end of the first feedback resistor and the first end of the second feedback resistor are both feedback ends of the feedback circuit, and the second end of the second feedback resistor is respectively connected to the second end of the feedback capacitor and the ground end.

[0020] Optionally, the error amplifier includes a first error transistor, a second error transistor, a third error transistor, a fourth error transistor, a fifth error transistor, a sixth error transistor, a seventh error transistor, an eighth error transistor, a ninth error transistor, and a tenth error transistor;

[0021] The gate of the second error transistor is the positive input terminal of the error amplifier, the gate of the third error transistor is the negative input terminal of the error amplifier, and the drain of the seventh error transistor and the drain of the ninth error transistor are both output terminals of the error amplifier;

[0022] The gate of the first error transistor is connected to the forward control voltage, the source of the first error transistor is connected to the source of the tenth error transistor and the source of the eleventh error transistor respectively, the drain of the first error transistor is connected to the source of the second error transistor and the source of the third error transistor respectively, the drain of the second error transistor is connected to the drain of the fourth error transistor and the source of the sixth error transistor respectively, the drain of the third error transistor is connected to the drain of the fifth error transistor and the source of the seventh error transistor respectively, the source of the fourth transistor is connected to the source of the fifth transistor, the gate of the fourth error transistor and the gate of the fifth error transistor are both connected to the first bias voltage, the gate of the sixth error transistor and the gate of the seventh error transistor are both connected to the second bias voltage, the drain of the sixth error transistor is connected to the drain of the eighth error transistor, the gate of the tenth error transistor and the gate of the eleventh error transistor respectively, the gate of the eighth error transistor and the gate of the ninth error transistor are both connected to the third bias voltage, the source of the eighth error transistor is connected to the drain of the tenth error transistor, and the source of the ninth error transistor is connected to the drain of the eleventh error transistor;

[0023] Optionally, the first error transistor, the second error transistor, the third error transistor, the eighth error transistor, the ninth error transistor, the tenth error transistor, and the eleventh error transistor are all N-type MOS transistors;

[0024] The fourth error transistor, the fifth error transistor, the sixth error transistor and the seventh error transistor are all P-type MOS transistors.

[0025] Optionally, the buffer circuit includes a first push-pull transistor, a second push-pull transistor, a third push-pull transistor, a fourth push-pull transistor, a fifth push-pull transistor, a sixth push-pull transistor, a seventh push-pull transistor, an eighth push-pull transistor, a ninth push-pull transistor, and a tenth push-pull transistor;

[0026] The gate of the second push-pull transistor and the gate of the sixth push-pull transistor are both input terminals of the buffer circuit, and the drain of the eighth push-pull transistor and the source of the ninth push-pull transistor are both output terminals of the buffer circuit;

[0027] The gate of the first push-pull transistor is connected to the forward control voltage, the source of the first push-pull transistor is connected to the source of the seventh push-pull transistor, the drain of the fifth push-pull transistor, and the source of the eighth push-pull transistor respectively, the drain of the first push-pull transistor is connected to the source of the second push-pull transistor and the gate of the fifth push-pull transistor respectively, the drain of the second push-pull transistor is connected to the drain of the third push-pull transistor, the gate of the third push-pull transistor, and the gate of the fourth push-pull transistor respectively, the source of the third push-pull transistor is connected to the source of the tenth push-pull transistor, the source of the fourth push-pull transistor, and the drain of the ninth push-pull transistor respectively, the drain of the tenth push-pull transistor is connected to the source of the sixth push-pull transistor and the gate of the ninth push-pull transistor respectively, the gate of the tenth push-pull transistor is connected to the reverse control voltage, the drain of the fourth push-pull transistor is connected to the source of the fifth push-pull transistor, the drain of the eighth push-pull transistor, and the source of the ninth push-pull transistor respectively, and the drain of the sixth push-pull transistor is connected to the drain of the seventh push-pull transistor, the gate of the sixth push-pull transistor, and the gate of the eighth push-pull transistor respectively.

[0028] Optionally, the first push-pull transistor, the second push-pull transistor, the seventh push-pull transistor, the eighth push-pull transistor, and the ninth push-pull transistor are all N-type MOS transistors;

[0029] The third push-pull transistor, the fourth push-pull transistor, the fifth push-pull transistor, the sixth push-pull transistor and the tenth push-pull transistor are all P-type MOS transistors.

[0030] The above solution of the present application has the following beneficial effects:

[0031] In some embodiments of the present application, by utilizing a feedforward circuit to perform phase-opposite superposition with the main path of the LDO, the ripple is effectively suppressed, and differential power supply input is achieved, thereby enhancing the power supply suppression performance of the entire LDO chip and reducing the interference of the power supply ripple on the output voltage. By introducing a buffer circuit, the LDO chip can quickly adopt different paths in the buffer circuit for different loads during actual application, thereby improving the transient response effect of the LDO chip without external capacitors. At the same time, by connecting an overshoot and undershoot suppression circuit to the output end of the buffer circuit, the voltage output by the buffer circuit can be processed, the degree of voltage overshoot and voltage undershoot can be reduced, the stability of the output voltage can be improved, and the performance of the LDO chip without external capacitors can be further improved.

[0032] Other beneficial effects of the present application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 A topological structure diagram of an LDO chip without external capacitors provided in an embodiment of the present application;

[0035] Figure 2 A schematic diagram of the structure of an operational amplifier provided in one embodiment of the present application;

[0036] Figure 3 A schematic diagram of the structure of an overshoot and undershoot suppression circuit provided in an embodiment of the present application;

[0037] Figure 4 A specific circuit topology diagram of an LDO chip without external capacitors provided in one embodiment of the present application;

[0038] Figure 5 A schematic diagram of a PSR curve provided in an embodiment of the present application;

[0039] Figure 6 A schematic diagram of a first instantaneous result provided in an embodiment of the present application;

[0040] Figure 7 A schematic diagram of a second instantaneous result provided in an embodiment of the present application;

[0041] Figure 8 A schematic diagram of a third instantaneous result provided in an embodiment of the present application;

[0042] Fig. 9 A topological diagram of a DCDC and LDO hybrid circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0044] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0045] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0046] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0047] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0048] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0049] In view of the problem of low performance of LDO chips without external capacitors, the present application provides an LDO chip without external capacitors. By utilizing a feedforward circuit to perform phase-opposite superposition with a main path of the LDO, ripple is effectively suppressed, and differential power input is realized, thereby enhancing the power suppression performance of the entire LDO chip and reducing the interference of the power ripple on the output voltage. By introducing a buffer circuit, the LDO chip can quickly adopt different paths in the buffer circuit for different loads during actual application, thereby improving the transient response effect of the LDO chip without external capacitors. At the same time, by connecting an overshoot and undershoot suppression circuit to the output end of the buffer circuit, the voltage output by the buffer circuit can be processed, the degree of voltage overshoot and voltage undershoot is reduced, the stability of the output voltage is improved, and the performance of the LDO chip without external capacitors is further improved.

[0050] Next, an exemplary description is given of the LDO chip without external capacitors provided in the present application.

[0051] like Figure 1 As shown, the LDO chip without external capacitor provided by the present application includes: an error amplifier (such as Figure 1 EA-amp), buffer circuit (such as Figure 1 buffer in), overshoot and undershoot suppression circuit (such as Figure 1 UndershootOvershoot), power tube (such as Figure 1 MP in), feedback circuit, feedforward circuit.

[0052] The positive input terminal of the error amplifier is connected to the feedback terminal of the feedback circuit, and the negative input terminal of the error amplifier is connected to the first reference voltage (such as Figure 1 The output of the error amplifier is connected to the input of the buffer circuit. The output of the buffer circuit is connected to the input of the overshoot and undershoot suppression circuit, the output of the feedforward circuit, and the gate of the power tube. The source of the power tube is connected to the input power supply (such as Figure 1 The drain of the power tube is connected to the output end of the overshoot and undershoot suppression circuit, the input end of the feedback circuit, and the output end of the LDO chip respectively.

[0053] The feed-forward circuit includes an operational amplifier (such as Figure 1 FA-amp in), summing amplifier (such as Figure 1 SA-amp in), enhanced capacitors (such as Figure 1 Ch1 in), enhancement resistor (such as Figure 1 Rh1 in the figure), the first end of the enhancement capacitor is the input end of the feedforward circuit, and the output end of the summing amplifier is the output end of the feedforward circuit.

[0054] The first terminal of the enhancement resistor is connected to a second reference voltage (such as Figure 1 The second end of the enhancement resistor is connected to the second end of the enhancement capacitor and the positive input end of the operational amplifier, and the output end of the operational amplifier is connected to the reverse input end of the operational amplifier and the input end of the summing amplifier.

[0055] The feedback circuit includes a first feedback resistor (such as Figure 1 R1 in), the second feedback resistor (such as Figure 1 R2 in), feedback capacitor (such as Figure 1 CL in.

[0056] The first end of the first feedback resistor and the first end of the feedback capacitor are both input ends of the feedback circuit, the second end of the first feedback resistor and the first end of the second feedback resistor are both feedback ends of the feedback circuit, and the second end of the second feedback resistor is connected to the second end of the feedback capacitor and the ground end (such as Figure 1 is connected to VSS in the circuit.

[0057] It should be noted that Figure 1 Here VG represents the gate voltage of the power tube, VFB represents the feedback voltage, and Vout represents the output voltage of the LDO chip.

[0058] like Figure 2 As shown, the operational amplifier includes a first operational transistor (such as Figure 2 Mf1 in), the second operational transistor (such as Figure 2 Mf2 in), the third operational transistor (such as Figure 2 Mf3 in), the fourth operational transistor (such as Figure 2 Mf4 in), the fifth operational transistor (such as Figure 2 Mf5 in ).

[0059] The gate of the third operational transistor is the positive input terminal of the operational amplifier (such as Figure 2The gate of the fourth operational transistor is the inverting input terminal of the operational amplifier (such as Figure 2 Vn in the figure), the drain of the fourth operational transistor and the drain of the second operational transistor are both output terminals of the operational amplifier (such as Figure 2 Vout_FA in ).

[0060] The source of the first operational transistor is connected to the source of the second operational transistor, the gate of the first operational transistor is connected to the gate of the second operational transistor, the drain of the second operational transistor, and the drain of the third operational transistor, the source of the third operational transistor is connected to the source of the fourth operational transistor and the drain of the fifth operational transistor, and the source of the fifth operational transistor is connected to the ground terminal (such as Figure 2 The gate of the fifth operational transistor is connected to the reverse control voltage (such as Figure 2 Vn_bias in ).

[0061] The first operational transistor, the second operational transistor, the third operational transistor, the fourth operational transistor and the fifth operational transistor are all P-type MOS transistors.

[0062] It should be noted that, since the first operational transistor and the second operational transistor are both P-type MOS transistors, for the P-type MOS transistor, the source needs to be connected to the input power supply, so the source of the first operational transistor and the source of the second operational transistor are also connected to the input power supply (such as Figure 2 The source of the first operational transistor and the source of the second operational transistor are connected to VDD, which is a fixed connection mode of the P-type MOS tube. Figure 1 The source negative feedback is realized by the feedforward circuit, and the voltage ripple transmitted by the operational amplifier is summed by the summing amplifier and then injected into the gate of the power tube, so as to partially eliminate the voltage ripple directly entering the power tube from VDD.

[0063] like Figure 3 As shown, the overshoot and undershoot suppression circuit includes a first transistor (such as Figure 3 Mc1 in), the second transistor (such as Figure 3 Mc2 in), the third transistor (such as Figure 3 Mc3 in), the fourth transistor (such as Figure 3 Mc4 in), the fifth transistor (such as Figure 3 Mc5 in), the sixth transistor (such as Figure 3 Mc6 in), the seventh transistor (such as Figure 3 Mc7 in), the eighth transistor (such as Figure 3 Mc8 in), the ninth transistor (such as Figure 3 Mc9 in), the tenth transistor (such as Figure 3 Mc10 in), the eleventh transistor (such as Figure 3 Mc11 in), the twelfth transistor (such as Figure 3 Mc12 in), the thirteenth transistor (such as Figure 3 Mc13 in), the fourteenth transistor (such as Figure 3 MI1 in), the fifteenth transistor (such as Figure 3 MI2 in), initial transistor (such as Figure 3 Mc0 in), the first resistor (such as Figure 3 R1 in), the second resistor (such as Figure 3 R2 in), the first capacitor (such as Figure 3 C1 in), the second capacitor (such as Figure 3 C2 in), the third capacitor (such as Figure 3 C3 in) and the fourth capacitor (such as Figure 3 C4 in ).

[0064] The first end of the first capacitor, the second end of the second capacitor, the first end of the third capacitor, and the second end of the fourth capacitor are all output ends of the overshoot and undershoot suppression circuit (such as Figure 3 The gate of the fourteenth transistor and the gate of the fifteenth transistor are both input terminals of the overshoot and undershoot suppression circuit (such as Figure 3 Vp_bias1 and Vn_bias1 in ).

[0065] The second end of the first capacitor is respectively connected to the source of the initial transistor and the first end of the first resistor, the drain of the initial transistor is connected to the drain of the thirteenth transistor, the gate of the initial transistor is respectively connected to the gate of the sixth transistor, the drain of the fourteenth transistor, and the drain of the fifth transistor, the second end of the first resistor is respectively connected to the source of the first transistor, the source of the thirteenth transistor, and the source of the sixth transistor, the drain of the first transistor is respectively connected to the drain of the second transistor and the gate of the fifth transistor, the gate of the second transistor is connected to the gate of the fifth transistor, the source of the second transistor is respectively connected to the drain of the third transistor, the gate of the third transistor, the gate of the fourth transistor, and the second end of the third capacitor, the source of the third transistor is connected to the source of the fourth transistor, the drain of the fourth transistor is connected to the source of the fifth transistor, and the drain of the fifth transistor is connected to the drain of the sixth transistor.

[0066] The first end of the second capacitor is connected to the gate of the ninth transistor and the gate of the tenth transistor respectively, the source of the tenth transistor is connected to the source of the ninth transistor, the drain of the tenth transistor is connected to the source of the eleventh transistor, the drain of the ninth transistor is connected to the gate of the ninth transistor and the source of the eighth transistor respectively, the gate of the eighth transistor is connected to the gate of the eleventh transistor, the drain of the seventh transistor and the drain of the eighth transistor respectively, the drain of the tenth transistor is connected to the source of the eleventh transistor, the drain of the eleventh transistor is connected to the gate of the thirteenth transistor, the drain of the twelfth transistor, the gate of the twelfth transistor and the drain of the fifteenth transistor respectively, the source of the twelfth transistor is connected to the source of the fifteenth transistor, the source of the seventh transistor and the first end of the second resistor respectively, the first end of the second resistor is connected to the source of the thirteenth transistor and the first end of the fourth capacitor respectively, and the gate of the seventh transistor is connected to the forward control voltage (such as Figure 3 The gate of the first transistor is connected to a reverse control voltage (such as Vp_bias in Figure 3 Vn_bias in ).

[0067] It should be noted that the source of the third transistor, the source of the fourth transistor, the first end of the second resistor, the source of the seventh transistor, the source of the fifteenth transistor, and the source of the twelfth transistor are also connected to the input power supply (such as Figure 3 The second end of the first resistor, the source of the first transistor, the source of the fourteenth transistor, the source of the sixth transistor, the source of the ninth transistor, and the source of the tenth transistor are also connected to the ground terminal (such as Figure 3 VSS in Figure 3 The connection between the transistor and VDD and the connection between the transistor and VSS are both fixed connection methods of the transistor. Figure 1 Not shown in the figure, Figure 3 VG in the figure represents the gate voltage of the power transistor. The initial transistor, the first transistor, the sixth transistor, the fourteenth transistor, the eleventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all P-type MOS transistors; the second transistor, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, the twelfth transistor, the thirteenth transistor, and the fifteenth transistor are all N-type MOS transistors.

[0068] according to Figure 1 The structure of the LDO chip without external capacitors is shown. Figure 2 The specific circuit topology of the LDO chip without external capacitors (without overshoot and undershoot suppression circuit and enhanced capacitor Ch1 and enhanced resistor Rh1 for filtering) obtained by the structure of the operational amplifier shown in FIG. Figure 4 shown.

[0069] like Figure 4As shown, the error amplifier includes a first error transistor (such as Figure 4 Ma1 in), the second error transistor (such as Figure 4 Ma2 in), the third error transistor (such as Figure 4 Ma3 in), the fourth error transistor (such as Figure 4 Ma4 in), the fifth error transistor (such as Figure 4 Ma5 in), the sixth error transistor (such as Figure 4 Ma6 in), the seventh error transistor (such as Figure 4 Ma7 in), the eighth error transistor (such as Figure 4 Ma8 in), the ninth error transistor (such as Figure 4 Ma9 in), the tenth error transistor (such as Figure 4 in Ma10).

[0070] The gate of the second error transistor is the positive input terminal of the error amplifier (such as Figure 4 The gate of the third error transistor is the inverting input terminal of the error amplifier (such as Figure 4 The drain of the seventh error transistor and the drain of the ninth error transistor are both output terminals of the error amplifier (such as Figure 4 in VEA).

[0071] The gate of the first error transistor is connected to a positive control voltage (such as Figure 4 vp_bias in, the source of the first error transistor is connected to the source of the tenth error transistor and the source of the eleventh error transistor respectively, the drain of the first error transistor is connected to the source of the second error transistor and the source of the third error transistor respectively, the drain of the second error transistor is connected to the drain of the fourth error transistor and the source of the sixth error transistor respectively, the drain of the third error transistor is connected to the drain of the fifth error transistor and the source of the seventh error transistor respectively, the source of the fourth transistor is connected to the source of the fifth transistor, and the gates of the fourth error transistor and the fifth error transistor are both connected to the first bias voltage (such as Figure 4 The gates of the sixth error transistor and the seventh error transistor are both connected to a second bias voltage (such as vb1). Figure 4 The drain of the sixth error transistor is connected to the drain of the eighth error transistor, the gate of the tenth error transistor, and the gate of the eleventh error transistor, respectively. The gates of the eighth error transistor and the ninth error transistor are both connected to a third bias voltage (such as Figure 4 vb3 in the figure), the source of the eighth error transistor is connected to the drain of the tenth error transistor, and the source of the ninth error transistor is connected to the drain of the eleventh error transistor.

[0072] It should be noted that the first error transistor, the second error transistor, the third error transistor, the eighth error transistor, the ninth error transistor, the tenth error transistor and the eleventh error transistor are all N-type MOS transistors; the fourth error transistor, the fifth error transistor, the sixth error transistor and the seventh error transistor are all P-type MOS transistors.

[0073] The buffer circuit includes a first push-pull transistor (such as Figure 4 Mb1 in), the second push-pull transistor (such as Figure 4 Mb2 in), the third push-pull transistor (such as Figure 4 Mb3 in), the fourth push-pull transistor (such as Figure 4 Mb4 in), the fifth push-pull transistor (such as Figure 4 Mb5 in), the sixth push-pull transistor (such as Figure 4 Mb6 in), the seventh push-pull transistor (such as Figure 4 Mb7 in), the eighth push-pull transistor (such as Figure 4 Mb8 in), the ninth push-pull transistor (such as Figure 4 Mb9 in), the tenth push-pull transistor (such as Figure 4 Mb10 in).

[0074] The gate of the second push-pull transistor and the gate of the sixth push-pull transistor are both input terminals of the buffer circuit, and the drain of the eighth push-pull transistor and the source of the ninth push-pull transistor are both output terminals of the buffer circuit.

[0075] The gate of the first push-pull transistor is connected to the forward control voltage, the source of the first push-pull transistor is connected to the source of the seventh push-pull transistor, the drain of the fifth push-pull transistor, and the source of the eighth push-pull transistor respectively, the drain of the first push-pull transistor is connected to the source of the second push-pull transistor and the gate of the fifth push-pull transistor respectively, the drain of the second push-pull transistor is connected to the drain of the third push-pull transistor, the gate of the third push-pull transistor, and the gate of the fourth push-pull transistor respectively, the source of the third push-pull transistor is connected to the source of the tenth push-pull transistor, the source of the fourth push-pull transistor, and the drain of the ninth push-pull transistor respectively, the drain of the tenth push-pull transistor is connected to the source of the sixth push-pull transistor and the gate of the ninth push-pull transistor respectively, the gate of the tenth push-pull transistor is connected to the reverse control voltage, the drain of the fourth push-pull transistor is connected to the source of the fifth push-pull transistor, the drain of the eighth push-pull transistor, and the source of the ninth push-pull transistor respectively, and the drain of the sixth push-pull transistor is connected to the drain of the seventh push-pull transistor, the gate of the sixth push-pull transistor, and the gate of the eighth push-pull transistor respectively.

[0076] It should be noted that the first push-pull transistor, the second push-pull transistor, the seventh push-pull transistor, the eighth push-pull transistor and the ninth push-pull transistor are all N-type MOS transistors; the third push-pull transistor, the fourth push-pull transistor, the fifth push-pull transistor, the sixth push-pull transistor and the tenth push-pull transistor are all P-type MOS transistors. Figure 4 In the figure, VDD represents the input voltage, VSS represents the ground terminal, RD represents the first adding resistor, RS represents the second adding resistor, Ms1 represents the first adding transistor, Ms2 represents the second adding transistor, and Mf6 represents the third adding transistor, wherein the source of the second adding transistor and the source of the first adding transistor are both output terminals of the summing amplifier, and the gate of the third adding transistor, the source of the third adding transistor and the first end of the second adding resistor are all input terminals of the summing amplifier; the gate of the third adding transistor is connected to the output terminal of the operational amplifier, the source of the third adding transistor is respectively connected to the inverting input terminal of the operational amplifier and the first end of the second adding resistor, the drain of the third adding transistor is respectively connected to the second end of the first adding resistor and the gate of the first adding transistor, the second end of the second adding resistor is respectively connected to the ground terminal and the drain of the second adding transistor, the gate of the second adding transistor is the Vb terminal, the Vb terminal represents the bias voltage, and the first end of the first adding resistor is connected to the first end of the first adding transistor. Figure 4 The + in the symbol indicates the addition of current.

[0077] The working principle of the LDO chip without external capacitors of the present application is exemplarily described below.

[0078] The feedforward circuit in the LDO chip without external capacitors of the present application is used to reduce the influence of the voltage ripple generated by the input voltage on the output voltage, and is mainly composed of a five-tube operational amplifier, a common source of source-level negative feedback, and a common source with a bias voltage. When the feedforward circuit is not added, the transfer function of the LDO chip is:

[0079]

[0080] Wherein, VOUT represents the output voltage, VDD represents the input voltage, gm,mp represents the transconductance of the power tube, rds,mp represents the channel resistance of the power tube, Zl(s) represents the impedance at the output of the LDO, R1 represents the first feedback resistor, R2 represents the second feedback resistor, AEA represents the gain of the error amplifier, Abuffer represents the gain of the buffer (buffer circuit), and wout represents the main pole of the LDO.

[0081] When the feedforward circuit is added, the transfer function of the LDO chip is:

[0082]

[0083] Where Hff(s) is the gain of the feedforward circuit, As0 is the gain of the summing amplifier, ws is the dominant pole of the summing amplifier, and s represents a pure imaginary number, which is used to describe the response of the system to sinusoidal input signals of different frequencies.

[0084] Since gm,mp*rds,mp>>1, we only need to set Theoretically, the voltage ripple can be made infinitely small and close to 0, and an excellent power supply rejection (PSR) effect can be obtained. In the feedforward circuit, a 1:1 voltage ripple replication is used. Here, a five-tube op amp is used as the first stage of the feedforward amplification. The voltage ripple at the output of the op amp can be expressed as:

[0085]

[0086] Since Ro2>>1 / gm1,

[0087]

[0088] Among them, Vout_FA is the voltage ripple output by the operational amplifier, I2 is the current flowing through the input tube, and Ro1 and Ro2 are the channel resistances of the load tube and the input tube respectively.

[0089] The voltage ripple of the feedforward circuit proposed in this application is copied 1:1 and then passes through the feedback loop. The resistor is used as the connection form in the deep negative feedback loop. The voltage gain at this time is After passing through the common source of the summing amplifier, since the main pole of the summing amplifier is far away from the bandwidth, the gain attenuation caused by its main pole is negligible. In addition, the use of an independent bias voltage in this structure can avoid the reduction of the gain of the feedforward ripple circuit caused by the reduction of the voltage gain in the loop, reduce the replication ratio, and lead to inaccurate replication and no enhancement effect. Compared with the existing structure, the summing amplifier is connected in the loop, which has high stability and better PSR enhancement ability, and achieves ripple suppression effect at medium and low frequencies. Finally, the power tube is input and the voltage ripple of the power tube branch is differentially eliminated to achieve a high PSR effect.

[0090] In this application, a buffer circuit is added to enhance transient state. The buffer circuit controls the change of the tail current of the overshoot and undershoot suppression circuit and utilizes the subthreshold current characteristics of the transistor to achieve transient enhancement. The buffer circuit adopts two load passing paths. When the load is light, the VEA voltage is higher and the VG voltage is higher, such as Figure 4As shown, Mb6-Mb9 start to work, Mb1-Mb5 cut off, under heavy load, Mb1-Mb5 conducts, Mb6-Mb9 cuts off, in the process of load current switching, light load-heavy load, due to insufficient loop bandwidth, the loop does not have time to respond, and cannot provide the large current required by the power tube. At this time, the load capacitor provides the required charge, resulting in a decrease in the output voltage, which further leads to a decrease in the feedback voltage. After the folded common source and common gate op amp output, the output voltage of the op amp decreases. At this time, the Mb1-Mb5 loop works, and the Due to the current source control of Mb1, the gate voltage of Mb2 decreases, so the source voltage of Mb2 will also decrease, and the current will be copied to Mb4 through Mb3. Similarly, the gate voltage of Mb5 is equal to the source voltage of Mb2, which will decrease, so the source voltage of Mb5 will decrease, and the gate voltage VG of the power tube is equal to the source voltage of Mb5, so the gate voltage of the power tube can be pulled down, and the current of the power tube can be pulled up (the pulled-up current is equal to gmp*ΔVGS), and the power tube can be adjusted to reach the load current, so that it responds faster. Heavy load-light load, the current required by the power tube is reduced, and the excess charge charges the output capacitor, resulting in an increase in the output voltage, and the output voltage of the op amp also increases. At this time, the Mb6-Mb10 loop works, and Mb10 acts as a current source to clamp the current. The source voltage of Mb6 increases, passes through Mb8, and finally the source voltage of Mb8 also increases, so the VG voltage increases, pulls up the gate voltage of PMOS, reduces the current of the power tube, and achieves a fast response effect.

[0091] However, due to loop bandwidth and transistor state, the current cannot change too much, resulting in insufficient transient effect. Therefore, another overshoot and undershoot suppression circuit is added, controlled by the buffer circuit, and the transistor size is increased so that all transistors are in the subthreshold region. The current change formula in the subthreshold region is:

[0092]

[0093] Where ID is the current after the change, I0 is the current before the change, Vgs is the gate-source voltage, ξ is a non-ideal factor, and VT is an intermediate parameter. K is the Boltzmann constant, T is the absolute temperature, and q is the elementary charge.

[0094] When the voltage changes, the current changes exponentially. Figure 4As shown, the source end of the transistor Mb6 in the buffer circuit controls the current source MI1 at the tail. The principle of increasing the current is to control the current of MI1 in a DC environment to completely absorb the current from Mc4 and Mc5, so that no current passes through Mc6, and therefore no current passes through Mc0, which does not cause any impact in steady state. In the switching process from light load to heavy load, due to the reduction of output voltage, the voltage at the source end of Mb6 will eventually decrease. The current consumed by the circuit source MI1 gradually decreases, and the excess current is transmitted to Mc0 through Mc6. The current of Mc0 increases, and the final changing current flows through Mc0 to adjust the gate voltage of the power tube. The current formula at this time is:

[0095]

[0096] Among them, the channel length modulation effect is ignored, Vgs is the gate-source voltage of the transistor, μn is the electron mobility, Cox is the gate oxide layer thickness, W and L are the width and length of the transistor respectively.

[0097] At the same time, the capacitive coupling path added to Mc0 causes the source voltage of Mc0 to decrease and the gate voltage to increase. Therefore, Mc0 changes from nA level current to uA level at the moment when Vgs increases and the copy current increases. The large current transmitted charges the power tube, thereby enhancing the transient response and reducing the undershoot voltage. In the switching process from heavy load to light load, the source end of Mb2 connected to the MI2 bias voltage increases the output voltage, causing the error amplifier output voltage to increase, the source voltage of Mb2 to increase, the gate voltage of MI2 to increase, the consumed current to decrease, and the excess current all flows through Mc13. At the same time, the capacitive coupling path added to Mc13 causes the source voltage of Mc13 to increase, the gate voltage to decrease, and the current copied through Mc12 to increase. Therefore, Mc13 changes from nA level current to uA level at the moment when Vgs decreases and the copy current increases. The final changed current passes through Mc3 to discharge the power tube and consume excess current. Thereby enhancing the transient response and reducing the overshoot voltage.

[0098] The performance of the LDO chip without external capacitors of the present application is exemplarily described below with reference to a specific example.

[0099] The simulation model of the LDO chip without external capacitors in this application was constructed using circuit simulation software such as Proteus and Multisim, and relevant experiments were performed. The PSR curve diagram obtained is shown in the figure below: Figure 5 As shown in the figure, the horizontal axis represents the frequency Freq, the unit is Hertz (Hz), the vertical axis represents the value of PSR, the unit is decibel (dB), the dotted line in the figure is the PSR curve of the LDO chip without PSR enhancement (ie, without feedforward circuit), and the solid line is the PSR curve with PSR enhancement (ie, the LDO chip of the present application).

[0100] The transient results of 1us are as follows Figure 6 As shown in the figure, the horizontal axis represents time (time), the unit is microsecond (us), Figure 6 (a) is a load current curve diagram of the LDO chip of the present application, where the vertical axis represents the current in milliamperes (mA). Figure 6 (b) is a transient curve diagram of the output voltage of the LDO chip of the present application, wherein the vertical axis represents the output voltage in volts (V), and the two curves are the output voltage transient curves of the LDO chip of the present application (with transient enhancement) and the LDO chip without transient enhancement, respectively.

[0101] The transient results of 100ns are as follows: Figure 7 As shown in the figure, the horizontal axis represents time (time), the unit is microsecond (us), Figure 7 (a) is a load current curve diagram of the LDO chip of the present application, where the vertical axis represents the current in milliamperes (mA). Figure 7 (b) is a transient curve diagram of the output voltage of the LDO chip of the present application, wherein the vertical axis represents the output voltage in volts (V), and the two curves are the output voltage transient curves of the LDO chip of the present application (with transient enhancement) and the LDO chip without transient enhancement, respectively.

[0102] The transient results of 500ns are as follows: Figure 8 As shown in the figure, the horizontal axis represents time (time), the unit is microsecond (us), Figure 8 (a) is a load current curve diagram of the LDO chip of the present application, where the vertical axis represents the current in milliamperes (mA). Figure 8 (b) is a transient curve diagram of the output voltage of the LDO chip of the present application, wherein the vertical axis represents the output voltage in volts (V), and the two curves are the output voltage transient curves of the LDO chip of the present application (with transient enhancement) and the LDO chip without transient enhancement, respectively.

[0103] It can be seen that the LDO chip of the present application realizes rapid conversion between voltage and current during load switching, significantly improves the gate conversion rate, and thus enhances the transient response effect. This design significantly reduces the overcharge and undercharge voltage values ​​and shortens the recovery time. Within the load switching time of 100ns, 500ns to 1us, the LDO chip exhibits excellent transient performance, especially when the load is switched at 100ns, the overshoot and undershoot voltages are reduced by 113mV and 107mV respectively, and the transient response performance is improved by 40%. In addition, the phase margin is always maintained above 45° to ensure the stability of the circuit.

[0104] In terms of PSR ripple elimination, the present application introduces a feedforward circuit between the gate of the power transistor (MP) and the power rail (VDD). The feedforward circuit is superimposed with the main path of the voltage ripple in opposite phase, effectively suppressing the ripple. By cooperating with the transconductance and channel resistance in the MP tube, the design realizes power supply differential input in the MP, thereby enhancing the PSR performance of the entire LDO chip. The overall PSR enhancement before 1MHz frequency is achieved, and in some embodiments, the enhancement effect can reach 41dB.

[0105] In some embodiments, the LDO chip of the present application can be mixed with a DCDC circuit to form a voltage stabilizing circuit, such as Fig. 9 As shown, the voltage stabilizing circuit includes a first switch, a second switch, a third switch, a fourth switch, a DCDC circuit, an LDO circuit (i.e., the LDO chip of the present application), and a comparator. The second end of the first switch and the first end of the second switch are both connected to the input voltage (Vcc), the second end of the first switch is respectively connected to the common end of the third switch and the first end of the DCDC circuit, the normally open end of the third switch is respectively connected to the normally open end of the fourth switch and the output end of the comparator, the normally closed end of the third switch is respectively connected to the second end of the DCDC circuit, the normally closed end of the fourth switch, and the positive input end of the comparator, the second end of the second switch is respectively connected to the common end of the fourth switch and the first end of the LDO circuit, the second end of the LDO circuit is connected to the output voltage (Vout), and the reverse input end of the comparator is connected to the reference voltage (VRFF_3V).

[0106] In the above circuit, the first switch is only turned on when the voltage is greater than 3V, the second switch is only turned on when the voltage is less than or equal to 3V, the third switch is connected to the normally closed end when the voltage is high, and the fourth switch is connected to the normally closed end when the voltage is low. After comparing and judging the voltage, the final output voltage passes through the LDO, but the voltage reduction range of the LDO is below 3V, so the voltage greater than 3V will produce a different duty to return to the initial voltage. Using a buck-type dcdc, the relationship between the output voltage and the input voltage under continuous clock pulses (CCM mode) is vout / vin=duty, and the duty is the output of the LDO after the duty cycle is gradually reduced to below 3V.

[0107] The above voltage stabilization circuit can adapt to a wider input voltage range through the dual configuration of DCDC-LDO and direct LDO path. The voltage after DC-DC processing enters the LDO circuit and adopts a simple feedforward circuit for further ripple elimination. It has high stability and will not affect the LDO main loop function to ensure the clean and stable output voltage.

[0108] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0109] The above is a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. An LDO chip without external capacitors, characterized in that: The LDO chip includes an error amplifier, a buffer circuit, an overshoot and undershoot suppression circuit, a power tube, a feedback circuit, and a feedforward circuit; The positive input terminal of the error amplifier is connected to the feedback terminal of the feedback circuit, the reverse input terminal of the error amplifier is connected to the first reference voltage, the output terminal of the error amplifier is connected to the input terminal of the buffer circuit, the output terminal of the buffer circuit is respectively connected to the input terminal of the overshoot and undershoot suppression circuit, the output terminal of the feedforward circuit, and the gate of the power tube, the source of the power tube is respectively connected to the input power supply and the input terminal of the feedforward circuit, and the drain of the power tube is respectively connected to the output terminal of the overshoot and undershoot suppression circuit, the input terminal of the feedback circuit, and the output terminal of the LDO chip.

2. The LDO chip according to claim 1, characterized in that: The feedforward circuit comprises an operational amplifier, a summing amplifier, an enhanced capacitor, and an enhanced resistor, wherein the first end of the enhanced capacitor is the input end of the feedforward circuit, and the output end of the summing amplifier is the output end of the feedforward circuit; The first end of the enhancement resistor is connected to the second reference voltage, the second end of the enhancement resistor is respectively connected to the second end of the enhancement capacitor and the positive input end of the operational amplifier, and the output end of the operational amplifier is respectively connected to the reverse input end of the operational amplifier and the input end of the summing amplifier.

3. The LDO chip according to claim 2, characterized in that: The operational amplifier includes a first operational transistor, a second operational transistor, a third operational transistor, a fourth operational transistor, and a fifth operational transistor; The gate of the third operational transistor is the positive input terminal of the operational amplifier, the gate of the fourth operational transistor is the negative input terminal of the operational amplifier, and the drain of the fourth operational transistor and the drain of the second operational transistor are both output terminals of the operational amplifier; The source of the first operational transistor is connected to the source of the second operational transistor, the gate of the first operational transistor is respectively connected to the gate of the second operational transistor, the drain of the second operational transistor, and the drain of the third operational transistor, the source of the third operational transistor is respectively connected to the source of the fourth operational transistor and the drain of the fifth operational transistor, the source of the fifth operational transistor is connected to the ground terminal, and the gate of the fifth operational transistor is connected to a reverse control voltage; The first operational transistor, the second operational transistor, the third operational transistor, the fourth operational transistor and the fifth operational transistor are all P-type MOS transistors.

4. The LDO chip according to claim 1, characterized in that: The overshoot and undershoot suppression circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, an initial transistor, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; The first end of the first capacitor, the second end of the second capacitor, the first end of the third capacitor, and the second end of the fourth capacitor are all output ends of the overshoot and undershoot suppression circuit, and the gate of the fourteenth transistor and the gate of the fifteenth transistor are both input ends of the overshoot and undershoot suppression circuit; The second end of the first capacitor is connected to the source of the initial transistor and the first end of the first resistor respectively, the drain of the initial transistor is connected to the drain of the thirteenth transistor, the gate of the initial transistor is connected to the gate of the sixth transistor, the drain of the fourteenth transistor, and the drain of the fifth transistor respectively, the second end of the first resistor is connected to the source of the first transistor, the source of the thirteenth transistor, and the source of the sixth transistor respectively, the drain of the first transistor is connected to the drain of the second transistor and the gate of the fifth transistor respectively, the gate of the second transistor is connected to the gate of the fifth transistor, the source of the second transistor is connected to the drain of the third transistor, the gate of the third transistor, the gate of the fourth transistor, and the second end of the third capacitor respectively, the source of the third transistor is connected to the source of the fourth transistor, the drain of the fourth transistor is connected to the source of the fifth transistor, and the drain of the fifth transistor is connected to the drain of the sixth transistor; The first end of the second capacitor is connected to the gate of the ninth transistor and the gate of the tenth transistor respectively, the source of the tenth transistor is connected to the source of the ninth transistor, the drain of the tenth transistor is connected to the source of the eleventh transistor, the drain of the ninth transistor is connected to the gate of the ninth transistor and the source of the eighth transistor respectively, the gate of the eighth transistor is connected to the gate of the eleventh transistor, the drain of the seventh transistor and the drain of the eighth transistor respectively, the drain of the tenth transistor is connected to the source of the eleventh transistor, the drain of the eleventh transistor is connected to the gate of the thirteenth transistor, the drain of the twelfth transistor, the gate of the twelfth transistor and the drain of the fifteenth transistor respectively, the source of the twelfth transistor is connected to the source of the fifteenth transistor, the source of the seventh transistor and the first end of the second resistor respectively, the first end of the second resistor is connected to the source of the thirteenth transistor and the first end of the fourth capacitor respectively, the gate of the seventh transistor is connected to the forward control voltage, and the gate of the first transistor is connected to the reverse control voltage.

5. The LDO chip according to claim 4, characterized in that: The initial transistor, the first transistor, the sixth transistor, the fourteenth transistor, the eleventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all P-type MOS transistors; The second transistor, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, the twelfth transistor, the thirteenth transistor, and the fifteenth transistor are all N-type MOS transistors.

6. The LDO chip according to claim 1, characterized in that: The feedback circuit includes a first feedback resistor, a second feedback resistor, and a feedback capacitor; The first end of the first feedback resistor and the first end of the feedback capacitor are both input ends of the feedback circuit, the second end of the first feedback resistor and the first end of the second feedback resistor are both feedback ends of the feedback circuit, and the second end of the second feedback resistor is respectively connected to the second end of the feedback capacitor and the ground end.

7. The LDO chip according to claim 1, characterized in that: The error amplifier includes a first error transistor, a second error transistor, a third error transistor, a fourth error transistor, a fifth error transistor, a sixth error transistor, a seventh error transistor, an eighth error transistor, a ninth error transistor, and a tenth error transistor; The gate of the second error transistor is the positive input terminal of the error amplifier, the gate of the third error transistor is the negative input terminal of the error amplifier, and the drain of the seventh error transistor and the drain of the ninth error transistor are both output terminals of the error amplifier; The gate of the first error transistor is connected to a forward control voltage, the source of the first error transistor is connected to the source of the tenth error transistor and the source of the eleventh error transistor, the drain of the first error transistor is connected to the source of the second error transistor and the source of the third error transistor, the drain of the second error transistor is connected to the drain of the fourth error transistor and the source of the sixth error transistor, the drain of the third error transistor is connected to the drain of the fifth error transistor and the source of the seventh error transistor, and the source of the fourth transistor is connected to the source of the fifth transistor. The fourth error transistor and the fifth error transistor are both connected to a first bias voltage, the gate of the sixth error transistor and the gate of the seventh error transistor are both connected to a second bias voltage, the drain of the sixth error transistor is respectively connected to the drain of the eighth error transistor, the gate of the tenth error transistor, and the gate of the eleventh error transistor, the gate of the eighth error transistor and the gate of the ninth error transistor are both connected to a third bias voltage, the source of the eighth error transistor is connected to the drain of the tenth error transistor, and the source of the ninth error transistor is connected to the drain of the eleventh error transistor.

8. The LDO chip according to claim 7, characterized in that: The first error transistor, the second error transistor, the third error transistor, the eighth error transistor, the ninth error transistor, the tenth error transistor, and the eleventh error transistor are all N-type MOS transistors; The fourth error transistor, the fifth error transistor, the sixth error transistor, and the seventh error transistor are all P-type MOS transistors.

9. The LDO chip according to claim 1, characterized in that: The buffer circuit includes a first push-pull transistor, a second push-pull transistor, a third push-pull transistor, a fourth push-pull transistor, a fifth push-pull transistor, a sixth push-pull transistor, a seventh push-pull transistor, an eighth push-pull transistor, a ninth push-pull transistor, and a tenth push-pull transistor; The gate of the second push-pull transistor and the gate of the sixth push-pull transistor are both input terminals of the buffer circuit, and the drain of the eighth push-pull transistor and the source of the ninth push-pull transistor are both output terminals of the buffer circuit; The gate of the first push-pull transistor is connected to a forward control voltage, the source of the first push-pull transistor is respectively connected to the source of the seventh push-pull transistor, the drain of the fifth push-pull transistor, and the source of the eighth push-pull transistor, the drain of the first push-pull transistor is respectively connected to the source of the second push-pull transistor and the gate of the fifth push-pull transistor, the drain of the second push-pull transistor is respectively connected to the drain of the third push-pull transistor, the gate of the third push-pull transistor, and the gate of the fourth push-pull transistor, the source of the third push-pull transistor is respectively connected to the source of the tenth push-pull transistor, The source of the fourth push-pull transistor and the drain of the ninth push-pull transistor are connected, the drain of the tenth push-pull transistor is respectively connected to the source of the sixth push-pull transistor and the gate of the ninth push-pull transistor, the gate of the tenth push-pull transistor is connected to a reverse control voltage, the drain of the fourth push-pull transistor is respectively connected to the source of the fifth push-pull transistor, the drain of the eighth push-pull transistor, and the source of the ninth push-pull transistor, and the drain of the sixth push-pull transistor is respectively connected to the drain of the seventh push-pull transistor, the gate of the sixth push-pull transistor, and the gate of the eighth push-pull transistor.

10. The LDO chip according to claim 9, characterized in that: The first push-pull transistor, the second push-pull transistor, the seventh push-pull transistor, the eighth push-pull transistor, and the ninth push-pull transistor are all N-type MOS transistors; The third push-pull transistor, the fourth push-pull transistor, the fifth push-pull transistor, the sixth push-pull transistor, and the tenth push-pull transistor are all P-type MOS transistors.

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