Complex programmable logic device upgrading method and device, equipment and storage medium
By assigning multiplexed I/O feature control bits during the initialization process after power-on in complex programmable logic devices, the problem of multiplexed I/O resources and logical resources cannot be taken into account, and the implementation is achieved without consuming resources Device upgrades have improved resource utilization.
Patent Information
- Application Number
- CN202411220316.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2025-01-10
AI Technical Summary
During the upgrade process of existing complex programmable logic devices, multiplexing I/O resources and logical resources cannot be taken into account, resulting in waste or excessive consumption of resources.
During the initialization process after power-on in complex programmable logic devices, multiplexed I/O feature control bits are assigned, including configuration mode feature control bits and user mode feature control bits, through which multiplexed I is set in different modes Functional status of /O to achieve data update without consuming logical resources or losing I/O resources.
Without consuming more logic resources and losing multiplexed I/O resources, the upgrade of complex programmable logic devices is achieved, and the utilization rate of I/O resources is improved.
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Figure CN119292620A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit technology, and in particular to a complex programmable logic device upgrading method, device, equipment and storage medium. Background Art
[0002] CPLD (Complex Programmable Logic Device) has the advantages of small size, low power consumption and fast power-on startup. In the development and production of products, users usually pre-burn firmware with certain functions into the embedded Flash of CPLD, and the CPLD will have the corresponding functions after restarting; in the after-sales upgrade and maintenance process of the product, users can re-burn the embedded Flash of CPLD through the upgrade interface reserved by CPLD to give CPLD new functions to realize the upgrade of CPLD. CPLD has many multiplexed I / O (Input / Output), which can be used as ordinary pins and special pins for burning embedded Flash. At present, there are two main ways to burn the embedded Flash of CPLD. One is to operate through multiplexing I / O; the other is to access the embedded Flash through the dedicated bus inside the CPLD. The first method will make the multiplexing I / O used for burning the embedded Flash no longer available to the user, thus losing the multiplexing I / O resources; the second method requires calling the internal bus for accessing the embedded Flash, which consumes more logic resources. Summary of the invention
[0003] The purpose of the present invention is to provide a complex programmable logic device upgrade method, device, equipment and storage medium to solve the technical problem in the prior art that I / O resources and logic resources cannot be reused when complex programmable logic devices are upgraded.
[0004] The technical solution of the present invention is as follows, which provides a complex programmable logic device upgrade method, comprising:
[0005] During the initialization process after the complex programmable logic device is powered on, the multiplexed I / O is provided with the feature control bit, wherein the feature control bit includes a configuration mode feature control bit and a user mode feature control bit;
[0006] After the initialization of the complex programmable logic device is completed, the multiplexed I / O selects the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and uses the multiplexed I / O to update the data of the embedded Flash of the complex programmable logic device;
[0007] When the complex programmable logic device is in user mode, the multiplexed I / O selects the user mode feature control bit to set the functional state of the multiplexed I / O in the user mode.
[0008] Furthermore, the complex programmable logic device upgrade method further includes:
[0009] When the complex programmable logic device is in user mode, the complex programmable logic device is reinitialized. After the complex programmable logic device is initialized, the multiplexed I / O selects the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and uses the multiplexed I / O to update the data of the embedded Flash.
[0010] Further, when the complex programmable logic device is in user mode, the complex programmable logic device is reinitialized, and after the initialization of the complex programmable logic device is completed, the multiplexed I / O is made to select the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and the embedded Flash is updated with data using the multiplexed I / O, including:
[0011] When the complex programmable logic device is in user mode, the INIT pin of the complex programmable logic device is pulled low, and the complex programmable logic device is reinitialized. After the initialization of the complex programmable logic device is completed, the multiplexed I / O selects the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and the embedded Flash is updated with data using the multiplexed I / O, and the INIT pin is released.
[0012] Further, reinitializing the complex programmable logic device includes: reinitializing the complex programmable logic device by pulling down a PROGRAM pin of the complex programmable logic device.
[0013] Further, the embedded Flash is updated with data by using the multiplexed I / O to release the INIT pin, including:
[0014] The embedded Flash is updated with data by using the multiplexed I / O to obtain updated data, and the INIT pin is released to load the updated data into the embedded Flash.
[0015] Furthermore, the multiplexed I / O has characteristic control bits, including:
[0016] The feature control bit of the multiplexed I / O in the embedded Flash is obtained, and the feature control bit is assigned to a working state configuration signal, so that the multiplexed I / O has the feature control bit through the working state configuration signal.
[0017] Further, the acquiring of the characteristic control bit of the multiplexed I / O in the embedded Flash includes: enabling the configuration control system to acquire the characteristic control bit of the multiplexed I / O in the embedded Flash.
[0018] Another technical solution of the present invention is as follows: a complex programmable logic device upgrade device is also provided, including a feature control bit assignment module, a data update module and a function state setting module;
[0019] The feature control bit assignment module is used to enable the multiplexed I / O to have a feature control bit during the initialization process after the complex programmable logic device is powered on, and the feature control bit includes a configuration mode feature control bit and a user mode feature control bit;
[0020] The data update module is used to enable the multiplexed I / O to select the configuration mode feature control bit after the initialization of the complex programmable logic device is completed, so as to set the functional state of the multiplexed I / O in the configuration mode, and use the multiplexed I / O to update the data of the embedded Flash of the complex programmable logic device;
[0021] The functional state setting module is used to enable the multiplexed I / O to select the user mode feature control bit when the complex programmable logic device is in user mode, so as to set the functional state of the multiplexed I / O in user mode.
[0022] Another technical solution of the present invention is as follows: an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program that can be executed by the processor, and when the processor executes the computer program, the complex programmable logic device upgrading method as described in any of the above technical solutions is implemented.
[0023] Another technical solution of the present invention is as follows: a computer-readable storage medium is also provided, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the complex programmable logic device upgrading method as described in any of the above technical solutions is implemented.
[0024] The beneficial effects of the present invention are as follows: during the initialization process after a complex programmable logic device is powered on, the multiplexed I / O is provided with a feature control bit, and the feature control bit includes a configuration mode feature control bit and a user mode feature control bit; after the initialization of the complex programmable logic device is completed, the multiplexed I / O selects the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and uses the multiplexed I / O to update data on the embedded Flash of the complex programmable logic device; when the complex programmable logic device is in user mode, the multiplexed I / O selects the user mode feature control bit to set the functional state of the multiplexed I / O in the user mode; through the above technical solution, the complex programmable logic device can be upgraded without consuming more logic resources and without losing multiplexed I / O resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 A schematic diagram of a flow chart of a complex programmable logic device upgrade method provided by an embodiment of the present invention;
[0026] Figure 2 A startup timing diagram of a complex programmable logic device provided by an embodiment of the present invention;
[0027] Figure 3 A logic block diagram of a complex programmable logic device upgrade provided by an embodiment of the present invention;
[0028] Figure 4 A schematic diagram of characteristic control bits of an SPI interface provided by an embodiment of the present invention;
[0029] Figure 5 A multiplexed I / O internal function block diagram provided by an embodiment of the present invention;
[0030] Figure 6 A timing diagram for online upgrading of a complex programmable logic device provided by an embodiment of the present invention;
[0031] Figure 7 A schematic diagram of the structure of a complex programmable logic device upgrade device provided by an embodiment of the present invention;
[0032] Figure 8 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention;
[0033] Fig. 9 A schematic diagram of the structure of a computer-readable storage medium provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0035] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0036] Figure 1 FIG. 1 is a flow chart of a complex programmable logic device upgrade method according to an embodiment of the present invention. It should be noted that the complex programmable logic device upgrade method according to the present invention is not limited to the above method if substantially the same results are achieved. Figure 1 The process sequence shown is limited. Figure 1 As shown, the complex programmable logic device upgrade method mainly includes the following steps:
[0037] S101, during the initialization process after the complex programmable logic device is powered on, enabling the multiplexed I / O to have a feature control bit, wherein the feature control bit includes a configuration mode feature control bit and a user mode feature control bit;
[0038] In a specific embodiment, the startup timing diagram of the complex programmable logic device is as follows: Figure 2 As shown, the startup process of the complex programmable logic device includes power-on, initialization, loading data stream, wake-up and user mode in sequence. Figure 2 In the figure, VCC represents the power-on voltage, PROGRAM is the configuration reset I / O (pin), which can be used for input, and can also be used to clear the configuration memory and restart the configuration process; INIT is the configuration handshake I / O (pin), which can be open-drain, can be used as an input or output pin, can be used as an indication pin for the initialization status of a complex programmable logic device, and can also control the delay configuration; DONE is also a configuration handshake I / O, which can be open-drain, can be used as an input or output pin, and can also be used as an indication pin for configuration completion.
[0039] In some embodiments, enabling the multiplexed I / O to have a feature control bit includes:
[0040] The feature control bit of the multiplexed I / O in the embedded Flash is obtained, and the feature control bit is assigned to a working state configuration signal, so that the multiplexed I / O has the feature control bit through the working state configuration signal.
[0041] In a specific embodiment, after the complex programmable logic device (chip) is powered on, during the initialization process, the feature control bits of the multiplexed I / O stored in the embedded Flash of the complex programmable logic device are read. In addition to storing the feature control bits of the multiplexed I / O, the embedded Flash can also store functional data (data stream).
[0042] As an example, the SPI (Serial Peripheral The interface may include 4 multiplexed I / Os, each multiplexed I / O has a 2-bit feature control bit, and the 2-bit feature control bit includes a 1-bit configuration mode feature control bit (for example, 0) and a 1-bit user mode feature control bit (for example, 1), which respectively control the functional state of the multiplexed I / O in the configuration mode and the user mode; when the multiplexed I / O selects the user mode feature control bit, even if the multiplexed I / O selects 1, the functional state of the multiplexed I / O in the user mode can be set, that is, the functional state of the multiplexed I / O is set to a common pin (common I / O pin), the multiplexed I / O can be connected to a programmable logic resource, and its input and output can be controlled by the user; when the multiplexed I / O selects the configuration mode feature control bit, even if the multiplexed I / O selects 0, the functional state of the multiplexed I / O in the configuration mode can be set, that is, the functional state of the multiplexed I / O is set to a dedicated programming pin (dedicated programming I / O pin), and the corresponding input or output remains unchanged.
[0043] In some embodiments, the acquiring of the feature control bit of the multiplexed I / O in the embedded Flash includes: enabling the configuration control system to acquire the feature control bit of the multiplexed I / O in the embedded Flash.
[0044] In a specific embodiment, after the configuration control system (CCS) obtains the characteristic control bit of the multiplexed I / O from the embedded Flash of the complex programmable logic device, it assigns it to the working state configuration signal, and the working state configuration signal enables the multiplexed I / O to have the characteristic control bit. It should be noted that the signal name of the working state configuration signal can be cfgmode, and its bit width is 2. It is an internal signal of the complex programmable logic device and can be used to configure the functional state of the multiplexed I / O in the configuration mode and the user mode. The working state configuration signal can be expressed as cfgmode[1:0], where cfgmode[0] controls the functional state of the multiplexed I / O in the configuration mode, and cfgmode[1] controls the functional state of the multiplexed I / O in the user mode.
[0045] In a specific embodiment, a logic block diagram of a complex programmable logic device upgrade, such as Figure 3 As shown, Figure 3 In the example, the bit width of the CCLK signal is 1. The CCLK pin of the embedded Flash can be used as an external interface input or as a clock input pin of the SPI interface (slave SPI interface); the bit width of the SN signal is 1. The SN pin can be used as an external interface input or as a chip select input pin of the SPI interface; the bit width of the SI signal is 1. The SI pin can be used as an external interface input or as a data input pin of the SPI interface; the bit width of the SO signal is 1. The SO pin can be used as an external interface output or as a data output pin of the SPI interface.
[0046] In a specific embodiment, the characteristic control bit diagram of the SPI interface is as follows: Figure 4 As shown, each multiplexed I / O has a 2-bit feature control bit, except Figure 4 The four multiplexed I / Os shown in the figure, other multiplexed I / Os can also have feature control bits. Figure 4 Bit[n] represents a 1-bit feature control bit (configuration mode feature control bit or user mode feature control bit), and 0 / 1 represents the value of the corresponding feature control bit.
[0047] S102, after the initialization of the complex programmable logic device is completed, the multiplexed I / O selects the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and uses the multiplexed I / O to update the data of the embedded Flash of the complex programmable logic device;
[0048] In a specific embodiment, the internal functional block diagram of the multiplexed I / O is as follows: Figure 5 As shown, Figure 5PAD in the middle represents multiplexed I / O. When the working state configuration signal makes the multiplexed I / O have a characteristic control bit, the functional state of the multiplexed I / O can be represented by a selector. The multiplexed I / O selects the configuration mode characteristic control bit 0, and then sets the functional state of the multiplexed I / O in the configuration mode, and sets the functional state of the multiplexed I / O to a dedicated pin for burning. At this time, the multiplexed I / O can be used as a dedicated pin for burning. The embedded Flash of the complex programmable logic device is updated with data by using the multiplexed I / O, and the updated data is loaded, so that the upgrade of the complex programmable logic device is realized.
[0049] S103, when the complex programmable logic device is in user mode, enabling the multiplexed I / O to select a user mode feature control bit to set a functional state of the multiplexed I / O in the user mode.
[0050] According to an embodiment of the present invention, during the initialization process after a complex programmable logic device is powered on, a multiplexed I / O is provided with a feature control bit, wherein the feature control bit includes a configuration mode feature control bit and a user mode feature control bit; after the initialization of the complex programmable logic device is completed, the multiplexed I / O is enabled to select the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and the multiplexed I / O is used to update data of an embedded Flash of the complex programmable logic device; when the complex programmable logic device is in user mode, the multiplexed I / O is enabled to select the user mode feature control bit to set the functional state of the multiplexed I / O in the user mode; by setting the functional state of the multiplexed I / O in the configuration mode, the embedded Flash is updated with the multiplexed I / O, and after the data update is completed, the functional state of the multiplexed I / O in the user mode is set; and the complex programmable logic device can be upgraded without consuming more logic resources or losing multiplexed I / O resources.
[0051] In a specific embodiment, Figure 5 As shown, when the working status configuration signal enables the multiplexed I / O to have a feature control bit, the functional state of the multiplexed I / O can be represented by a selector, and the multiplexed I / O selects the user mode feature control bit 1, so as to set the functional state of the multiplexed I / O in user mode, and set the functional state of the multiplexed I / O to a normal pin. At this time, the multiplexed I / O can be used as a normal pin.
[0052] In some embodiments, the complex programmable logic device upgrade method further includes:
[0053] When the complex programmable logic device is in user mode, the complex programmable logic device is reinitialized. After the complex programmable logic device is initialized, the multiplexed I / O selects the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and uses the multiplexed I / O to update the data of the embedded Flash.
[0054] In a specific embodiment, online upgrade is a common demand of users who use complex programmable logic devices. Online upgrade means burning the embedded Flash during the operation of the complex programmable logic device. In order to save I / O and not consume logic resources, the four multiplexed I / Os from the SPI interface can be used to burn the embedded Flash and can also be used as ordinary pins for users. It is necessary to configure the multiplexed I / O functional status in stages, as well as the delayed configuration function of the INIT signal. When the complex programmable logic device is in user mode, the complex programmable logic device is reinitialized. After the initialization is completed, the configuration control system can be prevented from automatically reading data (functional data) from the embedded Flash and loading the data stream, so that the multiplexed I / O selects the configuration mode feature control bit to set the functional status of the multiplexed I / O in the configuration mode, and the embedded Flash is updated using the multiplexed I / O.
[0055] In some embodiments, when the complex programmable logic device is in user mode, the complex programmable logic device is reinitialized, and after the complex programmable logic device is initialized, the multiplexed I / O selects the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and the embedded Flash is updated with data using the multiplexed I / O, including:
[0056] When the complex programmable logic device is in user mode, the INIT pin of the complex programmable logic device is pulled low, and the complex programmable logic device is reinitialized. After the initialization of the complex programmable logic device is completed, the multiplexed I / O selects the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and the embedded Flash is updated with data using the multiplexed I / O, and the INIT pin is released.
[0057] In a specific embodiment, when the complex programmable logic device is in user mode, the complex programmable logic device can be reinitialized by pulling down the INIT signal (the signal of the INIT pin). When the initialization is completed, because the INIT signal was previously pulled down, the configuration control system can be prevented from automatically reading data (functional data) from the embedded Flash and loading the data stream, so that the multiplexed I / O (from the SPI interface) selects the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode. The multiplexed I / O can be used to update the embedded Flash data. After the embedded Flash data is updated, the INIT signal is pulled high (the INIT pin is released), and the complex programmable logic device re-enters the user mode.
[0058] In some embodiments, reinitializing the complex programmable logic device includes: reinitializing the complex programmable logic device by pulling down a PROGRAM pin of the complex programmable logic device.
[0059] In a specific embodiment, when the complex programmable logic device is in user mode, the complex programmable logic device can be reinitialized by pulling down the INIT signal (the signal of the INIT pin) and by pulling down the PROGRAM pin (the signal of the PROGRAM pin) of the complex programmable logic device.
[0060] In some embodiments, updating the embedded Flash with data by using the multiplexed I / O and releasing the INIT pin includes:
[0061] The embedded Flash is updated with data by using the multiplexed I / O to obtain updated data, and the INIT pin is released to load the updated data into the embedded Flash.
[0062] In a specific embodiment, the embedded Flash is loaded with updated data. After the updated data is loaded, the complex programmable logic device re-enters the user mode. The timing diagram of the online upgrade of the complex programmable logic device is as follows: Figure 6 As shown, Figure 6 Where clk is the clock signal, Trstn is the minimum reset time, which is related to the characteristics of complex programmable logic devices, Tpl is the initialization time, and Tprogram is the time of the configuration mode.
[0063] The complex programmable logic device upgrade method provided by the embodiment of the present invention is to enable the multiplexed I / O to have a feature control bit during the initialization process after the complex programmable logic device is powered on, and the feature control bit includes a configuration mode feature control bit and a user mode feature control bit; after the initialization of the complex programmable logic device is completed, the multiplexed I / O is enabled to select the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and the multiplexed I / O is used to update the data of the embedded Flash of the complex programmable logic device; when the complex programmable logic device is in the user mode, the multiplexed I / O is enabled to select the user mode feature control bit to set the functional state of the multiplexed I / O in the user mode; by setting the functional state of the multiplexed I / O in the configuration mode, the embedded Flash is updated with the multiplexed I / O, and after the data update is completed, the functional state of the multiplexed I / O in the user mode is set; the complex programmable logic device upgrade can be realized without consuming more logic resources and without losing multiplexed I / O resources.
[0064] In the complex programmable logic device upgrade method provided by the embodiment of the present invention, the reused I / O can be used as a configuration-related dedicated pin or as an ordinary pin. Whether it is used as a configuration-related dedicated pin or as an ordinary pin depends on the control of the feature control bit. The feature control bit can be stored in a dedicated space of the embedded Flash. During the power-on initialization process of the complex programmable logic device, the value of the feature control bit will be read from the Flash to configure the functional state (working state) of the reused I / O. After the initialization is completed, the functional state of the reused I / O is determined. After the initialization is completed, the user can rewrite the feature control bit as needed through the reused I / O that can access the embedded Flash.
[0065] The complex programmable logic device upgrade method provided by the embodiment of the present invention configures the feature control bit when the complex programmable logic device completes initialization and has not entered the user mode, so that the multiplexed I / O is used as a dedicated pin for burning the embedded Flash in the configuration mode. After the complex programmable logic device enters the user mode, the multiplexed I / O becomes a common pin, so that the multiplexed I / O can be used for burning and for users, without losing I / O resources, improving the utilization rate of I / O, and not consuming additional logic resources. When the complex programmable logic device is in the user mode, the INIT pin of the complex programmable logic device is pulled down, and the complex programmable logic device is reinitialized. After the initialization of the complex programmable logic device is completed, the multiplexed I / O selects the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and the embedded Flash is updated with the multiplexed I / O. The INIT pin is released, and the complex programmable logic device re-enters the user mode, so that the online upgrade of the complex programmable logic device can be realized, and the I / O resources are also not lost, and the additional logic resources are not consumed.
[0066] Based on the above complex programmable logic device upgrade method, an embodiment of the present invention provides a complex programmable logic device upgrade device, and its structural diagram is as follows: Figure 7 As shown, the complex programmable logic device upgrade device 70 includes a feature control bit assignment module 71, a data update module 72 and a function state setting module 73;
[0067] The feature control bit assignment module 71 is used to enable the multiplexed I / O to have a feature control bit during the initialization process after the complex programmable logic device is powered on, and the feature control bit includes a configuration mode feature control bit and a user mode feature control bit;
[0068] The data update module 72 is used to enable the multiplexed I / O to select the configuration mode feature control bit after the initialization of the complex programmable logic device is completed, so as to set the functional state of the multiplexed I / O in the configuration mode, and use the multiplexed I / O to update the data of the embedded Flash of the complex programmable logic device;
[0069] The functional state setting module 73 is used to enable the multiplexed I / O to select the user mode feature control bit when the complex programmable logic device is in user mode, so as to set the functional state of the multiplexed I / O in user mode.
[0070] For other details about how the above-mentioned technical solutions are implemented by each unit in the above-mentioned complex programmable logic device upgrading device 70, reference may be made to the description of the complex programmable logic device upgrading method provided in the above-mentioned invention embodiment, which will not be repeated here.
[0071] Based on the above complex programmable logic device upgrade method, an embodiment of the present invention further provides an electronic device, a structural diagram of which is as follows: Figure 8 As shown, the electronic device 80 includes a processor 81 and a memory 82 coupled to the processor 81. The memory 82 stores a computer program, and when the computer program is executed by the processor 81, the processor 81 executes the steps of the complex programmable logic device upgrade method in the above embodiment.
[0072] For other details about the implementation of the above technical solution by the processor 81 in the above electronic device 80, please refer to the description of the complex programmable logic device upgrading method provided in the above invention embodiment, which will not be repeated here.
[0073] Among them, the processor 81 can also be called a CPU (Central Processing Unit), and the processor 81 may be an integrated circuit chip with signal processing capabilities; the processor 81 can also be a general-purpose processor, DSP (Digital Signal Process), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, among which the general-purpose processor can be a microprocessor or the processor 81 can also be any conventional processor, etc.
[0074] The embodiment of the present invention further provides a computer-readable storage medium, a schematic diagram of which is shown in FIG. Fig. 9 As shown, a readable computer program 91 is stored on the storage medium 90; wherein, the computer program 91 can be stored in the storage medium 90 in the form of a software product, including several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium 90 includes: a U disk, a mobile hard disk, a magnetic disk or an optical disk, a ROM (Read-Only Memory), a RAM (Random Access Memory), and other media that can store program codes, or a terminal device such as a computer, a server, a mobile phone, and a tablet.
[0075] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.
[0076] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0077] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium.
[0078] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.
[0079] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, a computer, a server, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or a data center that includes one or more available media integrations. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.
[0080] The technical solution provided by the present application is introduced in detail above. The principles and implementation methods of the present application are explained by using specific examples in the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
[0081] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.
[0082] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices and computer program products according to the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0083] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0084] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0085] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A complex programmable logic device upgrade method, characterized in that: include: During the initialization process after the complex programmable logic device is powered on, the multiplexed I / O is provided with a feature control bit, wherein the feature control bit includes a configuration mode feature control bit and a user mode feature control bit; After the initialization of the complex programmable logic device is completed, the multiplexed I / O selects the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and uses the multiplexed I / O to update the data of the embedded Flash of the complex programmable logic device; When the complex programmable logic device is in user mode, the multiplexed I / O selects the user mode feature control bit to set the functional state of the multiplexed I / O in the user mode.
2. The complex programmable logic device upgrading method according to claim 1, characterized in that: The complex programmable logic device upgrading method further includes: When the complex programmable logic device is in user mode, the complex programmable logic device is reinitialized. After the complex programmable logic device is initialized, the multiplexed I / O selects the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and uses the multiplexed I / O to update the data of the embedded Flash.
3. The complex programmable logic device upgrade method according to claim 2, characterized in that: When the complex programmable logic device is in user mode, the complex programmable logic device is reinitialized, and after the complex programmable logic device is initialized, the multiplexed I / O selects the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and the embedded Flash is updated with data using the multiplexed I / O, including: When the complex programmable logic device is in user mode, the INIT pin of the complex programmable logic device is pulled low, and the complex programmable logic device is reinitialized. After the initialization of the complex programmable logic device is completed, the multiplexed I / O selects the configuration mode feature control bit to set the functional state of the multiplexed I / O in the configuration mode, and the embedded Flash is updated with data using the multiplexed I / O, and the INIT pin is released.
4. The complex programmable logic device upgrading method according to claim 2 or 3, characterized in that: The complex programmable logic device is reinitialized, comprising: reinitializing the complex programmable logic device by pulling down a PROGRAM pin of the complex programmable logic device.
5. The complex programmable logic device upgrade method according to claim 3, characterized in that: The embedded Flash is updated with data by using the multiplexed I / O to release the INIT pin, including: The embedded Flash is updated with data by using the multiplexed I / O to obtain updated data, and the INIT pin is released to load the updated data into the embedded Flash.
6. The complex programmable logic device upgrade method according to claim 1, characterized in that: Enables multiplexed I / O to have feature control bits, including: The feature control bit of the multiplexed I / O in the embedded Flash is obtained, and the feature control bit is assigned to a working state configuration signal, so that the multiplexed I / O has the feature control bit through the working state configuration signal.
7. The complex programmable logic device upgrade method according to claim 6, characterized in that: The method of obtaining the characteristic control bit of the multiplexed I / O in the embedded Flash comprises: enabling the configuration control system to obtain the characteristic control bit of the multiplexed I / O in the embedded Flash.
8. A complex programmable logic device upgrade device, characterized in that: It includes a feature control bit assignment module, a data update module and a function status setting module; The feature control bit assignment module is used to enable the multiplexed I / O to have a feature control bit during the initialization process after the complex programmable logic device is powered on, and the feature control bit includes a configuration mode feature control bit and a user mode feature control bit; The data update module is used to enable the multiplexed I / O to select the configuration mode feature control bit after the initialization of the complex programmable logic device is completed, so as to set the functional state of the multiplexed I / O in the configuration mode, and use the multiplexed I / O to update the data of the embedded Flash of the complex programmable logic device; The functional state setting module is used to enable the multiplexed I / O to select the user mode feature control bit when the complex programmable logic device is in user mode, so as to set the functional state of the multiplexed I / O in user mode.
9. An electronic device, comprising a memory and a processor, wherein the memory stores a computer program executable by the processor, wherein: When the processor executes the computer program, the complex programmable logic device upgrading method as described in any one of claims 1 to 7 is implemented.
10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the complex programmable logic device upgrading method as described in any one of claims 1 to 7 is implemented.