Method and device for controlling multi-core software system, vehicle and storage medium

Abstract

The invention provides a method and device for controlling a multi-core software system, a vehicle and a storage medium. The method comprises the following steps: when a demand for writing first data of a first kernel into a second kernel exists, determining whether the first data is allowed to be written under a current condition based on a read-write flag bit; and when the read-write flag bit indicates that the first data is allowed to be written, interrupting the first operation. This can prevent other kernels from changing the first data and reading the first data from the shared memory region before the write operation, thereby destroying the integrity of the first data. After the first operation is interrupted, backup data of the first data are completely written into the shared memory area, and the read-write flag bit is adjusted to be used for indicating that the first data are allowed to be read. In this way, the second kernel explicitly securely transmits the first data from the first kernel to the shared memory region, and further obtains the first data. According to the method, the data consistency between the cores is ensured through the cross-core data processing module, and logic unexpected execution caused by data read-write conflicts or tampering is avoided.

Description

Technical Field

[0001] The present application relates to the field of vehicle embedded software technology, and more specifically, to a method, device, vehicle and storage medium for controlling a multi-core software system in the field of vehicle embedded software technology. Background Art

[0002] With the development of vehicle embedded software technology and the iteration of application requirements, the computing core architecture tends to be integrated, and the decentralized single functions of each module are developing towards a centralized domain controller mode, thus giving rise to multi-core software systems. The application of multi-core software systems solves the performance bottleneck of single-core processors and reduces the complexity of control interaction caused by independent functions.

[0003] In the related art, in a multi-core software system, when software components of different central processing units (CPU) cores are transmitting data, the multi-core software system will open a shared memory area for them, and the communicating parties complete the data transmission by reading and writing data in the shared memory area. However, due to the task concurrency characteristics of the multi-core software system, the data in the shared memory area may be read and written by software components of different CPU cores at the same time, resulting in data read and write conflicts and inconsistencies.

[0004] Therefore, a method for controlling a multi-core software system is urgently needed to ensure the consistency of data in a shared memory area. Summary of the invention

[0005] The present application provides a method, device, vehicle and storage medium for controlling a multi-core software system. The method can ensure data consistency between cores through a cross-core data processing module, avoiding unexpected logical execution caused by data read and write conflicts or tampering.

[0006] In a first aspect, a method for controlling a multi-core software system is provided, the multi-core software system comprising a first core and a second core, the method being executed by a cross-core data processing module of the first core, the method comprising: in response to a trigger instruction for writing first data of the first core into the second core, obtaining a read-write flag, the read-write flag being used to indicate that writing of the first data is permitted or reading of the first data is permitted; in a case where the read-write flag indicates that writing of the first data is permitted, interrupting a first operation, and writing backup data of the first data into a shared memory area in the multi-core software system, the first operation being an operation of writing second data to the first core and reading the first data from the shared memory area, the second data being associated with the first data; in a case where the backup data is completely written into the shared memory area, adjusting the read-write flag to indicate that reading of the first data is permitted, so that the cross-core data processing module of the second core reads the first data from the shared memory area.

[0007] In the above technical solution, for a multi-core software system including multiple cores (including a first core and a second core), the cross-core data processing module of the first core can respond to the trigger instruction of writing the first data of the first core into the second core, and obtain the read-write flag. That is to say, when there is a need to write the first data of the first core into the second core, it is determined whether the current condition allows the first data to be written based on the read-write flag. When the read-write flag indicates that the first data is allowed to be written, all operations of writing the second data to the first core and reading the first data from the shared memory area are interrupted. This is to prevent the cross-core data processing module of other cores from writing (modifying) the first data in the first core before the write operation, resulting in the consistency of the first data finally written to the second core with the modified first data; and during the write operation, the cross-core data processing module of other cores reads the first data from the shared memory area, resulting in the read first data being the first data that is not completely written, thereby destroying the integrity of the first data. Further, after the first operation is interrupted, the backup data of the first data is completely written into the shared memory area, and the read-write flag is adjusted to indicate that the first data is allowed to be read. In this way, the second kernel can clearly know that the first data has been safely transferred from the first kernel to the shared memory area, and can further obtain the first data. This method uses a "valve-type" design implemented by a cross-core data processing module and a read-write flag to uniformly control the kernel's external data read / write instructions, thereby ensuring data consistency between kernels and avoiding unexpected logical execution caused by data read-write conflicts or tampering. Furthermore, the cross-core data processing module creates a data backup for the first data, so that the original data in the first kernel is not directly operated during the transmission of the first data, which can play a role in data isolation. In addition, compared with direct communication between kernels, this method uses a shared memory area as a data transmission intermediary, and the first data does not have to be frequently transmitted through the processor bus between different kernels, which can reduce the delay in data transmission.

[0008] In combination with the first aspect, in some possible implementations, the step of the cross-core data processing module of the second core reading the first data from the shared memory area includes: when the read-write flag indicates that reading the first data is allowed, the cross-core data processing module of the second core reads the first data from the shared memory area; when the first data in the shared memory area is completely read and written to the second core, the cross-core data processing module of the second core restores the read-write flag to indicate that writing the first data is allowed.

[0009] In the above technical solution, when the read / write flag indicates that the first data is allowed to be read, it indicates that the second core is allowed to read the first data from the shared internal area. At this time, the cross-core data processing module of the second core performs the read operation of the first data. Further, as the read operation proceeds, when the first data is completely read and written to the second core, the cross-core data processing module of the second core restores the read / write flag to indicate that the first data is allowed to be written. In this way, other cores can be allowed to perform write operations on the first data, meeting the data writing requirements of other cores.

[0010] In combination with the first aspect and the above-mentioned implementation methods, in some possible implementation methods, the cross-core data processing module of the second core reads the first data from the shared memory area, including: the cross-core data processing module of the second core interrupts the second operation and reads the first data from the shared memory area, and the second operation is an operation for other cores to read the first data from the shared memory area.

[0011] In the above technical solution, before the cross-core data processing module of the second core reads the first data from the shared memory area, the cross-core data processing module of the second core in the method interrupts other cores from reading the first data from the shared memory area. This process can prevent other cores from accessing and modifying the first data at the same time before the first data is read, and prevent data confusion or inconsistency caused by concurrent reading of the first data.

[0012] In combination with the first aspect and the above-mentioned implementation methods, in some possible implementation methods, interrupting the first operation and writing the backup data of the first data into the shared memory area in the multi-core software system includes: determining the importance level of the first data; based on the importance level, constructing a data transmission channel between the first kernel and the shared memory area; interrupting the first operation and writing the backup data of the first data into the shared memory area through the data transmission channel.

[0013] In the above technical solution, before writing the backup data of the first data into the shared memory area, the method determines the importance level of the first data, and based on the importance level, constructs a data transmission channel between the first kernel and the shared memory area. In this way, the consumed data transmission resources (i.e., communication resources and bandwidth resources) correspond to the importance level corresponding to the first data. Among them, communication resources refer to hardware resources and software resources used for data exchange in a multi-core software system, including network interfaces, communication protocol stacks, bus systems, etc., and bandwidth resources refer to the maximum rate at which data can be transmitted in a data transmission channel. Therefore, the method writes the backup data of the first data into the shared memory area through the data transmission channel, and can complete the writing task of the first data with reasonable data transmission resources without wasting redundant data transmission resources.

[0014] In combination with the first aspect and the above-mentioned implementation methods, in some possible implementation methods, determining the importance level of the first data includes: determining the importance level based on the data volume of the first data; or, determining the importance level based on the timeliness of the first data; or, determining the importance level based on the data type of the first data, where the data type is used to indicate the physical meaning of the first data.

[0015] In the above technical solution, a large amount of vehicle user data may be rated as important data, i.e., data of important level, because of its application value in market analysis and business decision-making. The size of the data volume may also affect the recovery cost after data leakage or damage, as well as the potential impact of data loss on the target business. Therefore, the importance level of the first data can be reasonably determined based on the data volume range. Furthermore, the more time-sensitive the data is, the greater the value is in vehicle control decisions, such as real-time traffic flow data and vehicle operation status data, which are crucial for traffic management, vehicle safety monitoring, etc. in a short time. Therefore, the importance level of the first data is determined based on timeliness. In addition, by classifying the first data, it is possible to distinguish which of the multiple data types such as sensitive personal information, off-vehicle data, cockpit data, software operation data, location trajectory data, etc., and it is possible to determine which data is given priority resource allocation. Therefore, the method determines the importance level of the first data through the above multiple methods, which helps to reasonably configure data transmission resources, and preferentially transmit or encrypt data with high value, high timeliness, and high sensitivity (high importance level).

[0016] In combination with the first aspect and the above-mentioned implementation methods, in some possible implementation methods, the data transmission channel includes an encryption channel, a fast packet channel and a slow packet channel, and based on the importance level, a data transmission channel is constructed between the first kernel and the shared memory area, including: when the importance level is the first level, an encryption channel is constructed between the first kernel and the shared memory area, and the encryption channel is a data transmission channel that uses data encryption technology; when the importance level is the second level, a fast packet channel is constructed between the first kernel and the shared memory area, and the data transmission speed of the fast packet channel is faster than that of the slow packet channel; when the importance level is the third level, a slow packet channel is constructed between the first kernel and the shared memory area, and the first level is higher than the second level, and the second level is higher than the third level.

[0017] In the above technical scheme, different importance levels correspond to the construction of different data transmission channels. Specifically, when the importance level is the first level, an encrypted channel is constructed between the first kernel and the shared memory area. In this way, the confidential first data will not be tampered with or leaked during the transmission process. When the importance level is the second level, a fast packet channel is constructed between the first kernel and the shared memory area. In this way, the first data can be transmitted and written to the shared memory area as quickly as possible, so that other kernels can read the first data faster. When the importance level is the third level, a slow packet channel is constructed between the first kernel and the shared memory area. In this way, not only can the slow packet channel be used to transmit the first data, but the fast packet channel can also be used to transmit other data at the same time. This parallel data transmission method can improve the transmission efficiency of data (including the first data).

[0018] In a second aspect, a device for controlling a multi-core software system is provided, the multi-core software system comprising a first kernel and a second kernel, the first kernel comprising a cross-core data processing module, the device comprising: an acquisition module, for obtaining a read / write flag in response to a trigger instruction for writing first data of the first kernel into the second kernel, the read / write flag being used to indicate that the first data is allowed to be written or read; a writing module, for interrupting a first operation and writing backup data of the first data into a shared memory area in the multi-core software system when the read / write flag indicates that the first data is allowed to be written, the first operation being an operation of writing second data to the first kernel and reading the first data from the shared memory area, the second data being associated with the first data; and an adjustment module, for adjusting the read / write flag to indicate that the first data is allowed to be read when the backup data is completely written into the shared memory area, so that the cross-core data processing module of the second kernel reads the first data from the shared memory area.

[0019] In combination with the second aspect, in some possible implementations, the device also includes: a reading module, which is used for the cross-core data processing module of the second core to read the first data from the shared memory area when the read-write flag indicates that the first data is allowed to be read; the adjustment module is also used for the cross-core data processing module of the second core to restore the read-write flag to indicate that the first data is allowed to be written when the first data in the shared memory area is completely read and written to the second core.

[0020] In combination with the second aspect and the above-mentioned implementation methods, in some possible implementation methods, the reading module is also used for the cross-core data processing module of the second core to interrupt the second operation and read the first data from the shared memory area. The second operation is an operation for other cores to read the first data from the shared memory area.

[0021] In combination with the second aspect and the above-mentioned implementation methods, in some possible implementation methods, the device also includes: a determination module, used to determine the importance level of the first data; a construction module, used to construct a data transmission channel between the first kernel and the shared memory area based on the importance level; the write operation is specifically used to interrupt the first operation and write the backup data of the first data to the shared memory area through the data transmission channel.

[0022] In combination with the second aspect and the above-mentioned implementation methods, in some possible implementation methods, the determination module is specifically used to: determine the importance level based on the data volume of the first data; or, determine the importance level based on the timeliness of the first data; or, determine the importance level based on the data type of the first data, and the data type is used to indicate the physical meaning of the first data.

[0023] In combination with the second aspect and the above-mentioned implementation methods, in some possible implementation methods, the data transmission channel includes an encryption channel, a fast packet channel and a slow packet channel. The construction module is specifically used to construct an encryption channel between the first kernel and the shared memory area when the importance level is the first level, and the encryption channel is a data transmission channel that uses data encryption technology; when the importance level is the second level, construct a fast packet channel between the first kernel and the shared memory area, and the data transmission speed of the fast packet channel is faster than that of the slow packet channel; when the importance level is the third level, construct a slow packet channel between the first kernel and the shared memory area, and the first level is higher than the second level, and the second level is higher than the third level.

[0024] In a third aspect, a multi-core software system is provided, including a first kernel, a second kernel and a shared memory area, the first kernel including a cross-core data processing module, the second kernel including a cross-core data processing module, and the cross-core data processing module of the first kernel is used to:

[0025] In response to a trigger instruction for writing the first data of the first core into the second core, obtaining a read / write flag, the read / write flag being used to indicate that writing the first data is allowed or reading the first data is allowed;

[0026] When the read / write flag indicates that the first data is allowed to be written, interrupting the first operation, and writing the backup data of the first data into the shared memory area in the multi-core software system, the first operation is an operation of writing the second data to the first core and reading the first data from the shared memory area, and the second data is associated with the first data;

[0027] When the backup data is completely written into the shared memory area, adjusting the read-write flag to indicate that reading of the first data is permitted;

[0028] The cross-core data processing module of the second core is used for reading the first data from the shared memory area.

[0029] In a fourth aspect, a vehicle is provided, comprising a memory and a processor. The memory is used to store executable program code, and the processor is used to call and run the executable program code from the memory, so that the vehicle executes the method in the first aspect or any possible implementation of the first aspect.

[0030] In a fifth aspect, a computer-readable storage medium is provided, which stores an executable program code. When the executable program code runs on a computer, the computer executes the method in the above-mentioned first aspect or any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic diagram of a scenario of using a vehicle provided in an embodiment of the present application;

[0032] Figure 2 is a schematic flow chart of a method for controlling a multi-core software system provided in an embodiment of the present application;

[0033] Figure 3 is a schematic diagram of cross-core data communication provided by an embodiment of the present application;

[0034] Figure 4 It is a structural schematic diagram of a device for controlling a multi-core software system provided in an embodiment of the present application;

[0035] Figure 5 It is a structural diagram of a multi-core software system provided in an embodiment of the present application;

[0036] Figure 6 It is a structural schematic diagram of a vehicle provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The technical solution in the present application will be described clearly and in detail below in conjunction with the accompanying drawings. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B: "and / or" in the text is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0038] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as suggesting or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0039] Figure 1 It is a schematic diagram of a scenario of using a vehicle provided in an embodiment of the present application.

[0040] For example, Figure 1 As shown, the vehicle user can travel to multiple destinations in the autonomous driving vehicle A. During the driving process of the autonomous driving vehicle A, the autonomous driving vehicle A can share vehicle speed information through the autonomous emergency braking (AEB) system and the adaptive cruise control (ACC) system included therein, thereby controlling the vehicle.

[0041] With the development of vehicle technology and the iteration of application requirements, the computing core architecture tends to be integrated, and the decentralized single functions of each module are developing towards a centralized domain controller mode. Multi-core software systems are also used in vehicles. In a multi-core software system, when software components of different central processing unit (CPU) cores are transmitting data, the multi-core software system will open up a shared memory area for them. The communicating parties complete the data transmission by reading and writing data in the shared memory area. However, the multi-core software system has the characteristics of task concurrency, and the data in the shared memory area may be read and written by software components of different CPU cores at the same time. This will cause data reading and writing conflicts and inconsistencies.

[0042] For example, in autonomous vehicle A, the current speed of autonomous vehicle A is 100km / h, and the ACC system is adjusting it to 95km / h. At this time, the AEB system starts to read the speed, but the ACC system has not yet completed the update of the speed. While the AEB system is reading the speed, the ACC system completes the update of the speed, that is, adjusting it from 100km / h to 95km / h. This will cause the AEB system to read the old speed and brake the autonomous vehicle A, resulting in excessive braking force, which in turn affects the driving safety of the autonomous vehicle A.

[0043] In order to solve the above problems, the present application proposes a method for controlling a multi-core software system to ensure the consistency of data in a shared memory area, so that the multi-core software system can better serve the vehicle.

[0044] Figure 2 It is a schematic flowchart of a method for controlling a multi-core software system provided in an embodiment of the present application.

[0045] It should be understood that the method for controlling a multi-core software system provided in the embodiment of the present application can be applied to Figure 1 The vehicle shown (e.g., autonomous driving vehicle A). In some embodiments, the operating system in the vehicle is a multi-core software system.

[0046] It should also be understood that the multi-core software system in the present application includes multiple cores, namely, central processing unit (CPU) cores, and each core includes a cross-core data processing module, which is used to receive / send data that software components in the core need to interact across cores. Among them, software components generally refer to different parts or modules of a software program. The software components include drivers, middleware, application frameworks or user applications of the operating system of the vehicle system. In other words, the operating system can perform data transmission and data processing through the multiple cores.

[0047] Exemplarily, the multi-core software system includes a first core and a second core, and the method is executed by a cross-core data processing module of the first core, such as Figure 2 As shown, the method 200 includes:

[0048] Step 201, in response to a trigger instruction for writing first data of the first core into the second core, obtaining a read / write flag, wherein the read / write flag is used to indicate that writing the first data is allowed or reading the first data is allowed.

[0049] It should be understood that the "trigger instruction" in the above step 201 can be triggered by the task scheduling strategy and synchronization mechanism of the operating system in the vehicle. In some embodiments, when the synchronization mechanism includes an event, it can be triggered by setting the event. In some embodiments, when the synchronization mechanism includes a semaphore, it can be triggered by the count of the semaphore being greater than a threshold. In some embodiments, when the synchronization mechanism includes a conditional variable, it can be triggered by the vehicle satisfying a preset conditional variable.

[0050] It should also be understood that the "read-write flag" in the above step 201 is used to synchronize the access of multiple cores (including the first core and the second core in step 201) in the multi-core software system to the shared data resources to avoid data competition and consistency problems. The read-write flag is used to indicate that the first data is allowed to be written or the first data is allowed to be read. In some embodiments, when the read-write flag is 0, it is used to indicate that the first data is allowed to be written. In some embodiments, when the read-write flag is 1, it is used to indicate that the first data is allowed to be read.

[0051] In a possible implementation, obtaining the read-write flag bit in step 201 includes: reading the read-write flag bit from a shared memory area in the multi-core software system.

[0052] It should be understood that the "shared memory area" in the above solution is a memory area independent of multiple cores in the multi-core software system, which is used to store data, including backup data and read-write flags of shared data written by one core to another core. The shared data includes the first data.

[0053] In the above technical solution, by setting the read-write flag bit in the shared memory area, the shared memory area can be accessed synchronously to prevent multiple cores from reading and writing shared data at the same time, which may cause data inconsistency. By using the read-write flag bit, it can be ensured that only one core modifies the data in the shared memory area at any time, thereby maintaining the integrity of the data and the stability of the multi-core software system.

[0054] Step 202, when the read-write flag indicates that writing of the first data is allowed, interrupt the first operation and write the backup data of the first data into the shared memory area in the multi-core software system, the first operation is an operation of writing the second data to the first kernel and reading the first data from the shared memory area, and the second data is associated with the first data.

[0055] It should be understood that the “read-write flag indicates that the first data is allowed to be written” in the above step 202 means that the read-write flag is 0. In addition, when the read-write flag does not indicate that the first data is allowed to be written, the step of “interrupting the first operation and writing the backup data of the first data into the shared memory area in the multi-core software system” is not performed.

[0056] It should also be understood that "the second data is associated with the first data" in the above step 202 means that the data type of the second data is the same as the first data. "Interrupting the operation of writing the second data to the first kernel" in the above step 202 means interrupting the operation of writing data of the same data type as the first data to the first kernel. In some embodiments, the first data is a plurality of vehicle speeds in a first time period, and "interrupting the operation of writing the second data to the first kernel" means interrupting the operation of writing the vehicle speed to the first kernel.

[0057] It should also be understood that in the above step 202, before the backup data of the first data is written into the shared memory area in the multi-core software system, the operation of writing the second data into the first kernel is interrupted, in order to prevent other kernels from tampering with the first data in the first kernel when the first kernel writes the first data into the shared memory area, thereby causing the tampered first data in the first kernel to be inconsistent with the first data in the shared memory area. And the operation of reading the first data from the shared memory area is interrupted, in order to prevent other kernels from tampering with the first data in the shared memory area when the second kernel reads the first data from the shared memory area, thereby causing the tampered first data in the shared memory area to be inconsistent with the first data written in the second kernel.

[0058] It should also be understood that the read-write flag and the data backup of the data to be written (such as the first data) are defined in the shared memory area. When the shared memory area is occupied, all tasks related to the shared memory area or the second-class interrupt service routine (ISR) cannot successfully apply to occupy the shared resources in the shared memory area (such as reading the first data). This can prevent the read-write flag and the data backup from being read or accessed by different tasks at the same time, causing data tampering. Among them, the interrupt service routine is a special type of program in the operating system of the vehicle system, which is mainly used to respond to interrupt requests generated by hardware or software, handle emergency events, and resume the execution of the main program after the processing is completed. The second-class ISR refers to the interrupt service program managed by the operating system. Unlike the first-class ISR, the second-class ISR can use the application program interface provided by the operating system, and perform task scheduling during the interrupt processing process, and can be interrupted by other interrupts. Among them, the first-class ISR does not interact with the operating system and has the highest priority.

[0059] In one possible implementation, interrupting the first operation in step 202 and writing the backup data of the first data into the shared memory area in the multi-core software system includes: determining the importance level of the first data; based on the importance level, building a data transmission channel between the first kernel and the shared memory area; interrupting the first operation and writing the backup data of the first data into the shared memory area through the data transmission channel.

[0060] It should be understood that the "importance level" in the above scheme is used to quantify the importance of the first data. Generally, the importance level of the first data can be determined based on the timeliness, value, protection requirements and data volume of the first data. In some embodiments, the importance level can be divided into a first level, a second level and a third level, the first level is higher than the second level, and the second level is higher than the third level.

[0061] It should also be understood that the data transmission channels corresponding to the first data of different levels are different, because the data of different levels have different requirements for transmission. For example, confidential data needs to be transmitted through an encrypted channel, and time-sensitive data needs to be transmitted through a fast packet channel.

[0062] In the above technical solution, before writing the backup data of the first data into the shared memory area, the method determines the importance level of the first data, and based on the importance level, constructs a data transmission channel between the first kernel and the shared memory area. In this way, the consumed data transmission resources (i.e., communication resources and bandwidth resources) correspond to the importance level corresponding to the first data. Among them, communication resources refer to hardware resources and software resources used for data exchange in a multi-core software system, including network interfaces, communication protocol stacks, bus systems, etc., and bandwidth resources refer to the maximum rate at which data can be transmitted in a data transmission channel. Therefore, the method writes the backup data of the first data into the shared memory area through the data transmission channel, and can complete the writing task of the first data with reasonable data transmission resources without wasting redundant data transmission resources.

[0063] In one possible implementation, determining the importance level of the first data includes: determining the importance level based on the data volume of the first data; or, determining the importance level based on the timeliness of the first data; or, determining the importance level based on the data type of the first data, where the data type is used to indicate the physical meaning of the first data.

[0064] It should be understood that in the above scheme, the "data volume range" is pre-set. "Timeliness" refers to the degree to which the first data remains correct in the course of time changes, and the timeliness can be characterized by the time interval between the time when the first data is generated and the current time. The longer the time interval between the time when the first data is generated and the current time, the worse the timeliness of the first data. "Data type" refers to the classification or attribute of the first data, which is used to describe the physical meaning of the first data.

[0065] In the above technical solution, a large amount of vehicle user data may be rated as important data, i.e., data of important level, because of its application value in market analysis and business decision-making. The size of the data volume may also affect the recovery cost after data leakage or damage, as well as the potential impact of data loss on the target business. Therefore, the importance level of the first data can be reasonably determined based on the data volume range. Furthermore, the more time-sensitive the data is, the greater the value is in vehicle control decisions, such as real-time traffic flow data and vehicle operation status data, which are crucial for traffic management, vehicle safety monitoring, etc. in a short time. Therefore, the importance level of the first data is determined based on timeliness. In addition, by classifying the first data, it is possible to distinguish which of the multiple data types such as sensitive personal information, off-vehicle data, cockpit data, software operation data, location trajectory data, etc., and it is possible to determine which data is given priority resource allocation. Therefore, the method determines the importance level of the first data through the above multiple methods, which helps to reasonably configure data transmission resources, and preferentially transmit or encrypt data with high value, high timeliness, and high sensitivity (high importance level).

[0066] In some embodiments, the importance level is determined based on the data volume of the first data, including: comparing the data volume with multiple preset data volume ranges to determine a target data volume range corresponding to the data volume; when the target data volume range is a first data volume range, determining the importance level to be a first level; when the target data volume range is a second data volume range, determining the importance level to be a second level; when the target data volume range is a third data volume range, determining the importance level to be a third level, the data volume corresponding to the first data volume range is greater than the data volume corresponding to the second data volume range, and the data volume corresponding to the second data volume range is greater than the data volume corresponding to the third data volume range.

[0067] In other embodiments, the timeliness is used to characterize the time interval between the time when the first data is generated and the current time, and the importance level is determined based on the timeliness of the first data, including: when the time interval is within a first time range, determining the importance level to be the first level; when the time interval is within a second time range, determining the importance level to be the second level; when the time interval is within a third time range, determining the importance level to be the third level, the time corresponding to the first time range is shorter than the time corresponding to the second time range, and the time corresponding to the second time range is shorter than the time corresponding to the third time range.

[0068] In other embodiments, the importance level is determined based on the data type of the first data, including: when the data type is a first data type, determining the importance level to be a first level, the first data type includes vehicle user information, and the vehicle user information is privacy information of the vehicle user; when the data type is a second data type, determining the importance level to be a second level, the second data type includes vehicle status, traffic conditions, and diagnostic information; when the data type is neither the first data type nor the second data type, determining the importance level to be a third level.

[0069] It should be understood that the vehicle user information includes the user's identity information, biometric information, payment information, driving habit information, and online behavior information.

[0070] In other embodiments, the importance level is determined based on the data volume, timeliness and data type of the first data, including: when the data type is the first data type, determining the importance level to be the first level; when the data type is not the first data type and the target data volume range corresponding to the data volume is the first data volume range, and the time interval is within the first time range, determining the importance level to be the first level; when the time interval is within the second time range and the data type is neither the first data type nor the second data type, determining the importance level to be the second level; when the data type is not the first data type and the time interval is within the third time range, and the data type is neither the first data type nor the second data type, determining the importance level to be the third level.

[0071] In one possible implementation, the data transmission channel includes an encryption channel, a fast packet channel and a slow packet channel. Based on the importance level, a data transmission channel is constructed between the first kernel and the shared memory area, including: when the importance level is a first level, an encryption channel is constructed between the first kernel and the shared memory area, and the encryption channel is a data transmission channel using data encryption technology; when the importance level is a second level, a fast packet channel is constructed between the first kernel and the shared memory area, and the data transmission speed of the fast packet channel is faster than that of the slow packet channel; when the importance level is a third level, a slow packet channel is constructed between the first kernel and the shared memory area, and the first level is higher than the second level, and the second level is higher than the third level.

[0072] It should be understood that in the above scheme, the "encrypted channel" can be specifically understood as a data transmission channel that encrypts the data it transmits. The "fast packet channel" can be specifically understood as a data transmission channel that transmits data at a faster rate. The "slow packet channel" can be specifically understood as a data transmission channel that transmits data at a slower rate.

[0073] In the above technical scheme, different importance levels correspond to the construction of different data transmission channels. Specifically, when the importance level is the first level, an encrypted channel is constructed between the first kernel and the shared memory area. In this way, the confidential first data will not be tampered with or leaked during the transmission process. When the importance level is the second level, a fast packet channel is constructed between the first kernel and the shared memory area. In this way, the first data can be transmitted and written to the shared memory area as quickly as possible, so that other kernels can read the first data faster. When the importance level is the third level, a slow packet channel is constructed between the first kernel and the shared memory area. In this way, not only can the slow packet channel be used to transmit the first data, but the fast packet channel can also be used to transmit other data at the same time. This parallel data transmission method can improve the transmission efficiency of data (including the first data).

[0074] Step 203, when the backup data is completely written into the shared memory area, the read-write flag is adjusted to indicate that reading of the first data is allowed, so that the cross-core data processing module of the second core reads the first data from the shared memory area.

[0075] It should be understood that in the above step 203, "the backup data is completely written to the shared memory area" means that the first data is completely copied to the shared memory area. When the read-write flag is 0 or 1 and the read-write flag is 0 for indicating that the first data is allowed to be written, and the read-write flag is 1 for indicating that the first data is allowed to be read, "adjusting the read-write flag to indicate that the first data is allowed to be read" can be understood as adjusting the read-write flag from 0 to 1.

[0076] It should also be understood that the "read-write flag is adjusted to indicate that reading the first data is allowed" in the above step 203 indicates that the backup data of the first data has been completely written into the shared memory area, and the first kernel has completed the write operation on the first data. The first data will no longer change, and other kernels are allowed to read the first data.

[0077] It should also be understood that in different cores, when cross-core data processing modules read the same data in a shared memory area or write the same data to a shared memory area, they can share the same read / write flag. Each reset of the read / write flag (from 0 to 1 and then back to 1) indicates that a complete data transfer is completed.

[0078] In some embodiments, the step of adjusting the read-write flag bit in step 203 to indicate that reading the first data is allowed includes: determining whether the current read-write flag bit indicates that writing the first data is allowed through an atomic operation instruction provided by an internal chip in the first core; when the current read-write flag bit indicates that writing the first data is allowed, adjusting the current read-write flag bit to indicate that reading the first data is allowed through the atomic operation instruction.

[0079] In one possible implementation, the step of the cross-core data processing module of the second kernel reading the first data from the shared memory area includes: when the read-write flag indicates that reading the first data is allowed, the cross-core data processing module of the second kernel reads the first data from the shared memory area; when the first data in the shared memory area is completely read and written to the second kernel, the cross-core data processing module of the second kernel restores the read-write flag to indicate that writing the first data is allowed.

[0080] It should be understood that "the first data in the shared memory area is completely read and written into the second kernel" in the above solution corresponds to the "trigger instruction to write the first data of the first kernel into the second kernel" in step 201. The process of writing the first data of the first kernel into the second kernel includes: the backup data of the first data of the first kernel is first written into the shared memory area by the cross-core data processing module of the first kernel, and then read from the shared memory area by the cross-core data processing module of the second kernel, and finally written into the second kernel.

[0081] It should also be understood that steps 201 to 203, and when the read-write flag indicates that the first data is allowed to be read, the cross-core data processing module of the second core reads the first data from the shared memory area; when the first data in the shared memory area is completely read and written to the second core, the cross-core data processing module of the second core restores the read-write flag to indicate that the first data is allowed to be written, which describes a complete data writing process of writing the first data of the first core to the second core. Therefore, after the second core completely reads and writes the first data from the shared memory area, it is necessary to restore the read-write flag to indicate that the first data is allowed to be written, so as to allow other cores to write data of the same data type as the first data.

[0082] In the above technical solution, when the read / write flag indicates that the first data is allowed to be read, it indicates that the second core is allowed to read the first data from the shared internal area. At this time, the cross-core data processing module of the second core performs the read operation of the first data. Further, as the read operation proceeds, when the first data is completely read and written to the second core, the cross-core data processing module of the second core restores the read / write flag to indicate that the first data is allowed to be written. In this way, other cores can be allowed to perform write operations on the first data, meeting the data writing requirements of other cores.

[0083] In some embodiments, during the data writing process in which the cross-core data processing module of the second core reads and writes the first data from the shared memory area, the cross-core data processing module of the second core obtains the cumulative delay duration for receiving the first data; when the cumulative delay duration is greater than the preset duration, a reminder message is output, and the reminder message is used to remind that a timeout failure has occurred in the data writing process.

[0084] In one possible implementation, the cross-core data processing module of the second core reads the first data from the shared memory area, including: the cross-core data processing module of the second core interrupts the second operation and reads the first data from the shared memory area, and the second operation is an operation in which other cores read the first data from the shared memory area.

[0085] It should be understood that the above scheme describes that when the cross-core data processing module of the second core reads the first data from the shared memory area, the operation of other cores reading the first data from the shared memory area is interrupted. That is, when the second core reads the first data from the shared memory area, other cores are not allowed to read the first data from the shared memory area.

[0086] In the above technical solution, before the cross-core data processing module of the second core reads the first data from the shared memory area, the cross-core data processing module of the second core in the method interrupts other cores from reading the first data from the shared memory area. This process can prevent other cores from accessing and modifying the first data at the same time before the first data is read, and prevent data confusion or inconsistency caused by concurrent reading of the first data.

[0087] Figure 3 This is a schematic diagram of cross-core data communication provided in an embodiment of the present application.

[0088] Exemplarily, taking the case where the first kernel and the second kernel included in the multi-core software system are kernel 1 and kernel 2 respectively as an example, the process of cross-core data communication between multiple kernels in the multi-core software system is described.

[0089] Specifically, Figure 3As shown, the cross-core data processing module of kernel 1 responds to the trigger instruction of writing the first data of kernel 1 into kernel 2, and obtains the read-write flag (wrflg), which is 0. The cross-core data processing module of kernel 0 determines that the current multi-core software system allows the first data to be written to kernel 2 through the read-write flag. At this time, the cross-core data processing module of kernel 1 interrupts the operation of writing the second data to kernel 1 and reading the first data from the shared memory area (Buffer area) in the multi-core software system, and uploads (writes) the backup data of the first data to the Buffer area, wherein the second data has the same data type as the first data. When the backup data of the first data is completely written into the Buffer area, the cross-core data processing module of kernel 1 adjusts the read-write flag from 0 to 1. At the same time, the cross-core data processing module of kernel 2 periodically reads the read-write flag, and when the read-write flag is 1, the cross-core data processing module of kernel 2 interrupts the operation of other kernels reading the first data from the Buffer area, and reads the first data from the Buffer area and writes it into kernel 2 to complete the writing task of the first data. When the first data in the shared memory area is completely read and written into the core 2, the cross-core data processing module of the core 2 restores the read-write flag from 1 to 0.

[0090] Figure 4 It is a structural diagram of a device for controlling a multi-core software system provided in an embodiment of the present application.

[0091] Exemplarily, the multi-core software system includes a first core and a second core, the first core includes a cross-core data processing module, such as Figure 4 As shown, the device 400 includes:

[0092] An acquisition module 401 is used for acquiring a read / write flag in response to a trigger instruction for writing the first data of the first kernel into the second kernel, where the read / write flag is used for indicating that the first data is allowed to be written or read;

[0093] A writing module 402 is used to interrupt a first operation and write backup data of the first data into a shared memory area in the multi-core software system when the read-write flag indicates that writing of the first data is allowed, wherein the first operation is an operation of writing second data to the first core and reading the first data from the shared memory area, and the second data is associated with the first data;

[0094] The adjustment module 403 is used to adjust the read-write flag to indicate that reading the first data is allowed when the backup data is completely written into the shared memory area, so that the cross-core data processing module of the second core reads the first data from the shared memory area.

[0095] Optionally, the device 400 also includes: a reading module, which is used for the cross-core data processing module of the second core to read the first data from the shared memory area when the read-write flag indicates that the first data is allowed to be read; the adjustment module 403 is also used for the cross-core data processing module of the second core to restore the read-write flag to indicate that the first data is allowed to be written when the first data in the shared memory area is completely read and written to the second core.

[0096] Optionally, the reading module is also used for the cross-core data processing module of the second core to interrupt the second operation and read the first data from the shared memory area. The second operation is an operation for other cores to read the first data from the shared memory area.

[0097] Optionally, the device 400 also includes: a determination module for determining the importance level of the first data; a construction module for constructing a data transmission channel between the first kernel and the shared memory area based on the importance level; the write operation 402 is specifically used to interrupt the first operation and write the backup data of the first data to the shared memory area through the data transmission channel.

[0098] Optionally, the determination module is specifically used to: determine the importance level based on the data volume of the first data; or, determine the importance level based on the timeliness of the first data; or, determine the importance level based on the data type of the first data, where the data type is used to indicate the physical meaning of the first data.

[0099] Optionally, the data transmission channel includes an encryption channel, a fast packet channel and a slow packet channel. The construction module is specifically used to construct an encryption channel between the first kernel and the shared memory area when the importance level is the first level, and the encryption channel is a data transmission channel using data encryption technology; to construct a fast packet channel between the first kernel and the shared memory area when the importance level is the second level, and the data transmission speed of the fast packet channel is faster than that of the slow packet channel; and to construct a slow packet channel between the first kernel and the shared memory area when the importance level is the third level, and the first level is higher than the second level, and the second level is higher than the third level.

[0100] Figure 5 It is a structural diagram of a multi-core software system provided in an embodiment of the present application.

[0101] For example, Figure 5As shown, the multi-core software system 500 includes a first kernel 501, a second kernel 502 and a shared memory area 503, the first kernel 501 includes a cross-core data processing module 504, the second kernel 502 includes a cross-core data processing module 505, and the cross-core data processing module 504 of the first kernel 501 is used to:

[0102] In response to a trigger instruction for writing the first data of the first core 501 into the second core 502, a read / write flag is obtained, where the read / write flag is used to indicate that the first data is allowed to be written or read;

[0103] When the read / write flag indicates that the first data is allowed to be written, the first operation is interrupted, and the backup data of the first data is written into the shared memory area 503 in the multi-core software system 500, the first operation is an operation of writing the second data to the first core 501 and reading the first data from the shared memory area 503, and the second data is associated with the first data;

[0104] When the backup data is completely written into the shared memory area 503, the read-write flag is adjusted to indicate that reading of the first data is permitted;

[0105] The cross-core data processing module 505 of the second core 502 is used to read the first data from the shared memory area 503 .

[0106] Figure 6 It is a structural schematic diagram of a vehicle provided in an embodiment of the present application.

[0107] For example, Figure 6 As shown, the vehicle 600 includes: a memory 601 and a processor 602, wherein the memory 601 stores an executable program code 603, and the processor 602 is used to call and execute the executable program code 603 to perform a method for controlling a multi-core software system.

[0108] In addition, an embodiment of the present application also protects a device, which may include a memory and a processor, wherein the memory stores executable program code, and the processor is used to call and execute the executable program code to execute a method for controlling a multi-core software system provided by an embodiment of the present application.

[0109] In this embodiment, the functional modules of the device can be divided according to the above method example. For example, each functional module can be corresponded, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0110] In the case of dividing each functional module according to each function, the device may also include an acquisition module, a writing module, an adjustment module, a determination module, a construction module, etc. It should be noted that all relevant contents involved in the above method embodiment can be referred to the functional description of the corresponding functional module, which will not be repeated here.

[0111] It should be understood that the device provided in this embodiment is used to execute the above-mentioned method of controlling a multi-core software system, and thus can achieve the same effect as the above-mentioned implementation method.

[0112] In the case of an integrated unit, the device may include a processing module and a storage module. When the device is applied to a vehicle, the processing module may be used to control and manage the actions of the vehicle. The storage module may be used to support the vehicle in executing related executable program codes, etc.

[0113] The processing module may be a processor or a controller, which may implement or execute various exemplary logic blocks, modules and circuits shown in conjunction with the disclosure of the present application. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc. The storage module may be a memory.

[0114] In addition, the device provided in the embodiments of the present application may specifically be a chip, component or module, and the chip may include a connected processor and memory; wherein the memory is used to store instructions, and when the processor calls and executes the instructions, the chip can execute a method for controlling a multi-core software system provided in the above embodiment.

[0115] This embodiment also provides a computer-readable storage medium, which stores executable program code. When the executable program code runs on a computer, the computer executes the above-mentioned related method steps to implement a method for controlling a multi-core software system provided by the above embodiment.

[0116] This embodiment also provides a computer program product. When the computer program product runs on a computer, it enables the computer to execute the above-mentioned related steps to implement a method for controlling a multi-core software system provided by the above embodiment.

[0117] Among them, the device, computer-readable storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be repeated here.

[0118] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0119] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0120] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for controlling a multi-core software system, characterized in that: The multi-core software system includes a first core and a second core, and the method is executed by a cross-core data processing module of the first core, including: In response to a trigger instruction to write the first data of the first kernel into the second kernel, obtaining a read / write flag bit, wherein the read / write flag bit is used to indicate that the first data is allowed to be written or read; When the read / write flag indicates that writing of the first data is allowed, interrupting the first operation and writing the backup data of the first data into the shared memory area in the multi-core software system, the first operation is an operation of writing the second data into the first core and reading the first data from the shared memory area, and the second data is associated with the first data; When the backup data is completely written into the shared memory area, the read-write flag is adjusted to indicate that reading of the first data is allowed, so that the cross-core data processing module of the second kernel reads the first data from the shared memory area.

2. The method according to claim 1, characterized in that The step of the cross-core data processing module of the second kernel reading the first data from the shared memory area includes: When the read / write flag indicates that reading the first data is allowed, the cross-core data processing module of the second core reads the first data from the shared memory area; When the first data in the shared memory area is completely read and written into the second kernel, the cross-core data processing module of the second kernel restores the read-write flag to indicate that writing of the first data is allowed.

3. The method according to claim 2, characterized in that The cross-core data processing module of the second core reads the first data from the shared memory area, including: The cross-core data processing module of the second core interrupts the second operation and reads the first data from the shared memory area. The second operation is an operation in which other cores read the first data from the shared memory area.

4. The method according to claim 1, characterized in that The interrupting the first operation and writing the backup data of the first data into a shared memory area in the multi-core software system includes: determining an importance level of the first data; Based on the importance level, constructing a data transmission channel between the first kernel and the shared memory area; The first operation is interrupted, and the backup data of the first data is written into the shared memory area through the data transmission channel.

5. The method according to claim 4, characterized in that The determining the importance level of the first data includes: determining the importance level based on the data volume of the first data; or, Determining the importance level based on the timeliness of the first data; or, The importance level is determined based on a data type of the first data, where the data type is used to indicate a physical meaning of the first data.

6. The method according to claim 4, characterized in that The data transmission channel includes an encryption channel, a fast packet channel, and a slow packet channel. The data transmission channel between the first kernel and the shared memory area is constructed based on the importance level, including: When the importance level is the first level, constructing an encryption channel between the first kernel and the shared memory area, wherein the encryption channel is a data transmission channel using a data encryption technology; When the importance level is the second level, a fast packet channel is constructed between the first kernel and the shared memory area, wherein the data transmission speed of the fast packet channel is faster than that of the slow packet channel; When the importance level is the third level, a slow packet channel is constructed between the first kernel and the shared memory area, the first level is higher than the second level, and the second level is higher than the third level.

7. A device for controlling a multi-core software system, characterized in that: The multi-core software system includes a first core and a second core, the first core includes a cross-core data processing module, and the device includes: an acquisition module, configured to acquire a read / write flag in response to a trigger instruction for writing the first data of the first kernel into the second kernel, wherein the read / write flag is used to indicate that the first data is allowed to be written or read; a writing module, configured to interrupt a first operation and write backup data of the first data into a shared memory area in the multi-core software system when the read-write flag indicates that writing of the first data is allowed, wherein the first operation is an operation of writing second data to the first core and reading the first data from the shared memory area, and the second data is associated with the first data; An adjustment module is used to adjust the read-write flag to indicate that reading the first data is allowed when the backup data is completely written into the shared memory area, so that the cross-core data processing module of the second kernel reads the first data from the shared memory area.

8. A multi-core software system, characterized in that: The multi-core software system includes a first core, a second core and a shared memory area, the first core includes a cross-core data processing module, the second core includes a cross-core data processing module, and the cross-core data processing module of the first core is used to: In response to a trigger instruction to write the first data of the first kernel into the second kernel, obtaining a read / write flag bit, wherein the read / write flag bit is used to indicate that the first data is allowed to be written or read; When the read / write flag indicates that writing of the first data is allowed, interrupting the first operation and writing the backup data of the first data into the shared memory area in the multi-core software system, the first operation is an operation of writing the second data into the first core and reading the first data from the shared memory area, and the second data is associated with the first data; In a case where the backup data is completely written into the shared memory area, adjusting the read-write flag to indicate that reading of the first data is permitted; The cross-core data processing module of the second kernel is used to read the first data from the shared memory area.

9. A vehicle, characterized in that: The vehicle comprises: A memory for storing executable program codes; A processor, configured to call and run the executable program code from the memory, so that the vehicle executes the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores an executable program code, and when the executable program code is executed, the method according to any one of claims 1 to 7 is implemented.

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