Wafer test result generation method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a wafer test result generation method and device, electronic equipment and a storage medium, and relates to the technical field of semiconductor chips, and the method comprises the steps: obtaining a plurality of test files generated by carrying out multiple tests on the same wafer; integrating the plurality of test files, and only reserving an optimal test result for a plurality of test results of the same semiconductor chip on the wafer; and obtaining a final test result of the wafer based on the integrated test file. The technical scheme provided by the embodiment of the invention can be suitable for a wafer test scene, and can solve the problems of low wafer test data processing efficiency and inaccurate test result extraction in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor chip technology, and in particular to a method, device, electronic equipment and storage medium for generating wafer test results. Background Art

[0002] In the semiconductor chip manufacturing process, wafer testing is a key link to ensure product quality and yield. Complete wafer testing can not only identify defective semiconductor chips (also called Die, bare chips), but also provide necessary data support for subsequent chip cutting, packaging and final testing. For example, in the subsequent wafer cutting process, it is necessary to rely on the Soft Bin Optimizer Map (SMap) file of the entire wafer to accurately cut out each qualified Die, and the generation of the Smap file depends on the complete wafer test results to ensure that the status of all Dies is correctly marked to avoid good products being cut by mistake or defective products not being eliminated. In addition, data analysis engineers are also highly dependent on the test results of the entire wafer when evaluating the yield of the wafer.

[0003] Currently, during the wafer testing process, each die is subject to rigorous functional and performance evaluation to verify whether it meets the expected standards. However, due to the accuracy limitations of the test equipment, the impact of the external environment, and subtle differences in the inherent properties of the die, some dies may be mistakenly marked as "fail" in the initial test, meaning they do not meet the qualified standards. In order to improve the accuracy of the test results, a repeated testing strategy is usually adopted. This repeated testing strategy can sometimes correct the misjudgment of the initial test, allowing a die that was originally considered unqualified to pass the test, thereby correcting its final status.

[0004] The result of the above dynamic testing process is that a series of files reflecting the results of different test rounds will be generated. When using the wafer test data later, professional data analysis engineers are usually required to open these files one by one to extract the final wafer test results. This practice not only increases the complexity of data management and slows down the workflow, but also hides the risk of errors caused by inaccurate information integration, affecting the final decision quality. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a wafer test result generation method, device, electronic device and storage medium to solve the problems of low wafer test data processing efficiency and inaccurate test result extraction in the prior art.

[0006] In a first aspect, an embodiment of the present invention provides a method for generating wafer test results, comprising: Obtain multiple test files generated by multiple tests on the same wafer; integrating the plurality of test files, wherein for a plurality of test results of a same semiconductor chip on a wafer, only an optimal test result is retained; Based on the integrated test files, the final test results of the wafer are obtained.

[0007] Furthermore, the integrating the multiple test files includes: Selecting a test file from the multiple test files as a test file template; Based on each of the remaining test files, perform the following blueprint modification process: Compared with the test file blueprint, a better new test result of the same semiconductor chip in the test file currently based on replaces the corresponding original test result in the test file blueprint; the test result of the new semiconductor chip in the test file currently based on is added to the test file blueprint.

[0008] Further, the blueprint modification process is performed based on each remaining test file in turn, specifically including: Identify the target node in the current test file; wherein the target node includes: a heterogeneous same-core test unit node and its descendant nodes having better chip quality attributes than the test file blueprint, and a heterogeneous different-core test unit node and its descendant nodes; The target node in the current test file and its association with the basic data definition node are updated in the test file blueprint.

[0009] Further, before selecting a test file from the plurality of test files, the method further includes: sorting the plurality of test files by size; The step of selecting a test file from the plurality of test files as a test file template includes: selecting a test file ranked first as the test file template.

[0010] Furthermore, the integrating the multiple test files includes: A pre-built module chain is called to integrate the plurality of test files.

[0011] Furthermore, before integrating the multiple test files, the method further includes: The multiple test files are converted into text formats.

[0012] Furthermore, before obtaining multiple test files generated by performing multiple tests on the same wafer, the method further includes: Perform initial testing on all semiconductor chips on the wafer and record the test results in a test file; The semiconductor chips on the wafer that did not meet the previous test standards are retested cyclically until the preset stop condition is met, and each retest result is independently recorded in a test file.

[0013] In a second aspect, an embodiment of the present invention provides a wafer test result generating device, comprising: A test file acquisition unit, used to acquire multiple test files generated by performing multiple tests on the same wafer; a test file integration unit, configured to integrate the plurality of test files, wherein for a plurality of test results of the same semiconductor chip on the wafer, only the best test result is retained; The test result generating unit is used to obtain the final test result of the wafer based on the integrated test file.

[0014] Furthermore, the test file integration unit includes: A blueprint determination subunit, used to select a test file from the multiple test files as a test file blueprint; The blueprint modification subunit is used to perform the following blueprint modification processing based on each remaining test file in turn: Compared with the test file blueprint, a better new test result of the same semiconductor chip in the test file currently based on replaces the corresponding original test result in the test file blueprint; the test result of the new semiconductor chip in the test file currently based on is added to the test file blueprint.

[0015] Furthermore, the blueprint modification subunit is specifically used for: Identify the target node in the current test file; wherein the target node includes: a heterogeneous same-core test unit node and its descendant nodes having better chip quality attributes than the test file blueprint, and a heterogeneous different-core test unit node and its descendant nodes; The target node in the current test file and its association with the basic data definition node are updated in the test file blueprint.

[0016] Furthermore, the device also includes a test file sorting unit, which is used to sort the multiple test files by size; The blueprint determination subunit is specifically used to select the test file ranked first as the test file blueprint.

[0017] Furthermore, the test file integration unit is specifically used to: A pre-built module chain is called to integrate the plurality of test files.

[0018] Furthermore, the device also includes: The format conversion unit is used to convert the multiple test files into text formats before the test file integration unit integrates the multiple test files.

[0019] Furthermore, the device also includes a test file generating unit, which is used to: Perform initial testing on all semiconductor chips on the wafer and record the test results in a test file; The semiconductor chips on the wafer that did not meet the previous test standards are retested cyclically until the preset stop condition is met, and each retest result is independently recorded in a test file.

[0020] In a third aspect, an embodiment of the present invention provides an electronic device, comprising: a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is arranged inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the wafer test result generation method described in the first aspect above.

[0021] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the wafer test result generating method described in the first aspect above.

[0022] The technical solution provided in the embodiment of the present invention can automatically integrate repeated test data and retain the optimal results, solve the data redundancy and consistency problems in wafer testing, improve test efficiency and accuracy, reduce the error rate of manual processing, and save test costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A flowchart of a method for generating wafer test results provided in Embodiment 1 of the present invention; Figure 2 A flowchart of a method for generating wafer test results provided in Embodiment 2 of the present invention; Figure 3A schematic diagram of some nodes in a tree data structure of a test file provided in the second embodiment of the present invention; Figure 4 A schematic diagram of a process flow of a method for generating wafer test results provided in Embodiment 3 of the present invention; Figure 5 A schematic diagram of a module chain structure provided in Embodiment 3 of the present invention; Figure 6 A schematic diagram of some nodes in a test file in a text format provided in Embodiment 3 of the present invention; Figure 7 A schematic diagram of an example of test file integration provided in Embodiment 3 of the present invention; Figure 8 A schematic structural diagram of a wafer test result generating device provided in a fourth embodiment of the present invention; Fig. 9 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] The technical solution of the present invention is described in detail below through various embodiments.

[0028] Embodiment 1 This embodiment provides a method for generating wafer test results, which can be performed by a corresponding wafer test result generating device, which can be integrated into a wafer test device. Figure 1 The method specifically includes the following steps 101-103.

[0029] Step 101: Acquire multiple test files generated by performing multiple tests on the same wafer.

[0030] In the specific process of wafer testing, the wafer to be tested can be first selected and placed on the test platform. The test platform is usually equipped with various test equipment, such as probe stations and test instruments. Subsequently, the test equipment is used to perform various tests on the semiconductor chips distributed on the wafer, such as electrical characteristics test, functional test, performance test, etc. After each wafer test is completed, the test equipment generates a test file to record the test results of all semiconductor chips tested this time. To ensure the integrity and accuracy of the data, the test files are compressed and encrypted in some cases. Test files usually include a wide range of test details and result information, not just a simple pass / fail mark, for example, they can include the following types of information: 1. Basic information, such as: Wafer number: a number that uniquely identifies each wafer; Chip location: The specific coordinates of the semiconductor chip on the wafer (e.g., X, Y coordinates); Test date and time: Time record of each test; Operator information: Name or ID of the person who performed the test; 2. Test scenarios, such as: Environmental conditions: environmental parameters such as temperature and humidity during testing; Power supply conditions: information such as voltage and frequency of the power supply; Test equipment: model, brand and version of the test equipment used; 3. Test items (1) Functional testing: Verify whether each semiconductor chip functions normally; (2) Electrical characteristics test, such as: Current and voltage measurement: measure the chip’s input / output current and voltage; Power consumption test: power consumption under different working conditions; (3) Performance testing, for example: Timing analysis: measure signal delay time and rise / fall time; Frequency response: Test the performance of the chip at different frequencies; (4) Reliability testing, for example: Thermal testing: stability testing under different temperature conditions; Aging test: performance after long-term operation; 4. Test results, such as: Test data: specific electrical parameters and performance indicators; Pass / Fail determination: whether each semiconductor chip meets the expected standards; Abnormal records: any abnormal conditions and specific parameters found during the test; 5. Data analysis, such as: Yield statistics: the ratio of qualified chips to the total number of chips; Failure analysis: in-depth analysis of the causes of failed chips; Trend analysis: Analyze potential problems in the production process based on historical data.

[0031] In practical applications, in order to verify the performance of semiconductor chips under different conditions (for example, at different temperatures, voltages or signal frequencies) and ensure the accuracy and reliability of the test, the same wafer needs to be tested repeatedly. The repeated testing strategy can be a full coverage method, that is, each test tests all semiconductor chips on the wafer, or a partial sampling method, that is, only a selected part of the semiconductor chips on the wafer is tested each time, but the overall process must ensure that each semiconductor chip is tested at least once, so as to achieve effective verification of the entire batch of chips.

[0032] As a preferred embodiment, before obtaining multiple test files generated by multiple tests on the same wafer, it also includes: performing an initial test on all semiconductor chips on the wafer and recording the test results in a test file; cyclically retesting the semiconductor chips on the wafer that did not meet the standards in the previous test until a preset stop condition is met, wherein each retest result is independently recorded in a test file. The stop condition may be that the number of retests reaches a set threshold. In this preferred embodiment, test resources are concentrated on problem chips, and the test process is optimized, which can not only save test time and resources and reduce test costs, but also ensure that the test results of problem chips are more accurate and reliable, which helps to identify and correct potential manufacturing defects or test errors.

[0033] The multiple test files generated by multiple tests on the same wafer may have various formats, which may depend on the manufacturer of the test equipment and industry standards, such as STDF, JSON or proprietary formats, and may be stored in a designated storage area of ​​the test equipment, such as a monitoring directory in a configuration file. When executing this step 101, these test files stored on the test equipment are read.

[0034] Step 102 : Integrate the multiple test files, wherein for multiple test results of the same semiconductor chip on the wafer, only retain the best test result.

[0035] In this step 102, each test file obtained in step 101 can be read and compared one by one to remove redundancy and update the semiconductor chip test results. The optimal test result refers to the test result with the best performance screened out according to the preset chip quality evaluation standard in multiple tests on the same semiconductor chip. In specific implementation, the redundancy removal and update of the semiconductor chip test results can be achieved by any of the following mechanisms.

[0036] 1. Optimal results screening mechanism ① Preprocess all test files to be integrated and extract the test results of each semiconductor chip.

[0037] ② Score the test results of each semiconductor chip according to predefined chip quality indicators (such as test accuracy, performance parameters, consistency, etc.).

[0038] ③For each semiconductor chip, retain the test result with the highest score and delete the remaining test records.

[0039] 2. Incremental update mechanism ① Set a baseline test file as a test file blueprint.

[0040] ②Process the remaining test files one by one, and for the test results in each file: Compare the semiconductor chip test results with the test results of the corresponding chip in the blueprint; if the new result is better, update the test record in the blueprint.

[0041] After iterative processing of all test files, the blueprint retains the optimal test information for each semiconductor chip.

[0042] 3. Difference comparison mechanism ①Create an empty test file template.

[0043] ②Process all test files to be integrated one by one. For each file: Compare the test records in the blueprint to find new or updated test results; if the new test result is better, update the corresponding original test result in the blueprint; if the test results are exactly the same, skip them to avoid duplication.

[0044] In this way, the blueprint will gradually accumulate the best test results while eliminating duplicate and poor quality results.

[0045] In addition, in order to enhance the maintainability, extensibility and reusability of the code, the present embodiment can construct a module chain structure to implement the multiple test file integration function in step 102. Specifically, the integration task can be decomposed into several independent subtasks, and a special module can be designed for each subtask; then the chain structure is initialized, and in this process, each module is connected to the chain structure as a node string according to the logical order of the integration process, thereby obtaining a complete module chain. Exemplarily, each module in the module chain can inherit an abstract base class, which encapsulates the module's task implementation interface and a pointer to the next node in the chain to ensure smooth collaboration between modules.

[0046] Then, the pre-built module chain is called to integrate the various test files obtained in step 101. Once the module chain is built, the operation of the module chain can be started through a start signal or a program entry point. The frontmost module in the chain is activated first and receives the first test file as input. After each module completes its task, it will find the next module through the pointer of the next node, and call the next module to continue processing based on the task implementation interface of the next module until all modules have completed their respective tasks. In order to process multiple test files, the module chain supports a loop calling mechanism, which means that for each test file to be integrated, the complete link process will be executed, thereby ensuring that all test data can be unified, comprehensive and thoroughly integrated regardless of the number of files.

[0047] The above module chain design scheme, with its dual advantages of modularity and chain structure, significantly enhances the convenience of file integration function maintenance and expansion. Independent module design ensures that the update of a single component does not hinder the overall operation and improves system stability; the chain architecture is flexible to assemble, quickly respond to functional changes, and meet diverse needs.

[0048] Optionally, if multiple test files generated by multiple tests on the same wafer are in non-text format, these test files are first converted to text format before performing the above step 102. When multiple tests are performed on the same wafer, multiple types of test files may be generated, and these files may be in non-text format, such as binary, proprietary format of specific hardware or software, etc. Converting these non-text test files to text format before file integration is a key step to ensure accurate and efficient data integration. Through this conversion process, the reliable access, management and processing efficiency of data can be improved.

[0049] Step 103: Obtain the final test result of the wafer based on the integrated test file.

[0050] In this step, the integrated test file can be directly used as the final test result of the wafer. If the integrated test file is in text format and the original test file is in non-text format, it is necessary to perform a non-text format conversion operation. Alternatively, the abnormal data and erroneous data in the integrated test file can be cleared, and missing data can be filled or excluded to ensure the accuracy and completeness of the final test result. Of course, the integrated data can be further statistically analyzed, and the analysis results can be summarized together with the integrated test file as the final test result of the wafer.

[0051] Embodiment 2 This embodiment optimizes the steps of integrating test files based on the solution of the above embodiment 1. Figure 2 , a wafer test result generating method includes the following steps 201-204.

[0052] Step 201: Acquire multiple test files generated by performing multiple tests on the same wafer.

[0053] This step 201 is the same as step 101 in the first embodiment and will not be described again here.

[0054] Step 202: Select a test file from the multiple test files as a test file template.

[0055] The selection of the test file blueprint can be carried out in any of the following ways: based on the time sequence, the earliest test file or the latest test file is selected as the blueprint; based on the quality of the test results, the test file with the highest yield is selected as the blueprint; based on random sampling, a test file is randomly selected as the blueprint. As a preferred implementation, all the test files obtained in step 201 are sorted by size, and the test file ranked first (largest) is selected as the test file blueprint. This method has the following advantages: Simplify the integration process: Using the largest file as the blueprint means that the file already contains the most comprehensive test results. When integrating other files, you only need to supplement the test results missing in the blueprint or update the test records with better results, which simplifies the complexity of data integration. Reduce data redundancy: The largest file usually covers all or most of the test scenarios, so during the integration process, you can avoid entering duplicate data, reduce data redundancy, and improve the neatness and efficiency of the data set; Improve data integrity: The larger the file used as a blueprint, the more comprehensive the test results it contains in theory. During the integration process, the final data set can be ensured to be as complete as possible, avoiding the omission of important test data. Easy to identify differences: Taking the largest file as the benchmark, it is easier to identify the new or different test results in other files compared with the original, so as to deal with the differences in a targeted manner and ensure the accuracy and timeliness of the integrated data; Optimized storage and processing: In subsequent data analysis and processing, an optimized and integrated blueprint file can reduce data processing time and storage resource consumption because most of the necessary data has been effectively integrated.

[0056] Step 203: Based on each of the remaining test files, perform the following blueprint modification process: Compared with the test file blueprint, a better new test result of the same semiconductor chip in the test file currently based on replaces the corresponding original test result in the test file blueprint; the test result of the new semiconductor chip in the test file currently based on is added to the test file blueprint.

[0057] Exemplarily, the test file records the wafer test results in a tree data structure, including the test point coordinates, test results, test equipment parameters, and test scenarios of the semiconductor chip. This structure distinguishes the test results of different semiconductor chips in the form of branches, and the test result details of each semiconductor chip are described in detail through the hierarchical structure of the test unit child node and its descendant nodes. Each node in the tree structure has its own unique identifier and attribute set in a test file. Typically, the identifiers of each node in all test files generated by multiple tests on the same wafer are different to ensure accurate tracking and differentiation of data. In this way, the identifiers of the test unit node and its descendant nodes representing the test result details of the same semiconductor chip in different test files are different. For example, for a specific semiconductor chip on the wafer: the test unit node NodeA and the child nodes SubNodeA1 and SubNodeA2 in the test file 1 describe the test result details of the chip during the first test; the test unit node NodeB and the child nodes SubNodeB1 and SubNodeB2 in the test file 2 describe the test result details of the chip during the second test. Then, the identifiers of nodes NodeA, SubNodeA1, SubNodeA2, NodeB, SubNodeB1 and SubNodeB2 are different. The identifiers may be distinguished by serial numbers, for example, the identifiers may be embodied as serial numbers.

[0058] In addition, the tree structure may also include basic data definition nodes, which are used to store specific data items related to specific test attributes and establish a reference relationship with the test unit node and its descendant nodes. Specifically, the basic data definition node can be linked to a certain attribute of the test unit node or its descendant nodes, so that the latter can directly reference the content stored in the former. Under this mechanism, the value of a certain attribute of the test unit node and / or its descendant nodes can be simplified to the unique identifier of the referenced basic data definition node, thereby building an efficient data reference relationship. Normally, the basic data definition node is usually used as the terminal node of the tree data structure and no longer has child nodes. It and the test unit child node and its descendant nodes are located in different branches of the tree data structure, ensuring the independence and clarity of the data.

[0059] The benefits of introducing basic data definition nodes in the tree data structure are: 1. Data consistency The basic data definition node provides a centralized management method to store specific data items related to test attributes, which can ensure that the consistency and accuracy of data are maintained when the same data items are referenced in multiple test unit nodes; 2. Reduce redundancy By using basic data to define nodes, you can avoid storing the same data repeatedly in different test unit nodes and their descendant nodes, which reduces redundancy, saves storage space, and reduces potential errors. 3. Easy to maintain When you need to update basic data, you only need to make a modification in the basic data definition node. All test unit nodes and their descendant nodes that reference this node will automatically reflect this change, greatly improving the efficiency of data maintenance. 4. Improve scalability The basic data definition nodes make the tree data structure more scalable; users can easily add new data items without making large-scale modifications to the entire structure, which helps to adapt to future changes in requirements; 5. Clear structure The reference relationship between the basic data definition node and the test unit node and its descendant nodes clearly shows the logical relationship between the data, which helps to understand and manage complex data structures.

[0060] For example, Figure 3 Some nodes in the tree data structure of a test file are shown, as follows: Info: Root node, the starting point for describing wafer test results; Lot: Batch node, a child node of Info, representing a collection of Dies on a wafer, used to track production and testing progress; Unit: test unit node, a child node of Lot, representing a Die in a wafer; Bin: test result classification node, a child node of Unit, indicating the level or classification of the test results, such as good products, defective products, etc. SerialNumber: Die serial number node, child node of Unit; Flow: test scene node, child node of Unit; Test: test item node, child node of Flow; BitString: a binary bit node, a child node of Test, used to indicate the pass / fail status of a test point in a test item; PinMeasure: Pin measurement node, a child node of Test, represents the measurement data of the chip pins, including but not limited to electrical parameters such as current, voltage, and resistance; Evaluation: Evaluation node, a child node of Test, describing the evaluation information of the test item results; PatternResult: Pattern result node, a child node of Test, which describes the test item result after executing a specific test pattern; StructureMeasure: a structure measurement node, a child node of Test, which describes the measurement data of the internal structure of the chip, such as the size of the circuit layout, the layer spacing, etc. Mfg: Test basic information node, a child node of Info, describes the basic background and context of the test, and can contain the following attributes: equipmentId, test equipment number information; equipmentType, test equipment type; mfgAreaName, test location; mfgStepName, test station; operatorId, test operator number; testCode, test program code; Component, a component node and a child node of Mfg, describes the component information directly related to the wafer manufacturing process; BinDesc: a child node of Info, a basic data definition node that describes the test result details; ParamRef: a child node of Info, a basic data definition node that describes the test parameter details; Pattern: a subnode of Info, a basic data definition node that describes the logical relationship between test conditions and expected results; PinRef: a child node of Info, a basic data definition node that describes the pin details involved in the test; TestDesc: a child node of Info, a basic data definition node that describes the test item details; Wafer: A child node of Info, a basic data definition node that describes detailed information about the wafer.

[0061] Based on the test file framework of the tree data structure, the implementation of step 203 can be refined to perform the following operations: Identify the target node in the current test file; wherein the target node includes: a heterogeneous same-core test unit node and its descendant nodes, and a heterogeneous different-core test unit node and its descendant nodes having better chip quality attributes than the test file blueprint; The target node in the current test file and its association with the basic data definition node are updated in the test file blueprint.

[0062] The updating in the test file blueprint may specifically include: 1. Merge different standard and different effect basic data definition nodes Add the different standard and different effect basic data definition node in the current test file to the test file blueprint, and give it a new identifier in the test file blueprint; 2. Migrate the test unit node and its descendant nodes of different standards and cores For the heterogeneous test unit nodes and their descendant nodes in the current test file: first, update the values ​​of the attributes of the basic data definition nodes that are referenced in the attribute set to the identifiers of the corresponding basic data definition nodes in the test file blueprint; then, migrate the entire node to the test file blueprint and assign it a new identifier in the test file blueprint.

[0063] 3. Optimize the test unit nodes of different standards and the same core If the chip quality attributes of the heterogeneous-standard but same-core test unit node in the current test file are better than those of the corresponding node in the test file blueprint, then for the heterogeneous-standard but same-core test unit node and its descendant nodes in the current test file, first, update the values ​​of the attributes of the basic data definition node referenced in the attribute set to the identifier of the corresponding basic data definition node in the test file blueprint; then, replace the heterogeneous-standard but same-core test unit node and its descendant nodes in the current test file with the corresponding node in the test file blueprint, but keep the original identifier of the corresponding node in the test file blueprint unchanged.

[0064] The different-standard but same-effect basic data definition nodes refer to: basic data definition nodes with different identifiers in the current test file and the test file blueprint but with the same key attribute name and value. The key attribute here does not include the attribute of the node identifier, which can be pre-set by those skilled in the art; the different-standard but same-effect basic data definition nodes in the current test file and the test file blueprint are a pair of nodes with a corresponding relationship; Different standard and different effect basic data definition nodes refer to: basic data definition nodes in the current test file that do not have the same identifier and key attribute name and value as any basic data definition node in the test file blueprint; Different-standard same-chip test unit nodes refer to nodes with different identifiers in the current test file and the test file blueprint but representing the same semiconductor chip; A different-standard and different-core test unit node refers to a node in the current test file that does not have the same identifier as any test unit node in the test file blueprint and does not represent the same semiconductor chip.

[0065] Those skilled in the art should understand that other update methods can also be used. For example, for the test unit node and its descendant nodes in the test file currently based on, the association relationship with the basic data definition node in the test file blueprint can be updated first, and its attributes are concentrated to reference the values ​​of the attributes of the basic data definition node with different standards but the same effect, and updated to the identifier of the corresponding basic data definition node with different standards but the same effect in the test file blueprint, and then distinguish between different standards and different cores and different standards and the same core, and migrate or optimize to the test file blueprint in different ways; or, first distinguish between different standards and different cores and different standards and the same core, and migrate or optimize to the test file blueprint in different ways, and then update the association relationship with the basic data definition node in the test file blueprint, and its attributes are concentrated to reference the values ​​of the attributes of the basic data definition node with different standards but the same effect in the test file currently based on, and updated to the identifier of the corresponding basic data definition node with different standards but the same effect in the test file blueprint. This embodiment does not make specific limitations on this.

[0066] Step 204: Obtain the final test result of the wafer based on the modified test file blueprint.

[0067] This step 204 is the same as step 103 in the first embodiment and will not be described again here.

[0068] Embodiment 3 This embodiment is based on all the above embodiments and provides a preferred embodiment. Figure 4 , a method for generating wafer test results, including the following steps 401-406.

[0069] Step 401: Access the configuration file monitoring directory.

[0070] Step 402: Determine whether there is a test file in the directory.

[0071] Initially, the configuration file monitoring directory stores multiple test files generated by multiple tests on the same wafer. If yes, then execute steps 403-405. If no, then jump to step 406.

[0072] Step 403: Read a test file in descending order.

[0073] Step 404: The read test file is used as the current test file and sent to the module chain to modify the test file template.

[0074] In this step 404, see Figure 5 The module chain includes a format conversion module 501, an information recording module 502 and a blueprint modification module 503 which are connected in sequence.

[0075] The current test file sent to the module chain records the wafer test results in a tree data structure and is encrypted and compressed. After decryption and decompression, the format conversion module 501 reads the current test file in a streaming manner. The file contains the node name and the attribute name and byte length contained in each node. It loops through the bytes in the stream and writes the text format file according to the structure of the node name and the attribute name and value contained in it. The data structure of the text format file can be seen in Figure 6 Example, in this example: Unit: test unit, representing a Die in a wafer, contains the following attributes: serialID, Die serial number; siteIndex, for wafer testing, it is a null value and meaningless; seqNumber, Unit serial number; startTimeStamp / endTimeStamp, start time and end time, record the timestamp of the test; chuckId, chuck ID, used to indicate the chuck position on the test machine; Flow: test scenario, including the following attributes: sequence, test scenario sequence number; context, test scenario name; result, test result under the test scenario; startTimestamp / endTimestamp, test start and end timestamp; Test: Test item, including the following properties: isBinnable, whether the test item performs binning operation; testDescId, test item description ID, used to point to the test item detailed description; result, the total result of the test item; componentHash, hash value, presented in the form of 0 and 1, each bit value represents a switch with a specific physical meaning; alarm, alarm flag, indicating whether an abnormality occurs during the test; lowSpecLimit / highSpecLimit, low specification limit and high specification limit, defining the test range; paramRefPtr, parameter reference pointer, used to point to the test parameter detailed description; startTimestamp / endTimestamp, the timestamp of the start and end of the test.

[0076] Then, the information recording module 502 reads the current test file in text format, records the node types and reference relationships in the current test file, and outputs the recording results and the current test file in text format to the blueprint modification module 503. The recording process specifically includes: Determine whether the current test file is the first test file to be linked; If yes, the information recording module 502 records the following contents in the current test file: a. all basic data definition nodes; b. all test unit nodes and their descendant nodes; c. the maximum sequence number of all test unit nodes; d. the maximum sequence number of all basic data definition nodes of the same type; If not, the information recording module 502 records the following contents in the current test file: a. different standards but the same effect basic data definition nodes and different standards but different effects basic data definition nodes; b. different standards but the same core test unit nodes and different standards but different core test unit nodes; c. the reference relationship between all test unit nodes and their descendant nodes and the basic data definition nodes.

[0077] Then, the blueprint modification module 503 determines whether the current test file is the first test file to be linked. If yes, the blueprint modification module 503 sets the current test file as the test file blueprint and saves it. If no, the blueprint modification module 503 performs the following steps: (1) Merge different standard and different effect basic data definition nodes Add the different standard and different effect basic data definition nodes in the current test file to the test file blueprint, and reset their serial numbers to: the maximum serial number of all the same basic data definition nodes in the test file blueprint plus 1; (2) Migrate the test unit node with different standards and cores and its descendant nodes ① Update the values ​​of the attributes of the heterogeneous-standard and heterogeneous-core test unit nodes and their descendant nodes that reference the basic data definition nodes in the current test file to the serial numbers of the corresponding basic data definition nodes in the test file blueprint; ② Add the heterogeneous standard and heterogeneous core test unit node and its descendant nodes in the current test file to the corresponding node in the test file blueprint, where the serial number of the heterogeneous standard and heterogeneous core test unit node is reset to: the maximum serial number of all test unit nodes in the test file blueprint plus 1; (3) Optimize the different-standard same-core test unit node and its descendant nodes Compare the chip quality attributes of the different-standard but same-core test units in the current test file with those in the test file blueprint to determine whether the former is better; If the former is better, perform the following file modification operations in sequence: ① Update the values ​​of the attributes of the different-standard but same-core test unit nodes and their descendant nodes that reference the basic data definition nodes in the current test file to the serial numbers of the corresponding basic data definition nodes in the test file blueprint; ② Replace the corresponding node in the test file blueprint with the different-standard but same-core test unit node and its descendant nodes in the current test file, but keep the serial number of the different-standard but same-core test unit node unchanged; If the latter is better, the file modification operations ① and ② in (3) above will not be performed.

[0078] Figure 7 A specific example of integrating a test file template with the current test file is given.

[0079] Step 405: Delete the test file input to the module chain this time under the configuration file monitoring directory. Return to step 402 to continue execution.

[0080] Step 406: Convert the test file template into a set non-text format for output.

[0081] The module chain will eventually output a deduplicated and complete test file blueprint. In this step 406, each node in the text-formatted test file blueprint can be converted into a set non-text format one by one according to the data structure and type defined in the spec.xml specification file. Typically, the non-text format is the test file format stored in the configuration file monitoring directory at the beginning. The spec.xml specification file defines the complete structure of the test file, including the data structure and type information of each node, indicating which attributes are required and which are optional. In the process of generating a test file in a non-text format, the definition in the spec.xml specification file will be read, and the data will be converted and stored according to the specified structure and data type. Exemplarily, the test file blueprint converted into a non-text format can be output to the configuration file monitoring directory.

[0082] Embodiment 4 This embodiment provides a wafer test result generating device, which can be used to execute the wafer test result generating method described in the embodiment of the present invention, and can be implemented by software and / or hardware and integrated in a wafer test device. Figure 8 , the device specifically includes the following units: The test file acquisition unit 801 is used to acquire multiple test files generated by performing multiple tests on the same wafer; A test file integration unit 802 is used to integrate the multiple test files, wherein for multiple test results of the same semiconductor chip on the wafer, only the best test result is retained; The test result generating unit 803 is used to obtain the final test result of the wafer based on the integrated test file.

[0083] The wafer test result generating device of this embodiment can implement the wafer test result generating method described in any of the aforementioned embodiments, and its implementation principle and corresponding technical effects are basically the same, which will not be repeated here.

[0084] In a specific implementation, the test file integration unit 802 may include: A blueprint determination subunit 8021 is used to select a test file from the multiple test files as a test file blueprint; The blueprint modification subunit 8022 is used to perform the following blueprint modification processing based on each remaining test file in turn: Compared with the test file blueprint, a better new test result of the same semiconductor chip in the test file currently based on replaces the corresponding original test result in the test file blueprint; the test result of the new semiconductor chip in the test file currently based on is added to the test file blueprint.

[0085] Exemplarily, the blueprint modification subunit 8022 is specifically used for: Identify the target node in the current test file; wherein the target node includes: a heterogeneous same-core test unit node and its descendant nodes having better chip quality attributes than the test file blueprint, and a heterogeneous different-core test unit node and its descendant nodes; The target node in the current test file and its association with the basic data definition node are updated in the test file blueprint.

[0086] Furthermore, the wafer test result generating device provided in this embodiment further includes a test file sorting unit 804, which is used to sort the multiple test files by size; The blueprint determination subunit 8021 is specifically used to select the test file ranked first as the test file blueprint.

[0087] As a preferred implementation, the test file integration unit 802 is specifically configured to call a pre-built module chain to integrate the multiple test files.

[0088] The wafer test result generating device provided in this embodiment also includes: The format conversion unit 805 is used to convert the multiple test files into text formats before the test file integration unit 802 integrates the multiple test files; The test file generation unit 806 is used to: perform an initial test on all semiconductor chips on the wafer and record the test results in a test file; cyclically retest the semiconductor chips on the wafer that did not meet the test standards in the previous test until the preset stop condition is met, wherein each retest result is independently recorded in a test file.

[0089] Fig. 9 FIG. 1 is a schematic diagram of the structure of an embodiment of an electronic device of the present invention, which can implement the process of the embodiment of the method of the present invention, such as Fig. 9As shown, the above-mentioned electronic device may include: a shell 91, a processor 92, a memory 93, a circuit board 94 and a power supply circuit 95, wherein the circuit board 94 is arranged inside the space enclosed by the shell 91, and the processor 92 and the memory 93 are arranged on the circuit board 94; the power supply circuit 95 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 93 is used to store executable program codes; the processor 92 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 93, so as to execute the wafer test result generation method described in any of the above-mentioned embodiments.

[0090] The specific execution process of the above steps by the processor 92 and the steps further executed by the processor 92 by running the executable program code can be found in the description of the method embodiment of the present invention, which will not be repeated here.

[0091] This electronic device exists in many forms, including but not limited to: (1) Server: A device that provides computing services. The server consists of a processor, hard disk, memory, system bus, etc. The server has a similar architecture to general computers, but because it needs to provide highly reliable services, it has higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability. (2) Other electronic equipment with data processing and communication functions.

[0092] Furthermore, an embodiment of the present invention also provides a computer-readable storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement the wafer test result generating method described in the above embodiment.

[0093] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0094] In the embodiments of the present invention, the term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0095] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0096] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0097] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0098] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0099] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for generating wafer test results, characterized in that: The method comprises: Obtain multiple test files generated by multiple tests on the same wafer; integrating the plurality of test files, wherein for a plurality of test results of a same semiconductor chip on a wafer, only an optimal test result is retained; Based on the integrated test files, the final test results of the wafer are obtained.

2. The method according to claim 1, characterized in that The integrating the multiple test files comprises: Selecting a test file from the multiple test files as a test file template; Based on each of the remaining test files, perform the following blueprint modification process: Compared with the test file blueprint, a new test result of the same semiconductor chip that is better in the test file currently based on replaces the corresponding original test result in the test file blueprint; the test result of the new semiconductor chip in the test file currently based on is added to the test file blueprint.

3. The method according to claim 2, characterized in that The blueprint modification process is performed based on each of the remaining test files in sequence, specifically including: Identify the target node in the current test file; wherein the target node includes: a heterogeneous same-core test unit node and its descendant nodes having better chip quality attributes than the test file blueprint, and a heterogeneous different-core test unit node and its descendant nodes; The target node in the current test file and its association with the basic data definition node are updated in the test file blueprint.

4. The method according to claim 2, characterized in that: Before selecting a test file from the plurality of test files, the method further includes: sorting the plurality of test files by size; The step of selecting a test file from the plurality of test files as a test file template includes: selecting a test file ranked first as the test file template.

5. The method according to claim 1, characterized in that The integrating the multiple test files comprises: A pre-built module chain is called to integrate the plurality of test files.

6. The method according to claim 1, characterized in that Before integrating the plurality of test files, the method further includes: The multiple test files are converted into text formats.

7. The method according to any one of claims 1 to 6, characterized in that Before acquiring multiple test files generated from multiple tests on the same wafer, also include: Perform initial testing on all semiconductor chips on the wafer and record the test results in a test file; The semiconductor chips on the wafer that did not meet the previous test standards are retested cyclically until the preset stop condition is met, and each retest result is independently recorded in a test file.

8. A wafer test result generating device, characterized in that: include: A test file acquisition unit, used to acquire multiple test files generated by performing multiple tests on the same wafer; a test file integration unit, configured to integrate the plurality of test files, wherein for a plurality of test results of the same semiconductor chip on the wafer, only the best test result is retained; The test result generating unit is used to obtain the final test result of the wafer based on the integrated test file.

9. The device according to claim 8, characterized in that The test file integration unit includes: A blueprint determination subunit, used to select a test file from the multiple test files as a test file blueprint; The blueprint modification subunit is used to perform the following blueprint modification processing based on each remaining test file in turn: Compared with the test file blueprint, a new test result of the same semiconductor chip that is better in the test file currently based on replaces the corresponding original test result in the test file blueprint; the test result of the new semiconductor chip in the test file currently based on is added to the test file blueprint.

10. The device according to claim 9, characterized in that The blueprint modification subunit is specifically used for: Identify the target node in the current test file; wherein the target node includes: a heterogeneous same-core test unit node and its descendant nodes having better chip quality attributes than the test file blueprint, and a heterogeneous different-core test unit node and its descendant nodes; The target node in the current test file and its association with the basic data definition node are updated in the test file blueprint.

11. The device according to claim 9, characterized in that The device also includes a test file sorting unit, which is used to sort the multiple test files by size; The blueprint determination subunit is specifically used to select the test file ranked first as the test file blueprint.

12. The device according to claim 8, characterized in that The test file integration unit is specifically used to call a pre-built module chain to integrate the multiple test files.

13. The device according to claim 8, characterized in that The device also includes: The format conversion unit is used to convert the multiple test files into text formats before the test file integration unit integrates the multiple test files.

14. The device according to any one of claims 8 to 13, characterized in that The device also includes a test file generating unit, which is used to: Perform initial testing on all semiconductor chips on the wafer and record the test results in a test file; The semiconductor chips on the wafer that did not meet the previous test standards are retested cyclically until the preset stop condition is met, and each retest result is independently recorded in a test file.

15. An electronic device, characterized in that: The electronic device comprises: a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program codes; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the method described in any one of the preceding claims 1-7.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the method described in any one of claims 1 to 7.

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