Computing device and box opening detection method

Abstract

The embodiment of the invention provides a computing device and a box opening detection method, the computing device comprises a box opening trigger circuit, a shutdown detection circuit, a power supply circuit, a programmable logic device and a controller, the shutdown detection circuit is connected between the box opening trigger circuit and the programmable logic device, and the controller is connected with the programmable logic device. When the computing device is powered off, the power supply circuit supplies power to the box opening trigger circuit and the shutdown detection circuit, and the programmable logic device and the controller are in a power-off state; when a case of the computing equipment is opened, the case opening trigger circuit sends a first case opening trigger signal to the shutdown detection circuit; the shutdown detection circuit generates and latches a first state signal based on the first box opening trigger signal; after the computing device is powered on, the controller obtains the first state signal from the latch of the shutdown detection circuit through the programmable logic device and determines that the case opening event exists when the computing device is in the shutdown state based on the first state signal, and the power consumption for detecting the case opening event is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of computing devices, and in particular to a computing device and an unpacking detection method. Background Art

[0002] In order to meet the physical anti-intrusion requirements of the server required by the customer, the server usually needs to be equipped with an unpacking detection function.

[0003] In the related art, when a server detects an unpacking event in a shutdown state, the server consumes a large amount of power. Summary of the invention

[0004] Embodiments of the present application provide a computing device and a method for detecting an unpacking event. When the computing device detects an unpacking event in a shutdown state, it is beneficial to reduce the power consumption of the computing device in detecting an unpacking event in a shutdown state.

[0005] In a first aspect, an embodiment of the present application provides a computing device, including: an unpacking trigger circuit, a shutdown detection circuit, a power supply circuit, a programmable logic device, and a controller, wherein the shutdown detection circuit is connected between the unpacking trigger circuit and the programmable logic device, and the controller is connected to the programmable logic device. When the computing device is powered off, the power supply circuit supplies power to the unpacking trigger circuit and the shutdown detection circuit, and the programmable logic device and the controller are in a power-off state;

[0006] The unpacking trigger circuit sends a first unpacking trigger signal to the shutdown detection circuit when the chassis of the computing device is opened;

[0007] The shutdown detection circuit includes a latch, the shutdown detection circuit generates a first state signal based on the first unpacking trigger signal, and the latch is used to latch the first state signal;

[0008] After the computing device is powered on, the controller obtains a first state signal from the latch through a programmable logic device, and determines based on the first state signal that an unpacking event occurs when the computing device is in a shutdown state.

[0009] It should be noted that when the computing device is powered off, the programmable logic device and the controller are in a power-off state, which means that when the computing device is powered off, the power supply circuit that provides power to enable the computing device to detect an unpacking event in the shutdown state does not supply power to the programmable logic device and the controller, resulting in a power-free state for the programmable logic device and the controller.

[0010] In the above technical solution, the computing device can supply power to the unpacking trigger circuit and the shutdown detection circuit through the power supply circuit when the computing device is powered off, so that the unpacking trigger circuit and the shutdown detection circuit can latch the first state signal corresponding to the unpacking event, so that after the computing device is powered on, the controller can obtain the first state signal in time through the programmable logic device, and quickly determine the unpacking event in the shutdown state according to the first state signal, so as to ensure the safety of the computing device; and, when the computing device is powered off, the power supply circuit supplies power to the circuit (unpacking trigger circuit, shutdown detection circuit) for realizing basic detection functions, and the shutdown detection circuit includes a latch for latching the first state signal, and the latch is a simple circuit storage unit with very low power consumption. At the same time, there is no need to power the programmable logic device and the controller with large current consumption, which effectively reduces the power consumption of the computing device in detecting the unpacking event in the shutdown state.

[0011] In a possible implementation, the unpacking trigger circuit includes a switch, the chassis includes a chassis cover, a first end of the switch is connected to the chassis cover, the chassis cover is connected to the ground, a second end of the switch is connected to the power supply circuit, and one end of the shutdown detection circuit is connected between the second end of the switch and the power supply circuit;

[0012] When the case cover is opened, the switch is disconnected, and the case opening trigger circuit, under the action of the power supply circuit, sends a first case opening trigger signal to the shutdown detection circuit.

[0013] In the above technical solution, by connecting the original case cover of the computing device to the case opening trigger circuit, the structure is simple, and no other sensor is needed to detect whether the case cover is opened, which greatly reduces the cost. The switch can enable the computing device to quickly and agilely detect the open and closed state of the case cover, and accurately transmit the first case opening trigger signal to the shutdown detection circuit, so that the computing device can timely detect the case opening detection event in the shutdown state, thereby ensuring the safety of the computing device.

[0014] In a possible implementation, the latch is a NAND latch, and the shutdown detection circuit further includes a first metal-oxide semiconductor MOS tube;

[0015] The set end of the NAND latch is connected to the drain of the first MOS transistor, the drain of the first MOS transistor is also connected to the power supply circuit, the gate of the first MOS transistor is connected between the second end of the switch and the power supply circuit, and the source of the first MOS transistor is connected to the ground;

[0016] The reset end of the NAND gate latch is connected to the programmable logic device and the power supply circuit respectively;

[0017] The output end of the NAND latch is connected to the programmable logic device;

[0018] When the gate of the first MOS tube receives the first box-opening trigger signal, the first MOS tube is turned on and sends an initial state signal to the NAND latch, so that the NAND latch generates a first state signal based on the initial state signal.

[0019] In the above technical solution, through the NAND gate latch and the first MOS tube in the shutdown detection circuit, after the chassis cover is opened, the first unpacking trigger signal sent by the unpacking trigger circuit can be converted into a first state signal, and the first state signal can be stably latched. Even if the chassis cover is repeatedly opened and closed afterwards, the first state signal previously latched by the NAND gate latch will not be lost, so that after the computing device is powered on, the controller can quickly obtain the first state signal from the NAND gate latch through the programmable logic device, and determine the unpacking event in the shutdown state according to the first state signal, thereby ensuring the security of the computing device.

[0020] In one possible implementation, the shutdown detection circuit also includes a first voltage-dividing resistor and a second voltage-dividing resistor, the drain of the first MOS tube is connected to the power supply circuit through the first voltage-dividing resistor, and the reset end of the NAND gate latch is connected to the power supply circuit through the second voltage-dividing resistor, and the resistance value of the second voltage-dividing resistor is greater than the resistance value of the first voltage-dividing resistor.

[0021] In the above technical solution, under the voltage-dividing effect of the first voltage-dividing resistor and the second voltage-dividing resistor, by controlling the resistance value of the second voltage-dividing resistor to be greater than the resistance value of the first voltage-dividing resistor, it can be ensured that the first MOS tube of the shutdown detection circuit is turned on when the first unpacking trigger signal is received, and it can be ensured that the reset end of the NAND gate latch connected to the second voltage-dividing resistor is at a high level, so that the NAND gate latch can generate a first state signal based on the initial state signal, so that after the computing device is powered on, the controller can quickly obtain the first state signal from the NAND gate latch through the programmable logic device, and determine the unpacking event in the shutdown state according to the first state signal, thereby ensuring the security of the computing device.

[0022] In a possible implementation, the latch is a NAND latch, and the shutdown detection circuit further includes a first metal-oxide semiconductor MOS transistor, a first voltage-dividing resistor, and a second voltage-dividing resistor;

[0023] The set end of the NAND latch is connected to the drain of the first MOS tube, the drain of the first MOS tube is also connected to the first end of the first voltage-dividing resistor, the second end of the first voltage-dividing resistor is connected to the power supply circuit, the gate of the first MOS tube is connected between the second end of the switch and the power supply circuit, and the source of the first MOS tube is connected to the ground;

[0024] The reset end of the NAND latch is connected to the first end of the second voltage-dividing resistor and the programmable logic device respectively, and the second end of the second voltage-dividing resistor is connected to the power supply circuit;

[0025] The output end of the NAND latch is connected to the programmable logic device.

[0026] In the above technical scheme, through the joint action of the NAND gate latch, the first MOS tube, the first voltage-dividing resistor and the second voltage-dividing resistor in the shutdown detection circuit, after the chassis cover is opened, the first unpacking trigger signal sent by the unpacking trigger circuit can be converted into a first state signal, and the first state signal can be stably latched. Even if the chassis cover is repeatedly opened and closed, the first state signal previously latched by the NAND gate latch will not be lost, so that after the computing device is powered on, the controller can quickly obtain the first state signal from the NAND gate latch through the programmable logic device, and determine the unpacking event in the shutdown state according to the first state signal, thereby ensuring the safety of the computing device.

[0027] In a possible implementation, the computing device further includes a power control circuit, and the shutdown detection circuit further includes a third voltage-dividing resistor and a fourth voltage-dividing resistor, a first resistance value of the fourth voltage-dividing resistor is less than a second resistance value of the third voltage-dividing resistor, and a difference between the second resistance value and the first resistance value is greater than a preset threshold value;

[0028] A first end of the third voltage-dividing resistor is connected to the source of the first MOS tube, and a second end of the third voltage-dividing resistor is connected to the ground;

[0029] A first end of the fourth voltage-dividing resistor is connected to a first end of the power control circuit, and a second end of the fourth voltage-dividing resistor is connected between the source of the first MOS tube and the third voltage-dividing resistor;

[0030] The second end of the power control circuit is connected to the power supply circuit. After the computing device is powered on, the power supply voltage of the power control circuit is greater than the power supply voltage of the power supply circuit. The power supply circuit is in a non-powered state under the action of the power control circuit. The power control circuit supplies power to the unpacking trigger circuit, the shutdown detection circuit, the programmable logic device and the controller. The first NMOS tube is in a cut-off state under the voltage dividing action of the third voltage dividing resistor and the fourth voltage dividing resistor.

[0031] In the above technical solution, by controlling the power supply voltage of the power control circuit to be greater than the power supply voltage of the power supply circuit, the power supply circuit does not need to be powered when the computing device is powered on, which is beneficial to saving the power supply loss of the power supply circuit; by setting the third voltage divider circuit and the fourth voltage divider resistor, it is ensured that the first NMOS tube is in the cut-off state after the computing device is powered on, so that the shutdown detection circuit maintains a stable state after startup, and the output signal of the shutdown detection circuit is not affected by the signal of the unpacking signal detection circuit, thereby reducing the power supply loss of the power control circuit.

[0032] In a possible implementation, the latch is a NOR latch, and the shutdown detection circuit further includes a fifth voltage-dividing resistor, wherein:

[0033] The set end of the NOR gate latch is connected between the second end of the switch and the power supply circuit;

[0034] The reset end of the NOR gate latch is connected to the first end of the fifth voltage-dividing resistor and the programmable logic device respectively, and the second end of the fifth voltage-dividing resistor is connected to the ground;

[0035] The output end of the NOR gate latch is connected to the programmable logic device.

[0036] In the above technical solution, by providing a NOR latch in the shutdown detection circuit, the structure of the shutdown detection circuit can be made simpler, and the power consumption and cost can be lowered.

[0037] In a possible implementation, the shutdown detection circuit further includes a first signal buffer and a second signal buffer, wherein:

[0038] An input end of the first signal buffer is connected to an output end of the latch, and an output end of the first signal buffer is connected to a programmable logic device;

[0039] The input end of the second signal buffer is connected to the programmable logic device, and the output end of the second signal buffer is connected to the reset end of the latch.

[0040] In the above technical solution, the computing device can amplify and isolate the first state signal output by the latch output terminal by setting a first signal buffer to ensure that the programmable logic device accurately and stably obtains the first state signal; and can amplify and isolate the reset signal output by the programmable logic device by setting a second signal buffer to ensure that the reset terminal of the latch accurately and stably obtains the reset signal.

[0041] In a possible implementation, the computing device further includes a power-on detection circuit and a power control circuit, and the power-on detection circuit includes a second MOS tube, wherein:

[0042] The gate of the second MOS tube is connected to the second end of the switch;

[0043] The drain of the second MOS tube is connected to the power control circuit and the programmable logic device respectively;

[0044] The source of the second MOS tube is connected to the ground.

[0045] In the above technical scheme, a shutdown detection circuit is separately provided to feedback the unpacking event of the computing device in the shutdown state, and a startup detection circuit is separately provided to feedback the unpacking event of the computing device in the startup state. This allows the computing device to realize independent detection of unpacking events of the computing device in different working states, and real-time detection of unpacking events in the startup state, thereby avoiding mutual influence between the startup detection circuit and the shutdown detection circuit; the computing device can realize the all-weather unpacking detection function, which is beneficial to ensuring the security of the computing device.

[0046] In a possible implementation, after the computing device is powered on, the unpacking trigger circuit sends a second unpacking trigger signal to the power-on detection circuit when the chassis cover is opened;

[0047] The power-on detection circuit generates a second state signal according to the second unpacking trigger signal, and outputs the second state signal to the programmable logic device;

[0048] The controller controls the programmable logic device to obtain a second status signal, and determines, based on the second status signal, that an unpacking event occurs when the computing device is in a power-on state.

[0049] In the above technical solution, the computing device, on the basis of realizing the detection of unpacking events when the computing device is in the shutdown state, can also realize real-time detection of unpacking events when the computing device is in the powered-on state through the power-on detection circuit, so that the computing device can realize the unpacking detection function around the clock, which is beneficial to ensuring the security of the computing device.

[0050] In one possible implementation, after determining that an unpacking event occurs when the computing device is in a shutdown state, the controller writes event information of the unpacking event into a target memory and / or an operation log of the controller, and sends a reset instruction to the programmable logic device;

[0051] The programmable logic device generates a reset signal in response to the reset instruction, and sends the reset signal to the reset terminal of the latch through the second signal buffer;

[0052] The latch performs a reset process on an output terminal of the latch based on a reset signal.

[0053] In the above technical solution, by recording the event information of the unpacking event in the operation log or writing it into the target memory, the user can quickly and timely discover the unpacking event of the computing device based on the operation log, so as to avoid physical intrusion of the computing device and ensure the security of the computing device. By resetting the latch, after the computing device is shut down, the shutdown detection circuit can continue to detect the unpacking event when the computing device is in the shutdown state.

[0054] In a second aspect, an embodiment of the present application provides an unpacking detection method, which is applied to a computing device, wherein the computing device includes an unpacking trigger circuit, a shutdown detection circuit, a power supply circuit, a programmable logic device, and a controller, wherein the shutdown detection circuit is connected between the unpacking trigger circuit and the programmable logic device, and the controller is connected to the programmable logic device. When the computing device is powered off, the power supply circuit supplies power to the unpacking trigger circuit and the shutdown detection circuit, and the programmable logic device and the controller are in a power-off state; the method includes:

[0055] The unpacking trigger circuit sends a first unpacking trigger signal to the shutdown detection circuit when the chassis of the computing device is opened;

[0056] The shutdown detection circuit includes a latch, the shutdown detection circuit generates a first state signal based on the first unpacking trigger signal, and the latch is used to latch the first state signal;

[0057] After the computing device is powered on, the controller obtains a first state signal from the latch through a programmable logic device, and determines based on the first state signal that an unpacking event occurs when the computing device is in a shutdown state.

[0058] In the above technical solution, when the computing device is powered off, the power supply circuit can be used to supply power to the unpacking trigger circuit and the shutdown detection circuit, so that the unpacking trigger circuit and the shutdown detection circuit can latch the first state signal corresponding to the unpacking event, so that after the computing device is powered on, the controller can obtain the first state signal in time through the programmable logic device, and quickly determine the unpacking event in the shutdown state according to the first state signal, so as to ensure the safety of the computing device; and, when the computing device is powered off, the power supply circuit supplies power to the circuit (unpacking trigger circuit, shutdown detection circuit) for realizing the basic detection function, and the shutdown detection circuit includes a latch for latching the first state signal, and the latch is a simple circuit storage unit with very low power consumption. At the same time, there is no need to power the programmable logic device and the controller with large current consumption, which effectively reduces the power consumption of the computing device in detecting the unpacking event in the shutdown state.

[0059] In a third aspect, an embodiment of the present application provides an unpacking detection method, which is applied to a controller of a computing device, wherein the computing device further includes an unpacking trigger circuit, a shutdown detection circuit, a power supply circuit, and a programmable logic device, wherein the shutdown detection circuit is connected between the unpacking trigger circuit and the programmable logic device, and the controller is connected to the programmable logic device. When the computing device is powered off, the power supply circuit supplies power to the unpacking trigger circuit and the shutdown detection circuit, and the programmable logic device and the controller are in a power-off state; the method includes:

[0060] After the computing device is powered on, the programmable logic device is controlled to obtain a first state signal from a latch, the latch is located in the shutdown detection circuit, the latch is used to latch the first state signal, the first state signal is generated by the shutdown detection circuit based on the first unboxing trigger signal, and the first unboxing trigger signal is sent by the unboxing trigger circuit to the shutdown detection circuit when the chassis of the computing device is opened;

[0061] An unpacking event is determined based on the first status signal when the computing device is in a shutdown state.

[0062] In the above technical solution, when the computing device is powered off, the power supply circuit can be used to supply power to the unpacking trigger circuit and the shutdown detection circuit, so that the unpacking trigger circuit and the shutdown detection circuit can latch the first state signal corresponding to the unpacking event, so that after the computing device is powered on, the controller can obtain the first state signal in time through the programmable logic device, and quickly determine the unpacking event in the shutdown state according to the first state signal, so as to ensure the safety of the computing device; and, when the computing device is powered off, the power supply circuit supplies power to the circuit (unpacking trigger circuit, shutdown detection circuit) for realizing the basic detection function, and the shutdown detection circuit includes a latch for latching the first state signal, and the latch is a simple circuit storage unit with very low power consumption. At the same time, there is no need to power the programmable logic device and the controller with large current consumption, which effectively reduces the power consumption of the computing device in detecting the unpacking event in the shutdown state.

[0063] In a possible implementation, after determining that an unpacking event occurs when the computing device is in a shutdown state, the method further includes:

[0064] Writing event information of the unpacking event into the target storage and / or the operation log of the controller;

[0065] A reset instruction is sent to the programmable logic device, the reset instruction is used to instruct the programmable logic device to generate a reset signal, and a reset signal is sent to the reset end of the latch, the reset signal is used to instruct the latch to reset the output end of the latch.

[0066] In the above technical solution, by recording the event information of the unpacking event in the operation log or writing it into the target memory, the user can quickly and timely discover the unpacking event of the computing device based on the operation log, so as to avoid physical intrusion of the computing device and ensure the security of the computing device. By resetting the latch, after the computing device is shut down, the shutdown detection circuit can continue to detect the unpacking event when the computing device is in the shutdown state.

[0067] In a possible implementation, the computing device further includes a power-on detection circuit and a power control circuit, the power control circuit is connected to the power supply circuit, the power-on detection circuit is respectively connected to the power supply circuit, the power control circuit, the unpacking trigger circuit and the programmable logic device, when the computing device is powered on, the power supply voltage of the power control circuit is greater than the power supply voltage of the power supply circuit, the power supply circuit is in a non-powered state under the action of the power control circuit, and the power control circuit supplies power to the unpacking trigger circuit, the shutdown detection circuit, the power-on detection circuit, the programmable logic device and the controller; the method further includes:

[0068] Controlling the programmable logic device to obtain a second state signal, where the second state signal is generated by the power-on detection circuit based on a second unboxing trigger signal, where the second unboxing trigger signal is sent by the unboxing trigger circuit to the power-on detection circuit when the chassis of the computing device is opened;

[0069] It is determined based on the second status signal that an unpacking event occurs when the computing device is in a powered-on state.

[0070] In the above technical scheme, the method can realize the real-time detection of unpacking events of the computing device in the powered-on state through the power-on detection circuit on the basis of realizing the detection of unpacking events of the computing device in the powered-on state, so that the computing device can realize the unpacking detection function around the clock, which is beneficial to ensure the security of the computing device.

[0071] In a possible implementation, the method may further include:

[0072] After the computing device is powered on, a first query instruction is sent to the programmable logic device, where the first query instruction is used to instruct the programmable logic device to obtain a current latch signal from the latch;

[0073] Obtaining first response information sent by the programmable logic device;

[0074] A first status signal is acquired according to the first response information.

[0075] In the above technical solution, the controller can obtain the first state signal from the latch through the programmable logic device, and accurately determine whether the computing device has an unpacking event in the shutdown state according to the first state signal. In addition, this process is conducive to realizing the reuse of the programmable logic device in the computing device and reducing the waste of GPIO resources in the controller.

[0076] In a possible implementation, the method may further include:

[0077] Sending a second query instruction to the programmable logic device, where the second query instruction is used to instruct the programmable logic device to obtain a current output signal of the power-on detection circuit;

[0078] Obtaining second response information sent by the programmable logic device;

[0079] A second status signal is acquired according to the second response information.

[0080] In the above technical solution, the controller can obtain the second state signal output by the power-on detection circuit through the programmable logic device, and accurately determine whether the computing device has an unpacking event in the power-on state according to the second state signal. In addition, this process is conducive to realizing the reuse of the programmable logic device in the computing device and reducing the waste of GPIO resources in the controller.

[0081] In a possible implementation, after sending the first query instruction to the programmable logic device, the method may further include:

[0082] After the computing device is powered on, obtaining third response information sent by the programmable logic device;

[0083] Acquire a third state signal according to the third response information;

[0084] It is determined based on the third status signal that there is no unpacking event when the computing device is in the shutdown state.

[0085] In the above technical solution, the controller can also obtain the third state signal from the latch through the programmable logic device, so that the controller can accurately determine that there is no unpacking event when the computing device is in the shutdown state. In addition, this process is conducive to realizing the reuse of the programmable logic device in the computing device and reducing the waste of GPIO resources in the controller.

[0086] In a possible implementation, after sending the second query instruction to the programmable logic device, the method may further include:

[0087] Acquire fourth response information sent by the programmable logic device;

[0088] Acquire a fourth state signal according to the fourth response information;

[0089] It is determined based on the fourth state signal that no unpacking event occurs when the computing device is in the power-on state.

[0090] In the above technical solution, the controller can also obtain the fourth state signal output by the power-on detection circuit through the programmable logic device, and accurately determine that there is no unpacking event in the computing device in the power-on state according to the fourth state signal. In addition, this process is conducive to realizing the reuse of the programmable logic device in the computing device and reducing the waste of GPIO resources in the controller.

[0091] In a fourth aspect, an embodiment of the present application provides a controller, which is applied to a computing device, wherein the computing device further includes an unpacking trigger circuit, a shutdown detection circuit, a power supply circuit, and a programmable logic device, wherein the shutdown detection circuit is connected between the unpacking trigger circuit and the programmable logic device, and the controller is connected to the programmable logic device. When the computing device is powered off, the power supply circuit supplies power to the unpacking trigger circuit and the shutdown detection circuit, and the programmable logic device and the controller are in a power-off state; the controller includes:

[0092] The acquisition module is used to control the programmable logic device to acquire a first state signal from a latch after the computing device is powered on. The latch is located in the shutdown detection circuit. The latch is used to latch the first state signal. The first state signal is generated by the shutdown detection circuit based on the first unboxing trigger signal. The first unboxing trigger signal is sent by the unboxing trigger circuit to the shutdown detection circuit when the chassis of the computing device is opened.

[0093] The processing module is used for determining, based on the first status signal, that an unpacking event occurs when the computing device is in a shutdown state.

[0094] In the above technical solution, when the computing device is powered off, the power supply circuit can be used to supply power to the unpacking trigger circuit and the shutdown detection circuit, so that the unpacking trigger circuit and the shutdown detection circuit can latch the first state signal corresponding to the unpacking event, so that after the computing device is powered on, the controller can obtain the first state signal in time through the programmable logic device, and quickly determine the unpacking event in the shutdown state according to the first state signal, so as to ensure the safety of the computing device; and, when the computing device is powered off, the power supply circuit supplies power to the circuit (unpacking trigger circuit, shutdown detection circuit) for realizing the basic detection function, and the shutdown detection circuit includes a latch for latching the first state signal, and the latch is a simple circuit storage unit with very low power consumption. At the same time, there is no need to power the programmable logic device and the controller with large current consumption, which effectively reduces the power consumption of the computing device in detecting the unpacking event in the shutdown state.

[0095] In a possible implementation, after determining that there is an unpacking event when the computing device is in a shutdown state, the controller further includes a sending module, wherein:

[0096] The processing module is further used to write the event information of the unpacking event into the target storage and / or the operation log of the controller;

[0097] The sending module is used to send a reset instruction to the programmable logic device, the reset instruction is used to instruct the programmable logic device to generate a reset signal, and send a reset signal to the reset end of the latch, the reset signal is used to instruct the latch to reset the output end of the latch.

[0098] In a possible implementation, the computing device further includes a power-on detection circuit and a power control circuit, the power control circuit is connected to the power supply circuit, the power-on detection circuit is respectively connected to the power supply circuit, the power control circuit, the unpacking trigger circuit and the programmable logic device, when the computing device is powered on, the power supply voltage of the power control circuit is greater than the power supply voltage of the power supply circuit, the power supply circuit is in a non-powered state under the action of the power control circuit, and the power control circuit supplies power to the unpacking trigger circuit, the power-off detection circuit, the power-on detection circuit, the programmable logic device and the controller;

[0099] The acquisition module is further used to control the programmable logic device to acquire a second state signal, where the second state signal is generated by the power-on detection circuit based on the second unboxing trigger signal, and the second unboxing trigger signal is sent by the unboxing trigger circuit to the power-on detection circuit when the chassis of the computing device is opened;

[0100] The processing module is further configured to determine, based on the second status signal, that an unpacking event occurs when the computing device is in a power-on state.

[0101] In a possible implementation, the sending module is further used to send a first query instruction to the programmable logic device after the computing device is powered on, where the first query instruction is used to instruct the programmable logic device to obtain a current latch signal from the latch;

[0102] The acquisition module is also used to acquire the first response information sent by the programmable logic device;

[0103] The acquisition module is further used to acquire a first status signal according to the first response information.

[0104] In a possible implementation, the sending module is further used to send a second query instruction to the programmable logic device, where the second query instruction is used to instruct the programmable logic device to obtain a current output signal of the power-on detection circuit;

[0105] The acquisition module is also used to acquire second response information sent by the programmable logic device;

[0106] A second status signal is acquired according to the second response information.

[0107] In a possible implementation, after sending the first query instruction to the programmable logic device, the acquisition module is further used to, after the computing device is powered on, acquire third response information sent by the programmable logic device;

[0108] The acquisition module is further used to acquire a third state signal according to the third response information;

[0109] The processing module is further configured to determine, based on the third status signal, that there is no unpacking event when the computing device is in the shutdown state.

[0110] In a possible implementation, after sending the second query instruction to the programmable logic device, the acquisition module is further used to acquire fourth response information sent by the programmable logic device;

[0111] The acquisition module is further used to acquire a fourth state signal according to the fourth response information;

[0112] The processing module is further configured to determine, based on the fourth status signal, that there is no unpacking event when the computing device is in the power-on state.

[0113] In a fifth aspect, an embodiment of the present application provides a chip, wherein the chip is used to execute a method as described in any one of the third aspects.

[0114] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a computer, the method as described in any one of the third aspects is implemented.

[0115] In a seventh aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements a method as described in any one of the third aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0116] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0117] Figure 1 A schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0118] Figure 2 A schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0119] Figure 3 A schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0120] Figure 4 A schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0121] Figure 5 A schematic diagram of a process flow of a box unpacking detection method provided in an embodiment of the present application;

[0122] Figure 6 A schematic diagram of another unpacking detection method provided in an embodiment of the present application;

[0123] Figure 7 A schematic diagram of another unpacking detection method provided in an embodiment of the present application;

[0124] Figure 8 A schematic diagram of the structure of a controller provided in an embodiment of the present application.

[0125] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0126] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0127] First, the relevant terms involved in the embodiments of the present application are introduced.

[0128] Unpacking event: refers to the event that the chassis of the server is opened. In some instances, the unpacking event can also be called the cover opening event. The unpacking event can be detected and alarmed to ensure the security of the computing device.

[0129] An embodiment of the present application provides a computing device, including: an unpacking trigger circuit, a shutdown detection circuit, a power supply circuit, a programmable logic device, and a controller, wherein the shutdown detection circuit is connected between the unpacking trigger circuit and the programmable logic device, and the controller is connected to the programmable logic device. When the computing device is powered off, the power supply circuit supplies power to the unpacking trigger circuit and the shutdown detection circuit, and the programmable logic device and the controller are in a power-off state; when the chassis of the computing device is opened, the unpacking trigger circuit sends a first opening trigger signal to the shutdown detection circuit; the shutdown detection circuit includes a latch, the shutdown detection circuit generates a first state signal based on the first unpacking trigger signal, and the latch is used to latch the first state signal; after the computing device is powered on, the controller obtains the first state signal from the latch through the programmable logic device, and determines based on the first state signal that there is an unpacking event when the computing device is in a shutdown state.

[0130] When the computing device is powered off, the power supply circuit can supply power to the unpacking trigger circuit and the shutdown detection circuit, so that the unpacking trigger circuit and the shutdown detection circuit can latch the first state signal corresponding to the unpacking event, so that after the computing device is powered on, the controller can obtain the first state signal in time through the programmable logic device, and quickly determine the unpacking event in the shutdown state according to the first state signal, so as to ensure the safety of the computing device; and when the computing device is powered off, the power supply circuit supplies power to the circuit (unpacking trigger circuit, shutdown detection circuit) for realizing basic detection functions, and the shutdown detection circuit includes a latch for latching the first state signal, and the latch is a simple circuit storage unit with very low power consumption. At the same time, there is no need to power the programmable logic device and the controller with large current consumption, which effectively reduces the power consumption of the computing device in detecting the unpacking event in the shutdown state.

[0131] The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0132] In order to facilitate understanding of the technical solution of the embodiment of the present application, first, the overall architecture of the computing device provided by the embodiment of the present application is described.

[0133] Figure 1 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. Figure 1 The computing device 10 includes a box opening trigger circuit 101, a shutdown detection circuit 102, a power supply circuit 103, a programmable logic device 104, and a controller 105, wherein:

[0134] In some embodiments, the computing device may be, but is not limited to, at least one of the following: a server, a whole cabinet, and a switch; the programmable logic device 104 may include, but is not limited to, a complex programmable logic device (CPLD) and a program running on a CPLD chip; the controller 103 may be, but is not limited to, a baseboard management controller (BMC) or a microcontroller unit (MCU).

[0135] The shutdown detection circuit 102 is connected between the unpacking trigger circuit 101 and the programmable logic device 104 , and the controller 105 is connected to the programmable logic device 104 .

[0136] When the computing device is powered off, the power supply circuit 103 supplies power to the unpacking trigger circuit 101 and the shutdown detection circuit 102 , and the programmable logic device 104 and the controller 105 are in a power-off state.

[0137] The power-off state can be used to indicate that the power supply circuit 103 does not supply power to the programmable logic device 104 and the controller 105. It should be noted that, when the computing device is powered off, there may be other power supply circuits other than the power supply circuit 103 that supply power to the controller 105 and / or the programmable logic device 104 separately. In this case, since other power supply circuits supply power to the controller 105 and / or the programmable logic device 104, it is not for the purpose of detecting the unpacking event when the computing device is powered off. It can be considered that the programmable logic device 104 and the controller 105 are also in the power-off state.

[0138] In some embodiments, the power supply circuit 103 may include a battery, which may include but is not limited to a button cell (BAT). When the computing device is powered off, it is not necessary to power the programmable logic device and the controller with high power consumption, so that the computing device has a low power demand for the power supply circuit, so that the power supply circuit of the computing device can use a button cell as a power supply to power the unpacking trigger circuit and the shutdown detection circuit in the shutdown state. The button cell has the characteristics of wide applicability, low price and low power consumption, and only the resistor and the non-gate circuit of the unpacking trigger circuit and the shutdown detection circuit consume a small amount of current, so that the unpacking trigger circuit and the shutdown detection circuit have the characteristics of low power consumption, which is conducive to reducing the power consumption and power supply cost of the computing device when detecting the unpacking event in the shutdown state.

[0139] When the chassis of the computing device is opened, the unpacking trigger circuit 101 sends a first unpacking trigger signal to the shutdown detection circuit 102 .

[0140] In some embodiments, the unpacking trigger circuit 101 can output a corresponding unpacking trigger signal according to the opening and closing state of the chassis. The unpacking trigger signal can be a high-level trigger signal or a low-level trigger signal. The unpacking trigger signal corresponding to when the chassis is opened can be determined as the first unpacking trigger signal.

[0141] In some embodiments, the case opening trigger circuit may include a switch, and the case may include a case cover.

[0142] Figure 2 This is a schematic diagram of another computing device provided in an embodiment of the present application. Figure 2 ,exist Figure 1Based on the structure of the computing device shown, the unpacking trigger circuit 101 includes a switch, the chassis includes a chassis cover, a first end of the switch is connected to the chassis cover, the chassis cover is connected to the ground, a second end of the switch is connected to the power supply circuit 103, and one end of the shutdown detection circuit 102 is connected between the second end of the switch and the power supply circuit 103, wherein when the chassis cover is opened, the switch is disconnected, and the unpacking trigger circuit 101, under the action of the power supply circuit 103, sends a first unpacking trigger signal to the shutdown detection circuit 102.

[0143] It can be understood that when the switch is disconnected, the power supply circuit 103 has a pull-up effect on the voltage at the second end of the switch, causing the unpacking trigger circuit 101 to send a high-level trigger signal to the shutdown detection circuit 102, and the high-level trigger signal can be determined as the first unpacking trigger signal. When the chassis cover is not opened, the switch is closed. At this time, since the chassis cover is grounded, the trigger signals at both ends of the switch are low-level trigger signals, and the unpacking trigger circuit can also send the low-level trigger signal to the unpacking trigger circuit.

[0144] In some embodiments, the case opening trigger circuit may further include a cable connector, one end of which may be connected to the case cover, and the other end of which may be connected to the first end of the switch, and the cable connector may be used to detect the open and closed state of the case cover. When the case cover is opened, the cable connector may transmit a first signal to the switch, the first signal being used to indicate that the case cover is opened, and the switch may perform an opening operation according to the first signal; when the case cover is closed, the cable connector may transmit a second signal to the switch, the second signal being used to indicate that the case cover is closed, and the switch may perform a closing operation according to the second signal.

[0145] By connecting the original case cover of the computing device to the case opening trigger circuit, the structure is simple, and no other sensors for detecting whether the case cover is opened are required, which greatly reduces the cost. The switch can enable the computing device to quickly and agilely detect the open and closed state of the case cover, and accurately transmit the first case opening trigger signal to the shutdown detection circuit, so that the computing device can timely detect the case opening detection event in the shutdown state, thereby ensuring the safety of the computing device.

[0146] The shutdown detection circuit 102 includes a latch. The shutdown detection circuit 102 generates a first state signal based on the first box-opening trigger signal. The latch is used to latch the first state signal.

[0147] In some embodiments, the latch may be a NAND latch or a NOR latch.

[0148] In some embodiments, the latch may be a reset set (RS) latch, the RS latch may be a NAND RS latch composed of a NAND gate circuit, or the RS latch may be a NOR RS latch composed of a NOR gate circuit.

[0149] Next, combine Figure 3 , the structure of the computing device when the latch is a NAND gate latch is described in detail; combined with Figure 4 , the structure of the computing device when the latch is a NOR gate latch is described in detail.

[0150] Figure 3 This is a schematic diagram of another computing device provided in an embodiment of the present application. Figure 3 The computing device 10 includes a box opening trigger circuit 101, a shutdown detection circuit 102, a power supply circuit 103, a programmable logic device 104, and a controller 105, wherein:

[0151] The unpacking trigger circuit 101 may include a switch module (S1) and a pull-up resistor (R1), wherein S1 is composed of a mechanical switch and a cable connector, a first end of S1 is connected to the chassis cover, a second end of S1 is connected to a first end of R1, and a second end of R1 is connected to the power supply circuit 103.

[0152] The chassis cover of the computing device may be a metal conductor, and the chassis cover is connected to the ground (GND).

[0153] The unboxing trigger circuit 101 may further include a filter capacitor (C1), a first end of C1 is connected between the second end of S1 and the first end of R1, a second end of C1 is connected to the ground, and C1 may be used to filter the first unboxing trigger signal generated by the unboxing trigger circuit.

[0154] The shutdown detection circuit 102 includes a latch, which is a NAND gate latch, and the NAND gate latch may include a NAND gate circuit. Figure 3 In the embodiment, the NAND gate latch may include two NAND gate circuits (U1 and U2) and a delay capacitor (C3), wherein U1 and U2 may form a NAND gate RS latch, and C3 may be used to ensure the stability of the output signal of the NAND gate RS latch.

[0155] The NAND latch may include a set terminal (S), a reset terminal (R), an output terminal (Q) and an inverting output terminal.

[0156] The shutdown detection circuit 102 may also include a first metal-oxide-semiconductor (MOS) transistor (Q1); the set end of the NAND latch is connected to the drain of the first MOS transistor, the drain of the first MOS transistor is also connected to the power supply circuit, the gate of the first MOS transistor is connected between the second end of the switch and the power supply circuit, and the source of the first MOS transistor is connected to the ground; the reset end of the NAND latch is respectively connected to the programmable logic device 104 and the power supply circuit 103; the output end of the NAND latch is connected to the programmable logic device 104; when the gate of the first MOS transistor receives the first unboxing trigger signal, the first MOS transistor is turned on and sends an initial state signal to the NAND latch, so that the NAND latch generates a first state signal based on the initial state signal.

[0157] The first MOS transistor may be an NMOS transistor or a PMOS transistor.

[0158] In some embodiments, the first MOS transistor may be an NMOS transistor, and the connection method of the gate, source and drain of the NMOS transistor may refer to Figure 3 The connection mode of Q1 in the circuit is used to realize that the gate of the first MOS tube is turned on when the first unboxing trigger signal is received. In other embodiments, the first MOS tube may also be a PMOS tube, and the gate, source and drain of the PMOS tube may also adopt other connection modes to realize that the gate of the first MOS tube is turned on when the first unboxing trigger signal is received. It should be noted that, under the condition that the gate of the first MOS tube is turned on when the first unboxing trigger signal is received, the embodiment of the present application does not limit the type of the first MOS tube and the connection mode of the gate, source and drain of the first MOS tube.

[0159] In a possible implementation, the shutdown detection circuit 102 also includes a first voltage-dividing resistor (R3) and a second voltage-dividing resistor (R4), the drain of the first MOS tube is connected to the power supply circuit 103 through the first voltage-dividing resistor (R3), and the reset end of the NAND latch is connected to the power supply circuit 103 through the second voltage-dividing resistor (R4), and the resistance value of the second voltage-dividing resistor is greater than the resistance value of the first voltage-dividing resistor.

[0160] The set end of the NAND latch is connected to the drain of the first MOS transistor (Q1), the drain of the first MOS transistor (Q1) is also connected to the first end of the first voltage-dividing resistor (R3), the second end of the first voltage-dividing resistor (R3) is connected to the power supply circuit 103, the gate of the first MOS transistor (Q1) is connected between the second end of the switch (S1) and the power supply circuit 103, and the source of the first MOS transistor (Q1) is connected to the ground.

[0161] The reset end of the NAND latch is connected to the first end of the second voltage-dividing resistor ( R4 ) and the programmable logic device 104 , respectively, and the second end of the second voltage-dividing resistor ( R4 ) is connected to the power supply circuit 103 .

[0162] The output terminal (Q) of the NAND latch is connected to the programmable logic device 104 .

[0163] The inverting output terminal of the NAND latch Connect to one end of C3 and the other end of C3 is grounded.

[0164] Since the first voltage-dividing resistor (R3) and the second voltage-dividing resistor (R4) are both connected to the power supply circuit 103, the first voltage-dividing resistor (R3) and the second voltage-dividing resistor (R4) can divide the output voltage of the power supply circuit 103. When the first MOS is not turned on, the drain of the first MOS can be at a high level under the pull-up effect of the first voltage-dividing resistor (R3). By controlling the resistance value of the second voltage-dividing resistor (R4) to be greater than the resistance value of the first voltage-dividing resistor (R3), the second voltage-dividing resistor (R4) can share more voltage. When the reset end of the NAND gate latch is not affected by the reset signal, the reset end of the NAND gate latch connected to the second voltage-dividing resistor (R4) can be stably at a high level, so that the subsequent NAND gate latch can accurately output the first state signal after receiving the initial state signal sent by the drain of the first MOS tube.

[0165] In some embodiments, the computing device 10 may further include a power control circuit 106 , which is connected to the power supply circuit 103 and the shutdown detection circuit 102 , respectively.

[0166] The shutdown detection circuit 102 also includes a third voltage-dividing resistor (R8) and a fourth voltage-dividing resistor (R9), wherein a first resistance value of the fourth voltage-dividing resistor (R9) is smaller than a second resistance value of the third voltage-dividing resistor (R8), and a difference between the second resistance value and the first resistance value is greater than a preset threshold.

[0167] A first end of the third voltage-dividing resistor (R8) is connected to the source of the first MOS tube (Q1), and a second end of the third voltage-dividing resistor (R8) is connected to the ground.

[0168] A first end of the fourth voltage-dividing resistor (R9) is connected to a first end of the power control circuit 106, and a second end of the fourth voltage-dividing resistor (R9) is connected between the source of the first MOS transistor (Q1) and the third voltage-dividing resistor (R8).

[0169] In some embodiments, the second end of the power control circuit 106 is connected to the power supply circuit 103. After the computing device is powered on, the power supply voltage of the power control circuit 106 is greater than the power supply voltage of the power supply circuit 103. The power supply circuit 103 is in a non-powered state under the action of the power control circuit 106. The power control circuit 106 supplies power to the unpacking trigger circuit 101, the shutdown detection circuit 102, the programmable logic device 104 and the controller 105. The first MOS tube (Q1) is in a cut-off state under the voltage dividing action of the third voltage dividing resistor (R8) and the fourth voltage dividing resistor (R9).

[0170] The non-powered state is used to indicate a state in which the power supply circuit cannot supply power to the back-end connection circuit, and the back-end connection circuit may include a shutdown detection circuit and an unpacking trigger circuit.

[0171] The power supply circuit 103 may include a button battery (Battery, BAT), a current limiting resistor (R0), a forward diode (D1) and a reverse diode (D2). The button battery (BAT) may be connected to the second end of R1 through R0 and D1, the negative electrode of D2 may be connected to the negative electrode of D1, and the positive electrode of D2 is connected to the second end of the power control circuit.

[0172] Exemplarily, the power supply circuit is powered by a button battery (BAT), and the power supply voltage may be 3 V. The power control circuit 106 may be powered by a standby power supply (Standby) in the computing device, and when the computing device is powered off, the power supply voltage may be 0 V; when the computing device is powered on, the power supply voltage may be 3.3 V.

[0173] When the computing device is powered on, since the power supply voltage of the power control circuit 106 is greater than the power supply voltage of the power supply circuit 103, D2 is turned on and D1 is turned off, so that the button battery in the power supply circuit 103 cannot supply power to the back-end connection circuit through D1. At this time, the power supply circuit is in a non-powered state, and the power control circuit 106 can supply power to the unpacking trigger circuit 101, the shutdown detection circuit 102, the programmable logic device 104 and the controller 105.

[0174] In some embodiments, the power control circuit 106 may include a forward diode ( D3 ), and a first terminal of the power control circuit 106 may be connected to R8 and R9 via D3 .

[0175] It is understandable that the greater the resistance value of the voltage divider resistor, the greater the voltage divider ratio. The voltage divider ratio of R8 and R9 to the output voltage of the first end of the power control circuit 106 can be adjusted by adjusting the preset threshold. When the preset threshold is larger, it means that the difference between the first resistance value and the second resistance value is larger, indicating that R8 shares more of the output voltage of the first end of the power control circuit 106.

[0176] After the power supply control circuit 106 supplies power, since the resistance value of R8 is greater than the resistance value of R9, a high level voltage division will be generated on R8 during the process of the current flowing through D3, R8 and R9 through the first end of the power supply control circuit. The high level voltage division can be used to clamp the source voltage of Q1, so that Q1 is in the off state. When Q1 is in the off state, the output signal of the shutdown detection circuit remains stable and will no longer change with the change of the unpacking trigger signal.

[0177] By controlling the power supply voltage of the power control circuit to be greater than the power supply voltage of the power supply circuit, the power supply circuit does not need to be powered when the computing device is powered on, which is beneficial to saving the power supply loss of the power supply circuit; by setting the third voltage divider circuit and the fourth voltage divider resistor, it is ensured that the first MOS tube is in a cut-off state after the computing device is powered on, so that the shutdown detection circuit maintains a stable state after startup, and the output signal of the shutdown detection circuit is not affected by the signal of the unpacking signal detection circuit, thereby reducing the power supply loss of the power control circuit.

[0178] In some embodiments, the shutdown detection circuit 102 may further include a resistor (R2), and the gate of Q1 may be connected between the second end of S1 and the power supply circuit 103 through R2. R2 may be an electrostatic discharge (ESD) resistor, and R2 may be used to perform anti-static treatment on the first unpacking trigger signal before the first unpacking trigger signal enters Q1.

[0179] In some embodiments, R4 and R3 may be connected between the second end of R1 and the power supply circuit 103 .

[0180] In some embodiments, the shutdown detection circuit 102 may further include a filter capacitor (C2) and a resistor (R10), wherein the first end of C2 and the first end of R10 may be connected between the output end (Q) of Q1 and the set end of the latch, and the second end of C2 and the second end of R10 are connected to ground.

[0181] The shutdown detection circuit 102 can filter and perform anti-static processing on the signal output from the output end of Q1 through C2 and R10 to ensure the stability of the signal.

[0182] In some embodiments, the shutdown detection circuit 102 may also include a first signal buffer (U3) and a second signal buffer (U4), wherein the input end of the first signal buffer (U3) is connected to the output end (Q) of the latch, and the output end of the first signal latch (U3) is connected to the programmable logic device 104; the input end of the second signal buffer (U4) is connected to the programmable logic device 104, and the output end of the second signal buffer (U4) is connected to the reset end of the latch.

[0183] In some embodiments, after determining that an unpacking event occurs when the computing device is in a shutdown state, the controller 105 writes event information of the unpacking event into the target memory and / or the operation log of the controller, and sends a reset instruction to the programmable logic device 104; the programmable logic device 104 generates a reset signal in response to the reset instruction, and sends the reset signal to the reset end of the latch through the second signal buffer (U4); the latch resets the output end of the latch based on the reset signal.

[0184] By resetting the latch, after the computing device is shut down, the shutdown detection circuit can continue to detect the unpacking event when the computing device is in the shutdown state.

[0185] The event information may include the occurrence time of the unpacking event. For example, the occurrence time of the unpacking event may be July 30, 2024. In some examples, the event information may also include the type of the unpacking event, and the type of the unpacking event may include an unpacking event in a powered-on state and an unpacking event in a powered-off state.

[0186] The target storage may be a storage preset by the user for storing various event information. In some embodiments, the target storage may be a non-volatile memory to avoid loss of event information of the unpacking event.

[0187] By recording the event information of the unpacking event in the operation log or writing it into the target storage, the user can quickly and timely discover the unpacking event of the computing device based on the operation log, so as to avoid physical intrusion into the computing device and ensure the security of the computing device.

[0188] By setting a first signal buffer, the computing device can amplify and isolate the first state signal output by the latch output terminal to ensure that the programmable logic device accurately and stably obtains the first state signal; by setting a second signal buffer, the computing device can amplify and isolate the reset signal output by the programmable logic device to ensure that the reset terminal of the latch accurately and stably obtains the reset signal.

[0189] Can be pre- Figure 3 The NAND latch shown configures a logic truth table so that the NAND latch can accurately perform reset and set actions based on the logic truth table. In an example, the logic truth table can be shown in Table 1:

[0190] Table 1

[0191]

[0192] In Table 1, when the logic value of the set terminal (S) or the reset terminal (R) is 1, it indicates that the set terminal (S) or the reset terminal (R) is at a high level; when the logic value of the set terminal (S) or the reset terminal (R) is 0, it indicates that the set terminal (S) or the reset terminal (R) is at a low level. According to Table 1, in the NAND latch, the reset terminal (R) and the set terminal (S) will not be at a low level at the same time, that is, the reset terminal (R) and the set terminal (S) are all at a high level, or there is one high level and one low level in the reset terminal (R) and the set terminal (S).

[0193] Next, combine Figure 3 , a latching process of the first state signal by the NAND latch when the computing device is powered off is described in detail.

[0194] When the chassis cover is opened, S1 is disconnected, and the second end of S1 is pulled up by R1 to generate a high-level trigger signal, i.e., the first unboxing trigger signal. The first unboxing trigger signal generated by the second end of S1 is transmitted to the gate of Q1 after being treated with anti-static by R2. Q1 is turned on under the action of the first unboxing trigger signal. After Q1 is turned on, the drain of Q1 generates a low-level initial state signal under the pull-down action of R8. The level value of the initial state signal can be the conduction voltage drop of R8 and Q1. The initial state signal reaches the set end of the NAND latch after being processed by R10 and C2. At this time, the set end of the NAND latch is at a low level, and the reset end of the NAND latch is at a high level under the action of R4. According to the logic truth table shown in Table 1, the first state signal output by the output end of the NAND latch is a high-level (logical value 1) signal. The first state signal can be isolated and amplified by U3 and then input into the programmable logic device.

[0195] If the chassis cover is closed after being opened, S1 is closed, and the second end of S1 generates a low-level trigger signal. After the anti-static treatment of R2, the low-level trigger signal is transmitted to the gate of Q1, that is, the gate of Q1 is at a low level. When the gate of Q1 is at a low level, Q1 remains in the cut-off state. Due to the voltage-dividing effect of R3 and R4, the voltage at the drain of Q1 continues to remain at a high level, that is, the set end of the NAND latch is at a high level. According to the logic truth table shown in Table 1, when the set end and the reset end of the NAND latch are both at a high level, the level value of the output end of the NAND latch does not change. At this time, the first state signal at the output end of the NAND latch is still a high level (logical value 1) signal.

[0196] The computing device provided in the embodiment of the present application can, through the joint action of the NAND gate latch, the first NMOS tube, the first voltage-dividing resistor and the second voltage-dividing resistor in the shutdown detection circuit, convert the first unpacking trigger signal sent by the unpacking trigger circuit into a first state signal after the chassis cover is opened, and stably latch the first state signal. Even if the chassis cover is repeatedly opened and closed afterwards, the first state signal previously latched by the NAND gate latch will not be lost, so that after the computing device is powered on, the controller can quickly obtain the first state signal from the NAND gate latch through the programmable logic device, and determine the unpacking event in the shutdown state according to the first state signal, thereby ensuring the security of the computing device.

[0197] After the controller obtains the first state signal through the programmable logic device, the controller can also perform a reset process on the NAND latch. The reset process of the NAND latch is described in detail below.

[0198] The controller 105 may send a reset instruction to the programmable logic device 104, and the reset instruction is used to instruct the programmable logic device to output a reset signal to the latch. The programmable logic device 104 may send a reset signal to U4, and U4 may isolate and amplify the reset signal to obtain a stable reset signal, and input the stable reset signal to the reset terminal (R) of the RS latch.

[0199] In some embodiments, the reset signal can be a low-level signal. Since the set terminal signal of the RS latch remains at a high level when the device is powered on and no unpacking event occurs, according to the logic truth table shown in Table 1, the output terminal of the RS latch will output a low-level signal.

[0200] The computing device provided in the embodiment of the present application controls the power supply voltage of the power control circuit to be greater than the power supply voltage of the power supply circuit, so that the power supply circuit does not need to be powered when the computing device is powered on, which is beneficial to saving the power supply loss of the power supply circuit; by setting a third voltage divider circuit and a fourth voltage divider resistor, it is ensured that the first NMOS tube is in a cut-off state after the computing device is powered on, so that the shutdown detection circuit maintains a stable state after powering on, and the output signal of the shutdown detection circuit is not affected by the signal of the unpacking signal detection circuit, thereby reducing the power supply loss of the power control circuit.

[0201] In some embodiments, the computing device 10 may further include a power-on detection circuit 107, which includes a second MOS tube (Q2), wherein the gate of the second MOS tube (Q2) is connected to the second end of the switch (S1); the drain of the second MOS tube (Q2) is respectively connected to the power control circuit 106 and the programmable logic device 104; and the source of the second MOS tube (Q2) is connected to the ground.

[0202] In some embodiments, the power-on detection circuit 107 may further include an ESD protection resistor, which is used to perform anti-static treatment on the signal transmitted in the power-on detection circuit. Figure 3 In the embodiment, the power-on detection circuit may include three ESD protection resistors, namely R5, R6 and R7. The gate of Q2 may be connected to the second end of S1 through R5, the drain of Q2 may be connected between the second end of the power control circuit 106 and the positive electrode of D2 through R6, and the programmable logic device 104 may be connected to the drain of Q2 through R7.

[0203] After the computing device is powered on, the unpacking trigger circuit 101 can send a second unpacking trigger signal to the power-on detection circuit 107 when the chassis cover is opened; the power-on detection circuit 107 generates a second state signal according to the second unpacking trigger signal, and outputs the second state signal to the programmable logic device 104; the controller 105 obtains the second state signal through the programmable logic device 104, and determines that there is an unpacking event when the computing device is in the power-on state based on the second state signal.

[0204] It should be noted that the second MOS tube may be an NMOS tube or a PMOS tube.

[0205] In some embodiments, the second MOS transistor may be an NMOS transistor, and the connection method of the gate, source and drain of the NMOS transistor may refer to Figure 3 The connection mode of Q2 is used to realize that the second MOS tube is turned on when the gate of the second MOS tube receives the second opening trigger signal.

[0206] In other embodiments, the second MOS tube may also be a PMOS tube, and the gate, source, and drain of the PMOS tube may also be connected in other ways to achieve that the gate of the second MOS tube is turned on when the second box-opening trigger signal is received. It should be noted that, under the condition that the gate of the second MOS tube is turned on when the second box-opening trigger signal is received, the embodiment of the present application does not limit the type of the second MOS tube and the connection method of the gate, source, and drain of the second MOS tube.

[0207] It should be noted that after the computing device is powered on, when the chassis cover is opened, the switch is disconnected, and the unboxing trigger circuit sends the second unboxing trigger signal to the power-on detection circuit under the action of the power control circuit. Although the unboxing trigger circuit can also send the second unboxing trigger signal to the shutdown detection circuit, since Q1 is in the cut-off state, the second unboxing trigger signal cannot be further transmitted to the back-end circuit, so that the output signal of the shutdown detection circuit will not change with the change of the second unboxing trigger signal.

[0208] If the signal output by the unpacking trigger circuit to the power-on detection circuit is high, the signal converted by Q2 is low; if the signal output by the unpacking trigger circuit to the power-on detection circuit is low, the signal converted by Q2 is high. The integrity of the signal converted by Q2 can be adjusted by the series resistor R7, so that the signal transmitted by Q2 to the programmable logic device is a stable signal to avoid signal fluctuations.

[0209] After the computing device is powered on, when the chassis cover is opened, S1 is disconnected, and the second end of S1 is pulled up by R1 to generate a high-level trigger signal, i.e., a second unboxing trigger signal. After being treated with anti-static electricity by R5, the second unboxing trigger signal is transmitted to the gate of Q2, and Q2 is turned on by the second unboxing trigger signal, and Q2 can convert the second unboxing trigger signal into a low-level second state signal. When the chassis cover is closed, S1 is closed, and the unboxing trigger circuit can output a low-level trigger signal to the power-on detection circuit, and the power-on detection circuit can output a high-level fourth state signal to the programmable logic device.

[0210] In a possible implementation, the programmable logic device may encode various signals to obtain encoded data corresponding to the various signals, and store the various signals and the corresponding encoded data accordingly.

[0211] The programmable logic device can communicate with the controller based on the Inter-Integrated Circuit (I2C) interface. The programmable logic device can pre-configure different bits in the I2C communication frame to store the coded data corresponding to different signals, so that the controller can accurately distinguish various signals of the computing device according to the coded data read in different bits. For example, the bit BIT0 can be set in the I2C communication frame to store the first coded data corresponding to the first state signal; the bit BIT1 can be set in the I2C communication frame to store the second coded data corresponding to the second state signal; the bit BIT2 can be set in the I2C communication frame to store the fifth coded data corresponding to the reset signal.

[0212] In an example, the corresponding relationship between the working state of the computing device, the state and output signal of the switch of the unpacking trigger circuit, the signal obtained or output by the programmable logic device, the encoded data, the bit and the indication information can be shown in Table 2:

[0213] Table 2

[0214]

[0215]

[0216] Please refer to Table 2. When the working state of the computing device is different or the state of the switch of the unboxing trigger circuit is different, the output signal of the unboxing trigger circuit and the state signal obtained by the programmable logic device are also different, so that the corresponding bits, encoded data or indication information are also different.

[0217] For example, after the computing device is powered off, if the chassis cover is opened and the switch is disconnected, the unpacking trigger circuit will output a first unpacking trigger signal to the shutdown detection circuit; the shutdown detection circuit can generate a first state signal based on the first unpacking trigger signal, and latch the first state signal in the latch. If the chassis cover has never been opened and the switch is closed, the unpacking trigger circuit can output a third unpacking trigger signal to the shutdown detection circuit, and the shutdown detection circuit can generate a third state signal based on the third unpacking trigger signal, and latch the third state signal in the latch.

[0218] After the computing device is powered on, the controller may send a first query instruction to the programmable logic device, and the first query instruction may be used to instruct the programmable logic device to obtain a current latch signal from the latch. After receiving the first query instruction sent by the controller, the programmable logic device may obtain a current latch signal from the latch, and the current latch signal may be a first state signal or a third state signal.

[0219] If the current latch signal obtained by the programmable logic device is a first state signal, the first state signal is encoded to obtain first encoded data (logical value 1), the first encoded data (logical value 1) is stored in BIT0 of the I2C communication frame, and the I2C communication frame written with the first encoded data is sent to the controller; the controller can read the first encoded data (logical value 1) in BIT0 of the I2C communication frame, and determine that there is an unpacking event in the computing device in the shutdown state according to the indication information corresponding to the first encoded data. If the current latch signal obtained by the programmable logic device is a third state signal, the third state signal is encoded to obtain third encoded data (logical value 0), the third encoded data (logical value 0) is stored in BIT0 of the I2C communication frame, and the I2C communication frame written with the third encoded data is sent to the controller; the controller can read the third encoded data (logical value 0) in BIT0 of the I2C communication frame, and determine that there is no unpacking event in the computing device in the shutdown state according to the indication information corresponding to the third encoded data.

[0220] After the controller determines that there is an unpacking event in the shutdown state of the computing device, the controller can write the fifth coded data (logical value 0) in BIT2 of the I2C communication frame, and send a reset instruction to the programmable logic device, and the reset instruction may include the I2C communication frame in which the fifth coded data is written. The programmable logic device can read the fifth coded data (logical value 0) in BIT2 according to the reset instruction, and send a reset signal to the reset end of the latch according to the indication information corresponding to the fifth coded data, and the latch can reset the latch output end according to the reset signal. After the target duration, the controller can write the sixth coded data (logical value 1) in BIT2 of the I2C communication frame, and send a release reset instruction to the programmable logic device, and the release reset instruction may include the I2C communication frame in which the sixth coded data is written. The programmable logic device can read the sixth coded data (logical value 1) in BIT2 according to the release reset instruction, and release the reset operation of the latch according to the indication information corresponding to the sixth coded data, and the reset end of the latch restores the high level.

[0221] The target duration may be the duration between the reset start time and the reset completion time. The target duration may be determined based on historical reset data of the latch.

[0222] When the computing device is powered on, if the chassis cover is open and the switch is disconnected, the unpacking trigger circuit will output a second unpacking trigger signal to the power-on detection circuit; the power-on detection circuit can generate a second state signal according to the second unpacking trigger signal. When the chassis cover is closed and the switch is closed, the unpacking trigger circuit will output a fourth unpacking trigger signal to the power-on detection circuit; the power-on detection circuit can generate a fourth state signal according to the fourth unpacking trigger signal.

[0223] When the computing device is in the power-on state, the controller can send a second query instruction to the programmable logic device, and the second query instruction can be used to instruct the programmable logic device to obtain the current output signal of the power-on detection circuit; the programmable logic device can obtain the current output signal of the power-on detection circuit after receiving the second query instruction sent by the controller.

[0224] It can be understood that the current output signal of the power-on detection circuit can be a second state signal or a fourth state signal.

[0225] If the current output signal is a second state signal, the programmable logic device encodes the second state signal to obtain second coded data (logical value 0), stores the second coded data (logical value 0) in BIT1 of the I2C communication frame, and sends the I2C communication frame with the second coded data written to the controller; the controller can read the second coded data (logical value 0) in BIT1 of the I2C communication frame, and determine, based on the indication information corresponding to the second coded data, that there is an unpacking event when the computing device is in the powered-on state.

[0226] If the current output signal is the fourth state signal, the programmable logic device encodes the fourth state signal to obtain fourth coded data (logical value 1), stores the fourth coded data (logical value 1) in BIT1 of the I2C communication frame, and sends the I2C communication frame with the fourth coded data written to the controller; the controller can read the fourth coded data (logical value 1) in BIT1 of the I2C communication frame, and determine, based on the indication information corresponding to the fourth coded data, that there is no unpacking event when the computing device is in the powered-on state.

[0227] In some embodiments, the controller may adopt a polling method to read the current output signal of the power-on detection circuit through a programmable logic device, so as to timely detect the unpacking event of the computing device in the power-on state.

[0228] In some embodiments, after the computing device is powered on, if the chassis cover is opened, the power-on detection circuit may also output a second unpacking trigger signal to the programmable logic device. The programmable logic device may also immediately report an interrupt signal to the controller after detecting the second unpacking trigger signal, so that the controller can monitor the unpacking event of the computing device in real time.

[0229] In some embodiments, the controller may also display the acquired status signals (e.g., the first status signal, the second status signal, the third status signal, or the fourth status signal) and the prompt information corresponding to the status signal in the user interface. By displaying the status signals and the corresponding prompt information in the user interface, the user can timely understand whether the computing device has been unpacked, timely discover physical intrusion of the computing device, and ensure the security of the computing device.

[0230] Compared with some embodiments, when the server is unpacked, an action signal is triggered by an action switch, and a delay register chip is used to store the action signal. Each time the server is powered on, the action signal stored in the delay register chip is read by a controller to determine whether an unpacking event occurs on the server. The computing device provided in the embodiment of the present application separately sets a shutdown detection circuit to feedback the unpacking event of the computing device in the shutdown state, and separately sets a power-on detection circuit to feedback the unpacking event of the computing device in the power-on state, so that the computing device can realize independent detection of the unpacking event of the computing device in different working states, and real-time detection of the unpacking event in the power-on state, avoiding mutual influence between the power-on detection circuit and the shutdown detection circuit; the shutdown detection circuit is provided with a latch and a signal buffer, which can ensure that the shutdown detection circuit outputs a stable first state signal, so that after the computing device is powered on, the programmable logic device can quickly obtain the first state signal through the latch; the programmable logic device in the computing device is reused to communicate with the controller, without additionally occupying the general-purpose input and output (GPIO resources) of the controller, avoiding affecting the pin allocation of the controller, and the unpacking signal detection circuit and the shutdown detection circuit mostly use basic devices such as mechanical switches, gate circuits, transistors and button batteries, which is conducive to reducing the cost of the unpacking trigger circuit.

[0231] Figure 4 This is a schematic diagram of another computing device provided in an embodiment of the present application. Figure 4 The computing device 10 includes an unpacking trigger circuit 101 , a shutdown detection circuit 102 , a power supply circuit 103 , a programmable logic device 104 , a controller 105 , a power control circuit 106 and a startup detection circuit 107 .

[0232] It should be noted that the structure, connection method and execution process of the unpacking trigger circuit 101 and the power-on detection circuit 107 can be referred to Figure 3 The structure, connection method and execution process of the unpacking trigger circuit 101 and the power-on detection circuit 107 in the embodiment will not be described in detail here.

[0233] The shutdown detection circuit 102 includes a latch and a fifth voltage-dividing resistor (R11). The latch may be a NOR latch, and the NOR latch may include a NOR gate circuit. Figure 4 In the embodiment, the NOR gate latch is composed of two NOR gate circuits (U5, U6) and a delay capacitor (C3).

[0234] The set end of the NOR gate latch is connected between the second end of the switch and the power supply circuit; the reset end of the NOR gate latch is respectively connected to the first end of the fifth voltage-dividing resistor (R11) and the programmable logic device, and the second end of the fifth voltage-dividing resistor (R11) is connected to the ground; and the output end of the NOR gate latch is connected to the programmable logic device.

[0235] U5 in the NOR gate latch is also connected to the power supply circuit and the power control circuit respectively, so that the power supply circuit and the power control circuit can supply power to U5.

[0236] In some embodiments, the shutdown detection circuit may further include an ESD protection resistor R2 and a filter capacitor C2, wherein the first end of R2 is connected between the second end of the switch and the power supply circuit, the second end of R2 is connected to the set end of the NOR latch, one end of C2 is connected between the second end of R2 and the set end of the NOR latch, and the other end is connected to the ground.

[0237] In some embodiments, the shutdown detection circuit may include a first signal buffer and a second signal buffer. The connection relationship between the first signal buffer and the second signal buffer may refer to Figure 3 The connection relationship between the first signal buffer and the second signal buffer in the embodiment will not be described in detail here.

[0238] Can be pre- Figure 4 The NOR gate latch shown configures a logic truth table so that the NOR gate latch can accurately perform reset and set actions based on the logic truth table. In an example, the logic truth table can be shown in Table 3:

[0239] Table 3

[0240]

[0241] In Table 3, when the logic value of the set terminal (S) or the reset terminal (R) is 1, it indicates that the set terminal (S) or the reset terminal (R) is at a high level; when the logic value of the set terminal (S) or the reset terminal (R) is 0, it indicates that the set terminal (S) or the reset terminal (R) is at a low level. According to Table 3, in the NOR latch, the reset terminal (R) and the set terminal (S) will not be at a high level at the same time, that is, the reset terminal (R) and the set terminal (S) are all at a low level, or there is one high level and one low level in the reset terminal (R) and the set terminal (S).

[0242] exist Figure 4In the computing device shown, when the computing device is powered off and the chassis cover is opened, S1 is disconnected, and the second end of S1 is pulled up by R1 to generate a high-level trigger signal, i.e., a first unpacking trigger signal. The first unpacking trigger signal reaches the set end of the NOR latch after being processed by R2 and C2. At this time, the set end of the NOR latch is at a high level, and the reset end of the NOR latch is at a low level under the pull-down action of R11. According to the logic truth table shown in Table 3, the first state signal output by the output end of the NOR latch is a high-level signal (logic value 1). The first state signal can be isolated and amplified by U3 and then input into the programmable logic device.

[0243] When the computing device is powered off, if the chassis cover is opened and then closed, S1 is closed, and the second end of S1 generates a low-level trigger signal, which reaches the set end of the NOR latch after being processed by R2 and C2, that is, the set end of the NOR latch is at a low level. According to the logic truth table shown in Table 3, when the set end and the reset end of the NOR latch are both at a low level, the level value of the output end of the NOR latch does not change. At this time, the first state signal of the output end of the NOR latch is still a high-level (logical value 1) signal.

[0244] When the computing device is powered off, if the chassis cover has not been opened, S1 is closed, the second end of S1 maintains a low-level trigger signal (the third opening trigger signal), or the output end of the NOT latch maintains a low level, and outputs a third state signal.

[0245] After the computing device is powered on, the controller can immediately send a first query instruction to the programmable logic device, and the programmable logic device can obtain the current latch signal from the NOR gate latch according to the first query instruction, and the current latch signal can be a first state signal or a third state signal. The programmable logic device can encode the first state signal (or the third state signal) to obtain the first coded data corresponding to the first state signal (or the third coded data corresponding to the third state signal), and send the first coded data (or the third coded data) to the controller. If the controller receives the first coded data, it is determined that there is an unpacking event when the computing device is in the shutdown state; if the controller receives the third coded data, it is determined that there is no unpacking event when the computing device is in the shutdown state.

[0246] It is understandable that after the controller acquires the first coded data, the shutdown detection circuit is in a stable state. At this time, the unpacking event that occurs when the computing device is in the power-on state will not affect the shutdown detection circuit. After the controller acquires the third coded data, the shutdown detection circuit may be affected by the unpacking event in the power-on state and generate a first state signal. Although the shutdown detection circuit can also be used to detect the unpacking event in the power-on state, the NOR gate latch of the shutdown detection circuit needs to be reset after each unpacking event before the next unpacking event can be detected, which makes the detection process of the unpacking event in the power-on state more cumbersome.

[0247] In order to facilitate the detection of unpacking events in the power-on state, after the computing device is powered on, the controller can immediately perform the following process: obtain the first coded data or the third coded data to determine whether the computing device has an unpacking event in the power-off state. After this process, the controller no longer pays attention to the signal latched in the NOR gate latch of the power-off detection circuit, but sends a second query instruction to the programmable logic device in a polling manner. The programmable logic device can obtain the current output signal of the power-on detection circuit according to the second query instruction. The current output signal can be a second state signal or a fourth state signal. The programmable logic device can encode the second state signal (or the fourth state signal) to obtain the second coded data corresponding to the second state signal (or the fourth coded data corresponding to the fourth state signal), and send the second coded data (or the fourth coded data) to the controller. If the controller receives the second coded data, it is determined that the computing device has an unpacking event in the power-on state; if the controller receives the fourth coded data, it is determined that the computing device does not have an unpacking event in the power-off state. The controller can control the programmable logic device to obtain the current output signal of the power-on detection circuit, and quickly determine whether an unpacking event occurs in the power-on state of the computing device based on the current output signal. After determining that an unpacking event occurs in the power-on state, there is no need to reset the power-on detection circuit, thereby making the detection process of an unpacking event in the power-on state relatively simple.

[0248] When the chassis cover is closed, when the computing device performs a power-off operation, the controller can also send a reset instruction to the programmable logic device, and the programmable logic device can respond to the reset instruction and send a reset signal to the reset end of the NOR gate latch through U4. The reset signal is a high-level signal. When the chassis cover is closed, the set end signal of the NOR gate latch remains at a low level, and the reset end signal is a high level. According to the logic truth table shown in Table 3, the output end of the NOR gate latch will output a low-level signal.

[0249] Compared to Figure 3 computing devices in Figure 4The computing device in the present invention replaces the NAND gate latch in the shutdown detection circuit with a NOR gate latch, so that the following components can be saved in the shutdown detection circuit: a first MOS tube (Q1), a first voltage-dividing resistor (R3), a second voltage-dividing resistor (R4), a third voltage-dividing resistor (R8), a fourth voltage-dividing resistor (R9) and a forward diode (D3), so that the structure of the shutdown detection circuit is simpler, and the power consumption and cost are lower.

[0250] Next, based on the computing device proposed in the above embodiment, the present application embodiment also provides a box opening detection method. Next, in combination with Figure 5 , the unpacking detection method is described in detail.

[0251] Figure 5 This is a flow chart of a method for unpacking detection provided in an embodiment of the present application. Figure 5 , the method may include:

[0252] S501: After the computing device is powered on, control the programmable logic device to obtain a first state signal from a latch.

[0253] The method can be executed by a controller in the computing device in the above embodiment, and the computing device may include an unpacking trigger circuit, a shutdown detection circuit, a power supply circuit and a programmable logic device. The shutdown detection circuit is connected between the unpacking trigger circuit and the programmable logic device, and the controller is connected to the programmable logic device. When the computing device is powered off, the power supply circuit supplies power to the unpacking trigger circuit and the shutdown detection circuit, and the programmable logic device and the controller are in a power-off state.

[0254] The latch is located in the shutdown detection circuit, and is used to latch a first state signal, which is generated by the shutdown detection circuit based on a first unpacking trigger signal, and the first unpacking trigger signal is sent by the unpacking trigger circuit to the shutdown detection circuit when the chassis of the computing device is opened.

[0255] It should be noted that the process of the shutdown detection circuit generating the first state signal based on the first unpacking trigger signal can refer to the specific execution process of generating the first state signal in the above embodiment, which will not be repeated here.

[0256] In some embodiments, the latch may be a NOR latch or a NAND latch.

[0257] In some embodiments, after the computing device is powered on, the controller may perform the following process: send a first query instruction to the programmable logic device, where the first query instruction may be used to instruct the programmable logic device to obtain a current latch signal from the latch; obtain first response information sent by the programmable logic device; and obtain a first status signal based on the first response information.

[0258] In some embodiments, the programmable logic device may perform the following operations: in response to a first query instruction, obtain a current latch signal of the latch from the latch; when the current latch signal is a first state signal, generate first response information; and send the first response information to the controller.

[0259] It can be understood that the current latch signal can be a first state signal or a third state signal.

[0260] If the current latch signal obtained by the programmable logic device is a first state signal, the first state signal is encoded to obtain first coded data, the first coded data is stored in BIT0 of the I2C communication frame, and a first response message is generated; the first response message is sent to the controller. If the current latch signal obtained by the programmable logic device is a third state signal, the third state signal is encoded to obtain third coded data, the third coded data is stored in BIT0 of the I2C communication frame, and a third response message is generated; the third response message is sent to the controller.

[0261] In some embodiments, after sending the first query instruction to the programmable logic device, the controller may also perform the following process: obtaining third response information sent by the programmable logic device; obtaining a third status signal based on the third response information; and determining based on the third status signal that there is no unpacking event when the computing device is in a shutdown state.

[0262] The controller may pre-store the correspondence shown in Table 2, and the controller may determine the first state signal based on the correspondence and the first coded data in the first response information; the controller may determine the third state signal based on the correspondence and the third coded data in the third response information.

[0263] S502: Determine, based on a first status signal, that an unpacking event occurs when the computing device is in a shutdown state.

[0264] In some embodiments, the controller may pre-store indication information corresponding to each state signal (such as Table 2), and the controller may determine whether an unpacking event occurs in the computing device according to the indication information corresponding to each state signal. For example, in Table 2, after the controller obtains the first state signal, it may determine that an unpacking event occurs when the computing device is in a shutdown state according to the indication information corresponding to the first state signal.

[0265] In some embodiments, the controller may also mark the validity of each status signal. For example, the acquisition source of each status signal and the validity mark corresponding to each status signal may be as shown in Table 4:

[0266] Table 4

[0267]

[0268]

[0269] For any status signal, the controller can determine whether the status signal is a valid signal based on the validity identifier corresponding to the status signal; when it is determined that the status signal is a valid signal, it is determined that an unpacking event has occurred on the computing device; when it is determined that the status signal is an invalid signal, it is determined that no unpacking event has occurred on the computing device.

[0270] For example, after the controller obtains the first state signal, it can determine that the valid identifier corresponding to the first state signal is "valid" according to the corresponding relationship shown in Table 4, then determine that the first state signal is a valid signal, and then determine that there is an unpacking event when the computing device is in the shutdown state.

[0271] The unpacking detection method provided in the embodiment of the present application can realize latching processing of a first state signal corresponding to an unpacking event through an unpacking trigger circuit and a shutdown detection circuit when the computing device is powered off, so that after the computing device is powered on, the controller can obtain the first state signal in time through a programmable logic device, and quickly determine the unpacking event according to the first state signal, thereby ensuring the security of the computing device; and, when the computing device is powered off, the power supply circuit supplies power to the circuit (unpacking trigger circuit, shutdown detection circuit) for realizing basic detection functions, and the shutdown detection circuit includes a latch for latching the first state signal, and the latch is a simple circuit storage unit with very low power consumption. At the same time, there is no need to power the programmable logic device and the controller with large current consumption, thereby effectively reducing the power consumption of the computing device when detecting an unpacking event when the computing device is in the shutdown state.

[0272] Figure 6 This is a flow chart of another unpacking detection method provided in the embodiment of the present application. Figure 6 , the method may include:

[0273] S601: After the computing device is powered on, control the programmable logic device to obtain a first state signal from a latch.

[0274] S602: Determine, based on a first status signal, that an unpacking event occurs when the computing device is in a shutdown state.

[0275] It should be noted that the specific execution process of step S601 and step S602 can refer to the specific execution process of step S501 and step S502, which will not be repeated here.

[0276] S603: Write the event information of the unpacking event into the target storage and / or the operation log of the controller.

[0277] The target storage may be a storage preset by the user for storing various event information. In some embodiments, the target storage may be a non-volatile memory to avoid loss of event information of the unpacking event.

[0278] The event information may include the occurrence time of the unpacking event and the type of the unpacking event. The type of the unpacking event may include an unpacking event in a powered-on state and an unpacking event in a powered-off state.

[0279] S604: Send a reset instruction to the programmable logic device.

[0280] The reset instruction can be used to instruct the programmable logic device to generate a reset signal and send the reset signal to the reset terminal of the latch.

[0281] The reset signal can be used to instruct the latch to reset the output terminal of the latch.

[0282] In some embodiments, the programmable logic device may perform the following steps: generating a reset signal in response to a reset instruction; and sending the reset signal to a reset terminal of a latch.

[0283] It should be noted that the specific execution process of resetting the output end of the latch can refer to the specific execution process of resetting the output end of the latch in the above embodiment, which will not be repeated here.

[0284] S605: Send a release reset instruction to the programmable logic device.

[0285] In some embodiments, the controller may execute step S605 after the target duration.

[0286] The target duration may be the duration between the reset start time and the reset completion time, and may be determined based on historical reset data of the latch.

[0287] In some embodiments, the programmable logic device may perform the following steps: generating a release-reset signal in response to a release-reset instruction; and sending the release-reset signal to a reset terminal of the latch.

[0288] The computing device may also include a power-on detection circuit and a power control circuit, the power control circuit is connected to the power supply circuit, and the power-on detection circuit is respectively connected to the power supply circuit, the power control circuit, the unpacking trigger circuit, and the programmable logic device. When the computing device is powered on, the power supply voltage of the power control circuit is greater than the power supply voltage of the power supply circuit, and the power supply circuit is in a non-powered state under the action of the power control circuit. The power control circuit can supply power to the unpacking trigger circuit, the shutdown detection circuit, the power-on detection circuit, the programmable logic device, and the controller.

[0289] When the computing device is powered by a power control circuit, the method may further include the following steps:

[0290] S606: Control the programmable logic device to obtain a second state signal.

[0291] The second status signal may be generated by the power-on detection circuit based on the second unpacking trigger signal, where the second unpacking trigger signal is sent by the unpacking trigger circuit to the power-on detection circuit when the chassis of the computing device is opened.

[0292] It should be noted that the process of the power-on detection circuit generating the second state signal based on the second unpacking trigger signal can refer to the specific execution process of generating the second state signal in the above embodiment, which will not be described again here.

[0293] In some embodiments, the controller can obtain the second status signal in the following manner: send a second query instruction to the programmable logic device, the second query instruction can be used to instruct the programmable logic device to obtain the current output signal of the power-on detection circuit; obtain second response information sent by the programmable logic device; and obtain the second status signal based on the second response information.

[0294] In some embodiments, the programmable logic device can perform the following operations: in response to a second query instruction, obtain a current output signal of the power-on detection circuit; when the current latch signal is a second state signal, generate a second response information; and send the second response information to the controller.

[0295] It can be understood that the current output signal may be a second state signal or a fourth state signal.

[0296] If the current output signal obtained by the programmable logic device is a second state signal, the second state signal is encoded to obtain second encoded data, the second encoded data is stored in BIT1 of the I2C communication frame, and second response information is generated; the second response information is sent to the controller. If the current output signal obtained by the programmable logic device is a fourth state signal, the fourth state signal is encoded to obtain fourth encoded data, the fourth encoded data is stored in BIT1 of the I2C communication frame, and fourth response information is generated; the fourth response information is sent to the controller.

[0297] In some embodiments, after sending the second query instruction to the programmable logic device, the controller may also perform the following process: obtaining fourth response information sent by the programmable logic device; obtaining a fourth status signal based on the fourth response information; and determining based on the fourth status signal that there is no unpacking event when the computing device is in the power-on state.

[0298] The controller may pre-store the correspondence shown in Table 2, and may determine the second state signal based on the correspondence and the second coded data in the second response information; the controller may determine the fourth state signal based on the correspondence and the fourth coded data in the fourth response information.

[0299] S607: Determine, based on the second status signal, that an unpacking event occurs when the computing device is in a powered-on state.

[0300] In some embodiments, the controller may pre-store indication information corresponding to each status signal (such as Table 2). After the controller obtains the second status signal, it may determine whether an unpacking event occurs when the computing device is in the power-on state based on the indication information corresponding to the second status signal.

[0301] In some embodiments, the controller may pre-store validity identifiers corresponding to various status signals (such as Table 4). After obtaining the second status signal, the controller may determine that the second status signal is a valid signal based on the validity identifier corresponding to the second status signal, and further determine that an unpacking event occurs when the computing device is in the power-on state.

[0302] The unpacking detection method provided in the embodiment of the present application can realize the detection of unpacking events of the computing device in the shutdown state, and realize the real-time detection of unpacking events of the computing device in the power-on state, so as to realize the all-weather unpacking detection function of the computing device, so as to timely discover the unpacking events of the computing device and ensure the safety of the computing device. In addition, when the computing device is powered off, the power supply circuit supplies power to the circuit (unpacking trigger circuit, shutdown detection circuit) for realizing the basic detection function, and the shutdown detection circuit includes a latch for latching the first state signal. The latch is a simple circuit storage unit with very low power consumption. At the same time, there is no need to power the programmable logic device and controller with large current consumption, which effectively reduces the power consumption of the computing device in detecting unpacking events in the shutdown state.

[0303] Figure 7 This is a flow chart of another unpacking detection method provided in the embodiment of the present application. Figure 7 , the method specifically comprises:

[0304] S701. After the computing device is powered on, the programmable logic device is controlled to obtain a current latch signal of the latch from the latch.

[0305] The method may be executed by a controller in the computing device shown in the above embodiment.

[0306] It should be noted that the specific execution process of obtaining the current latch signal in step S701 can refer to the specific execution process of obtaining the current latch signal in step S501, which will not be repeated here.

[0307] S702: Determine, based on the current latch signal, whether there is an unpacking event when the computing device is in a shutdown state.

[0308] If yes, execute steps S703 to S705;

[0309] If not, execute step S706.

[0310] In a possible implementation, if the current latch signal is a first state signal, it is determined that an unpacking event occurs when the computing device is in a shutdown state; if the current latch signal is a third state signal, it is determined that no unpacking event occurs when the computing device is in a shutdown state.

[0311] S703: Write the event information of the unpacking event into the target storage and / or the operation log of the controller.

[0312] The event information may include the time when the unpacking event occurred. By recording the event information of the unpacking event in the operation log, the user can quickly and timely discover the unpacking event of the computing device based on the operation log, so as to avoid physical intrusion into the computing device and ensure the security of the computing device.

[0313] S704: Send a reset instruction to the programmable logic device.

[0314] S705: Send a release reset instruction to the programmable logic device.

[0315] It should be noted that the specific execution process of steps S704 and S705 can refer to the specific execution process of steps S604 and S605, which will not be repeated here.

[0316] S706: Control the programmable logic device to obtain the current output signal of the power-on detection circuit.

[0317] In some embodiments, when the computing device is in a powered-on state, step S706 may be performed in a polling manner.

[0318] In some embodiments, when the unpacking trigger circuit detects an unpacking event in the power-on state, it can output a second unpacking trigger signal to the power-on detection circuit. The power-on detection circuit can send a second status signal to the programmable logic device based on the second unpacking trigger signal. The programmable logic device can report an interrupt signal to the controller based on the second status signal, so that the computing device can monitor the unpacking event in the power-on state in real time to ensure the security of the computing device.

[0319] S707: Determine, based on the current output signal, whether there is an unpacking event when the computing device is powered on.

[0320] If yes, then execute step S703 first, and then execute step S706.

[0321] If not, the process returns to step S706 until the computing device is powered off.

[0322] In a possible implementation, if the current output signal is the second state signal, it is determined that an unpacking event occurs when the computing device is in the powered-on state; if the current output signal is the fourth state signal, it is determined that no unpacking event occurs when the computing device is in the powered-on state.

[0323] The unpacking detection method provided in the embodiment of the present application can realize the detection of unpacking events of the computing device in the shutdown state, and realize the real-time detection of unpacking events of the computing device in the power-on state, so as to realize the all-weather unpacking detection function of the computing device, so as to timely discover the unpacking events of the computing device and ensure the safety of the computing device. In addition, when the computing device is powered off, the power supply circuit supplies power to the circuit (unpacking trigger circuit, shutdown detection circuit) for realizing the basic detection function, and the shutdown detection circuit includes a latch for latching the first state signal. The latch is a simple circuit storage unit with very low power consumption. At the same time, there is no need to power the programmable logic device and controller with large current consumption, which effectively reduces the power consumption of the computing device in detecting unpacking events in the shutdown state.

[0324] Figure 8 This is a schematic diagram of the structure of a controller provided in an embodiment of the present application. Figure 8 , the controller 105 can be applied to the computing device 10 in the above embodiment, the computing device also includes an unpacking trigger circuit, a shutdown detection circuit, a power supply circuit and a programmable logic device, the shutdown detection circuit is connected between the unpacking trigger circuit and the programmable logic device, the controller is connected to the programmable logic device, when the computing device is powered off, the power supply circuit supplies power to the unpacking trigger circuit and the shutdown detection circuit, and the programmable logic device and the controller are in a power-off state; the controller may include: an acquisition module 1051, a processing module 1052 and a sending module 1053, wherein,

[0325] The acquisition module 1051 is used to control the programmable logic device to acquire a first state signal from a latch after the computing device is powered on. The latch is located in the shutdown detection circuit. The latch is used to latch the first state signal. The first state signal is generated by the shutdown detection circuit based on the first unboxing trigger signal. The first unboxing trigger signal is sent by the unboxing trigger circuit to the shutdown detection circuit when the chassis of the computing device is opened.

[0326] The processing module 1052 is configured to determine, based on the first status signal, that an unpacking event occurs when the computing device is in a shutdown state.

[0327] In a possible implementation, after determining that an unpacking event occurs when the computing device is in a shutdown state, the processing module 1052 is further configured to write event information of the unpacking event into a target memory and / or an operation log of the controller;

[0328] The sending module 1053 is used to send a reset instruction to the programmable logic device, the reset instruction is used to instruct the programmable logic device to generate a reset signal, and send a reset signal to the reset end of the latch, the reset signal is used to instruct the latch to reset the output end of the latch.

[0329] In a possible implementation, the computing device further includes a power-on detection circuit and a power control circuit, the power control circuit is connected to the power supply circuit, the power-on detection circuit is respectively connected to the power supply circuit, the power control circuit, the unpacking trigger circuit and the programmable logic device, when the computing device is powered on, the power supply voltage of the power control circuit is greater than the power supply voltage of the power supply circuit, the power supply circuit is in a non-powered state under the action of the power control circuit, and the power control circuit supplies power to the unpacking trigger circuit, the power-off detection circuit, the power-on detection circuit, the programmable logic device and the controller;

[0330] The acquisition module 1051 is further used to control the programmable logic device to acquire a second state signal, where the second state signal is generated by the power-on detection circuit based on the second unboxing trigger signal, and the second unboxing trigger signal is sent by the unboxing trigger circuit to the power-on detection circuit when the chassis of the computing device is opened;

[0331] The processing module 1052 is further configured to determine, based on the second status signal, that an unpacking event occurs when the computing device is in a powered-on state.

[0332] In a possible implementation, the sending module 1053 is further used to send a first query instruction to the programmable logic device after the computing device is powered on, where the first query instruction may be used to instruct the programmable logic device to obtain a current latch signal from the latch;

[0333] The acquisition module 1051 is also used to acquire the first response information sent by the programmable logic device;

[0334] The acquisition module 1051 is further configured to acquire a first status signal according to the first response information.

[0335] In a possible implementation, the sending module 1053 is further used to send a second query instruction to the programmable logic device, where the second query instruction can be used to instruct the programmable logic device to obtain a current output signal of the power-on detection circuit;

[0336] The acquisition module 1051 is further used to acquire second response information sent by the programmable logic device; and acquire a second state signal according to the second response information.

[0337] In a possible implementation, the acquisition module 1051 is further used to, after the computing device is powered on, acquire third response information sent by the programmable logic device;

[0338] The acquisition module 1051 is further configured to acquire a third state signal according to the third response information;

[0339] The processing module 1052 is further configured to determine, based on the third status signal, that there is no unpacking event when the computing device is in the shutdown state.

[0340] In a possible implementation, the acquisition module 1051 is further used to acquire fourth response information sent by the programmable logic device;

[0341] The acquisition module 1051 is further configured to acquire a fourth state signal according to the fourth response information;

[0342] The processing module 1052 is further configured to determine, based on the fourth status signal, that there is no unpacking event when the computing device is in the power-on state.

[0343] The controller provided in the embodiment of the present application can be used to implement the unpacking detection method as described in the above embodiment. Its implementation principle and technical effect are similar and will not be described in detail here.

[0344] An embodiment of the present application provides a computer-readable storage medium, on which computer-executable instructions are stored; when the computer-executable instructions are executed by a processor, they are used to implement the unpacking detection method as described in the above embodiment, and the implementation principle and technical effect are similar, which will not be elaborated here.

[0345] An embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the computer executes the unpacking detection method described in the above embodiment. The implementation principle and technical effect are similar and will not be described in detail here.

[0346] All or part of the steps of the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a readable memory. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned memory (storage medium) includes: read-only memory (English: read-only memory, abbreviated: ROM), RAM, flash memory, hard disk, solid state drive, magnetic tape (English: magnetic tape), floppy disk (English: floppy disk), optical disc (English: optical disc) and any combination thereof.

[0347] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable terminal device to generate a machine, so that the instructions executed by the processing unit of the computer or other programmable terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0348] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0349] These computer program instructions can also be loaded onto a computer or other programmable terminal device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0350] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, rather than to limit them. Although the embodiments of the present application have been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A computing device, characterized in that: include: An unpacking trigger circuit, a shutdown detection circuit, a power supply circuit, a programmable logic device, and a controller, wherein the shutdown detection circuit is connected between the unpacking trigger circuit and the programmable logic device, and the controller is connected to the programmable logic device. When the computing device is powered off, the power supply circuit supplies power to the unpacking trigger circuit and the shutdown detection circuit, and the programmable logic device and the controller are in a power-off state; The unpacking trigger circuit sends a first unpacking trigger signal to the shutdown detection circuit when the chassis of the computing device is opened; The shutdown detection circuit comprises a latch, the shutdown detection circuit generates a first state signal based on the first unpacking trigger signal, and the latch is used to latch the first state signal; After the computing device is powered on, the controller obtains the first state signal from the latch through the programmable logic device, and determines, based on the first state signal, that an unpacking event occurs when the computing device is in a shutdown state.

2. The computing device according to claim 1, wherein: The unpacking trigger circuit includes a switch, the chassis includes a chassis cover, a first end of the switch is connected to the chassis cover, the chassis cover is connected to the ground, a second end of the switch is connected to the power supply circuit, and one end of the shutdown detection circuit is connected between the second end of the switch and the power supply circuit; When the chassis cover is opened, the switch is turned off, and the unpacking trigger circuit, under the action of the power supply circuit, sends the first unpacking trigger signal to the shutdown detection circuit.

3. The computing device according to claim 2, characterized in that The latch is a NAND latch, and the shutdown detection circuit further includes a first metal-oxide semiconductor MOS tube; The set end of the NAND latch is connected to the drain of the first MOS transistor, the drain of the first MOS transistor is also connected to the power supply circuit, the gate of the first MOS transistor is connected between the second end of the switch and the power supply circuit, and the source of the first MOS transistor is connected to the ground; The reset end of the NAND latch is connected to the programmable logic device and the power supply circuit respectively; The output end of the NAND latch is connected to the programmable logic device; When the gate of the first MOS transistor receives the first box-opening trigger signal, the first MOS transistor is turned on and sends an initial state signal to the NAND latch, so that the NAND latch generates the first state signal based on the initial state signal.

4. The computing device according to claim 3, characterized in that The shutdown detection circuit also includes a first voltage-dividing resistor and a second voltage-dividing resistor. The drain of the first MOS tube is connected to the power supply circuit through the first voltage-dividing resistor, and the reset end of the NAND latch is connected to the power supply circuit through the second voltage-dividing resistor. The resistance value of the second voltage-dividing resistor is greater than the resistance value of the first voltage-dividing resistor.

5. The computing device according to claim 4, characterized in that The computing device further includes a power control circuit, the shutdown detection circuit further includes a third voltage-dividing resistor and a fourth voltage-dividing resistor, a first resistance value of the fourth voltage-dividing resistor is less than a second resistance value of the third voltage-dividing resistor, and a difference between the second resistance value and the first resistance value is greater than a preset threshold value; A first end of the third voltage-dividing resistor is connected to the source of the first MOS tube, and a second end of the third voltage-dividing resistor is connected to the ground; A first end of the fourth voltage-dividing resistor is connected to a first end of the power control circuit, and a second end of the fourth voltage-dividing resistor is connected between the source of the first MOS tube and the third voltage-dividing resistor; The second end of the power control circuit is connected to the power supply circuit. After the computing device is powered on, the power supply voltage of the power control circuit is greater than the power supply voltage of the power supply circuit. The power supply circuit is in a non-powered state under the action of the power control circuit. The power control circuit supplies power to the unpacking trigger circuit, the shutdown detection circuit, the programmable logic device and the controller. The first MOS tube is in a cut-off state under the voltage dividing action of the third voltage dividing resistor and the fourth voltage dividing resistor.

6. The computing device according to claim 2, wherein: The latch is a NOR latch, and the shutdown detection circuit further includes a fifth voltage-dividing resistor, wherein: The set end of the NOR latch is connected between the second end of the switch and the power supply circuit; The reset end of the NOR latch is connected to the first end of the fifth voltage-dividing resistor and the programmable logic device respectively, and the second end of the fifth voltage-dividing resistor is connected to the ground; The output end of the NOR latch is connected to the programmable logic device.

7. The computing device according to any one of claims 2 to 6, characterized in that: The computing device further includes a power-on detection circuit and a power control circuit, wherein the power-on detection circuit includes a second MOS tube, wherein: The gate of the second MOS tube is connected to the second end of the switch; The drain of the second MOS tube is connected to the power control circuit and the programmable logic device respectively; The source of the second MOS tube is connected to the ground.

8. The computing device according to any one of claims 1 to 7, characterized in that: After determining that an unpacking event occurs when the computing device is in a shutdown state, the controller writes event information of the unpacking event into a target memory and / or an operation log of the controller, and sends a reset instruction to the programmable logic device; The programmable logic device generates a reset signal in response to the reset instruction, and sends the reset signal to the reset terminal of the latch; The latch performs a reset process on an output terminal of the latch based on the reset signal.

9. A method for unpacking detection, characterized in that: In a controller applied to a computing device, the computing device further comprises an unpacking trigger circuit, a shutdown detection circuit, a power supply circuit and a programmable logic device, the shutdown detection circuit is connected between the unpacking trigger circuit and the programmable logic device, the controller is connected to the programmable logic device, when the computing device is powered off, the power supply circuit supplies power to the unpacking trigger circuit and the shutdown detection circuit, and the programmable logic device and the controller are in a power-off state; the method comprises: After the computing device is powered on, the programmable logic device is controlled to obtain a first state signal from a latch, the latch is located in the shutdown detection circuit, the latch is used to latch the first state signal, the first state signal is generated by the shutdown detection circuit based on a first unboxing trigger signal, and the first unboxing trigger signal is sent by the unboxing trigger circuit to the shutdown detection circuit when the chassis of the computing device is opened; It is determined based on the first status signal that an unpacking event occurs when the computing device is in a shutdown state.

10. The method according to claim 9, characterized in that After determining that an unpacking event occurs when the computing device is in a shutdown state, the method further includes: Writing the event information of the unpacking event into the target storage and / or the operation log of the controller; A reset instruction is sent to the programmable logic device, wherein the reset instruction is used to instruct the programmable logic device to generate a reset signal, and the reset signal is sent to a reset end of the latch, wherein the reset signal is used to instruct the latch to reset an output end of the latch.

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