A memory error monitoring method, device, system, equipment, medium and product

Abstract

The present invention discloses a memory error monitoring method, device, system, equipment, medium and product, and relates to the field of memory test technology. The method is to first start to enter the interrupt mode to monitor whether the signal input pin receives the memory error trigger signal from the CPU, if so, the interrupt response is used to process the memory error, and switch to the query mode, and then in the query mode, the CPU's memory error register is regularly queried to see whether there is a memory error information update, if so, the interrupt response is used to process the memory error, and re-timing is performed, and if no memory error information update is found within a certain period of time, the interrupt mode is re-entered, so that the first memory error in each memory error storm can be avoided from being missed, and the purpose of timely obtaining the first memory error information generated by the CPU and timely interrupting the response to process the memory error can be achieved without causing a serious burden on the system, which is beneficial to improving the efficiency of memory testing and is convenient for practical application and promotion.

Description

Technical Field

[0001] The present invention belongs to the field of memory testing technology, and in particular relates to a memory error monitoring method, device, system, equipment, medium and product. Background Art

[0002] For the monitoring / supervision task of memory errors, each memory manufacturer has its own RAS (Reliability, Availability and Serviceability) mechanism to capture memory errors in a timely and accurate manner, so as to handle the errors and avoid affecting the system as much as possible.

[0003] At present, there are generally two connection channels from the CPU (Central Processing Unit) to the BMC (Baseboard Management Controller, which is an embedded management controller located on the server motherboard and is responsible for monitoring, managing and remotely operating the server), namely, the CPU's error signal output pin ERROR_PIN will be connected to the BMC's GPIO (General-purpose input / output) pin, and the CPU's PECI (Platform Environment Control Interface) pin will be connected to the BMC's PECI bus. When the CPU finds a memory error based on the RAS mechanism, it will put the memory error information on the relevant registers and output a pulse signal through the error signal output pin ERROR_PIN to trigger an interrupt on the BMC side, and then the BMC will obtain the detailed memory error information through the PECI bus, and finally notify the OS (Operating System) to perform the corresponding memory error processing. However, if many errors occur, the CPU will frequently generate pulse signals to notify the BMC interrupt. After the BMC obtains the memory error information, it will also frequently generate SMI (System Management Interrupt) interrupts to notify the CPU to handle the errors. This is a heavy burden for both the BMC and the CPU, because the SMI interrupt has the highest priority. The CPU has to stop existing work to handle the SMI interrupt, causing a serious decline in system performance.

[0004] In response to the above problem, the existing practice is that the BMC does not respond to the pulse signal sent by the CPU through the error signal output pin ERROR_PIN, but starts a timer to obtain memory error information through the PECI bus at a regular interval, and then formulates a strategy to notify the CPU to handle the error. However, this may result in the first memory error not being obtained (because the memory error information generated later will overwrite the memory error information generated earlier), that is, only one memory error information can be obtained through the PECI bus, and the later memory error information will overwrite the previous memory error information in the register, which may cause the previous error information to not be obtained in time.

[0005] In summary, how to promptly obtain the first memory error information generated by the CPU and promptly interrupt the response to handle the memory error without causing a serious burden on the system is a topic that technical personnel in this field urgently need to study. Summary of the invention

[0006] The object of the present invention is to provide a memory error monitoring method, apparatus, system, computer equipment, computer-readable storage medium and computer program product to solve the problem that existing memory error monitoring solutions either cause a serious burden on the BMC, CPU and system, or may not obtain the memory error generated for the first time.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] In a first aspect, a memory error monitoring method is provided, which is executed by a motherboard management controller and includes:

[0009] Start into interrupt mode: monitor whether the signal input pin receives a memory error trigger signal from the CPU, wherein the signal input pin is connected to the error signal output pin of the CPU;

[0010] If it is found that the signal input pin has received the memory error trigger signal, an interrupt response is performed to process the memory error, and the query mode is switched to: a first timer and a second timer are started respectively, and then when the timing value of the first timer reaches a first preset duration, a query is made as to whether the memory error register of the CPU has memory error information updated;

[0011] If it is found that the memory error register has memory error information updated, interrupt response processing memory error, and restart the first timer and the second timer;

[0012] If no memory error information update is found in the memory error register when the timing value of the second timer reaches a second preset time length, the interrupt mode is switched to, wherein the second preset time length is greater than the first preset time length.

[0013] Based on the above invention content, a new scheme for memory error monitoring by switching between interrupt mode and query mode is provided, that is, first start to enter the interrupt mode to monitor whether the signal input pin receives a memory error trigger signal from the CPU. If so, the interrupt response processes the memory error and switches to the query mode. Then, in the query mode, the CPU's memory error register is periodically queried to see whether there is any memory error information update. If so, the interrupt response processes the memory error and re-timing is performed. If no memory error information update is found within a certain period of time, the interrupt mode is re-entered. In this way, it is possible to avoid missing the first memory error in each memory error storm, thereby achieving the purpose of timely obtaining the first memory error information generated by the CPU and timely interrupting the response to process the memory error without causing a serious burden on the system. This is beneficial to improving the efficiency of memory testing and is convenient for practical application and promotion.

[0014] In one possible design, the interrupt response to handle memory errors includes:

[0015] Register an interrupt service routine;

[0016] Using the interrupt service routine to capture memory error information from a memory error register of the CPU;

[0017] According to the captured memory error information, the CPU is notified via SMI / SCI interrupt to handle the memory error: the operating system is notified via ACPI to perform memory error processing corresponding to the memory error information.

[0018] In a possible design, querying whether the memory error register of the CPU has memory error information updated includes:

[0019] The memory error register of the CPU is accessed through the PECI bus connected to the CPU, and the memory error register is queried whether there is any memory error information update.

[0020] In one possible design, after querying whether the memory error register of the CPU has memory error information updated, the method further includes:

[0021] If it is found that the memory error register has no memory error information update, only the first timer is restarted.

[0022] In one possible design, the second preset duration is greater than or equal to 4 seconds and less than or equal to 6 seconds.

[0023] In a second aspect, a memory error monitoring device is provided, which is suitable for being arranged in a motherboard management controller, and includes a working mode startup unit, a trigger signal response unit, an error update response unit and a working mode switching unit;

[0024] The working mode startup unit is used to start entering the interrupt mode: monitor whether the signal input pin receives a memory error trigger signal from the CPU, wherein the signal input pin is connected to the error signal output pin of the CPU;

[0025] The trigger signal response unit is communicatively connected to the working mode start unit, and is used for interrupting the response to process the memory error if it is found that the signal input pin has received the memory error trigger signal, and switching to the query mode: starting the first timer and the second timer respectively, and then when the timing value of the first timer reaches the first preset time length, querying whether the memory error register of the CPU has memory error information updated;

[0026] The error update response unit is communicatively connected to the trigger signal response unit, and is used for interrupting the response processing of the memory error if it is found that the memory error register has memory error information updated, and restarting the first timer and the second timer;

[0027] The working mode switching unit is communicatively connected to the trigger signal response unit, and is used to switch into the interrupt mode if no memory error information update is found in the memory error register when the timing value of the second timer reaches a second preset time length, wherein the second preset time length is greater than the first preset time length.

[0028] In a third aspect, the present invention provides a memory error monitoring system, comprising a CPU and a motherboard management controller, wherein the CPU has a built-in memory error register, an error signal output pin of the CPU is connected to a signal input pin of the motherboard management controller, and the motherboard management controller is also connected to the CPU via a PECI bus;

[0029] The CPU is used to store memory error information in the memory error register when a memory error is found through the RAS mechanism, and transmit a memory error trigger signal to the signal input pin through the error signal output pin;

[0030] The motherboard management controller is used to execute the memory error monitoring method as described in the first aspect or any possible design of the first aspect.

[0031] In a fourth aspect, the present invention provides a control device, comprising a storage module, a processing module and a transceiver module which are communicatively connected in sequence, wherein the storage module is used to store a computer program, the transceiver module is used to send and receive messages, and the processing module is used to read the computer program and execute the memory error monitoring method as described in the first aspect or any possible design of the first aspect.

[0032] In a fifth aspect, the present invention provides a computer-readable storage medium having instructions stored thereon. When the instructions are executed on a computer, the memory error monitoring method as described in the first aspect or any possible design of the first aspect is executed.

[0033] In a sixth aspect, the present invention provides a computer program product, comprising a computer program or instructions, which, when executed by a computer, implement the memory error monitoring method as described in the first aspect or any possible design of the first aspect.

[0034] Beneficial effects of the above scheme:

[0035] (1) The present invention creatively provides a new scheme for memory error monitoring by switching between interrupt mode and query mode, that is, first starting to enter the interrupt mode to monitor whether the signal input pin receives a memory error trigger signal from the CPU. If so, the interrupt response is used to process the memory error and the query mode is switched. Then, in the query mode, the CPU's memory error register is periodically queried to see whether there is any memory error information update. If so, the interrupt response is used to process the memory error and the timing is reset. If no memory error information update is found within a certain period of time, the interrupt mode is re-entered. In this way, the first memory error in each memory error storm can be avoided from being missed, so as to achieve the purpose of timely obtaining the first memory error information generated by the CPU and timely interrupting the response to process the memory error without causing a serious burden on the system, thereby improving the efficiency of memory testing and facilitating practical application and promotion. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 A flowchart of a memory error monitoring method provided in an embodiment of the present application.

[0038] Figure 2 A schematic diagram of the structure of a memory error monitoring device provided in an embodiment of the present application.

[0039] Figure 3 A schematic diagram of the structure of a memory error monitoring system provided in an embodiment of the present application.

[0040] Figure 4 A schematic diagram of the structure of a control device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structures of the drawings is only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these embodiments without creative work. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention.

[0042] It should be understood that although the terms first and second, etc. may be used herein to describe various objects, these objects should not be limited by these terms. These terms are only used to distinguish one object from another object. For example, a first object can be referred to as a second object, and similarly, a second object can be referred to as a first object without departing from the scope of the exemplary embodiments of the present invention.

[0043] It should be understood that the term "and / or" that may appear in this document is merely a description of the association relationship between associated objects, indicating that there may be three relationships. For example, A and / or B can indicate three situations: A exists alone, B exists alone, or A and B exist at the same time. For another example, A, B and / or C can indicate the existence of any one of A, B and C or any combination of them. The term " / and" that may appear in this document describes another type of association object relationship, indicating that there may be two relationships. For example, A / and B can indicate two situations: A exists alone or A and B exist at the same time. In addition, the character " / " that may appear in this document generally indicates that the previous and next associated objects are in an "or" relationship.

[0044] Example

[0045] like Figure 1 As shown, the memory error monitoring method provided in the first aspect of this embodiment can be, but is not limited to, executed by a motherboard management controller having certain computing resources and connected to a CPU, wherein the CPU has a built-in memory error register, the error signal output pin of the CPU is connected to the signal input pin of the motherboard management controller, and the motherboard management controller is also connected to the CPU via a PECI bus; the CPU is used to store the memory error information in the memory error register when a memory error is found through the RAS mechanism, and transmit a memory error trigger signal to the signal input pin through the error signal output pin. The memory error monitoring method includes, but is not limited to, the following steps S1 to S4.

[0046] S1. Start to enter the interrupt mode: monitor whether the signal input pin receives a memory error trigger signal from the CPU, wherein the signal input pin is connected to the error signal output pin of the CPU.

[0047] In the step S1, the motherboard management controller can automatically enter the interrupt mode by default after startup. The memory error trigger signal is output when the CPU finds a memory error through the existing RAS mechanism (and the memory error information needs to be stored in the memory error register), and is specifically but not limited to a pulse signal. In addition, the signal input pin can be but not limited to a GPIO pin.

[0048] S2. If it is found that the signal input pin has received the memory error trigger signal, the interrupt response processes the memory error and switches to the query mode: start the first timer and the second timer respectively, and then when the timing value of the first timer reaches the first preset duration, query whether the memory error register of the CPU has memory error information updated.

[0049] In step S2, the specific process of the above-mentioned interrupt response to handle memory errors is to first trigger an interrupt, then obtain detailed memory error information through the PECI bus, and finally notify the OS to perform corresponding memory error processing; specifically, the interrupt response to handle memory errors includes but is not limited to the following steps S21 to S23.

[0050] S21. Register an interrupt service routine.

[0051] In the step S21, the interrupt service routine may be registered conventionally and configured as a high priority so as to be executed preferentially.

[0052] S22. Using the interrupt service program to capture memory error information from the memory error register of the CPU.

[0053] In the step S22, the memory error register of the CPU needs to be accessed through the PECI bus connected to the CPU, so that the memory error information can be conventionally captured from the memory error register.

[0054] S23. Based on the captured memory error information, the CPU is notified via SMI / SCI (System Control Interrupt) interrupt to handle the memory error: the operating system is notified via ACPI (Advanced Configuration and Power Management Interface) to perform memory error processing corresponding to the memory error information.

[0055] In step S23, the specific means of the above-mentioned SMI / SCI interrupt notification and ACPI notification are both existing technical means, and the specific means of the above-mentioned operating system performing memory error processing corresponding to the memory error information are also existing technical means.

[0056] In step S2, since there will always be memory error information in the memory error register of the CPU, it is necessary to query whether the memory error register has updated memory error information, so as to confirm whether there are any newly discovered memory errors recently, and then determine whether an interrupt response is required to handle the memory error. Specifically, querying whether the memory error register of the CPU has updated memory error information includes but is not limited to the following steps: accessing the memory error register of the CPU by connecting the PECI bus of the CPU, and querying whether the memory error register has updated memory error information. The specific method of the aforementioned query to determine whether the memory error register has updated memory error information can be completed based on, but not limited to, the storage timestamp of the memory error information: obtaining the storage timestamp of the memory error information, if the time from the storage timestamp to the current timestamp is less than or equal to the first preset time, then confirming that the memory error register has updated memory error information, otherwise confirming that the memory error register has no memory error information update. In addition, the first preset time can be, but is not limited to, 1 second as an example.

[0057] S3. If it is found that the memory error register has memory error information updated, an interrupt response is performed to process the memory error, and the first timer and the second timer are restarted.

[0058] In the step S3, the specific details of the above-mentioned interrupt response processing memory error can be directly obtained by referring to the above-mentioned steps S21 to S23. After restarting the first timer and the second timer, if the timing value of the first timer reaches the first preset duration again, the memory error register of the CPU will be queried again to see if there is any memory error information update, so as to achieve the purpose of performing interrupt response processing memory errors at a regular interval and reduce the burden on the BMC, CPU and system. In addition, after querying the memory error register of the CPU to see if there is any memory error information update, the method also includes but is not limited to: if it is found that the memory error register has no memory error information update, only restart the first timer (of course, if the timing value of the first timer reaches the first preset duration again, the memory error register of the CPU will be queried again to see if there is any memory error information update).

[0059] S4. If no memory error information update is found in the memory error register when the timing value of the second timer reaches the second preset time length, switch to the interrupt mode, wherein the second preset time length is greater than the first preset time length.

[0060] In step S4, it is considered that memory errors always appear explosively, but after the storm, they stop appearing. Therefore, if no new memory errors are found within a certain period of time, it is necessary to re-enter the interrupt mode to avoid missing the first memory error in a memory error storm. In addition, the second preset time length is specifically greater than or equal to 4 seconds and less than or equal to 6 seconds, and is generally 5 seconds.

[0061] Therefore, based on the memory error monitoring method described in the aforementioned steps S1 to S4, a new scheme for memory error monitoring by switching between interrupt mode and query mode is provided, that is, first starting to enter the interrupt mode to monitor whether the signal input pin receives a memory error trigger signal from the CPU. If so, the interrupt response is used to process the memory error, and the query mode is switched. Then, in the query mode, the CPU's memory error register is periodically queried to see whether there is any memory error information update. If so, the interrupt response is used to process the memory error, and the timing is re-set. If no memory error information update is found within a certain period of time, the interrupt mode is re-entered. In this way, the first memory error in each memory error storm can be avoided from being missed, and the purpose of timely obtaining the first memory error information generated by the CPU and timely interrupting the response to process the memory error can be achieved without causing a serious burden on the system. This is beneficial to improving the efficiency of memory testing and is convenient for practical application and promotion.

[0062] like Figure 2 As shown, the second aspect of this embodiment provides a virtual device for implementing the memory error monitoring method described in the first aspect, which is suitable for being arranged in a motherboard management controller, and includes a working mode startup unit, a trigger signal response unit, an error update response unit and a working mode switching unit;

[0063] The working mode startup unit is used to start entering the interrupt mode: monitor whether the signal input pin receives a memory error trigger signal from the CPU, wherein the signal input pin is connected to the error signal output pin of the CPU;

[0064] The trigger signal response unit is communicatively connected to the working mode start unit, and is used for interrupting the response to process the memory error if it is found that the signal input pin has received the memory error trigger signal, and switching to the query mode: starting the first timer and the second timer respectively, and then when the timing value of the first timer reaches the first preset time length, querying whether the memory error register of the CPU has memory error information updated;

[0065] The error update response unit is communicatively connected to the trigger signal response unit, and is used for interrupting the response processing of the memory error if it is found that the memory error register has memory error information updated, and restarting the first timer and the second timer;

[0066] The working mode switching unit is communicatively connected to the trigger signal response unit, and is used to switch into the interrupt mode if no memory error information update is found in the memory error register when the timing value of the second timer reaches a second preset time length, wherein the second preset time length is greater than the first preset time length.

[0067] In one possible design, it also includes an error non-update response unit that is communicatively connected to the trigger signal response unit, wherein the error non-update response unit is used to restart only the first timer if it is found that the memory error register has no memory error information update.

[0068] The working process, working details and technical effects of the aforementioned device provided in the second aspect of this embodiment can be referred to the memory error monitoring method described in the first aspect, and will not be repeated here.

[0069] like Figure 3 As shown, the third aspect of this embodiment provides a physical system for implementing the memory error monitoring method described in the first aspect, including a CPU and a motherboard management controller, wherein the CPU has a built-in memory error register, the error signal output pin of the CPU is connected to the signal input pin of the motherboard management controller, and the motherboard management controller is also connected to the CPU via a PECI bus;

[0070] The CPU is used to store memory error information in the memory error register when a memory error is found through the RAS mechanism, and transmit a memory error trigger signal to the signal input pin through the error signal output pin;

[0071] The motherboard management controller is used to execute the memory error monitoring method as described in the first aspect.

[0072] The working process, working details and technical effects of the aforementioned system provided in the third aspect of this embodiment can be found in the memory error monitoring method described in the first aspect, and will not be repeated here.

[0073] like Figure 4As shown, the fourth aspect of this embodiment provides a control device for executing the memory error monitoring method as described in the first aspect, including a storage module, a processing module and a transceiver module that are sequentially connected in communication, wherein the storage module is used to store a computer program, the transceiver module is used to send and receive messages, and the processing module is used to read the computer program and execute the memory error monitoring method as described in the first aspect. For example, the storage module may include, but is not limited to, a random access memory (Random-Access Memory, RAM), a read-only memory (Read-Only Memory, ROM), a flash memory (Flash Memory), a first-in-first-out memory (First Input First Output, FIFO) and / or a first-in-last-out memory (First Input Last Output, FILO), etc.; the processing module may include, but is not limited to, a microprocessor of the STM32F105 series. In addition, the control device may also include, but is not limited to, a power module, a display screen and other necessary components.

[0074] The working process, working details and technical effects of the aforementioned control device provided in the fourth aspect of this embodiment can be referred to the memory error monitoring method described in the first aspect, and will not be repeated here.

[0075] In a fifth aspect of this embodiment, there is provided a computer-readable storage medium storing instructions including the memory error monitoring method as described in the first aspect, that is, the computer-readable storage medium stores instructions, and when the instructions are executed on a computer, the memory error monitoring method as described in the first aspect is executed. The computer-readable storage medium refers to a carrier for storing data, which may include but is not limited to computer-readable storage media such as floppy disks, optical disks, hard disks, flash memories, USB flash drives, and / or memory sticks (MemoryStick), and the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0076] The working process, working details and technical effects of the aforementioned computer-readable storage medium provided in the fifth aspect of this embodiment can be referred to the memory error monitoring method described in the first aspect, and will not be repeated here.

[0077] A sixth aspect of this embodiment provides a computer program product, including a computer program or instructions, wherein the computer program or instructions, when executed by a computer, implement the memory error monitoring method as described in the first aspect. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.

[0078] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A memory error monitoring method, characterized in that: Performed by the Baseboard Management Controller, including: Start into interrupt mode: monitor whether the signal input pin receives a memory error trigger signal from the CPU, wherein the signal input pin is connected to the error signal output pin of the CPU; If it is found that the signal input pin has received the memory error trigger signal, an interrupt response is performed to process the memory error, and the query mode is switched to: a first timer and a second timer are started respectively, and then when the timing value of the first timer reaches a first preset duration, the memory error register of the CPU is queried whether there is any memory error information update, wherein the querying of whether there is any memory error information update of the memory error register of the CPU includes: obtaining a storage timestamp of the memory error information, and if the duration from the storage timestamp to the current timestamp is less than or equal to the first preset duration, confirming that there is any memory error information update of the memory error register, otherwise confirming that there is no memory error information update of the memory error register; If it is found that the memory error register has memory error information updated, then the memory error is processed by interrupt response, and the first timer and the second timer are restarted; if it is found that the memory error register has no memory error information updated, then only the first timer is restarted; If no memory error information update is found in the memory error register when the timing value of the second timer reaches a second preset time length, the interrupt mode is switched to, wherein the second preset time length is greater than the first preset time length.

2. The memory error monitoring method according to claim 1, characterized in that: Interrupt response processing memory errors, including: Register an interrupt service routine; Using the interrupt service routine to capture memory error information from a memory error register of the CPU; According to the captured memory error information, the CPU is notified via SMI / SCI interrupt to handle the memory error: the operating system is notified via ACPI to perform memory error processing corresponding to the memory error information.

3. The memory error monitoring method according to claim 1, characterized in that: Checking whether the memory error register of the CPU has memory error information updated includes: The memory error register of the CPU is accessed through the PECI bus connected to the CPU, and the memory error register is queried whether there is any memory error information update.

4. The memory error monitoring method according to claim 1, characterized in that: The second preset duration is greater than or equal to 4 seconds and less than or equal to 6 seconds.

5. A memory error monitoring device, characterized in that: Suitable for being arranged in a mainboard management controller, it includes a working mode startup unit, a trigger signal response unit, an error update response unit and a working mode switching unit; The working mode startup unit is used to start entering the interrupt mode: monitor whether the signal input pin receives a memory error trigger signal from the CPU, wherein the signal input pin is connected to the error signal output pin of the CPU; The trigger signal response unit is communicatively connected to the working mode start unit, and is used for interrupting the response processing of the memory error if it is found that the signal input pin has received the memory error trigger signal, and switching to the query mode: starting the first timer and the second timer respectively, and then when the timing value of the first timer reaches the first preset duration, querying whether the memory error register of the CPU has any memory error information update, wherein querying whether the memory error register of the CPU has any memory error information update includes: obtaining the storage timestamp of the memory error information, if the duration from the storage timestamp to the current timestamp is less than or equal to the first preset duration, confirming that the memory error register has any memory error information update, otherwise confirming that the memory error register has no memory error information update; The error update response unit is communicatively connected to the trigger signal response unit, and is used for interrupting the response processing of the memory error and restarting the first timer and the second timer if it is found that the memory error register has memory error information updated, and restarting only the first timer if it is found that the memory error register has no memory error information updated; The working mode switching unit is communicatively connected to the trigger signal response unit, and is used to switch into the interrupt mode if no memory error information update is found in the memory error register when the timing value of the second timer reaches a second preset time length, wherein the second preset time length is greater than the first preset time length.

6. A memory error monitoring system, characterized in that: It includes a CPU and a motherboard management controller, wherein the CPU has a built-in memory error register, the error signal output pin of the CPU is connected to the signal input pin of the motherboard management controller, and the motherboard management controller is also connected to the CPU via a PECI bus; The CPU is used to store memory error information in the memory error register when a memory error is found through the RAS mechanism, and transmit a memory error trigger signal to the signal input pin through the error signal output pin; The motherboard management controller is used to execute the memory error monitoring method as claimed in any one of claims 1 to 4.

7. A control device, characterized in that: It includes a storage module, a processing module and a transceiver module which are communicatively connected in sequence, wherein the storage module is used to store computer programs, the transceiver module is used to send and receive messages, and the processing module is used to read the computer program to execute the memory error monitoring method as described in any one of claims 1 to 4.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores instructions, and when the instructions are executed on a computer, the memory error monitoring method as described in any one of claims 1 to 4 is executed.

9. A computer program product comprising a computer program or instructions, characterized in that The computer program or the instruction implements the memory error monitoring method according to any one of claims 1 to 4 when executed by a computer.

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