Layout layout and automatic splicing method capable of configuring LDO (Low Dropout Regulator) module

Abstract

The invention relates to the technical field of linear voltage regulators, and discloses a layout layout and automatic splicing method capable of configuring LDO modules, which comprises the following steps: S1, planning Floorplan, drawing each analog module leafcell to obtain an analog module layout, reserving an interface to a boundary boundary, defining a boundary boundary layer for program identification, and meanwhile, establishing a layout layout and an automatic splicing method of a configurable LDO module, the layout layout and the automatic splicing method of the configurable LDO module, the layout layout and the automatic splicing method of the configurable LDO module, the layout layout and the automatic splicing method of the configurable LDO module; controlling the position of a pin through a layout wiring tool, and operating to obtain a digital module layout; s2, compiling a splicing code, calculating each parameter of each LDO module through a fitting function, splicing the analog module layout and the digital module layout, and respectively obtaining an analog part layout and a digital part layout; and S3, checking the spliced digital part layout and the spliced analog part layout in sequence, and carrying out design rule checking (DRC) and layout schematic diagram consistency checking (LVS) after the digital part layout and the analog part layout pass the checking. A stable, rapid and multi-configuration effect is achieved by performing customized drawing on a simulation layout and performing configurable splicing on the simulation layout and a digital layout generated by depending on an automatic layout and wiring tool.

Description

Technical Field

[0001] The invention relates to the technical field of linear regulators, and in particular to a layout and automatic splicing method of a configurable LDO module. Background Art

[0002] Digital LDO (DLDO) has attracted much attention due to its low voltage working capability and good process scalability. Compared with traditional analog LDO (ALDO), the dynamic voltage comparator in DLDO replaces the error amplifier, and multiple small MOS tubes replace a single large power tube. The change in architecture has increased the number of analog modules and made the layout more automated, the process can be more automated, and the migration process is faster.

[0003] The layout of DLDO is a mixed digital-analog layout, which needs to take into account the integration of analog and digital layouts and the overall layout performance. The digital module is automatically laid out and routed, the analog layout is manually drawn, and the power ground and signal routing are manually connected as a whole. The analog layout requires a lot of manual work time, and each LDO needs to be manually laid out and connected separately. In view of the large number and relatively regular splicing requirements of DLDO, it is necessary to explore a splicing solution that can achieve configurable, fast, and stable completion of the layout splicing while fully realizing the overall function of the chip. Summary of the invention

[0004] The purpose of the present invention is to solve the shortcomings of the above-mentioned prior art, and to provide a layout layout and automatic splicing method for a configurable LDO module. By customizing the drawing of the analog layout, using the boundary layer as the splicing identification coordinate, and performing configurable splicing with the digital layout generated by the automatic layout and routing tool, compared with the previous shortcomings of time-consuming and labor-intensive splicing of too many modules in the digital-analog layout, a stable, fast and multi-configuration effect can be achieved, and the rapid generation of multiple LDO layouts with the same architecture but different configurations can be realized.

[0005] The present invention provides a layout and automatic splicing method of a configurable LDO module, comprising the following steps:

[0006] S1: Plan the Floorplan, draw the leaf cells of each analog module to obtain the analog module layout, reserve the interface to the boundary, define the boundary layer for program recognition, and at the same time, control the pin position through the layout and routing tool and run to obtain the digital module layout;

[0007] S2: Write the splicing code, calculate the parameters of each LDO module through the fitting function, and splice the analog module layout and the digital module layout to obtain the analog part layout and the digital part layout respectively;

[0008] S3: Check the spliced ​​digital part layout and analog part layout in turn. After they pass, perform design rule check DRC and layout principle Figure 1 Consistency check LVS.

[0009] Furthermore, the LDO module includes a power tube array, a comparator, an undershoot detection module, a load capacitor and a load resistor, and the LDO module layout splicing further includes:

[0010] Pre-draw the leaf cell layout of each simulation module and add a boundary layer as an identification coordinate. Call the layout editing library, design the placement function, and input parameters, including the current layout, the cell to be placed, the initial point coordinates, the total number of placements, the placement direction, and the upper limit of the placement rows and columns. Perform coordinate transformation and shift operations on the leaf cell layout to complete the layout.

[0011] Wherein, in step S1, planning the Floorplan and drawing the leaf cell layout of each simulation module further includes:

[0012] Determine the position and size of each analog module according to the design requirements, use the layout editor to create a new layout project, import the GDS file of the required analog module into the layout project, place the analog module in the layout editor, and rotate and scale it as needed.

[0013] Preferably, in step S1, controlling the pin positions and running the digital module layout by a layout and routing tool further comprises:

[0014] Appropriate constraints are set in the layout and routing tool to guide the layout and routing process. First, layout is performed to specify whether the pin position is located on a specific boundary of the module or is placed relative to other pins. After the layout is completed, the layout and routing tool is used to route the digital module. In this process, the tool automatically generates connection paths based on the connection relationship of the design and draws them on the layout.

[0015] Furthermore, in step S2, for the power tube array in the LDO module, splicing the analog module layout further includes:

[0016] A power tube cell includes several signal lines and several PMOS. After drawing the boundary, the width and height of the boundary layer are obtained as w and h respectively. The number of PMOS is calculated according to the fitting function, and the number of cells required in the array is calculated. n The placement coordinate position is (x init +n*w,y init ), where (x init ,y init ) is the coordinates of the first Cell.

[0017] Preferably, for the power tube array in the LDO module, splicing the digital module layout further includes:

[0018] S21: According to the pre-planned floorplan, the number of PMOS is calculated by fitting function, and the track value is obtained according to the integrated circuit process. The spacing between each signal line is d=2*track;

[0019] S22: The digital module is placed in the first quadrant, the lower left corner origin is placed at (0,0), the bottom of the digital module is used as the connection point of the power tube, and the PIN pins are placed in batches in the form of absolute coordinates by calling commands through the layout and routing tool. init +track*2*n,0), wherein the digital module width calculation formula is as follows:

[0020] Digital width =(Num pmos_coarse +Num pmos_fine )*d+offset, where Num pmos_coarse Num is the number of coarse adjustment PMOS pmos_fine To fine-tune the number of PMOS, the offset is the reserved digital module powerring width;

[0021] S23: When splicing PMOS, start by aligning the first signal line, and then place it to the right. pmos The placement coordinates are (x init +Width pmos cell*Num pmosCell *n,-height pmosCell ), where Num pmosCell is the number of PMOS in a power tube Cell, width pmosCell is the width of the power tube Cell, height pmosCell is the height of the power tube Cell.

[0022] Preferably, in step S2, for the load resistor in the LDO module, splicing the analog module layout and the digital module layout further comprises:

[0023] The load resistor is in series, and the layout of the load resistor module includes several vertical resistors and several corners, considering the connection and hierarchy of the circuit and ensuring that the actual layout is consistent with the principle Figure 1 To write a resistor splicing function separately, the total number of resistors Num R =Total resistance / single vertical resistance. If the number of columns is even, the vertical resistance is turned upside down and then placed. When the vertical resistance is connected, it is connected through the M1 wire at the boundary. The corner is planned as a wire during calculation.

[0024] More preferably, in step S2, for the load capacitor in the LDO module, splicing the analog module layout and the digital module layout further comprises:

[0025] The load capacitor is in parallel. The layout of the load capacitor module includes several small capacitors. Each capacitor can be connected to each other up and down, left and right. Through holes M3 and M1 are drawn at the upper and lower ends of the capacitor, and through holes M2 are drawn on the left and right, and then the port VOUT is connected;

[0026] When aligning the boundary layer up and down and left and right, one end relies on the automatic connection of its upper and lower parts M3, while the other end is spliced ​​by connecting the left and right M2 and the upper and lower POLY layers to achieve a parallel effect.

[0027] Furthermore, in step S3, performing a design rule check DRC further includes:

[0028] Based on the selected semiconductor process, the corresponding design rule file is set, and the design rule check DRC is run on the designed layout using the EDA tool. If there is a violation of the rule, an error report is generated to indicate the specific location and type of the violation. Then, according to the error report, the necessary adjustments are made to the design in the layout editing environment. After correction, the design rule check DRC is run again until no violation of the rule occurs.

[0029] Preferably, in step S3, the layout principle is performed Figure 1 The consistency check LVS further includes:

[0030] Ensure that there is a complete and accurate schematic, extract the netlist from the schematic and the spliced ​​layout, use EDA tools to compare the netlist of the schematic with the netlist extracted from the layout, mark any mismatches, including extra connections, actual connections, and inconsistent device parameters, generate an LVS difference report, return to the layout editing environment to make corresponding corrections, and then re-do the layout schematic after corrections. Figure 1 Consistency check LVS verification until the layout completely corresponds to the schematic.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] (1) The present invention customizes the simulation layout, pre-draws the leaf cell layout and adds the boundary layer as an identification coordinate, calls the layout editing library, and writes code to realize the splicing of the layout;

[0033] (2) The present invention completes the layout by designing and defining the placement functions such as array, and defining the input parameters as the current layout, the cell to be placed, the coordinates of the initial point, the total number of placements, the placement direction, and the upper limit of the placement rows and columns, so as to perform operations such as coordinate transformation and flipping on the leaf cells;

[0034] (3) The present invention uses configurable splicing with a digital layout generated by an automatic layout and routing tool. Compared with the previous shortcomings of splicing digital and analog layouts with too many modules, which is time-consuming and labor-intensive, the present technology can achieve a stable, fast, and multi-configuration effect;

[0035] (4) The present invention has good process transferability. The entire splicing solution can be effective for leaf cell blocks of different layouts at the same time. It only needs to modify the relevant parameters after redrawing the leaf cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0037] In the attached picture:

[0038] Figure 1 A flow chart of a layout layout and automatic splicing method of a configurable LDO module of the present invention;

[0039] Figure 2 This is a schematic diagram of the layout structure of an LDO top-level module of the present invention;

[0040] Figure 3 A schematic diagram of a Cell simulation structure of a power tube of the present invention;

[0041] Figure 4 A schematic diagram of splicing a PMOS array module of the present invention;

[0042] Figure 5 A schematic diagram of a vertical strip resistor and a corner simulation structure of the present invention;

[0043] Figure 6 A schematic diagram of a load resistance module splicing of the present invention;

[0044] Figure 7 A schematic diagram of a capacitor simulation structure of the present invention;

[0045] Figure 8 A schematic diagram of a load capacitor module splicing of the present invention;

[0046] Fig. 9 This is an LDO layout splicing example 1 of the present invention;

[0047] Fig.10 This is a second example of LDO layout splicing of the present invention;

[0048] Fig.11 This is a third example of LDO layout splicing according to the present invention. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0050] Those skilled in the art will appreciate that, unless otherwise stated, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0051] The specific implementation of the present invention is described below with reference to the accompanying drawings and embodiments.

[0052] Example 1

[0053] like Figure 1 As shown, the technical solution of a layout layout and automatic splicing method of a configurable LDO module provided in this embodiment includes the following steps:

[0054] S1: Plan the Floorplan, draw the leaf cells of each analog module to obtain the analog module layout, reserve the interface to the boundary, define the boundary layer for program recognition, and at the same time, control the pin position through the layout and routing tool and run to obtain the digital module layout;

[0055] S2: Write the splicing code, calculate the parameters of each LDO module through the fitting function, and splice the analog module layout and the digital module layout to obtain the analog part layout and the digital part layout respectively;

[0056] S3: Check the spliced ​​digital part layout and analog part layout in turn. After they pass, perform design rule check DRC and layout principle Figure 1 Consistency check LVS.

[0057] Among them, Figure 2 As shown, the LDO module includes a power tube array, a comparator, an undershoot detection module, a load capacitor and a load resistor. In this embodiment, the LDO module layout splicing further includes:

[0058] Pre-draw the leaf cell layout of each simulation module and add a boundary layer as an identification coordinate. Call the layout editing library, design the placement function, and input parameters, including the current layout, the cell to be placed, the initial point coordinates, the total number of placements, the placement direction, and the upper limit of the placement rows and columns. Perform coordinate transformation and shift operations on the leaf cell layout to complete the layout.

[0059] Furthermore, in step S1, planning the Floorplan, drawing the leaf cell layout of each simulation module further includes:

[0060] Determine the position and size of each analog module according to the design requirements, use the layout editor to create a new layout project, import the GDS file of the required analog module into the layout project, place the analog module in the layout editor, and rotate and scale it as needed.

[0061] In addition, controlling the pin position through the placement and routing tool and running to obtain the digital module layout further includes:

[0062] Appropriate constraints are set in the layout and routing tool to guide the layout and routing process. First, layout is performed to specify whether the pin position is located on a specific boundary of the module or is placed relative to other pins. After the layout is completed, the layout and routing tool is used to route the digital module. In this process, the tool automatically generates connection paths based on the connection relationship of the design and draws them on the layout.

[0063] Furthermore, in step S2, for the power tube array in the LDO module, splicing the analog module layout further includes:

[0064] A power tube cell includes several signal lines and several PMOS. After drawing the boundary, the width and height of the boundary layer are obtained as w and h respectively. The number of PMOS is calculated according to the fitting function, and the number of cells required in the array is calculated. n The placement coordinate position is (x init +n*w,y init ), where (x init ,y init ) is the coordinates of the first Cell.

[0065] This embodiment takes fine-tuning PMOS as an example. Figure 3 As shown, there are 4 signal lines in a power tube layout, and 4 pmos form a cell. The boundary is drawn as the yellow line part, and the width and height of the boundary layer are obtained as w,h. When splicing, assuming that we fine-tune the number of PMOS to 32, then a 1*8 array is required, such as Figure 4 As shown, Cell n The placement coordinate position is (x init +n*w,y init ).

[0066] For the power tube array in the LDO module, splicing the digital module layout further includes:

[0067] S21: According to the pre-planned floorplan, the number of PMOS is calculated by fitting function, and the track value is obtained according to the integrated circuit process. The spacing between each signal line is d=2*track;

[0068] S22: The digital module is placed in the first quadrant, the lower left corner origin is placed at (0,0), the bottom of the digital module is used as the connection point of the power tube, and the PIN pins are placed in batches in the form of absolute coordinates by calling commands through the layout and routing tool. init +track*2*n,0), wherein the digital module width calculation formula is as follows:

[0069] Digital width =(Num pmos_coarse +Num pmos_fine )*d+offset, where Num pmos_coarse Num is the number of coarse adjustment PMOS pmos_fineTo fine-tune the number of PMOS, the offset is the reserved digital module powerring width;

[0070] S23: When splicing PMOS, start by aligning the first signal line, and then place it to the right. pmos The placement coordinates are (x init +Width pmos cell*Num pmosCell *n,-height pmosCell ), where Num pmosCell is the number of PMOS in a power tube Cell, width pmosCell is the width of the power tube Cell, height pmosCell is the height of the power tube Cell.

[0071] This embodiment takes the SMIC55 process as an example, the track value is 0.2, and the signal line spacing of each MOS is defined as 0.2*2=0.4. pmos The placement coordinates are (x init +0.4*4*n,-height pmosCell ).

[0072] In step S2, for the load resistor in the LDO module, splicing the analog module layout and the digital module layout further includes:

[0073] The load resistor is in series, such as Figure 5 As shown, the layout of the load resistor module includes several vertical resistors and several corners, taking into account the connection and hierarchy of the circuit and ensuring that the actual layout is consistent with the principle Figure 1 To write a resistor splicing function separately, the total number of resistors Num R =Total resistance / single vertical resistance. If the number of columns is even, flip the vertical resistance upside down and place it again. At the same time, add an offset to the corner of the top layer. x =width R_bar / 2, when the upper and lower parts are spliced ​​and connected, the connection is made through the M1 wire at the boundary, and the corner is planned as a wire during calculation.

[0074] In this embodiment, if Figure 6 As shown, assuming that the total resistance is 500KΩ, the resistance of a single vertical bar is 4.5KΩ, and the upper and lower splicing connections are connected through the M1 wire at the boundary. To facilitate the calculation of the resistance value, the corners are planned as wires. The total number of resistors is R=450 / 4.5K=100, and the splicing array can be 2*50 / 5*20 / 10*10 / 25*4, etc. Figure 6 The display shows a 5*20 spliced ​​array.

[0075] In addition, for the load capacitor in the LDO module, splicing the analog module layout and the digital module layout further includes:

[0076] The load capacitors are connected in parallel, such as Figure 7 As shown, the layout of the load capacitor module includes a plurality of capacitors, each of which can be spliced ​​with each other up and down, left and right, and through holes M3 and M1 are drawn at the upper and lower ends of the capacitor, and through holes M2 are drawn at the left and right, and then the port VOUT is connected;

[0077] like Figure 8 As shown, when the boundary layer is aligned up and down, one end relies on the automatic connection of its upper and lower parts M3, while the other end is spliced ​​by connecting the left and right M2 and the upper and lower POLY layers to achieve a parallel effect. In this embodiment, taking the number of capacitors as 45 as an example, the spliced ​​array can be 5*9, such as Figure 8 shown.

[0078] In step S3, performing a design rule check DRC further includes:

[0079] Based on the selected semiconductor process, the corresponding design rule file is set, and the design rule check DRC is run on the designed layout using the EDA tool. If there is a violation of the rule, an error report is generated to indicate the specific location and type of the violation. Then, according to the error report, the necessary adjustments are made to the design in the layout editing environment. After correction, the design rule check DRC is run again until no violation of the rule occurs.

[0080] In addition, the layout principle Figure 1 The consistency check LVS further includes:

[0081] Ensure that there is a complete and accurate schematic, extract the netlist from the schematic and the spliced ​​layout, use EDA tools to compare the netlist of the schematic with the netlist extracted from the layout, mark any mismatches, including extra connections, actual connections, and inconsistent device parameters, generate an LVS difference report, return to the layout editing environment to make corresponding corrections, and then re-do the layout schematic after corrections. Figure 1 Consistency check LVS verification until the layout completely corresponds to the schematic.

[0082] This embodiment customizes the drawing of the analog layout, uses the boundary layer as the splicing identification coordinate, and performs configurable splicing with the digital layout generated by the automatic layout and routing tool. Compared with the previous time-consuming and labor-intensive shortcomings of splicing too many modules of the digital-analog layout, this technology can achieve a stable, fast, and multi-configuration effect. At the same time, the present invention has good process transferability, and the entire splicing scheme can be effective for different layout leafcell blocks at the same time, and only the relevant parameters need to be modified after the leafcell is redrawn.

[0083] Example 2

[0084] For LDOs with the same process and different configurations, the layout and splicing method of Example 1 has good versatility.

[0085] Here are three different LDO configurations:

[0086] LDO1 splicing as Fig. 9 As shown,

[0087] Digital control module output 50bit

[0088] Number of PMOS: 50

[0089] Load resistor array:8*10

[0090] Load capacitance array: 10*10;

[0091] LDO2 splicing as Fig.10 As shown,

[0092] Digital control module output 150bit

[0093] Number of PMOS: 150

[0094] Load resistor array:8*10

[0095] Load capacitance array: 10*10;

[0096] LDO3 splicing as Fig.11 As shown,

[0097] Digital control module output 540bit

[0098] Number of PMOS: 540

[0099] Load resistor array:2*40

[0100] Load capacitor array: 4*25.

[0101] Example 3

[0102] Pre-draw the simulation module. If the module is relatively simple, you can use the open source library to write a program to draw the layer by layer to achieve the purpose of variable module parameters. The advantage is that you can save the process of drawing leaf cells and the configurability can be further improved. The disadvantage is that it takes longer and requires a deeper understanding of the process design rules.

[0103] Obviously, those skilled in the art can make various changes and modifications to the invention without departing from the spirit and scope of the invention. Thus, if these modifications and variations of the invention fall within the scope of the claims of the invention and their equivalents, the invention is also intended to include these modifications and variations.

[0104] Finally, it should be noted that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A layout layout and automatic splicing method for a configurable LDO module, characterized in that: The steps include: S1: Plan the Floorplan, draw the leaf cells of each analog module to obtain the analog module layout, reserve the interface to the boundary, define the boundary layer for program recognition, and at the same time, control the pin position through the layout and routing tool and run to obtain the digital module layout; S2: Write the splicing code, calculate the parameters of each LDO module through the fitting function, and splice the analog module layout and the digital module layout to obtain the analog part layout and the digital part layout respectively; S3: Check the spliced ​​digital part layout and analog part layout in turn. If they pass the inspection, perform the design rule check DRC and the layout schematic consistency check LVS.

2. The layout layout and automatic splicing method of the configurable LDO module according to claim 1, characterized in that: The LDO module includes a power tube array, a comparator, an undershoot detection module, a load capacitor and a load resistor. The LDO module layout splicing further includes: Pre-draw the leaf cell layout of each simulation module and add a boundary layer as an identification coordinate. Call the layout editing library, design the placement function, and input parameters, including the current layout, the cell to be placed, the initial point coordinates, the total number of placements, the placement direction, and the upper limit of the placement rows and columns. Perform coordinate transformation and flipping operations on the leaf cell layout to complete the layout.

3. The layout layout and automatic splicing method of the configurable LDO module according to claim 1, characterized in that: In step S1, planning the Floorplan, drawing the leaf cell layout of each simulation module further includes: Determine the position and size of each analog module according to the design requirements, use the layout editor to create a new layout project, import the GDS file of the required analog module into the layout project, place the analog module in the layout editor, and rotate and shift it as needed.

4. The layout layout and automatic splicing method of the configurable LDO module according to claim 1, characterized in that: In step S1, controlling the pin position and running the layout of the digital module by the layout and routing tool further includes: Appropriate constraints are set in the layout and routing tool to guide the layout and routing process. First, layout is performed to specify whether the pin position is located on a specific boundary of the module or is placed relative to other pins. After the layout is completed, the layout and routing tool is used to route the digital module. In this process, the tool automatically generates connection paths based on the connection relationship of the design and draws them on the layout.

5. The layout layout and automatic splicing method of the configurable LDO module according to claim 2, characterized in that: In step S2, for the power tube array in the LDO module, splicing the analog module layout further includes: A power tube cell includes several signal lines and several PMOS. After drawing the boundary, the width and height of the boundary layer are obtained as w and h respectively. The number of PMOS is calculated according to the fitting function, and the number of cells required in the array is calculated. n The placement coordinate position is (x init +n*w,y init ), where (x init ,y init ) is the coordinates of the first Cell.

6. The layout layout and automatic splicing method of the configurable LDO module according to claim 5, characterized in that: In step S2, for the power tube array in the LDO module, splicing the digital module layout further includes: S21: According to the pre-planned floorplan, the number of PMOS is calculated by fitting function, and the track value is obtained according to the integrated circuit process. The spacing between each signal line is d=2*track; S22: The digital module is placed in the first quadrant, the lower left corner origin is placed at (0, 0), the bottom of the digital module is used as the connection point of the power tube, and the PIN pins are placed in batches in the form of absolute coordinates by calling commands through the layout and routing tool. init +track*2*n, 0), wherein the digital module width calculation formula is as follows: Digital width =(Num pmos_coarse +Num pmos_fine )*d+offset, Among them, Num pmos_coarse Num is the number of coarse adjustment PMOS pmos_fine To fine-tune the number of PMOS, the offset is the reserved digital module powerring width; S23: When splicing PMOS, start by aligning the first signal line, and then place it to the right. pmos The placement coordinates are (x init +Width pmoscell *Num pmosCell *n,-height pmosCell ), where Num pmosCell is the number of PMOS in a power tube Cell, width pmosCell is the width of the power tube Cell, height pmosCell is the height of the power tube Cell.

7. The layout layout and automatic splicing method of the configurable LDO module according to claim 2, characterized in that: The layout layout and automatic splicing method of a configurable LDO module according to claim 2, characterized in that in step S2, for the load resistor in the LDO module, splicing the analog module layout and the digital module layout further comprises: The load resistor is in series. The layout of the load resistor module includes several vertical resistors and several corners. Considering the connection and hierarchy of the circuit and ensuring that the actual layout is consistent with the schematic diagram, a resistor splicing function is written separately. The total number of resistors Num R =Total resistance / single vertical resistance. If the number of columns is even, flip the vertical resistance upside down and place it again. At the same time, add an offset to the corner of the top layer. x =widthR _bar / 2, when the upper and lower parts are spliced ​​and connected, the connection is made through the M1 wire at the boundary, and the corner is planned as a wire during calculation.

8. The layout layout and automatic splicing method of the configurable LDO module according to claim 2, characterized in that: In step S2, for the load capacitor in the LDO module, splicing the analog module layout and the digital module layout further includes: The load capacitor is in parallel. The layout of the load capacitor module includes several small capacitors. Each capacitor can be connected to each other up and down, left and right. Through holes M3 and M1 are drawn at the upper and lower ends of the capacitor, and through holes M2 are drawn on the left and right, and then the port VOUT is connected; When aligning the boundary layer up and down and left and right, one end relies on the automatic connection of its upper and lower parts M3, while the other end is spliced ​​by connecting the left and right M2 and the upper and lower POLY layers to achieve a parallel effect.

9. The layout layout and automatic splicing method of the configurable LDO module according to claim 1, characterized in that: In step S3, performing a design rule check DRC further includes: Based on the selected semiconductor process, the corresponding design rule file is set, and the design rule check DRC is run on the designed layout using the EDA tool. If there is a violation of the rule, an error report is generated to indicate the specific location and type of the violation. Then, according to the error report, the necessary adjustments are made to the design in the layout editing environment. After correction, the design rule check DRC is run again until no violation of the rule occurs.

10. The method for layout and automatic splicing of a configurable LDO module according to claim 1, characterized in that: In step S3, performing layout schematic consistency check LVS further includes: Ensure that there is a complete and accurate schematic, extract the netlist from the schematic and the spliced ​​layout, use EDA tools to compare the netlist of the schematic with the netlist extracted from the layout, mark any mismatches, including extra connections, actual connections, and inconsistent device parameters, generate an LVS difference report, return to the layout editing environment to make corresponding corrections, and perform layout-schematic consistency check LVS verification again after corrections until the layout fully corresponds to the schematic.

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