Wafer appearance defect detection method and device and computer equipment

Abstract

The invention relates to a wafer appearance defect detection method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: acquiring a wafer image; performing channel segmentation processing on the wafer image, and extracting a target channel image; performing first defect detection on the target channel image to obtain a first detection result; determining a plurality of detection points on the wafer image according to the first detection result; performing second defect detection on the detection point to obtain a second detection result; and determining a defect detection result of the wafer according to the first detection result and the second detection result. According to the wafer appearance defect detection method, the target channel image is extracted, and the defect detection is performed on the target channel image twice, so that the accuracy of the defect detection result is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a method, device, computer equipment, computer-readable storage medium and computer program product for detecting appearance defects of wafers. Background Art

[0002] Before the wafer is shipped after being processed by the manufacturing process, it is usually necessary to conduct an appearance defect inspection to check whether there are defects such as particles, scratches, defects, bubbles, etc. Currently, most of the wafer images are magnified by microscopes, and defects are confirmed by manual observation. However, manual visual inspection is time-consuming and labor-intensive, and is prone to omissions, with low accuracy. Summary of the invention

[0003] Based on this, it is necessary to provide a more accurate wafer appearance defect detection method, device, computer equipment, computer readable storage medium and computer program product.

[0004] In order to achieve the above objectives, on the one hand, the present application provides a wafer appearance defect detection method, comprising:

[0005] Acquire wafer images;

[0006] Performing channel segmentation processing on the wafer image to extract a target channel image;

[0007] Performing a first defect detection on the target channel image to obtain a first detection result;

[0008] Determine a plurality of detection points on the wafer image according to the first detection result;

[0009] Performing a second defect inspection on the inspection point to obtain a second inspection result;

[0010] A defect detection result of the wafer is determined according to the first detection result and the second detection result.

[0011] In one embodiment, acquiring the wafer image includes:

[0012] Acquire an initial image of the wafer to be tested taken by a camera device, wherein the camera device is tilted to a vertical plane of the wafer to be tested to shoot;

[0013] Obtaining device parameters of the camera device;

[0014] The initial image is corrected according to the equipment parameters to correct the initial image to the wafer image taken at an angle perpendicular to the wafer to be tested.

[0015] In one embodiment, performing channel segmentation processing on the wafer image to extract the target channel image includes:

[0016] Obtaining pixel distribution histograms of the wafer image in red channel, green channel and blue channel;

[0017] Segmenting the wafer image to obtain a red channel image, a green channel image, and a yellow channel image;

[0018] The target channel image is determined according to the contrast of the red channel image, the contrast of the green channel image, the contrast of the yellow channel image, and the pixel distribution histogram.

[0019] In one embodiment, the first detection result includes defect coordinates, and determining a plurality of detection points on the wafer image according to the first detection result includes:

[0020] Dividing the wafer to be tested into a preset number of areas;

[0021] When the first detection result is that there is no defect, randomly selecting a coordinate in each of the areas as the detection point;

[0022] When the first detection result indicates that a defect exists, the defect coordinates are obtained and the defect coordinates are used as the detection point.

[0023] In one embodiment, the first detection result also includes the number of defects, and when the first detection result indicates that a defect exists, obtaining the defect coordinates and using the defect coordinates as the detection point includes:

[0024] Obtaining the number of defects;

[0025] When the number of defects is greater than or equal to a preset number, the defect coordinates are used as the detection points;

[0026] When the number of defects is less than a preset number, the defect coordinates are used as part of the detection points, and the area where the defects exist is determined based on the defect coordinates, and at least one coordinate is randomly selected in other areas where no defects exist as the remaining detection points.

[0027] In one embodiment, the defect detection result includes defect coordinates, and after determining the defect detection result of the wafer according to the first detection result and the second detection result, the method further includes:

[0028] When the defect detection result indicates that a defect exists, mapping the defect coordinates to a corresponding chip area; the wafer to be tested includes a plurality of chip areas;

[0029] Determine the abnormality level of each chip area according to the defect detection result; the abnormality level includes a first level, a second level and a third level;

[0030] When the abnormality level of the chip area is the first level, no warning information is output for the chip area;

[0031] When the abnormality level of the chip area is the second level, outputting first warning information to the chip area to prompt a user that a wafer test of the chip area may fail;

[0032] When the abnormality level of the chip area is the third level, a second warning message is output to the chip area to prompt the user that the chip area is scrapped and wafer testing is not required.

[0033] In a second aspect, the present application also provides a wafer appearance defect detection device, comprising:

[0034] An image acquisition module, used for acquiring wafer images;

[0035] An image processing module, used to perform channel segmentation processing on the wafer image and extract a target channel image;

[0036] A defect detection module is used to perform a first defect detection on the target channel image to obtain a first detection result; determine a plurality of detection points on the wafer image according to the first detection result; perform a second defect detection on the detection points to obtain a second detection result; and determine a defect detection result of the wafer according to the first detection result and the second detection result.

[0037] In a third aspect, the present application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the wafer appearance defect detection method provided in any of the above embodiments is implemented.

[0038] In a fourth aspect, the present application also provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method for detecting wafer appearance defects provided in any of the above embodiments is implemented.

[0039] In a fifth aspect, the present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the wafer appearance defect detection method provided in any of the above embodiments.

[0040] In the above-mentioned wafer appearance defect detection method, device, computer equipment, computer-readable storage medium and computer program product, by acquiring a wafer image, channel segmentation processing is performed on the wafer image to extract the target channel image. Since the target channel image is the channel image with the most obvious defect features, the target channel image is extracted and the defect features are strengthened, so that the accuracy of the subsequent defect detection results based on the target channel image can be improved. Afterwards, a first defect detection is performed on the target channel image to obtain a first detection result, and multiple detection points on the wafer image are determined based on the first detection result, which can avoid blindly selecting detection points for a second defect detection and improve detection efficiency. Furthermore, a second defect detection is performed on the detection point to obtain a second detection result, and the defect detection result of the wafer is determined based on the first detection result and the second detection result. It can be understood that the first defect detection is to detect the entire wafer image, that is, the detection at the macro level, and the second defect detection is to detect the detection points on the wafer image, that is, the area where defects may exist, that is, the detection at the micro level. By performing the first defect detection on the entire wafer image, the number, size and coordinates of defects that may exist on the wafer image can be determined. After that, the second defect detection is performed on the selected detection points to clarify the appearance of the defects and determine the defect category, thereby improving the accuracy of the defect detection results. In addition, the scrap standard of the wafer can be confirmed based on the defect category determined by the second defect detection. Wafers that meet the scrap standard do not need to undergo subsequent wafer testing, which can reduce the waste of testing resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 A schematic diagram of an application scenario of a wafer appearance defect detection method provided in an embodiment;

[0043] Figure 2 A schematic diagram of a process flow of a wafer appearance defect detection method provided in an embodiment;

[0044] Figure 3 A schematic diagram of a process for obtaining a wafer image provided by an embodiment;

[0045] Figure 4 A schematic diagram of the positions of a camera device and a wafer to be tested in one embodiment;

[0046] Figure 5 (a) is a pixel distribution histogram of the wafer image in the red channel;

[0047] Figure 5(b) is a pixel distribution histogram of the wafer image in the green channel;

[0048] Figure 5(c) is a pixel distribution histogram of the wafer image in the blue channel;

[0049] Figure 6 (a) is a wafer image;

[0050] Figure 6 (b) is the red channel image;

[0051] Figure 6 (c) is the green channel image;

[0052] Figure 6 (d) is the blue channel image;

[0053] Figure 7 A schematic flow chart of a wafer appearance defect detection method provided in another embodiment;

[0054] Figure 8 A structural block diagram of a wafer appearance defect detection device provided by an embodiment;

[0055] Fig. 9 An internal block diagram of a computer device provided by an embodiment. DETAILED DESCRIPTION

[0056] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0058] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] After the wafer has been processed through various processes, it is necessary to conduct appearance defect inspection to determine whether the wafer has defects such as particles, scratches, defects, bubbles, etc. Currently, most inspection personnel manually capture the wafer image with a camera, then enlarge it and manually visually inspect the defects. However, manual visual inspection is prone to missing defects and consumes human resources.

[0060] Based on this, the present application proposes a wafer appearance defect detection method, which can be applied to Figure 1 The wafer appearance defect detection system shown in FIG. The wafer appearance defect detection system may include a light source 102, a camera 104, and a detection device 106. Among them, the light source 102 is used to provide the camera 104 with the light source required to capture the wafer image. In some embodiments, the light source 102 may use a yellow light source. Compared with other colored lights, the defects in the wafer image captured under the yellow light source are more obvious and clearer. The camera 104 may be a camera. The detection device 106 may perform appearance defect detection based on the wafer image. The detection device 104 may be a computer device, a computer, a personal notebook, etc.

[0061] In one embodiment, Figure 2 As shown, the present application provides a method for detecting wafer appearance defects, including steps S210-S260.

[0062] S210, acquiring a wafer image.

[0063] The wafer image can be acquired through a camera device.

[0064] S220, performing channel segmentation processing on the wafer image to extract the target channel image.

[0065] Wafer images are mainly composed of three colors: red, green, and blue. The wafer images can be segmented according to the three colors to divide the color image into three separate channel images. Each channel image represents the red component, blue component, and green component in the wafer image. Among the three channel images, the channel image with the most obvious defect features can be used as the target channel image.

[0066] S230, performing a first defect detection on the target channel image to obtain a first detection result.

[0067] The first detection result may include information such as defect coordinates, defect quantity and defect size. Exemplarily, the YoLoV5 algorithm model may be used to perform the first defect detection on the target channel image to obtain the first detection result. Specifically, the wafer image may be normalized first, and the size of the wafer image may be adjusted to a preset size. The preset size may be reasonably set according to the actual scenario, and the embodiment of the present application is not limited here. Afterwards, the normalized wafer image is divided into N*N grids, the graphics of each grid are scanned, and the corresponding confidence level is output. The confidence level indicates the probability that there is a defect in the grid. The higher the confidence level, the more likely it is that there is a defect in the grid. When the confidence level exceeds the set threshold, it can be considered that there is a defect in the grid, and the center coordinates and size of the box surrounding the defect are output. The center coordinates of the box surrounding the defect can be used as the defect coordinates, and the size of the box surrounding the defect can be used as the defect size.

[0068] S240, determining a plurality of inspection points on the wafer image according to the first inspection result.

[0069] S250, performing a second defect inspection on the inspection point to obtain a second inspection result.

[0070] After obtaining the first inspection result, multiple inspection points on the wafer image can be determined according to the first inspection result, and these inspection points can be enlarged to facilitate the second defect inspection. The second inspection result includes whether there is a defect at the inspection point, the defect size, the appearance of the defect, etc.

[0071] S260, determining a defect detection result of the wafer according to the first detection result and the second detection result.

[0072] In an embodiment of the present application, by acquiring a wafer image, performing channel segmentation processing on the wafer image, and extracting a target channel image, since the target channel image is the channel image with the most obvious defect features, by extracting the target channel image and strengthening the defect features, the accuracy of the subsequent defect detection results based on the target channel image can be improved. Afterwards, the target channel image is subjected to a first defect detection, a first detection result is obtained, and multiple detection points on the wafer image are determined according to the first detection result, which can avoid blindly selecting the detection point for a second defect detection and improve the detection efficiency. Further, a second defect detection is performed on the detection point to obtain a second detection result, and the defect detection result of the wafer is determined according to the first detection result and the second detection result. It can be understood that the first defect detection is to detect the entire wafer image, and the second defect detection is to detect the detection points on the wafer image, that is, the area where defects may exist, and the defect detection is performed. By performing the first defect detection on the entire wafer image, the number, size and coordinates of defects that may exist on the wafer image can be determined. Afterwards, by performing a second defect detection on the selected detection point, the appearance of the defect is clarified, the defect category is determined, and the accuracy of the defect detection result is improved. In addition, the defect category determined by the second defect detection can be used to confirm whether the wafer meets the scrap standard. Wafers that meet the scrap standard do not need to undergo subsequent wafer testing, which can reduce the waste of testing resources.

[0073] In one embodiment, Figure 3 As shown, acquiring a wafer image includes steps S310 - S330 .

[0074] S310, acquiring an initial image of the wafer to be tested taken by a camera device, wherein the camera device takes the image while tilted to a vertical surface of the wafer to be tested.

[0075] It is understandable that Figure 4 As shown, due to the limitation of the machine space, the camera device takes an initial image of the wafer at position 1. In the initial image, the wafer is elliptical.

[0076] S320, obtaining device parameters of the camera device.

[0077] The equipment parameters include the distance between the camera device and the wafer to be tested, and the tilt angle of the camera device compared to the vertical plane of the wafer to be tested.

[0078] S330, performing correction processing on the initial image according to the equipment parameters, and correcting the initial image to a wafer image taken at an angle perpendicular to the wafer to be measured.

[0079] Before performing appearance defect inspection on the wafer, the pixel correspondence between the initial image taken by the camera at position 1 and the wafer image taken by the camera at position 2 can be determined by experiment. For example, (x, y) represents the pixel coordinates of the wafer image taken by the camera at position 2, and (u, v) represents the pixel coordinates of the initial image taken by the camera at position 1. The pixel coordinate correspondence between the initial image and the wafer image is:

[0080]

[0081] Among them, the matrix , is the transformation coefficient.

[0082] According to formula (1), we can get:

[0083]

[0084]

[0085] Let a33=1, determine the coordinates of 4 sets of corresponding points, and then solve the transformation coefficient A.

[0086] A correspondence table of transformation coefficient A, tilt angle, and distance can be established, and the transformation coefficient A can be obtained by querying the correspondence table according to the equipment parameters. The initial image is corrected based on the transformation coefficient A, and the initial image is corrected to a wafer image taken at an angle perpendicular to the wafer to be measured.

[0087] In this embodiment, an initial image taken by a camera device and equipment parameters of the camera device are obtained, and correction processing is performed on the initial image based on the equipment parameters to convert the initial image into a wafer image taken perpendicularly to the surface of the wafer to be tested. This solves the problem that the camera device cannot take pictures perpendicularly to the wafer to be tested due to the small internal space of the machine.

[0088] In one embodiment, channel segmentation processing is performed on a wafer image to extract a target channel image, including obtaining pixel distribution histograms of the wafer image in a red channel, a green channel, and a blue channel, segmenting the wafer image to obtain a red channel image, a green channel image, and a yellow channel image, and determining the target channel image based on the contrast of the red channel image, the contrast of the green channel image, the contrast of the yellow channel image, and the pixel distribution histogram.

[0089] For example, FIG5(a) is a pixel distribution histogram of a wafer image in the red channel, FIG5(b) is a pixel distribution histogram of a wafer image in the green channel, and FIG5(c) is a pixel distribution histogram of a wafer image in the blue channel. The horizontal axis represents the grayscale of each color component, and the vertical axis represents the number of pixels of each color component. It can be seen from FIG5(a) to FIG5(c) that the total number of pixels in the red channel and the green channel is large, while the total number of pixels in the blue channel is the least.

[0090] Furthermore, the wafer image is segmented to obtain the red channel image, green channel image and yellow channel image, as shown in Figure 6 (a) to Figure 6 (d). Among them, Figure 6 (a) represents the wafer image, Figure 6 (b) represents the red channel image, Figure 6 (c) represents the green channel image, and Figure 6 (d) represents the blue channel image. It can be seen from Figure 6 (b) to Figure 6 (d) that the contrast between the defect area and the normal area in the red channel image is the strongest. Combined with the large number of pixels in the red channel, the red channel image is used as the target channel image, which can improve the accuracy of the defect detection results.

[0091] In one embodiment, multiple inspection points on the wafer image are determined based on the first inspection result, including dividing the wafer to be tested into a preset number of areas, randomly selecting a coordinate in each area as a inspection point when the first inspection result is that there is no defect, and obtaining the defect coordinates when the first inspection result is that there is a defect, and using the defect coordinates as the inspection point.

[0092] Exemplarily, the preset number can be 5, 6, 7, 8, 9, etc. The preset number can be reasonably set according to the actual scene requirements, and the embodiments of the present application are not limited here.

[0093] It can be understood that, when it is determined according to the first test result that the wafer to be tested does not have defects, a coordinate can be randomly selected in each area as a test point to perform a second defect test. When it is determined according to the first test result that the wafer to be tested has defects, the defect coordinates can be obtained according to the first test result, and the defect coordinates can be used as the test point to perform a second defect test.

[0094] Furthermore, when it is determined that the wafer to be tested has defects according to the first detection result, the number of defects can also be obtained according to the first detection result. When the number of defects is greater than or equal to the preset number, the defect coordinates are used as detection points to perform a second defect detection. When the number of defects is less than the preset number, the defect coordinates are used as part of the detection points, and the area with defects is determined according to the defect coordinates, and at least one coordinate is randomly selected as the remaining detection point in other areas without defects to ensure that the number of detection points reaches at least the preset number.

[0095] In one embodiment, Figure 7 As shown, after determining the defect detection result of the wafer based on the first detection result and the second detection result, the wafer appearance defect detection method of the present application further includes steps S710 - S750.

[0096] S710, when the defect detection result indicates the presence of a defect, map the defect coordinates to the corresponding chip area. The wafer to be tested includes multiple chip areas.

[0097] S720, determine the abnormality level of each chip area according to the defect detection result. The abnormality levels include the first level, the second level, and the third level.

[0098] S730, when the abnormality level of the chip area is the first level, do not output a warning message for this chip area.

[0099] S740, when the abnormality level of the chip area is the second level, output a first warning message for this chip area to prompt the user that the wafer test of the chip area may not pass.

[0100] S750, when the abnormality level of the chip area is the third level, output a second warning message for this chip area to prompt the user that the chip area is scrapped and there is no need to perform a wafer test.

[0101] Circuit Probing (CP) of the wafer means dividing the wafer into multiple chip areas (dies) and performing electrical performance tests on each chip area. In this embodiment, when the defect detection result indicates the presence of a defect, the defect coordinates can be mapped to the chip area. Specifically, the defect coordinates are (a, b), the upper right corner coordinates of the chip area are (c, d), and the length and width dimensions of the chip area are w and h. The traversal method can be used to match the defect coordinates with the coordinates of each chip area. If the conditions c - w < a < c and d - h < b < d are met, it means that the defect coordinates match the chip area successfully, and the defect coordinates can be mapped to this chip area.

[0102] Furthermore, determine the abnormality level of this chip area according to the defect detection result. In this embodiment, the abnormality levels are divided into the first level, the second level, and the third level. Among them, the first level means that there is no defect or there is a defect, but the defect size is very small and has little impact on the product performance. The second level means that there is a defect and this defect has a certain impact on the product performance. The third level means that there is a defect and the defect size is very large and has reached the scrapping standard, or this defect is a defect with a very high lethality rate. After that, the abnormality level of each chip area can be determined according to the defect detection result, and the corresponding warning message can be output.

[0103] In this embodiment, the abnormality level of each chip area on the wafer to be tested is determined according to the defect detection result, and the corresponding warning information is output. When the abnormality level of the chip area is the third level, the second warning information is output for the chip area to prompt the user that the chip area is scrapped and there is no need to perform wafer testing, thereby reducing the waste of CP testing resources.

[0104] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0105] Based on the same inventive concept, the embodiment of the present application also provides a wafer appearance defect detection device for implementing the wafer appearance defect detection method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more wafer appearance defect detection device embodiments provided below can refer to the limitations of the wafer appearance defect detection method above, and will not be repeated here.

[0106] In an exemplary embodiment, Figure 8 As shown, a wafer appearance defect detection device is provided, including: an image acquisition module 810, an image processing module 820 and a defect detection module 830, wherein:

[0107] The image acquisition module 810 is used to acquire wafer images.

[0108] The image processing module 820 is used to perform channel segmentation processing on the wafer image and extract the target channel image.

[0109] The defect detection module 830 is used to perform a first defect detection on the target channel image to obtain a first detection result; determine multiple detection points on the wafer image based on the first detection result; perform a second defect detection on the detection points to obtain a second detection result; and determine the defect detection result of the wafer based on the first detection result and the second detection result.

[0110] Each module in the above-mentioned wafer appearance defect detection device can be implemented in whole or in part by software, hardware and their combination. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the corresponding operations of each of the above modules.

[0111] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Fig. 9 As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be realized through WIFI, a mobile cellular network, near field communication (Near Field Communication, NFC) or other technologies. When the computer program is executed by the processor, a method for detecting wafer appearance defects is realized. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0112] Those skilled in the art will understand that Fig. 9 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0113] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the wafer appearance defect detection method provided in any of the above embodiments is implemented.

[0114] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the wafer appearance defect detection method provided in any of the above embodiments is implemented.

[0115] In one embodiment, a computer program product is provided, including a computer program, which, when executed by a processor, implements the wafer appearance defect detection method provided in any of the above embodiments.

[0116] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0117] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0118] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A wafer appearance defect detection method, characterized in that: include: Acquire wafer images; Performing channel segmentation processing on the wafer image to extract a target channel image; Performing a first defect detection on the target channel image to obtain a first detection result; Determine a plurality of detection points on the wafer image according to the first detection result; Performing a second defect inspection on the inspection point to obtain a second inspection result; A defect detection result of the wafer is determined according to the first detection result and the second detection result.

2. The method according to claim 1, characterized in that The step of acquiring a wafer image comprises: Acquire an initial image of the wafer to be tested taken by a camera device, wherein the camera device is tilted to a vertical plane of the wafer to be tested for shooting; Obtaining device parameters of the camera device; The initial image is corrected according to the equipment parameters to correct the initial image to the wafer image taken at an angle perpendicular to the wafer to be tested.

3. The method according to claim 1, characterized in that: The performing channel segmentation processing on the wafer image to extract the target channel image includes: Obtaining pixel distribution histograms of the wafer image in red channel, green channel and blue channel; Segmenting the wafer image to obtain a red channel image, a green channel image, and a yellow channel image; The target channel image is determined according to the contrast of the red channel image, the contrast of the green channel image, the contrast of the yellow channel image, and the pixel distribution histogram.

4. The method according to claim 1, characterized in that The first detection result includes defect coordinates, and determining a plurality of detection points on the wafer image according to the first detection result includes: Dividing the wafer to be tested into a preset number of areas; When the first detection result is that there is no defect, randomly selecting a coordinate in each of the areas as the detection point; When the first detection result indicates that a defect exists, the defect coordinates are obtained and the defect coordinates are used as the detection point.

5. The method according to claim 4, characterized in that The first detection result also includes the number of defects. When the first detection result indicates that a defect exists, obtaining the defect coordinates and using the defect coordinates as the detection point includes: Obtaining the number of defects; When the number of defects is greater than or equal to a preset number, the defect coordinates are used as the detection points; When the number of defects is less than a preset number, the defect coordinates are used as part of the detection points, and the area where the defects exist is determined based on the defect coordinates, and at least one coordinate is randomly selected in other areas where no defects exist as the remaining detection points.

6. The method according to claim 1, characterized in that The defect detection result includes defect coordinates. After determining the defect detection result of the wafer according to the first detection result and the second detection result, the method further includes: When the defect detection result indicates that a defect exists, mapping the defect coordinates to a corresponding chip area; the wafer to be tested includes a plurality of chip areas; Determine the abnormality level of each chip area according to the defect detection result; the abnormality level includes a first level, a second level and a third level; When the abnormality level of the chip area is the first level, no warning information is output for the chip area; When the abnormality level of the chip area is the second level, outputting first warning information to the chip area to prompt a user that a wafer test of the chip area may fail; When the abnormality level of the chip area is the third level, a second warning message is output to the chip area to prompt the user that the chip area is scrapped and wafer testing is not required.

7. A wafer appearance defect detection device, characterized in that: The device comprises: An image acquisition module, used for acquiring wafer images; An image processing module, used for performing channel segmentation processing on the wafer image to extract a target channel image; A defect detection module is used to perform a first defect detection on the target channel image to obtain a first detection result; determine a plurality of detection points on the wafer image according to the first detection result; perform a second defect detection on the detection points to obtain a second detection result; and determine a defect detection result of the wafer according to the first detection result and the second detection result.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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