Memory

Abstract

The invention provides a memory. The memory comprises an array region and a peripheral region, the array area comprises a plurality of storage groups; the peripheral area comprises a plurality of data processing centers and a column gating enable signal generation circuit which are sequentially arranged along a first direction; each data processing center is correspondingly connected with one storage group; the column gating enable signal generation circuit is connected with the plurality of data processing centers through a first connection path; the first connection path comprises a first connection line extending along a first direction and a plurality of second connection lines extending along a second direction, the first connection line is connected with the column gating enable signal generation circuit, one end of each second connection line is connected with the first connection line, and the other end of each second connection line is connected with a data processing center; the second direction intersects the first direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory. Background Art

[0002] In the related art, the column select line (CSL) signal generated by the read command (READ) is used to turn on the isolation transistors of the bit line and the local data line (LIO) to read data from the memory array. The width of the CSL pulse is controlled by the column select enable signal CSL_EN and the storage group address enable signal CSL_DIS. However, the column select enable signal CSL_EN and the storage group address enable signal CSL_DIS are transmitted to the corresponding storage group through separate wiring, resulting in a large waste of wiring area. Summary of the invention

[0003] In view of this, the main purpose of the present application is to provide a memory.

[0004] To achieve the above purpose, the technical solution of this application is implemented as follows:

[0005] An embodiment of the present application provides a memory, including an array area and a peripheral area;

[0006] The array area includes a plurality of storage groups;

[0007] The peripheral area includes:

[0008] A plurality of data processing centers arranged in sequence along a first direction, each of the data processing centers being connected to a corresponding storage group;

[0009] A column selection enable signal generating circuit is connected to the multiple data processing centers through a first connection path; the first connection path includes: a first connection line extending along the first direction and multiple second connection lines extending along the second direction, the first connection line is connected to the column selection enable signal generating circuit, one end of each of the second connection lines is connected to the first connection line, and the other end of each of the second connection lines is connected to a data processing center; the second direction intersects with the first direction.

[0010] In some embodiments, the first connecting line extends from above a first data processing center along the first direction to above a second data processing center, and the first data processing center and the second data processing center are respectively the first and last data processing centers among a plurality of data processing centers arranged in sequence along the first direction; each second connecting line is located above a corresponding data processing center.

[0011] In some embodiments, the column strobe enable signal generating circuit is used to receive a first initial column strobe enable signal and generate a column strobe enable signal; each of the data processing centers comprises:

[0012] The column strobe signal generating circuit is used to receive the command address signal, the column strobe enable signal and the storage group address enable signal, and perform logic operation on the command address signal, the column strobe enable signal and the storage group address enable signal to generate the column strobe signal.

[0013] In some embodiments, the memory further comprises:

[0014] A redundant column address calculation module, used to receive the command address signal and calculate the command address signal, so that when the storage group corresponding to the address in the command address signal is a bad storage group, an address corresponding to a new storage group after the bad storage group is replaced is obtained, and an updated command address signal is generated;

[0015] The column strobe signal generating circuit is used to receive an updated command address signal, the column strobe enable signal and a storage group address enable signal, and perform logic operations on the updated command address signal, the column strobe enable signal and the storage group address enable signal to generate a column strobe signal.

[0016] In some embodiments, the column enable signal generating circuit includes:

[0017] an initial column strobe enable signal generating circuit, configured to receive a second initial column strobe enable signal and a power supply voltage signal, and perform a logic operation on the second initial column strobe enable signal and the power supply voltage signal to obtain a third initial column strobe enable signal;

[0018] The first delay circuit is used to receive the third initial column enable signal and delay the third initial column enable signal to generate the column enable signal.

[0019] In some embodiments, the delay time of the first delay circuit is greater than the calculation time of the redundant column address calculation module, and is less than the duration of the command address signal being in an enabled state.

[0020] In some embodiments, the first delay circuit comprises:

[0021] A first NAND gate, used for receiving the third initial column gating enable signal and the first state signal, and outputting a first intermediate column gating enable signal;

[0022] a second NAND gate, used for receiving the third initial column gating enable signal and the second state signal, and outputting a second intermediate column gating enable signal; the first state signal and the second state signal are a pair of complementary signals;

[0023] N first NOT gates are connected in sequence, and are used to receive the second middle column gate enable signal and output a third middle column gate enable signal; wherein N is an even number greater than zero;

[0024] The third NAND gate is used to receive the third middle column enable signal and the first middle column enable signal, and output the column enable signal.

[0025] In some embodiments, the column enable signal generating circuit further includes:

[0026] The second delay circuit is used to receive the first initial column enable signal, delay the first initial column enable signal, and output the second initial column enable signal.

[0027] In some embodiments, the column selection signal generating circuit includes:

[0028] A fourth NAND gate, a second NAND gate, a first NOR gate and a second NOR gate; the two input ends of the fourth NAND gate are respectively used to receive the command address signal and the column enable signal, and the output end of the fourth NAND gate is connected to the input end of the second NAND gate; the output end of the second NAND gate is connected to the first input end of the first NOR gate; the second input end of the first NOR gate is connected to the output end of the second NOR gate, and the output end of the first NOR gate is connected to the first input end of the second NOR gate; the second input end of the second NOR gate is used to receive the storage group address enable signal; wherein, the output end of the first NOR gate is used to output the column enable signal.

[0029] In some embodiments, the peripheral region further comprises:

[0030] A plurality of storage group address enable signal generating circuits, each of which corresponds to one storage group; the storage group address enable signal generating circuit is used to receive the command address signal of the storage group corresponding to the storage group address enable signal generating circuit, the first initial column enable signal, the column enable control signal, the test adjustment signal of the storage group corresponding to the storage group address enable signal generating circuit, and the test adjustment complementary signal of the storage group corresponding to the storage group address enable signal generating circuit, and generate the storage group address enable signal corresponding to the storage group address enable signal generating circuit.

[0031] A memory provided by an embodiment of the present application includes an array area and a peripheral area; the array area includes a plurality of storage groups; the peripheral area includes a plurality of data processing centers and a column gating enable signal generating circuit arranged in sequence along a first direction; each data processing center is connected to a storage group; the column gating enable signal generating circuit is connected to the plurality of data processing centers through a first connection path; the first connection path includes a first connection line extending along the first direction and a plurality of second connection lines extending along the second direction, the first connection line is connected to the column gating enable signal generating circuit, one end of each second connection line is connected to the first connection line, and the other end of each second connection line is connected to a data processing center; the second direction intersects with the first direction. The present application reduces the number of transmission lines of the column gating enable signal by making the column gating enable signal generating circuit connected to the plurality of data processing centers only through a first connection path, and the transmission distance is correspondingly shortened, thereby greatly reducing the wiring area and reducing the occupation of the peripheral area channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A top view schematic diagram of the transmission lines of the column strobe enable signal CSL_EN and the storage group address enable signal CSL_DIS in the related art;

[0033] Figure 2 A schematic top view of the transmission lines of the column enable signal CSL_EN and the storage group address enable signal CSL_DIS provided in an embodiment of the present application;

[0034] Figure 3 A schematic top view of the wiring distribution of the first connection path provided in an embodiment of the present application;

[0035] Figure 4 A schematic diagram of a circuit of a peripheral area of ​​a memory provided by an embodiment of the present application;

[0036] Figure 5 A pulse waveform diagram of a column strobe enable signal CSL_EN and a storage group address enable signal CSL_DIS provided in an embodiment of the present application;

[0037] Figure 6 A schematic diagram of a first initial column gating enable signal generating circuit provided in an embodiment of the present application;

[0038] Figure 7 A schematic diagram of a column enable control signal generating circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solution of the present application is further elaborated in detail below in conjunction with the accompanying drawings and specific embodiments of the specification.

[0040] like Figure 1As shown, it is a top view schematic diagram of the transmission line 200 of the column strobe enable signal CSL_EN and the storage bank address enable signal CSL_DIS in the related art, wherein a memory including 8 storage groups (Bankgroup, BGA~BGH) is used as an example for explanation, and the peripheral area of ​​the memory includes 8 data processing centers 100 (Datacenter) arranged in sequence along the first direction X, and each data processing center 100 is connected to a corresponding storage group. The column strobe enable signal CSL_EN and the storage bank address enable signal CSL_DIS are connected to each of the 8 data processing centers 100 through a separate transmission line 200.

[0041] It should be noted that Figure 1 Since the transmission lines 200 of the column selection enable signal CSL_EN and the storage group address enable signal CSL_DIS are distributed in the same manner, the transmission lines 200 of the column selection enable signal CSL_EN and the storage group address enable signal CSL_DIS are superimposed for illustration, wherein the oblique line plus the number mark 2 on a horizontal arrow represents two lines, and two horizontal arrows located in the same horizontal direction represent the same line. That is, a total of 8 transmission lines 200 are required to transmit the column selection enable signal CSL_EN and the storage group address enable signal CSL_DIS to each data processing center 100 separately. If the transmission distance of a data processing center 100 is d, the total length of the line is 40d (the total length of the line of the column selection enable signal CSL_EN is 20d + the total length of the line of the storage group address enable signal CSL_DIS is 20d), resulting in a large waste of wiring area.

[0042] Since the transmission speed of the column select signal CSL is required to be as fast as possible, a horizontal high-speed line, namely the fourth metal line (M4), is required. However, the resources of the horizontal high-speed lines in the peripheral area are relatively tight, so it is necessary to reduce the number of transmission lines 200 of the column select enable signal CSL_EN and the storage group address enable signal CSL_DIS and the occupied wiring area.

[0043] Combine the following Figure 2 , Figure 3 and Figure 4 The technical solution of this application is described in detail, wherein: Figure 2 A top view schematic diagram of a transmission line 200 of a column strobe enable signal CSL_EN and a storage group address enable signal CSL_DIS provided in an embodiment of the present application, Figure 3 A top view schematic diagram of the wiring distribution of the first connecting path 300 provided in an embodiment of the present application, Figure 4 A circuit diagram of a peripheral area of ​​a memory provided in an embodiment of the present application.

[0044] The embodiment of the present application provides a memory, including an array area and a peripheral area; the array area includes a plurality of storage groups; the peripheral area includes a plurality of data processing centers 100 and a column strobe enable signal generating circuit 10 arranged in sequence along a first direction X; each of the data processing centers 100 is connected to a corresponding storage group; the column strobe enable signal generating circuit 10 is connected to the plurality of data processing centers 100 through a first connecting path 300; the first connecting path 300 includes a first connecting line 301 extending along the first direction X and a plurality of second connecting lines 302 extending along a second direction Y, the first connecting line 301 is connected to the column strobe enable signal generating circuit 10, one end of each of the second connecting lines 302 is connected to the first connecting line 301, and the other end of each of the second connecting lines 302 is connected to a data processing center 100; the second direction Y intersects with the first direction X, Figure 3 In the example, the second direction Y is perpendicular to the first direction X.

[0045] It can be understood that the first connection path 300 is used to transmit the column selection enable signal CSL_EN. The present application connects the column selection enable signal generating circuit 10 to multiple data processing centers 100 only through one first connection path 300. Only one first connection line 301 extending along the first direction X and multiple second connection lines 302 extending along the second direction Y are required to transmit the column selection enable signal CSL_EN to multiple data processing centers 100, so that the number of transmission lines 200 (horizontally) of the column selection enable signal CSL_EN is reduced, and the transmission distance is also shortened accordingly, thereby greatly reducing the wiring area, reducing the occupation of peripheral area channels, and alleviating the situation of relatively tight horizontal high-speed line resources.

[0046] Specifically, Figure 2 As shown, the memory includes 8 storage groups (BGA to BGH) as an example for explanation. The oblique line plus the number 1 on a horizontal arrow represents a line, and two horizontal arrows in the same horizontal direction represent the same line. That is, only one transmission line 200 (horizontally) is needed to transmit the column selection enable signal CSL_EN to each data processing center 100. Since the length of the second connection line 302 is small and can be ignored, if the transmission distance of a data processing center 100 is d, the total length of the line of a first connection path 300 is 8d, that is, the transmission line 200 (horizontally) of the column selection enable signal CSL_EN transmitted to each data processing center 100 is reduced from 4 to 1, the transmission distance is reduced from 20d to 8d, and the wiring area is greatly reduced.

[0047] In some embodiments, the first connecting line 301 extends from above the first data processing center 100 along the first direction X to above the second data processing center 100, and the first data processing center 100 and the second data processing center 100 are respectively the first and last data processing centers 100 among multiple data processing centers 100 arranged in sequence along the first direction X; each of the second connecting lines 302 is located above a corresponding data processing center 100.

[0048] Specifically, Figure 3 As shown, it can be understood that the first connection line 301 extends from above the first data processing center 100 (corresponding to the connection BGA) along the first direction X to above the second data processing center 100 (corresponding to the connection BGH), that is, the first connection line 301 covers all the data processing centers 100 along the first direction X, so it is possible to transmit the column selection enable signal CSL_EN to each data processing center 100 only through one first connection line 301, and then connect with each data processing center 100 through the second connection line 302.

[0049] It should be noted that Figure 3 In the figure, the column selection enable signal CSL_EN is input from the area between the data processing center 100 corresponding to BGD and the data processing center 100 corresponding to BGE to the first connection line 301 as an example. In practical applications, the column selection enable signal CSL_EN can be input from the area between any two adjacent data processing centers 100 or the area where any data processing center 100 is located to the first connection line 301, and the present application is not limited thereto. When the column selection enable signal CSL_EN is input from the area between the data processing center 100 corresponding to BGD and the data processing center 100 corresponding to BGE to the first connection line 301, the distance transmitted to the first and last data processing centers 100 (corresponding to the connection between BGA and BGH) is relatively short, both of which are 4d (the transmission distance of one data processing center 100 is d), reducing the transmission loss.

[0050] In some embodiments, Figure 3 As shown, a buffer circuit 400 is provided on the second connection line 302 for delaying the column enable signal CSL_EN and inputting it to the data processing center 100. It can also enhance the signal driving capability without changing the logic value of the column enable signal CSL_EN.

[0051] In some embodiments, Figure 4As shown, the column enable signal generating circuit 10 is used to receive the first initial column enable signal CSLEN0T and generate a column enable signal CSL_EN; each of the data processing centers 100 includes: a column enable signal generating circuit 20, which is used to receive a command address signal CA, the column enable signal CSL_EN and a storage group address enable signal CSL_DIS, and performs logic operations on the command address signal CA, the column enable signal CSL_EN and the storage group address enable signal CSL_DIS to generate a column enable signal CSL.

[0052] It can be understood that each data processing center 100 includes a column selection signal generating circuit 20 for generating a column selection signal CSL and transmitting the generated column selection signal CSL to a corresponding storage group, thereby reading out data stored in the corresponding storage group. Figure 4 Only one column selection signal generating circuit 20 of the data processing center 100 is drawn. Specifically, if the memory includes 8 storage groups, for example, 7 column selection signal generating circuits 20 need to be set up to achieve corresponding connection with the 8 storage groups.

[0053] It can be understood that multiple data processing centers 100 can share one column enable signal generating circuit 10, that is, the column enable signal CSL_EN generated by one column enable signal generating circuit 10 is connected to the input ends of eight column enable signal generating circuits 20 through a first connection path 300.

[0054] It should be noted that the command address signal CA includes the storage group information (BG_A / B / C / D / E / F / G / H), and the storage group information includes the storage group address (BANK), that is, the command address signal CA can be used to determine which storage group in BGA~BGH to read data. Figure 4 As shown, the peripheral area of ​​the memory includes a first sampler 60 for sampling the command address signal CA. When a READ command is received, the command address signal CA is input into the column selection signal generating circuit 20.

[0055] It should be noted that the storage group address enable signal CSL_DIS is generated by the corresponding storage group address enable signal generating circuit 50. Figure 4Only the storage group address enable signal generating circuits 50 corresponding to the storage groups BGA and BGH are drawn. Specifically, the number of storage group address enable signal generating circuits 50 corresponds to the number of storage groups. For example, if the memory includes 8 storage groups, there are 8 storage group address enable signal generating circuits 50. The input end of the column selection signal generating circuit 20 of the data processing center 100 corresponding to the storage group BGA is connected to the output end of the storage group address enable signal generating circuit 50 corresponding to the storage group BGA. That is, if Figure 4 The column strobe signal generating circuit 20 is arranged in the data processing center 100 corresponding to the storage group BGA, and the storage group address enable signal CSL_DIS received by the column strobe signal generating circuit 20 is the output signal BGA_CSLDIS of the storage group address enable signal generating circuit 50 corresponding to the BGA. Figure 4 The column strobe signal generating circuit 20 is arranged in the data processing center 100 corresponding to the storage group BGH, and the storage group address enable signal CSL_DIS received by the column strobe signal generating circuit 20 is the output signal BGH_CSLDIS of the storage group address enable signal generating circuit 50 corresponding to BGH.

[0056] In some embodiments, the peripheral region further includes a first initial column gating enable signal generating circuit, such as Figure 6 As shown, it is a schematic diagram of the first initial column gating enable signal generating circuit provided by the embodiment of the present application, the first initial column gating enable signal generating circuit includes a plurality of shift registers 70 connected in sequence, the first shift register is used to receive the READ command signal, the complementary clock signal PCLKB and the delayed clock signal PCLKD, specifically, the D end of the first shift register receives the READ command signal, the CK end of the first shift register receives the complementary clock signal PCLKB, the CKB end of the first shift register receives the delayed clock signal PCLKD, the output end Q of the first shift register is connected to the input end D of the second shift register, and the output end Q of the second shift register is used to output the first initial column gating enable signal CSLEN0T. Among them, the plurality of shift registers 70 are also used to output shift clock signals such as CSLEN1B, CSLEN2T, CSLEN3B, CSLEN4T, CSLEN5B, CSLEN6T, CSLEN7B, and CSLEN8T.

[0057] Continue reading Figure 4In some embodiments, the memory further includes a redundant column address calculation module 30, which is used to receive the command address signal CA and calculate the command address signal CA, so that when the storage group corresponding to the address in the command address signal CA is a bad storage group, the address corresponding to the new storage group after the bad storage group is replaced is obtained, and an updated command address signal CA is generated; the column selection signal generating circuit 20 is used to receive the updated command address signal CA, the column selection enable signal CSL_EN and the storage group address enable signal CSL_DIS, and perform logic operations on the updated command address signal CA, the column selection enable signal CSL_EN and the storage group address enable signal CSL_DIS to generate a column selection signal CSL.

[0058] It can be understood that the command address signal CA must first be transmitted to the redundant column address calculation module 30 for calculation to determine whether the storage group corresponding to the address in the command address signal CA is a bad storage group. If the storage group corresponding to the address in the command address signal CA is a bad storage group, the address corresponding to the new storage group after the bad storage group is replaced is used as the address in the command address signal CA (i.e., an updated command address signal CA is generated), and the updated command address signal CA is input to the corresponding column selection signal generating circuit 20; if the storage group corresponding to the address in the command address signal CA is not a bad storage group, the original command address signal CA is input to the corresponding column selection signal generating circuit 20. Specifically, for example, if the storage group read is BGA, it is input to the column selection signal generating circuit 20 of the data processing center 100 corresponding to the BGA.

[0059] In some embodiments, Figure 4 As shown, the column enable signal generating circuit 10 includes an initial column enable signal generating circuit 11 and a first delay circuit 16; the initial column enable signal generating circuit 11 is used to receive a second initial column enable signal S1 and a power supply voltage signal VDD, and perform a logic operation on the second initial column enable signal S1 and the power supply voltage signal VDD to obtain a third initial column enable signal S2; the first delay circuit 16 is used to receive the third initial column enable signal S2, and delay the third initial column enable signal S2 to generate the column enable signal CSL_EN.

[0060] It is understandable that since the command address signal CA needs to be first transmitted to the redundant column address calculation module 30 for calculation, this calculation process takes time, and the column enable signal CSL_EN cannot be directly output during this period of time. In this embodiment, the first delay circuit 16 is set to match the time of this calculation process, so that the column enable signal CSL_EN can be synchronized with the command address signal CA. If the first delay circuit 16 is not set, the third initial column enable signal S2 is directly input to the column enable signal generation circuit 20 as the column enable signal CSL_EN, and the redundant column address calculation module 30 has not yet completed the calculation, and has not determined whether the storage group corresponding to the address in the command address signal CA is a bad storage group, which may cause a read error.

[0061] In some embodiments, the initial column enable signal generating circuit 11 includes a NAND gate and a NOT gate, the two input ends of the NAND gate are respectively used to receive the second initial column enable signal S1 and the power supply voltage signal VDD, the output end of the NAND gate is connected to the input end of the NOT gate, and the output end of the NOT gate is used to output the third initial column enable signal S2.

[0062] In some embodiments, the delay time of the first delay circuit 16 is greater than the calculation time of the redundant column address calculation module 30 and is less than the duration of the command address signal CA being in the enabled state.

[0063] It can be understood that in order to ensure that the redundant column address calculation module 30 can complete the calculation, the delay time of the first delay circuit 16 needs to be greater than the calculation time of the redundant column address calculation module 30; in order to perform logical operations with the command address signal CA when the command address signal CA is valid, the delay time of the first delay circuit 16 also needs to be less than the duration that the command address signal CA is in the enabled state.

[0064] In some embodiments, the pulse width of the command address signal CA is at least 8 clock cycles (tCK), because the command address signal CA will first go to the column selection signal generating circuit 20 of the corresponding data processing center 100 relative to the column selection enable signal CSL_EN, as long as the absolute delay between the two (i.e., the delay time of the first delay circuit 16) is less than 6 clock cycles, the logical operation condition can be met (i.e., when the column selection enable signal CSL_EN reaches the input end of the column selection signal generating circuit 20, the duration of the command address signal CA in the enabled state is greater than 2 clock cycles). According to the mainstream frequency of the fifth generation dynamic random access memory (DDR5) of 6400 in the related art, 6 clock cycles are 1.875ns, which is much greater than the calculation time (1ns) of the redundant column address calculation module 30. Therefore, this embodiment can not only ensure that the redundant column address calculation module 30 can complete the calculation, but also perform logical operations with the command address signal CA when the command address signal CA is valid.

[0065] In some embodiments, the first delay circuit 16 includes a first NAND gate 12, a second NAND gate 13, N first NAND gates 14 and a third NAND gate 15; the first NAND gate 12 is used to receive the third initial column enable signal S2 and the first state signal TM_CSL0B, and output the first intermediate column enable signal Z1; the second NAND gate 13 is used to receive the third initial column enable signal S2 and the second state signal TM_CSL0T, and output the second intermediate column enable signal Z2; the first state signal TM_CSL0B and the second state signal TM_CSL0T are a pair of complementary signals; the N first NAND gates 14 are connected in sequence, and are used to receive the second intermediate column enable signal Z2, and output the third intermediate column enable signal Z3; the N is an even number greater than zero; the third NAND gate 15 is used to receive the third intermediate column enable signal Z3 and the first intermediate column enable signal Z1, and output the column enable signal CSL_EN.

[0066] It should be noted that the first state signal TM_CSL0B and the second state signal TM_CSL0T are delay parameters stored after being tested in the test mode. In this embodiment, by adding the first state signal TM_CSL0B and the second state signal TM_CSL0T to the first delay circuit 16, it can be used to match the calculation time of the redundant column address calculation module 30 under different process angles, so as to finely adjust the time (tAA) from the READ command signal to the output of the first data.

[0067] In some embodiments, the column enable signal generating circuit 10 further includes a second delay circuit 40 for receiving the first initial column enable signal CSLEN0T, delaying the first initial column enable signal CSLEN0T, and outputting the second initial column enable signal S1.

[0068] It is understandable that if Figure 5 As shown in FIG. 1 , a pulse waveform diagram of a column strobe enable signal CSL_EN and a storage group address enable signal CSL_DIS provided in an embodiment of the present application is shown in FIG. Figure 5 It can be seen that the storage group address enable signal CSL_DIS lags behind the column enable signal CSL_EN by 4, 5, 6, 7, 8 clock cycles (tck). In this embodiment, the second delay circuit 40 is set to delay the first initial column enable signal CSLEN0T, thereby compensating for the absolute delay of the storage group address enable signal CSL_DIS after clock shifting.

[0069] In some embodiments, the second delay circuit 40 includes M NOT gates connected in sequence, where M is an even number greater than zero.

[0070] In some embodiments, the column selection signal generating circuit 20 includes a fourth NAND gate 21, a second NAND gate 22, a first NOR gate 23 and a second NOR gate 24; the two input ends of the fourth NAND gate 21 are respectively used to receive the command address signal CA and the column selection enable signal CSL_EN, and the output end of the fourth NAND gate 21 is connected to the input end of the second NAND gate 22; the output end of the second NAND gate 22 is connected to the first input end of the first NOR gate 23; the second input end of the first NOR gate 23 is connected to the output end of the second NOR gate 24, and the output end of the first NOR gate 23 is connected to the first input end of the second NOR gate 24; the second input end of the second NOR gate 24 is used to receive the storage group address enable signal CSL_DIS; wherein, the output end of the first NOR gate 23 is used to output the column selection signal CSL.

[0071] In some embodiments, the peripheral area also includes multiple storage group address enable signal generating circuits 50, each of the storage group address enable signal generating circuits 50 corresponds to one of the storage groups; the storage group address enable signal generating circuit 50 is used to receive the command address signal CA of the storage group corresponding to the storage group address enable signal generating circuit 50, the first initial column enable signal CSLEN0T, the column enable control signal CSL_SLAVE, the test adjustment signal of the storage group corresponding to the storage group address enable signal generating circuit 50, and the test adjustment complementary signal of the storage group corresponding to the storage group address enable signal generating circuit 50, and generate the storage group address enable signal CSL_DIS corresponding to the storage group address enable signal generating circuit 50.

[0072] It should be noted that the number of storage group address enable signal generating circuits 50 corresponds to the number of storage groups. For example, if the memory includes 8 storage groups (BGA to BGH), the number of storage group address enable signal generating circuits 50 is 8. Figure 4 Only the storage group address enable signal generating circuits 50 corresponding to the storage groups BGA and BGH are shown. Since the components and structures of the eight storage group address enable signal generating circuits 50 are the same, the storage group address enable signal generating circuit 50 corresponding to the storage group BGA is taken as an example for detailed description.

[0073] In the storage group address enable signal generating circuit 50 corresponding to the storage group BGA, the storage group address enable signal generating circuit 50 is used to receive the command address signal CABG_A corresponding to the storage group BGA, the first initial column enable signal CSLEN0T, the column enable control signal CSL_SLAVE, the test adjustment signal TM_CSL1B corresponding to the storage group BGA, and the test adjustment complementary signal TM_CSL1T corresponding to the storage group BGA, and generate the storage group address enable signal BGA_CSLDIS corresponding to the storage group BGA.

[0074] It should be noted that the eight storage group address enable signal generating circuits 50 differ in that the received command address signals CA, test adjustment signals and test adjustment complementary signals are different, and the output storage group address enable signals CSL_DIS are also different.

[0075] Specifically, the command address signal CA received by the storage group BGB is BG_B, the test adjustment signal received is TM_CSL2B, the test adjustment complementary signal received is TM_CSL2T, and the storage group address enable signal CSL_DIS output is BGB_CSLDIS; the command address signal CA received by the storage group BGC is BG_C, the test adjustment signal received is TM_CSL3B, the test adjustment complementary signal received is TM_CSL3T, and the storage group address enable signal CSL_DIS output is BGC_CSLDIS; the command address signal CA received by the storage group BGD is BG_D, the test adjustment signal received is TM_CSL4B, the test adjustment complementary signal received is TM_CSL4T, and the storage group address enable signal CSL_DIS output is BGD_CSLDIS; the command address signal CA received by the storage group BGE is BG_E, the test adjustment signal received is TM_CSL5B, and the test adjustment complementary signal received is TM_CSL5T. The test adjustment complementary signal is TM_CSL5T, and the output storage group address enable signal CSL_DIS is BGE_CSLDIS; the command address signal CA received by the storage group BGF is BG_F, the received test adjustment signal is TM_CSL6B, the received test adjustment complementary signal is TM_CSL6T, and the output storage group address enable signal CSL_DIS is BGF_CSLDIS; the command address signal CA received by the storage group BGG is BG_G, the received test adjustment signal is TM_CSL7B, the received test adjustment complementary signal is TM_CSL7T, and the output storage group address enable signal CSL_DIS is BGG_CSLDIS; the command address signal CA received by the storage group BGH is BG_H, the received test adjustment signal is TM_CSL8B, the received test adjustment complementary signal is TM_CSL8T, and the output storage group address enable signal CSL_DIS is BGH_CSLDIS.

[0076] It should be noted that the test adjustment signals TM_CSL1B to TM_CSL8B and the test adjustment complementary signals TM_CSL1T to TM_CSL8T are all delay parameters stored after the test mode test. In this embodiment, by adding the test adjustment signals TM_CSL1B to TM_CSL8B and the test adjustment complementary signals TM_CSL1T to TM_CSL8T in the storage group address enable signal generating circuit 50, it can be used to match the calculation time of the redundant column address calculation module 30 under different process angles, so as to finely adjust the time (tAA) from the READ command signal to the output of the first data.

[0077] Detailed, such as Figure 4As shown, the storage group address enable signal generating circuit 50 may include the same structure as the first delay circuit 16, that is, in the storage group address enable signal generating circuit 50, the storage group address enable signal CSL_DIS will also be output with a corresponding delay, thereby matching the calculation time of the redundant column address calculation module 30.

[0078] Specifically, in some embodiments, the storage group address enable signal generating circuit 50 further includes a second sampler 51 and a third sampler 52, the input end of the second sampler 51 receives the command address signal CA (e.g., BG_A) and the first initial column strobe enable signal CSLEN0T of the storage group corresponding to the storage group address enable signal generating circuit 50, the output end of the second sampler 51 is used to output the first intermediate enable signal S3, the input end of the third sampler 52 receives the first intermediate enable signal S3 and the column strobe control signal CSL_SLAVE, and the output end of the third sampler 52 is used to output the second intermediate enable signal S4. In addition, the storage group address enable signal generating circuit 50 further includes a NAND gate and a NOT gate, the two input ends of the NAND gate receive the second intermediate enable signal S4 and the column strobe control signal CSL_SLAVE respectively, the output end of the NAND gate is connected to the input end of the NOT gate, and the output end of the NOT gate is used to output the third intermediate enable signal S5. The third intermediate enable signal S5 is delayed by the delay circuit to generate a storage group address enable signal CSL_DIS.

[0079] In some embodiments, the peripheral region further includes a column gating control signal generating circuit, such as Figure 7 As shown, it is a schematic diagram of a column selection control signal generating circuit provided in an embodiment of the present application, wherein the column selection control signal generating circuit includes a fifth NAND gate 80, a sixth NAND gate 81, a third NAND gate 84, a seventh NAND gate 85, an eighth NAND gate 86, a fourth NAND gate 87, a third NOR gate 82, a ninth NAND gate 88, a tenth NAND gate 89, a fifth NAND gate 90, an eleventh NAND gate 92, a twelfth NAND gate 94, a sixth NAND gate 93, a fourth NOR gate 91, a thirteenth NAND gate 95, a fourteenth NAND gate 97, a seventh NAND gate 96, an eighth NAND gate 98 and a fifteenth NAND gate 83.

[0080] Among them, the two input ends of the fifth NAND gate 80 receive tCCDL_8B and tCCDL_9B respectively, the output end of the fifth NAND gate 80 is connected to an input end of the sixth NAND gate 81; the other input end of the sixth NAND gate 81 is connected to the output end of the third NAND gate 84, the output end of the sixth NAND gate 81 is connected to an input end of the third NOR gate 82; the input end of the third NAND gate 84 receives CSLEN4T.

[0081] The two input ends of the seventh NAND gate 85 receive tCCDL_10B and tCCDL_11B respectively, and the output end of the seventh NAND gate 85 is connected to one input end of the eighth NAND gate 86; the other input end of the eighth NAND gate 86 is connected to the output end of the fourth NAND gate 87, and the output end of the eighth NAND gate 86 is connected to the other input end of the third NOR gate 82; the input end of the fourth NAND gate 87 receives CSLEN5T; the output end of the third NOR gate 82 is connected to one input end of the fifteenth NAND gate 83.

[0082] The two input ends of the ninth NAND gate 88 receive tCCDL_12B and tCCDL_13B respectively, and the output end of the ninth NAND gate 88 is connected to an input end of the tenth NAND gate 89; the other input end of the tenth NAND gate 89 is connected to the output end of the fifth NAND gate 90, and the output end of the tenth NAND gate 89 is connected to an input end of the fourth NOR gate 91; the input end of the fifth NAND gate 90 receives CSLEN6T.

[0083] The two input ends of the eleventh NAND gate 92 receive tCCDL_14B and tCCDL_15B respectively, and the output end of the eleventh NAND gate 92 is connected to an input end of the twelfth NAND gate 94; the other input end of the twelfth NAND gate 94 is connected to the output end of the sixth NAND gate 93, and the output end of the twelfth NAND gate 94 is connected to the other input end of the fourth NOR gate 91; the input end of the sixth NAND gate 93 receives CSLEN7T; the output end of the fourth NOR gate 91 is connected to an input end of the fifteenth NAND gate 83.

[0084] The two input ends of the thirteenth NAND gate 95 receive tCCDL_16B and VDD respectively, and the output end of the thirteenth NAND gate 95 is connected to an input end of the fourteenth NAND gate 97; the other input end of the fourteenth NAND gate 97 is connected to the output end of the seventh NAND gate 96, and the output end of the fourteenth NAND gate 97 is connected to the input end of the eighth NAND gate 98; the input end of the seventh NAND gate 96 receives CSLEN8T; the output end of the eighth NAND gate 98 is connected to an input end of the fifteenth NAND gate 83; the output end of the fifteenth NAND gate 83 is used to output the column selection control signal CSL_SLAVE.

[0085] It should be noted that the tCCDL_8B~tCCDL_16B signals refer to the minimum delay tCCD_L between two read operations on the same memory bank in the same memory group. Figure 6 The first initial column enable signal generating circuit generates a shift clock signal, wherein CSLEN5T is an inverted signal of CSLEN5B, and CSLEN7T is an inverted signal of CSLEN7B.

[0086] In summary, a memory provided by an embodiment of the present application includes an array area and a peripheral area; the array area includes multiple storage groups; the peripheral area includes multiple data processing centers and a column enable signal generating circuit arranged in sequence along a first direction; each data processing center is connected to a corresponding storage group; the column enable signal generating circuit is connected to multiple data processing centers through a first connection path; the first connection path includes a first connection line extending along the first direction and multiple second connection lines extending along the second direction, the first connection line is connected to the column enable signal generating circuit, one end of each second connection line is connected to the first connection line, and the other end of each second connection line is connected to a data processing center; the second direction intersects with the first direction. The present application enables the column selection enable signal generating circuit to be connected to multiple data processing centers through only one first connection path, so that the number of transmission lines of the column selection enable signal is reduced and the transmission distance is shortened accordingly, thereby greatly reducing the wiring area and reducing the occupation of the peripheral area channel, and solving the technical problem that a large amount of wiring area is wasted because the column selection enable signal and the storage group address enable signal are transmitted to the corresponding storage group through separate wiring.

[0087] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application.

Claims

1. A memory, characterized in that: including an array area and a peripheral area; The array area includes a plurality of storage groups; The peripheral area includes: A plurality of data processing centers arranged in sequence along a first direction, each of the data processing centers being connected to a corresponding storage group; A column selection enable signal generating circuit is connected to the multiple data processing centers through a first connection path; the first connection path includes: a first connection line extending along the first direction and multiple second connection lines extending along the second direction, the first connection line is connected to the column selection enable signal generating circuit, one end of each of the second connection lines is connected to the first connection line, and the other end of each of the second connection lines is connected to a data processing center; the second direction intersects with the first direction.

2. The memory according to claim 1, characterized in that: The first connecting line extends from above the first data processing center along the first direction to above the second data processing center, the first data processing center and the second data processing center are respectively the first and last data processing centers among a plurality of data processing centers arranged in sequence along the first direction; each of the second connecting lines is located above a corresponding data processing center.

3. The memory according to claim 1, characterized in that: The column strobe enable signal generating circuit is used to receive the first initial column strobe enable signal and generate a column strobe enable signal; each of the data processing centers comprises: The column strobe signal generating circuit is used to receive the command address signal, the column strobe enable signal and the storage group address enable signal, and perform logic operation on the command address signal, the column strobe enable signal and the storage group address enable signal to generate the column strobe signal.

4. The memory according to claim 3, characterized in that: The memory also includes: A redundant column address calculation module, used to receive the command address signal and calculate the command address signal, so that when the storage group corresponding to the address in the command address signal is a bad storage group, an address corresponding to a new storage group after the bad storage group is replaced is obtained, and an updated command address signal is generated; The column strobe signal generating circuit is used to receive an updated command address signal, the column strobe enable signal and a storage group address enable signal, and perform logic operations on the updated command address signal, the column strobe enable signal and the storage group address enable signal to generate a column strobe signal.

5. The memory according to claim 4, characterized in that: The column gating enable signal generating circuit comprises: an initial column strobe enable signal generating circuit, configured to receive a second initial column strobe enable signal and a power supply voltage signal, and perform a logic operation on the second initial column strobe enable signal and the power supply voltage signal to obtain a third initial column strobe enable signal; The first delay circuit is used to receive the third initial column enable signal and delay the third initial column enable signal to generate the column enable signal.

6. The memory according to claim 5, characterized in that: The delay time of the first delay circuit is greater than the calculation time of the redundant column address calculation module, and is less than the duration of the command address signal being in an enabled state.

7. The memory according to claim 5, characterized in that: The first delay circuit comprises: A first NAND gate, used for receiving the third initial column gating enable signal and the first state signal, and outputting a first intermediate column gating enable signal; a second NAND gate, used for receiving the third initial column gating enable signal and the second state signal, and outputting a second intermediate column gating enable signal; the first state signal and the second state signal are a pair of complementary signals; N first NOT gates are connected in sequence, and are used to receive the second middle column gate enable signal and output a third middle column gate enable signal; wherein N is an even number greater than zero; The third NAND gate is used to receive the third middle column enable signal and the first middle column enable signal, and output the column enable signal.

8. The memory according to claim 5, characterized in that: The column strobe enable signal generating circuit further comprises: The second delay circuit is used to receive the first initial column enable signal, delay the first initial column enable signal, and output the second initial column enable signal.

9. The memory according to claim 3, characterized in that: The column selection signal generating circuit comprises: A fourth NAND gate, a second NAND gate, a first NOR gate and a second NOR gate; the two input ends of the fourth NAND gate are respectively used to receive the command address signal and the column enable signal, and the output end of the fourth NAND gate is connected to the input end of the second NAND gate; the output end of the second NAND gate is connected to the first input end of the first NOR gate; the second input end of the first NOR gate is connected to the output end of the second NOR gate, and the output end of the first NOR gate is connected to the first input end of the second NOR gate; the second input end of the second NOR gate is used to receive the storage group address enable signal; wherein, the output end of the first NOR gate is used to output the column enable signal.

10. The memory according to claim 3, characterized in that: The peripheral area also includes: A plurality of storage group address enable signal generating circuits, each of which corresponds to one storage group; the storage group address enable signal generating circuit is used to receive the command address signal of the storage group corresponding to the storage group address enable signal generating circuit, the first initial column enable signal, the column enable control signal, the test adjustment signal of the storage group corresponding to the storage group address enable signal generating circuit, and the test adjustment complementary signal of the storage group corresponding to the storage group address enable signal generating circuit, and generate the storage group address enable signal corresponding to the storage group address enable signal generating circuit.

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