Control circuit and memory

Abstract

The invention provides a control circuit and a memory. The control circuit comprises an enabling circuit, a decoding circuit and a signal generating circuit, wherein the enable circuit generates an enable signal whose effective level starts from the effective edge of the activation command signal and ends at the effective edge of the pre-charge command signal; the decoding circuit outputs a decoding signal obtained by decoding the instruction signal when the enable signal is in an effective level; the signal generation circuit generates a control signal for a read or write operation of the memory based on the decoded signal. According to the scheme, the time sequence matching condition between the signals can be consolidated.

Description

Technical Field

[0001] The present application relates to memory technology, and in particular to a control circuit and a memory. Background Art

[0002] With the development of memory technology, memories are widely used in various fields. For example, dynamic random access memory (DRAM) is widely used.

[0003] In actual applications, when the memory is working, the memory controller will send a series of instructions that meet the timing requirements between commands to realize related operations such as reading or writing the memory. Only by ensuring the timing matching between the instructions during the operation of the chip can the normal operation of the memory be realized. Therefore, it is necessary to provide a control scheme that can effectively achieve the timing matching between signals. Summary of the invention

[0004] Embodiments of the present application provide a control circuit and a memory.

[0005] According to some embodiments, the first aspect of the present application provides a control circuit, including: an enable circuit, a decoding circuit and a signal generating circuit; the enable circuit receives an activation command signal and a pre-charge command signal, and is used to generate an enable signal based on the activation command signal and the pre-charge command signal; wherein the effective level of the enable signal starts at the effective edge of the activation command signal and ends at the effective edge of the pre-charge command signal; the decoding circuit is connected to the enable circuit, is used to receive the instruction signal and the enable signal, and when the enable signal is at an effective level, outputs a decoded signal obtained by decoding the instruction signal; the signal generating circuit is connected to the decoding circuit, is used to generate a control signal based on the decoding signal; the control signal is used in the read or write operation of the memory.

[0006] According to some embodiments, the second aspect of the present application provides a memory, comprising: a storage array, a first-in-first-out circuit, and a control circuit as described above; the control circuit receives an activation command signal and a precharge command signal, and is used to output a control signal; the control signal comprises a first-in-first-out input pointer control signal and a first-in-first-out output pointer control signal; the first-in-first-out circuit is connected to the control circuit, and is used to store and output address information corresponding to a read or write operation of the memory in response to the first-in-first-out input pointer control signal and the first-in-first-out output pointer control signal.

[0007] The control circuit and memory provided in the embodiment of the present application include an enabling circuit, a decoding circuit and a signal generating circuit. The enabling circuit generates an enabling signal, the effective level of which starts when the activation command signal arrives and ends when the precharge command signal arrives. The decoding circuit receives the command signal and outputs the decoding signal corresponding to the command signal when the enable signal is at an effective level, so that the signal generating circuit generates a control signal for the read or write operation of the memory according to the received decoding signal. In this scheme, the time period for the decoding circuit to output the decoding signal is controlled, that is, the relevant operation is performed only after the activation command signal is received and before the precharge command signal is received, thereby consolidating the timing matching between the signals, and avoiding the timing changes of some signals in some scenarios, such as the activation command signal and the read / write command, which leads to the destruction of the timing relationship between the relevant signals in the subsequent read or write operation, thereby improving the accuracy and reliability of the memory operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the description, are used to explain the principles of the embodiments of the present application.

[0009] Figure 1 An example diagram of a memory architecture according to an embodiment;

[0010] Figure 2 A structural diagram of a storage unit according to an embodiment of the present invention;

[0011] Figure 3 is a schematic diagram of a working architecture of an example memory;

[0012] Figure 4 is a structural schematic diagram of an exemplary control circuit;

[0013] Figure 5 is a timing diagram of an example;

[0014] Figure 6 is a structural schematic diagram of an exemplary control circuit;

[0015] Figure 7 is a structural schematic diagram of an exemplary control circuit;

[0016] Figure 8 is a structural schematic diagram of an exemplary control circuit;

[0017] Fig. 9 is a structural schematic diagram of an exemplary control circuit;

[0018] Fig.10 is a structural schematic diagram of an exemplary control circuit;

[0019] Fig.11 is a schematic structural diagram of a signal generating circuit of an example;

[0020] Fig.12 is a structural schematic diagram of an exemplary processing circuit;

[0021] Fig.13 is a schematic structural diagram of an exemplary pulse generating circuit;

[0022] Fig.14 is a timing diagram of an example;

[0023] Fig.15 is a structural schematic diagram of an exemplary processing circuit;

[0024] Fig.16 is a schematic diagram of the structure of a preprocessing circuit of an example;

[0025] Fig.17 A structural diagram of a memory device of an example;

[0026] Fig.18 FIG. 1 is a schematic diagram of a first-in-first-out circuit as an example.

[0027] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0028] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application.

[0029] The terms "including" and "having" in this application are used to express an open-ended inclusive meaning, and mean that in addition to the listed elements / components / etc., there may be other elements / components / etc.; the logical symbol " / " is used to express the logical meaning of "or"; the terms "first" and "second" are only used as marks or distinctions, and are not intended to limit the order or quantity of their objects. In addition, the different elements and regions in the drawings are only shown schematically, and are therefore not limited to the sizes or distances shown in the drawings. The "connection" in this application can be a direct connection or an indirect connection.

[0030] The technical solution is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0031] The technical solution is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0032] Figure 1 FIG. 1 is an example diagram of a memory architecture shown in an embodiment, such as Figure 1 As shown, taking DRAM as an example, it includes data input / output buffer, row decoder, column decoder, sense amplifier and storage array. Among them, the data input / output buffer belongs to the peripheral area circuit, and the sense amplifier, row decoder, column decoder and storage array belong to the array area circuit. The storage array is mainly composed of word lines, bit lines and storage cells. The word lines in the storage array extend in the row direction, and the bit lines in the storage array extend in the column direction. The intersection of the word lines and the bit lines is the storage cell of the storage array.

[0033] Each storage unit is used to store one bit of data. Figure 2 As shown, Figure 2 This is a structural example diagram of a memory cell according to an embodiment, and the memory cell is mainly composed of a transistor switch M and a capacitor C. The capacitor is used to store data, and the transistor switch is used to turn off or on according to the selected state.

[0034] A certain storage cell can be activated by controlling the word line and the bit line to access the storage cell. Take the read scenario as an example: when the data in the storage cell needs to be read, the word line of the row where the storage cell is located can be selected through the row decoder, and accordingly, the transistor M in the diagram is turned on, and the state of the capacitor C at this time can be sensed by sensing and amplifying the bit line signal. For example, if the bit data stored in the storage cell is 1, then after the transistor M is turned on, 1 will be read from the bit line of the storage cell, and vice versa. In addition, take the write scenario as an example: when bit data needs to be written to a certain storage cell, such as writing 1. The word line of the row where the storage cell is located can be selected through the row decoder, and the corresponding transistor M in the diagram is turned on, and by setting the logic level of the bit line to 1, the capacitor C is charged, that is, 1 is written to the storage cell. Conversely, if 0 is to be written, the logic level of the bit line is set to 0, so that the capacitor C is discharged, that is, 0 is written to the storage cell.

[0035] In combination with the above-mentioned example principle, when the memory is working, the memory controller will send a series of commands that meet the timing requirements between commands to the memory, and perform related operations such as reading or writing data in the memory. Correspondingly, the timing matching between the commands will affect the operation of the memory. For example, considering the minimum delay time between consecutive commands, a first-in, first-out (FIFO) structure is used to ensure that the data at the maximum depth can be correctly read / written, so it is necessary to ensure that the control signal of the first-in, first-out structure corresponds to the operation data of the read / write operation. For another example, when the memory is working, it is also necessary to ensure the timing matching of the signals used in the read / write operation, such as the read operation on-chip terminal control signal RD_ODT or the write operation on-chip terminal control signal WR_ODT, during the read / write operation.

[0036] As an example, based on the decoded signal decoded by the decoding circuit, an input / output pointer control signal of a first-in-first-out structure is generated to achieve the correct correspondence between the instruction and data of the read / write operation. As an example, Figure 3 A schematic diagram of the working architecture of a memory is shown in FIG. Figure 3The architecture shown has an example workflow as follows: when the memory is working, the memory responds to the activation command signal (ACT CMD) sent by the memory controller to activate a row of the storage array, and then the memory responds to the received read / write command (WR / RD CMD), locates to the corresponding column of the storage array, and performs data write / read operations on the corresponding storage unit. Specifically, the memory decodes the instruction signal sent by the memory controller to obtain a decoding signal CMD DEC. On the one hand, the decoding signal is used as the input of the input pointer control counting structure FIFO_IN_COUNT in the first-in-first-out structure FIFO_DEPTH, so that the input pointer control counting structure FIFO_IN_COUNT generates the input pointer control signal CLK_IN in response to the decoding signal. On the other hand, the decoding signal CMD DEC is also provided to the output pointer control counting structure FIFO_OUT_COUNT in the first-in-first-out structure FIFO_DEPTH after a certain delay (the example in the figure is delayed by the shift delay device SHIFT DELAY), so that the output pointer control counting structure FIFO_OUT_COUNT generates the output pointer control signal CLK_OUT in response to the decoding signal. The input pointer control signal CLK_IN and the output pointer control signal CLK_OUT generated here are used to control the first-in-first-out circuit FIFO in the first-in-first-out structure FIFO_DEPTH to perform the storage and retrieval of temporarily stored data. The data temporarily stored in the first-in-first-out circuit FIFO here include but are not limited to address information such as storage group (Bank Group, BG for short) information (BG<…>), storage block information (BA<…>), column address information (C<…>) and row address information (R<…>). The input pointer control signal CLK_IN and the output pointer control signal CLK_OUT can control the first-in-first-out circuit FIFO to transmit the latched address information to the address bus according to the timing requirements, so as to locate the corresponding storage unit in the storage array of the memory according to the current address information in the read / write operation, and perform data operations on it, so as to realize the normal operation of the memory.

[0037] In actual applications, in some cases, there may be situations where the timing between some command signals changes compared to the timing under normal read / write operations. For example, when the memory performs normal read / write operations, the activation command signal (ACT CMD) is usually issued before the read / write command (WR / RD CMD), but there are some scenarios, such as when performing chip AVL (Advanced Validation Labs) verification, the read / write command may precede the activation command signal. In response to the above situation, the timing of the control signal used in the read / write operation generated in response to these instruction signals will also change compared to the timing under normal read / write operations, resulting in a timing mismatch between the control signal with the changed timing and other signals, resulting in read / write errors and affecting the normal operation of the memory.

[0038] Some aspects of the embodiments of the present application relate to the above considerations. The following is an example introduction of the solution in combination with some embodiments.

[0039] In some embodiments, Figure 4 FIG. 1 is a schematic diagram of a control circuit of an example. Figure 4 As shown, the control circuit includes: an enabling circuit 1, a decoding circuit 2 and a signal generating circuit 3;

[0040] An enabling circuit 1 receives an activation command signal ACT CMD and a precharge command signal PreCharge CMD, and is used to generate an enabling signal EN based on the activation command signal ACT CMD and the precharge command signal PreCharge CMD; wherein the effective level of the enabling signal EN starts at an effective edge of the activation command signal ACT CMD and ends at an effective edge of the precharge command signal PreCharge CMD;

[0041] The decoding circuit 2 is connected to the enabling circuit 1, and is used to receive the instruction signal IN and the enabling signal EN, and when the enabling signal EN is at an effective level, output a decoding signal DEC CMD obtained by decoding the instruction signal IN;

[0042] The signal generating circuit 3 is connected to the decoding circuit 2 and is used to generate a control signal CTR based on the decoding signal DEC CMD; the control signal CTR is used in the read or write operation of the memory.

[0043] In practical applications, the circuit provided in this embodiment can be applied to various memories. As an example, it can be applied to, including but not limited to, double data rate synchronous dynamic random access memory (DDR for short).

[0044] Specifically, under normal circumstances, when the memory is working, the activation command signal arrives before the read / write command. As an example, the read / write command can be obtained by decoding the current instruction signal IN. Among them, the above-mentioned decoding signal DECCMD can be obtained by decoding the instruction signal IN, such as but not limited to the read / write command, the on-chip terminal control signal for read operation or the on-chip terminal control signal for write operation. In practical applications, when the chip select signal (CS) is in a valid state, such as a low level state, the instruction signal IN can be decoded to obtain the corresponding decoding signal DEC CMD. For example, the instruction signal IN of this column includes but is not limited to the chip select signal (CS), command and address signal (CA), etc. In one example, the decoding circuit 2 can use the CA<4:0> information when the chip select signal CS is in a valid state for decoding. Based on the relevant standards of the memory, the valid signals corresponding to different decoding signals, that is, the values ​​of each bit in CA<4:0> are different. Only when the actual values ​​of each bit in the current instruction signal CA<4:0> meet the values ​​of each bit in the valid signal corresponding to the decoding signal, the decoding circuit 2 outputs the valid pulse of the decoding signal, which is regarded as outputting the decoding signal. Specifically, which signals the instruction signal IN contains can be determined according to the actual situation. In the figure, the instruction signal includes the chip select signal CS, and each command and address signal CA0~CA4 as an example. It should be noted that this is just an example, and the number of signals and command and address signals actually contained in the instruction signal is not limited, for example, it can also be CA0~CA5, CA0~CA8, etc.

[0045] Combined with the above example about the FIFO structure, an example is given to illustrate: In one case, if the situation proposed in this example that may cause timing changes is not considered, the input / output pointer control signal of the FIFO structure will immediately start generating and counting in response to the received read / write command. Accordingly, the read / write command before the activation command signal arrives will erroneously cause the input / output pointer control signal to start generating. For example, when the timing of each command signal sent by the memory controller meets the timing relationship of normal operation, for example, assuming that the currently received command signal meets the inter-command timing, the specific example is as follows: ACT CMD→WRA(HLLH)→WRA(LHL H)→PRECHARGE CMD→ACT CMD→RD(HLLH)→PRECHARGE CMD. Among them, ACT CMD is the activation command signal, WRA (…) is the Write with auto precharge command, that is, precharge will be automatically performed after writing is executed. For example, HLLH in WRA (HLLH) indicates that the data written to the data end (DQ end) of the memory is 1111 00000000 1111; PRECHARGE CMD is the precharge command signal; RD (…) is the read command for reading data at a certain address. It can be seen that whenever a read / write command arrives, the corresponding input / output pointer control signal starts counting, but the shift clock signal responded by the shift delay (SHIFT DELAY) of the first-in-first-out structure will only flip when ACT CMD arrives. Under this premise and in combination with the above timing, when ACT CMD arrives, the shift clock signal flips normally; thereafter, when WRA (HLLH) arrives, on the one hand, the input pointer control signal CLK_IN<…> starts to be generated, and on the other hand, after WRA (HLLH) is delayed by the shift delay device, in response to the delayed WRA (HLLH), the output pointer control signal CLK_OUT<…> starts to be generated. In response, the timing of the input pointer control signal and the output pointer control signal at this time match, so the address information corresponding to the subsequent RD (HLLH) is consistent with the address information corresponding to WRA (HLLH), thereby being able to accurately control the normal operation of the first-in-first-out circuit FIFO and achieve accurate read / write operations.

[0046] For another example, when the timing of the command signals sent by the memory controller does not meet the timing relationship of normal operation, for example, assuming that the read / write command precedes the activation command signal, the specific example is as follows: WR (HLHL) → ACT CMD → WRA (HLLH) → WRA (LHL H) → PRECHARGE CMD → ACT CMD → RD (HLLH) → PRECHARGE CMD. Based on this timing, the WR (HLHL) command before the ACT CMD causes the input pointer control signal CLK_IN to start generating. <0> , but ACTCMD has not arrived yet, so there is no shift clock signal and CLK_OUT will not be generated <0> ; and WRA (HLLH) after ACT CMD generates CLK_IN <1> At this time, the shift clock signal begins to flip, so in response to WRA after the shift delay, CLK_OUT begins to be generated <0> , but at this time CLK_OUT <0> What is latched is the address information corresponding to the earliest WRA (HLHL), not the current CLK_IN. <1> The latched address information causes RD (HLLH) to be unable to read the data that WRA (HLLH) should write into the storage array, and instead reads CLK_IN <0> The latched information is HLHL, causing errors in read / write operations.

[0047] Taking the above problems into consideration, in the control circuit of this example, the enable circuit 1 generates an enable signal based on the activation command signal ACT CMD and the precharge command signal PreCharge CMD. The enable signal is at an effective level in a certain period of time, that is, a period of time is defined based on the enable signal. Specifically, the start time of the time period is aligned with the effective edge of the activation command signal, and the end time of the time period is aligned with the effective edge of the precharge command signal. The "alignment" here refers to the alignment within the error range taking into account signal transmission delays, etc., that is, it includes complete timing consistency, and also includes alignment within the error range even if there is a certain deviation. Among them, the effective edge refers to the transition edge of the signal from an invalid level to a valid level, which can be a rising edge (that is, the signal flips from state "0" to state "1") or a falling edge (that is, the signal flips from state "1" to state "0"). Among them, the effective level of the enable signal can be pre-designed, for example, it can be a high level or a low level. As an example, the effective edges of the activation command signal and the precharge command signal are both rising edges, and the effective level of the enable signal is a high level. As an example, Figure 5 A timing diagram of an example is shown in FIG. Figure 5 As shown, the timing state of the activation command signal ACT CMD, the timing state of the precharge command signal PreCharge CMD, the timing state of the enable signal EN, and the timing state of the decoding signal DEC CMD output by the decoding circuit 2 are shown.

[0048] See also Figure 5 , the enable signal EN is at a valid level during the marked valid time period, the start time of the valid time period is aligned with the rising edge of the activation command signal ACT CMD, and the end time is aligned with the rising edge of the precharge command signal PreCharge CMD. Based on the enable signal EN output by the enable circuit 1, the decoding circuit 2 will output the decoding signal DEC CMD obtained by decoding the instruction signal only when the enable signal EN is at a valid level. In other words, outside the valid time period defined by the enable circuit 1 (the period when the enable signal EN is at a valid level), even if the decoding circuit 2 decodes the currently received instruction signal IN to obtain a decoding signal, it will not output the decoding signal. Combined with Figure 5 In the example of, before the activation command signal ACT CMD arrives, the decoding circuit 2 decodes to obtain a decoding signal (a pulse signal shown by a dotted line under the decoding signal DEC CMD in the figure), but since it is not in the valid time period defined by the enable signal EN at this time, the decoding circuit 2 does not output the decoding signal. The dotted pulse in the figure indicates that the decoding circuit does not actually output the decoding signal, thereby avoiding the timing error of the subsequent signal. Here, "output" refers to outputting valid information, for example, not outputting a signal or outputting an invalid default signal (for example, a fixed low level) are both considered as not outputting a decoding signal. As an example, the decoding circuit may not perform decoding when the enable signal is not at a valid level, or, when the enable signal is not at a valid level, even if the decoding is performed to obtain a decoding signal, the decoding signal is not output. Correspondingly, the signal generating circuit 3 generates a control signal for a read or write operation based on the decoding signal output by the decoding circuit 2. Among them, the control signal CTR is used for read / write operations, which includes but is not limited to an input pointer control signal, an output pointer control signal, an ODT signal, etc.

[0049] This example limits the decoding circuit 2 to output the decoding signal within the effective time period defined by the enabling circuit 1, thereby avoiding the problem that the timing of the signal changes in some situations will cause the timing error of the control signal of the entire read / write operation, and ensuring the accuracy and reliability of the read / write operation. Taking the control signal CTR including the input pointer control signal and the output pointer control signal as an example, Figure 5The timing states of the input pointer control signal CLK_IN<…> and the output pointer control signal CLK_OUT<…> are also shown in FIG. It should be noted that the figure takes the first-in-first-out depth (N) of 4 as an example, so the input pointer control signal includes CLK_IN<…> <0> ~CLK_IN <3> , the output pointer control signal includes CLK_OUT <0> ~CLK_OUT <3> . It can be understood that the figure is only an example. In actual applications, the first-in-first-out depths of different decoding signals are different. For example, the first-in-first-out depth of the write mode command (WRP) is N = (tWR + BL / 2) / tCCD_S, for example, the calculation result is 13; the first-in-first-out depth of the read command (RD) is N = RL / tCCD_S, for example, the calculation result is 9. In addition, the delay length of the decoding signal after the shift delay is also set based on the requirements of each command operation, and this example does not limit this. Accordingly, the number of input / output pointer control signals generated corresponds to the first-in-first-out depth. For example, the input pointer control signal includes CLK_IN <0> ~CLK_IN <n-1>, the output pointer control signal includes CLK_OUT <0> ~CLK_OUT <n-1>.like Figure 5 As shown, based on the solution provided in this example, before the command signal ACT CMD is activated, the decoded signal obtained by the decoding circuit 2 is not effectively output, thereby not affecting the timing of the subsequent signals. Specifically, the input pointer control signal CLK_IN<3:0> and the output pointer control signal CLK_OUT<3:0> generated in the figure satisfy the corresponding relationship, and the offset between the two is the delay length of the shift delay of the decoding information. Based on the timing coordination between the input pointer control signal CLK_IN<3:0> and the output pointer control signal CLK_OUT<3:0>, assuming that the input address signal is as follows Figure 5 The ADDR shown in FIG. 1 includes 1st, 2nd, 3rd and 4th. Based on the input pointer control signal CLK_IN<3:0>, as shown in FIG. Figure 5 As shown in the figure, the corresponding input pointer IN_POINT<3:0> is shown in the figure. At each rising edge of the input pointer IN_POINT<3:0>, the address signal is sampled. Based on the input pointer, the sampled data is latched into each latch unit of the first-in-first-out circuit according to the first-in-first-out, and the data FIFO_DATA3~FIFO_DATA0 latched by each latch unit are obtained, which are the 4th~1st latch units mentioned above respectively. st . Accordingly, as shown in the figure, based on the output pointer control signal CLK_OUT<3:0>, the corresponding output pointer OUT_POINT<3:0> is shown in the figure, and the latched data is sampled at each rising edge of the output pointer OUT_POINT<3:0> and output to the address bus ADDR_BUS, and finally the data in the address bus are 1st, 2nd, 3rd and 4th in sequence, and the obtained data is accurate, thereby achieving accurate operation. Therefore, through this example, it is possible to avoid erroneous operations caused by changes in signal timing in some situations, ensure the timing matching between the control signals for read / write operations generated subsequently, and improve the accuracy and reliability of read / write operations.

[0050] Specifically, the enabling circuit 1 is used to generate an enabling signal defining a valid time period, and its implementation structure is not limited. In one example, Figure 6 FIG. 1 is a schematic diagram of a control circuit of an example. Figure 6 As shown, the enabling circuit 1 includes: a first NAND gate 11 and a second NAND gate 12;

[0051] A first input end of the first NAND gate 11 receives a precharge command signal PreCharge CMD, a second input end of the first NAND gate 11 is connected to an output end of the second NAND gate 12, and an output end of the first NAND gate 11 is connected to a decoding circuit 2 for outputting an enable signal EN;

[0052] A first input terminal of the second NAND gate 12 is connected to the output terminal of the first NAND gate 11 , and a second input terminal of the second NAND gate 12 receives the activation command signal ACT CMD.

[0053] In practical applications, the activation command signal ACT CMD and the precharge command signal PreCharge CMD can be generated by corresponding generation circuits based on the received command signal. Figure 6 As shown, the activation command signal ACTCMD is generated by a decoding circuit ACT CMDDEC in response to the internal even / odd clock PCLK_E / O based on the chip select signal CS and the command and address signal CA<…> (for example, CA<13:0>); the precharge command signal PreCharge CMD is generated by another decoding circuit PreCharge CMDDEC in response to the internal even / odd clock PCLK_E / O based on the chip select signal CS and the command and address signal CA<…> (for example, CA<13:0>).

[0054] Specifically, in this example, the first NAND gate 11 and the second NAND gate 12 form an SR latch structure. The first input terminal of the first NAND gate 11 serves as a set terminal of the SR latch structure, which receives a precharge command signal, and the set terminal is valid at a low level; the second input terminal of the second NAND gate 12 serves as a reset terminal of the SR latch structure, which receives an activation command signal, and the reset terminal is valid at a low level.

[0055] Correspondingly, when the activation command signal and the precharge command signal are both at low levels, the output of the SR latch structure is in the initial state; then when the activation command signal arrives, the second input terminal of the second NAND gate 12 (i.e., the reset terminal of the SR latch structure) is at a high level, and the precharge command signal has not arrived at this time, so the first input terminal of the first NAND gate 11 (i.e., the set terminal of the SR latch structure) is at a low level, so the set terminal is valid, and the output signal of the SR latch structure is flipped to a high level; then after the pulse of the activation command signal ends, it returns to a low level, and the second input terminal of the second NAND gate 12 and the first input terminal of the first NAND gate 11 are again At a low level, the SR latch structure keeps outputting a high-level enable signal EN; until the precharge command signal arrives, the first input terminal of the first NAND gate 11 (i.e., the set terminal of the SR latch structure) flips to a high level. At this time, the second input terminal of the second NAND gate 12 (i.e., the reset terminal of the SR latch structure) is at a low level, so the reset terminal is valid, and the enable signal EN output by the SR latch structure flips to a low level; similarly, after the pulse of the precharge command signal ends, the first input terminal of the first NAND gate 11 and the second input terminal of the second NAND gate 12 are at a low level again, and the SR latch structure keeps outputting a low-level enable signal EN. Through the above principle, an enable signal is generated whose effective time period starts at the arrival of the activation command signal and ends at the arrival of the precharge command signal.

[0056] In this example, the enable circuit includes a latch structure consisting of a first NAND gate and a second NAND gate, thereby outputting an enable signal with a valid time period based on an activation command signal and a pre-charge command signal, and by adopting a conventional structure, it can further facilitate circuit design, simplify the circuit structure and reduce costs.

[0057] In another example, Figure 7 FIG. 1 is a schematic diagram of a control circuit of an example. Figure 7 As shown, the enabling circuit 1 includes: a first NOT gate 13, a second NOT gate 14, a third NAND gate 15 and a fourth NAND gate 16;

[0058] The input end of the first NOT gate 13 receives the activation command signal ACT CMD, and the output end of the first NOT gate 13 is connected to the first input end of the third NAND gate 15; the second input end of the third NAND gate 15 is connected to the output end of the fourth NAND gate 16, and the output end of the third NAND gate 15 is connected to the decoding circuit for outputting the enable signal EN;

[0059] The first input terminal of the fourth NAND gate 16 is connected to the output terminal of the third NAND gate 15 ; the input terminal of the second NAND gate 14 receives the precharge command signal PreCharge CMD, and the output terminal of the second NAND gate 14 is connected to the second input terminal of the fourth NAND gate 16 .

[0060] Among them, the generation method of the activation command signal and the pre-charge command signal is also not limited. As an example, the aforementioned example method of generating the activation command signal and the pre-charge command signal can also be used. Specifically, in this example, the third NAND gate 15 and the fourth NAND gate 16 constitute an SR latch structure. Among them, the first input terminal of the third NAND gate 15 serves as the set terminal of the SR latch structure, and the set terminal receives the inverted signal of the activation command signal output by the first NAND gate 13, and the set terminal of the SR latch structure is valid at a low level; the second input terminal of the fourth NAND gate 16 serves as the reset terminal of the SR latch structure, and the reset terminal receives the inverted signal of the pre-charge command signal output by the second NAND gate 14, and the reset terminal of the SR latch structure is valid at a low level.

[0061] Correspondingly, when the activation command signal and the precharge command signal are both at a low level, their inverted signals are both at a high level, and the SR latch structure maintains the output of the initial state, for example, a fixed low level; when the activation command signal arrives, after the inversion of the first NOT gate 13, the first output terminal of the third NAND gate 15 (i.e., the set terminal of the SR latch structure) is at a low level, and the precharge command signal has not arrived at this time, so the second input terminal of the fourth NAND gate 16 (i.e., the reset terminal of the SR latch structure) is still at a high level, so the set terminal is valid, and the enable signal EN output by the SR latch structure flips to a high level; after the pulse of the activation command signal ends, it returns to a low level, and the third NAND gate 15 The first output terminal and the second input terminal of the fourth NAND gate 16 are at a high level again, and the enable signal of the high level is maintained; until the pre-charge command signal arrives, after the inversion of the second NAND gate 14, the second input terminal of the fourth NAND gate 16 (i.e., the reset terminal of the RS latch structure) is flipped to a low level. At this time, the first output terminal of the third NAND gate 15 (i.e., the set terminal of the SR latch structure) is at a high level, so the reset terminal is valid, and the enable signal EN output by the SR latch structure is flipped to a low level; similarly, after the pulse of the pre-charge command signal ends, the first output terminal of the third NAND gate 15 and the second input terminal of the fourth NAND gate 16 are at a high level again, and the enable signal of the low level is maintained. Through the above principle, an enable signal is generated whose effective time period starts at the arrival of the activation command signal and ends at the arrival of the pre-charge command signal.

[0062] In this example, the enable circuit includes a latch structure consisting of two NOT gates and two NAND gates, thereby outputting an enable signal with a valid time period based on an activation command signal and a pre-charge command signal, and by adopting a conventional structure, it can further facilitate circuit design, simplify the circuit structure and reduce costs.

[0063] In another example, Figure 8 FIG. 1 is a schematic diagram of a control circuit of an example. Figure 8 As shown, the enabling circuit 1 includes: a first NOR gate 17, a second NOR gate 18 and a third NOR gate 19;

[0064] The first input end of the first NOR gate 17 receives the activation command signal ACT CMD, the second input end of the first NOR gate 17 is connected to the output end of the second NOR gate 18, the output end of the first NOR gate 17 is connected to the input end of the third NOR gate 19; the output end of the third NOR gate 19 is connected to the decoding circuit for outputting the enable signal EN;

[0065] A first input terminal of the second NOR gate 18 is connected to the output terminal of the first NOR gate 17 , and a second input terminal of the second NOR gate 18 receives a precharge command signal PreCharge CMD.

[0066] Among them, the generation method of the activation command signal and the precharge command signal is also not limited. As an example, the aforementioned example method of generating the activation command signal and the precharge command signal can also be used. Specifically, in this example, the first NOR gate 17 and the second NOR gate 18 constitute an RS latch structure. Among them, the first input terminal of the first NOR gate 17 serves as the reset terminal of the RS latch structure, the reset terminal receives the activation command signal, and the reset terminal of the RS latch structure is valid at a high level; the second input terminal of the second NOR gate 18 serves as the set terminal of the RS latch structure, the set terminal receives the precharge command signal, and the set terminal is valid at a high level.

[0067] Correspondingly, when the activation command signal and the precharge command signal are both at low levels, the RS latch structure maintains the output of the initial state, for example, a fixed high level, and accordingly, after the inversion of the third NOT gate 19, an enable signal EN at a low level in the initial state is obtained; thereafter, when the activation command signal arrives, the first input terminal of the first NOR gate 17 (i.e., the reset terminal of the RS latch structure) is at a high level, and at this time the precharge command signal has not arrived, so the second input terminal of the second NOR gate 18 (i.e., the set terminal of the RS latch structure) is still at a low level, so the reset terminal is valid, and the output signal of the RS latch structure is flipped to a low level, and after the inversion of the third NOT gate 19, the enable signal EN is flipped to a high level; thereafter, after the pulse of the activation command signal ends, it returns to a low level, and the first input terminal of the first NOR gate 17 and the second The second input of the NOR gate 18 is at a low level again, and the RS latch structure keeps outputting a low level. After the inversion of the third NOR gate 19, the enable signal EN keeps at a high level. Until the precharge command signal arrives, the second input of the second NOR gate 18 (i.e., the set end of the RS latch structure) flips to a high level. At this time, the first input of the first NOR gate 17 (i.e., the reset end of the RS latch structure) is at a low level, so the set end is valid, and the RS latch structure outputs a high level. After the inversion of the third NOR gate 19, the enable signal EN flips to a low level. Similarly, after the pulse of the precharge command signal ends, the second input of the second NOR gate 18 and the first input of the first NOR gate 17 are at a low level again, and the RS latch structure keeps outputting a high level. After the inversion of the third NOR gate 19, the enable signal EN keeps at a low level. Through the above principle, an enable signal is generated whose effective time period starts at the arrival of the activation command signal and ends at the arrival of the precharge command signal.

[0068] In this example, the enable circuit includes a latch structure consisting of a NOT gate and two NOR gates, thereby outputting an enable signal with a valid time period based on an activation command signal and a pre-charge command signal, and by adopting a conventional structure, it can further facilitate circuit design, simplify the circuit structure and reduce costs.

[0069] Specifically, within the effective time period defined by the enable signal EN output by the enable circuit 1, the decoding circuit 2 only outputs the decoding signal within the effective time period. The specific structure of the decoding circuit 2 is not limited. In one example, Fig. 9 FIG. 1 is a schematic diagram of a control circuit of an example. Fig. 9 As shown, the decoding circuit 2 includes: a first NAND circuit 21 and a NOR circuit 22;

[0070] The first NAND circuit 21 has n+1 input terminals, receiving an enable signal EN and n input signals; the n input signals are recorded as the first input signal, the second input signal, ... the ith input signal, ... the nth input signal, if the ith bit of the valid command corresponding to the decoding circuit 2 is high level, the ith input signal is the ith bit of the command signal, if the ith bit of the valid command corresponding to the decoding circuit 2 is low level, the ith input signal is the inverted signal of the ith bit of the command signal, wherein 1≤i≤n, i is an integer;

[0071] An input end of the NOR circuit 22 is connected to at least one output end of the first NAND circuit 21 , and an output end of the NOR circuit 22 is connected to the signal generating circuit 3 .

[0072] Among them, the decoding circuit 2 is used to detect whether the bits of the command signal actually received at present are consistent with the values ​​of the bits of the valid command corresponding to itself. If they are consistent, a valid signal (for example, a high-level signal) is output, otherwise no valid signal is output (for example, a low-level signal is output). In practical applications, corresponding decoding circuits can be set for different decoding signals. Specifically, the number of decoding circuits and the corresponding decoding signals can be set according to actual conditions. For example, a corresponding number of decoding circuits can be set according to the number of decoding signals that are desired to be decoded. Among them, the valid command corresponding to the decoding circuit refers to the value of the command signal corresponding to the decoding signal used by the decoding circuit for decoding. The value of the command signal mentioned here refers to the value combination of each bit of the command signal. For example, the valid command corresponding to the decoding circuit 2 specifically includes the values ​​of the command signal, such as the chip select signal (CS), the command and address signal (CA), etc., that is, a combination of a high level "1" or a low level "0". In this example, the first NAND circuit 21 is used to generate a pulse signal, i.e., a decoding signal DECCMD, by combining the input signal composed of CS and CA signals and their inverted signals through combinational logic (the first NAND circuit and the NOR circuit). The valid command corresponding to the decoding circuit 1 can be determined based on SPEC, which will not be elaborated in detail here.

[0073] The specific structure of the first NAND circuit 21 is not limited. As an example, the structure of the first NAND circuit 21 can be determined according to the number of bits of the valid command corresponding to the decoding circuit 2. For example, assuming that the number of bits of the valid command corresponding to the decoding circuit 2 is small, the first NAND circuit 21 can be implemented by a multi-input NAND gate; if the number of bits of the valid command corresponding to the decoding circuit 2 is large, for example, assuming that the n input signals include the input signal corresponding to CS and the input signal corresponding to CA<4:0>, then for example, Fig. 9 As shown, the first NAND circuit 21 may include a plurality of multi-input NAND gates 211, receiving an enable signal EN and n input signals; accordingly, the NOR circuit 22 performs a NOR operation on the output results of the plurality of multi-input NAND gates 211 in the first NAND circuit 21 to obtain a decoded signal. It should be noted that the figure is only a schematic diagram, and the input terminals shown in the figure are used to illustrate the input terminals of the plurality of multi-input NAND gates 211 (such as a three-input NAND gate). In actual applications, the multi-input NAND gate 211 can adopt a conventional NAND gate circuit, such as a two-input NAND gate, a three-input NAND gate, etc.

[0074] Based on the scheme of this example, it can be understood that only when the current actual instruction signal is consistent with the valid command corresponding to the decoding circuit and the enable signal is at a valid level, the decoding circuit outputs the corresponding decoding signal, thereby avoiding the timing of some signals changing in some cases, resulting in erroneous output of the decoding signal and affecting subsequent read / write operations. And the conventional structure such as NAND and NOR is adopted to simplify the circuit and reduce the cost.

[0075] In another example, Fig.10 FIG. 1 is a schematic diagram of a control circuit of an example. Fig.10 As shown, the decoding circuit 2 includes: a first transmission gate 23 and a first multi-input AND gate 24;

[0076] The first multi-input AND gate 24 has n input terminals, and receives n input signals; the n input signals are recorded as the first input signal, the second input signal, ... the ith input signal, ... the nth input signal, if the ith bit of the valid command corresponding to the decoding circuit is high level, the ith input signal is the ith bit of the command signal, if the ith bit of the valid command corresponding to the decoding circuit is low level, the ith input signal is the inverted signal of the ith bit of the command signal, wherein 1≤i≤n, i is an integer;

[0077] The input end of the first transmission gate 23 is connected to the output end of the first multi-input AND gate 24, the output end of the first transmission gate 23 is connected to the signal generating circuit 3, and the control end of the first transmission gate 23 receives the enable signal EN; the first transmission gate 23 is used to turn on when the enable signal EN is at a valid level.

[0078] Specifically, in this example, the enable signal is used to control the first transmission gate 23, which is achieved by controlling whether the first transmission gate 23 is turned on. Only when the enable signal is at an effective level, the decoding circuit 2 outputs a decoding signal. Among them, the first multi-input AND gate 24 is used to decode the instruction signal to obtain a decoding signal, and its specific structure is not limited. As an example, the structure of the first multi-input AND gate 24 can also be determined according to the number of input signals. For example, assuming that the input signal is small, the first multi-input AND gate 24 can be implemented by a single multi-input AND gate; if the input signal is large, multiple first multi-input AND gates can be set, and each first multi-input AND gate receives a part of the n input signals; accordingly, an OR-NON circuit can also be set to perform an OR operation on the output results of multiple first multi-input AND gates to obtain a decoding signal. As an example, the first transmission gate 23 can be composed of a symmetrically connected NMOS transistor and a PMOS transistor. Accordingly, the control end of the first transmission gate 23 mentioned here includes the gates of the NMOS transistor and the PMOS transistor. As an example, the enable signal can be inverted by setting a NOT gate to obtain an inverted signal of the enable signal. Here, the control end of the first transmission gate receives the enable signal, which specifically refers to the gate of the NMOS transistor of the first transmission gate 23 receiving the enable signal, and the gate of the PMOS transistor of the first transmission gate 23 receiving the inverted signal of the enable signal. Similarly, the figure is only a schematic diagram, and does not limit the specific structure of the first multi-input AND gate 24. For example, the first multi-input AND gate 24 may specifically include a two-input AND gate or a three-input AND gate, and may also include a plurality of two-input AND gates and / or three-input AND gates. The figure shows that the first multi-input AND gate 24 is used to perform AND logic operations on each input signal.

[0079] Based on the scheme of this example, it can be understood that only when the current actual instruction signal is consistent with the valid command corresponding to the decoding circuit and the enable signal is at a valid level, the decoding circuit outputs the corresponding decoding signal, thereby avoiding the timing of some signals changing in some cases, resulting in erroneous output of the decoding signal and affecting subsequent read / write operations. In addition, the transmission gate has a lower on-resistance and a higher off-resistance, so it can improve the response speed and response effect.

[0080] In combination with the above-mentioned example solution, the enabling circuit 1 provides an enabling signal defining a valid time period, and the decoding circuit 2 outputs a decoding signal obtained by decoding the instruction signal only below the valid time period, so that the signal generating circuit 3 generates a control signal for a read / write operation based on the decoding signal, thereby achieving accurate read / write operations and avoiding timing errors. In order to better understand the solution, as an example, the structure and principle of the control circuit are illustrated in combination with the scenario of implementing FIFO control.

[0081] In one example, Fig.11 FIG. 1 is a schematic diagram of a structure of a signal generating circuit of an example, such as Fig.11 As shown, the signal generating circuit 3 includes: two processing circuits, respectively denoted as a first processing circuit 31 and a second processing circuit 32, and a delay circuit 33;

[0082] The input end of the delay circuit 33 is connected to the output end of the decoding circuit 2, and is used to output the decoding signal DEC CMD after delaying it for a preset time length;

[0083] The first processing circuit 31 is connected to the output end of the decoding circuit 2, and is used to use the decoding signal DEC CMD as the input signal of the first processing circuit 31 to generate a corresponding control signal, and the control signal includes a first-in-first-out input pointer control signal CLK_IN<…>; the second processing circuit 32 is connected to the output end of the delay circuit 33, and is used to use the signal output by the delay circuit 33 as the input signal of the second processing circuit 32 to generate a corresponding control signal, and the control signal includes a first-in-first-out output pointer control signal CLK_OUT<…>.

[0084] Among them, the working principles of the first processing circuit and the second processing circuit can be similar, and the signals input to the first processing circuit and the second processing circuit are both decoding signals DEC CMD, but the difference is that the decoding signal input to the first processing circuit is not delayed, while the decoding signal input to the second processing circuit is delayed by the delay circuit 33. In practical applications, the external command sent by the memory controller is decoded by the memory and then decoded into an internal command, and then after the column selection write delay (CAS Write Latency, referred to as CWL), the data end (DQ end) of the memory transmits data, so during this period, the internal command needs to be shifted and delayed accordingly, that is, the delay applied by the delay circuit 33. The specific shift delay amount can be determined according to the actual situation and is not limited here. In combination with the above scheme, it can be seen that in this example, the decoding circuit 2 will output the decoding signal DEC CMD only when the enable signal EN is at a valid level. Correspondingly, the first processing circuit only generates the input pointer control signal in response to the decoding signal DEC CMD at this time, thereby avoiding the false start-up of the first processing circuit 31 due to changes in signal timing, such as the timing of the activation command signal and the read / write command, which in turn causes the generated input pointer control signal to not match the timing of the output pointer control signal, thereby affecting the accuracy of the read / write operation.

[0085] Specifically, the control signals generated in this example include a first-in-first-out input pointer control signal for controlling the FIFO circuit, also called an input pointer control signal CLK_IN<…>, and a first-in-first-out input pointer control signal, also called an output pointer control signal CLK_OUT<…>. As an example, the first processing circuit 31 generates an input pointer control signal CLK_IN<…> according to the decoding signal DECCMD output by the decoding circuit 2; the second processing circuit 32 generates an output pointer control signal CLK_OUT<…> according to the decoding signal DEC CMD delayed by the delay circuit 33. In an example, the structures of the two processing circuits, namely the first processing circuit and the second processing circuit, can be implemented with the same structure.

[0086] As an example, Fig.12 is a schematic diagram of a processing circuit of an example, such as Fig.12 As shown, each processing circuit (the first processing circuit 31 or the second processing circuit 32) includes: a preprocessing circuit 41, a pulse generating circuit 42, a multi-stage trigger circuit 43 and an output circuit 44 corresponding to each stage of the trigger circuit;

[0087] The pre-processing circuit 41 receives the input signal of the processing circuit, and is used to generate a clock signal CMDT, an inverted signal CMDB of the clock signal, and a selection signal CMDDLY after timing alignment processing according to the input signal of the processing circuit;

[0088] The pulse generating circuit 42 is used to generate a pulse input signal PS when the output signals of the first-stage trigger circuit 43 and the last-stage trigger circuit 43 are both in a reset state; the in-phase clock terminal of each stage trigger circuit 43 receives the clock signal CMDT, the inverted clock terminal receives the inverted signal CMDB of the clock signal, and the reset terminal receives the reset signal RST of the trigger circuit 43, and outputs a signal in a reset state in response to the effective reset signal RST; the input terminal of the first-stage trigger circuit 43 is connected to the output terminal of the pulse generating circuit 42 for receiving the pulse input signal PS, and the input terminal of each stage trigger circuit 43 except the first-stage trigger circuit 43 is connected to the output terminal of the previous stage trigger circuit 43;

[0089] The first input terminal of the output circuit 44 receives the selection signal CMDDLY, and the second input terminal of the output circuit 44 is connected to the output terminal of the corresponding trigger circuit 43. The output circuit 44 is used to output the signal output by the corresponding trigger circuit 43 when the selection signal CMDDLY is valid; the control signal includes the signal output by the output circuit 44 corresponding to the multi-stage trigger circuit 43.

[0090] The input signal of the first processing circuit 31 is the decoded signal DEC CMD that has not been delayed, the input signal of the second processing circuit 32 is the decoded signal DEC CMD that has been shift-delayed by the delay circuit 33, the output signal of the first processing circuit 31 is the input pointer control signal, and the input signal of the second processing circuit 32 is the output pointer control signal. In order to distinguish, the input signal of the first processing circuit is referred to as CMD_IN, and the input signal of the second processing circuit is referred to as CMD_OUT. Fig.12 Only the specific structure of a single processing circuit is shown in the figure. The processing circuit shown in the figure can be regarded as the first processing circuit or the second processing circuit. The input signal corresponding to the input signal in the figure is represented by CMD_IN / CMD_OUT to represent the input signal of the first processing circuit / the second processing circuit, and the corresponding output signal is represented by CLK_IN / CLK_OUT to represent the output signal of the first processing circuit / the second processing circuit. However, in actual applications, the structures of the two processing circuits can be the same, so only the structural schematic diagram of a single processing circuit is shown here.

[0091] Specifically, the preprocessing circuit 41 generates a clock signal CMDT, an inverted signal CMDB of the clock signal, and a selection signal CMDDLY; the pulse generating circuit 42 provides a pulse signal PS for inputting into the trigger circuit 43. Accordingly, the trigger circuits 43 at each level respond to the clock signal and shift the pulse signal according to the clock number of the clock signal to obtain a signal P outputted by the trigger circuit 43 at each level. <0> ~P <n-1>, N is the first-in-first-out depth; and the output circuit 44 controls the output signal of each stage of the trigger circuit 43 to be output only when the selection signal CMDDLY is valid, and obtains CLK_IN / CLK_OUT <0> ~CLK_IN / CLK_OUT <n-1>, so that the timing relationship between the pointer control signals is accurate. The specific structure of the trigger circuit 43 is not limited, for example, it can include a single trigger, or, in order to improve the accuracy of the pulse shift, it can also be as follows Fig.12 As shown, each level of trigger circuit 43 includes a first trigger 431 and a second trigger 432; the input end of the first trigger 431 serves as the input end of the trigger circuit 43, the input end of the second trigger 432 is connected to the output end of the first trigger 431, and the output end of the second trigger 432 serves as the output end of the trigger circuit 43; the in-phase clock end of the first trigger 431 receives the inverted signal CMDB of the clock signal, and the inverted clock end of the second trigger 432 is connected to the in-phase clock end of the first trigger 431; the inverted clock end of the first trigger 431 receives the clock signal CMDT, and the in-phase clock end of the second trigger 432 is connected to the inverted clock end of the first trigger 431.

[0092] In one example, Fig.13 FIG. 1 is a schematic diagram of a structure of a pulse generating circuit as an example. Fig.13 As shown, the pulse generating circuit 42 includes: a sixth NAND gate 421 and an eighth NAND gate 422;

[0093] The first input terminal of the sixth NAND gate 421 receives the output signal P of the first-stage trigger circuit 43. <0> The inverted signal PB <0> The second input terminal of the sixth NAND gate 421 receives the output signal P of the last stage trigger circuit 43. <n-1>The output end of the sixth NAND gate 421 is connected to the input end of the eighth NAND gate 422; the output end of the eighth NAND gate 422 is connected to the input end of the first-stage trigger circuit 43.

[0094] Among them, the signal in the reset state output by each stage of the trigger circuit except the last stage of the trigger circuit in response to the valid reset signal is a low-level signal; the signal in the reset state output by the last stage of the trigger circuit in response to the valid reset signal is a high-level signal. In practical applications, the specific reset method of the trigger circuit is not limited. For example, the effective state of the reset signal can be determined according to the reset structure inside the trigger circuit, for example, high level is valid or low level is valid, and the reset state that the trigger circuit can reach in response to the reset signal at the reset end can determine whether it is necessary to add an inverter or other designs. In short, it is only necessary to combine the actual situation to realize that the above-mentioned signals of the last stage and other stages of the trigger circuit in the reset state meet the above requirements, and the specific implementation method is not limited. Similarly, the method of generating the reset signal is not limited. For example, if Fig.13 As shown, the control circuit may further include: a reset circuit 5, including: a thirteenth NOT gate 51 and a fourteenth NOT gate 52; the input end of the thirteenth NOT gate 51 receives an initial reset signal RST, and the output end of the thirteenth NOT gate 51 is connected to the input end of the fourteenth NOT gate 52; the output end of the fourteenth NOT gate 52 is connected to the reset end of the second trigger 432 of the last stage trigger circuit 43; the output end of the thirteenth NOT gate 51 is connected to the reset end of the second trigger 432 of each stage trigger circuit 43 except the last stage trigger circuit 43.

[0095] Specifically, in the initial state, all trigger circuits are reset and in the reset state. It should be noted that the previous diagram only takes the last-stage trigger circuit responding to the reset signal RESETD that is consistent with the level state of the initial reset signal, and the other trigger circuits responding to the reset signal RESETB that is opposite to the level state of the initial reset signal as an example. In actual applications, the reset signal responded by each stage of the trigger circuit can be either RESETD or RESETB, which can be determined according to the reset mechanism of the trigger circuit itself, as long as the trigger circuits at each stage respond to their respective reset signals to reach the above-mentioned initial state. At this time, the output signal P of the last stage of the trigger circuit <n-1>is a high level signal, the output signal P of the first stage trigger circuit <0> It is a low level signal, and its inverted signal PB <0> is a high level signal, so both inputs of the sixth NAND gate 421 are high level signals, and the sixth NAND gate 421 outputs a low level signal, which is inverted by the eighth NOT gate 422 and outputs a high level signal to the first-stage trigger circuit 43. It should be noted that in the initial state, although the output signal P of the last-stage trigger circuit is <n-1>It is a high level signal, but the selection signal CMDDLY is not in a valid state at this time, so the output circuit corresponding to the last stage trigger circuit will not output the high level, so it will not cause CLK_IN / CLK_OUT <n-1>Afterwards, the first-stage trigger circuit 43 responds to the clock signal and updates the output signal P <0> is a high-level signal. At this time, the inverted signal of the output signal of the first-stage trigger circuit is updated to a low-level state, and the output of the sixth NAND gate 421 is flipped to a high-level signal. After passing through the eighth NAND gate 422, the input of the first-stage trigger circuit is updated to a low-level signal. In response to the next clock signal, the output of the first-stage trigger circuit is flipped to a low-level signal, realizing a shift output of the high-level signal provided by the pulse generating circuit 42, and similarly, until the last trigger circuit completes the last shift in sequence. For example, Fig.14 A timing diagram of an example is shown in FIG. Fig.14 As shown, it shows the pulse input signal PS, the initial reset signal RST, the output signal P of each level of the trigger circuit <0> ~P <n-1>And the timing relationship of the selection signal CMDDLY (the figure only shows the timing relationship of the input pointer control signal CLK_IN, taking the first processing circuit as an example). In this example, the pulse generating circuit is composed of a NOT gate and a NAND gate, so as to provide a pulse input to the entire trigger circuit, and is implemented using a conventional structure, which can simplify circuit design and process and reduce costs.

[0096] In one example, Fig.15 is a schematic diagram of a processing circuit of an example, such as Fig.15 As shown, the output circuit 44 includes: a ninth NOT gate 441, a tenth NOT gate 442, a seventh NAND gate 443 and an eleventh NOT gate 444;

[0097] The input end of the ninth NOT gate 441 is connected to the in-phase output end of the corresponding trigger circuit 43, and the output end of the ninth NOT gate 441 is connected to the input end of the tenth NOT gate 442; the output end of the tenth NOT gate 442 is connected to the first input end of the seventh NAND gate 443; the second input end of the seventh NAND gate 443 receives the selection signal CMDDLY, the output end of the seventh NAND gate 443 is connected to the input end of the eleventh NOT gate 444, and the output end of the eleventh NOT gate 444 outputs the control signal CLK_IN / CLK_OUT<…> as the output end of the output circuit 44;

[0098] The output end of the ninth NOT gate 441 in the output circuit 44 corresponding to the first-stage trigger circuit 43 is used to output the output signal P of the first-stage trigger circuit. <0> The inverted signal PB <0> The output circuit 44 corresponding to the last stage trigger circuit 43 further includes a twelfth NOT gate 445, the input end of the twelfth NOT gate 445 is connected to the output end of the ninth NOT gate 441 in the output circuit 44 corresponding to the last stage trigger circuit 43, and is used to output the output signal P of the last stage trigger circuit 43. <n-1>.

[0099] Specifically, the final output control signal CLK_IN / CLK_OUT<…> is output by each stage of the trigger circuit. <0> ~P <n-1>The high-level pulse and the selection signal CMDDLY are ANDed to realize sampling of the pulse signal within the high-level pulse interval to obtain CLK_IN / CLK_OUT<…>. In practical applications, the method of obtaining the signal of the input pulse generating circuit 42 is not limited. In addition to the situation shown in the figure, it can also be provided by the output end of the last-stage trigger circuit, or it can also be provided by the output end of the tenth NOT gate in the output circuit corresponding to the last-stage trigger circuit, and is not limited to the illustrated example. The method of the example in the figure can optimize the timing matching situation. In this example, the output circuit is composed of a plurality of NOT gates and NAND gates, so that the output signal of the trigger circuit is output only when the selection signal is valid, and it is implemented using a conventional structure, which can simplify circuit design and process and reduce costs.

[0100] In one example, Fig.16 FIG. 1 is a schematic diagram of a preprocessing circuit as an example. Fig.16 As shown, the pre-processing circuit 41 may include: a fourth NOT gate 411, a fifth NOT gate 412, a sixth NOT gate 413, a seventh NOT gate 414 and a delay element 415;

[0101] The input end of the fourth NOT gate 411 receives the input signal CMD_IN / CMD_OUT of the processing circuit, the output end of the fourth NOT gate 411 is connected to the input end of the fifth NOT gate 412, the output end of the fifth NOT gate 412 is connected to the input end of the sixth NOT gate 413, the output end of the sixth NOT gate 413 is connected to the input end of the seventh NOT gate 414; the output end of the sixth NOT gate 413 is used to output the inverted signal CMDB of the clock signal CMDT, and the seventh NOT gate 414 is used to output the clock signal CMDT;

[0102] The input end of the delay element 415 is connected to the output end of the fifth NOT gate 412 , and the delay element 415 is used to delay the received signal and output it as the selection signal CMDDLY.

[0103] In this example, the preprocessing circuit is composed of a plurality of NOT gates and delay units, thereby providing a clock signal and a strobe signal, and is implemented using a conventional structure, which can simplify circuit design and process and reduce costs. In addition, the strobe signal CMDDLY is obtained after delay in order to prevent the timing deviation between the high-level pulse output by the trigger circuit and the strobe signal CMDDLY, because the output of the trigger circuit is delayed compared to the input signal of the processing circuit, and therefore the input signal of the processing circuit needs to be delayed to obtain the strobe signal, thereby ensuring that the corresponding signal within the high-level pulse interval output by the trigger circuit can be completely sampled.

[0104] In the control circuit provided by the embodiment of the present application, the enable circuit generates an enable signal, the effective level of which starts when the activation command signal arrives and ends when the precharge command signal arrives. The decoding circuit receives the command signal and outputs the decoding signal corresponding to the command signal when the enable signal is at an effective level, so that the signal generation circuit generates a control signal for the read or write operation of the memory according to the received decoding signal. In this scheme, the time period for the decoding circuit to output the decoding signal is controlled, that is, the relevant operation is performed only after the activation command signal is received and before the precharge command signal is received, thereby consolidating the timing matching between the signals, and avoiding the timing changes of some signals in some scenarios, such as the activation command signal and the read / write command, which leads to the destruction of the timing relationship between the relevant signals in the subsequent read or write operation, thereby improving the accuracy and reliability of the memory operation.

[0105] Embodiment 2

[0106] Fig.17 A structural example diagram of a memory is shown as follows: Fig.17 As shown, the memory includes: a storage array 71, a first-in-first-out circuit 72, and a control circuit 73 as in any of the previous examples;

[0107] The control circuit 73 receives the activation command signal ACT CMD and the precharge command signal PreCharge CMD, and is used to output a control signal CTR; the control signal CTR includes a first-in-first-out input pointer control signal CLK_IN and a first-in-first-out output pointer control signal CLK_OUT;

[0108] The FIFO circuit 72 is connected to the control circuit 73 and is used to store and output address information corresponding to the read or write operation of the memory in response to the FIFO input pointer control signal CLK_IN and the FIFO output pointer control signal CLK_OUT.

[0109] Specifically, the first-in-first-out circuit 72 stores and outputs the address information corresponding to the read or write operation of the memory in response to the input pointer control signal and the output pointer control signal, respectively. The specific structure is not limited, for example, Fig.18 FIG. 1 is a schematic diagram of a first-in-first-out circuit as an example. Fig.18 As shown, the first-in-first-out circuit 72 may include: a buffer circuit 721 and a plurality of data processing circuits 722, each of which corresponds to one bit D of the address information. <0> ~D <n-1>; Input pointer control signals include CLK_IN <0> ~CLK_IN <n-1>, the inverting signal is CLKB_IN <0> ~CLKB_IN <n-1>; Output pointer control signals include CLK_OUT <0> ~CLK_OUT <n-1>, the inverted signal is CLKB_OUT <0> ~CLKB_OUT <n-1>; The data processing circuit 722 includes: a second transmission gate 81, a first latch circuit 82, a third transmission gate 83, a second latch circuit 84, a fourth transmission gate 85 and a first transistor 86; the input end of the second transmission gate 81 receives the corresponding bit, the output end of the second transmission gate 81 is connected to the input end of the first latch circuit 82, and the second transmission gate 81 is turned on in response to the corresponding input pointer control signal being at the first level; the output end of the first latch circuit 82 is connected to the input end of the third transmission gate 83, and is used to output the currently received data in response to the corresponding input pointer control signal being at the first level, and to output the currently latched data in response to the corresponding input pointer control signal being at the second level; the output end of the third transmission gate 83 is connected to the input end of the second latch circuit 84, and is used to turn on in response to the corresponding input pointer control signal being at the second level; The output end of the second latch circuit 84 is connected to the input end of the fourth transmission gate 85, and is used to output the currently received data in response to the corresponding input pointer control signal being at the second level, and to output the currently latched data in response to the corresponding input pointer control signal being at the first level; the output end of the fourth transmission gate 85 is connected to the data transmission line Q; one end of the first transistor 86 is connected to the output end of the third transmission gate 83, the other end of the first transistor 86 is grounded, and the control end of the first transistor 86 receives the data reset signal RES; the buffer circuit 721 includes: a third latch circuit 87 and a second transistor 88; the input end of the third latch circuit 87 is connected to the data transmission line Q, the output end of the third latch circuit 87 is connected to one end of the second transistor 88, the other end of the second transistor 88 is grounded, and the control end of the second transistor 88 receives the negative power supply signal Vss. In one example, the first level is a low level, and the second level is a high level.

[0110] Specifically, the number of data processing circuits can be determined according to the first-in-first-out depth of the first-in-first-out circuit. As an example, the first latch circuit 82 includes a fifteenth NOT gate 821 and a first controllable NOT gate 822; the input end of the fifteenth NOT gate 821 is connected to the output end of the first controllable NOT gate 822, serving as the input end of the first latch circuit 82; the output end of the fifteenth NOT gate 821 and the input end of the first controllable NOT gate 822 serve as the output end of the first latch circuit 82; the in-phase control end of the first controllable NOT gate 822 receives the corresponding input pointer control signal, and the inverting control end of the first controllable NOT gate 822 receives the inverted phase of the corresponding input pointer control signal. No.; the second latch circuit 84 includes a sixteenth NOT gate 841 and a second controllable NOT gate 842; the input end of the sixteenth NOT gate 841 is connected to the output end of the second controllable NOT gate 842, serving as the input end of the second latch circuit 84; the output end of the sixteenth NOT gate 841 is connected to the input end of the second controllable NOT gate 842, serving as the output end of the second latch circuit 84; the in-phase control end of the second controllable NOT gate 842 receives the inverted signal of the corresponding input pointer control signal, and the inverted control end of the second controllable NOT gate 842 receives the corresponding input pointer control signal.

[0111] In the memory provided by this embodiment, the enabling circuit generates an enabling signal, the effective level of which starts when the activation command signal arrives and ends when the precharge command signal arrives. The decoding circuit receives the command signal and outputs the decoding signal corresponding to the command signal when the enabling signal is at an effective level, so that the signal generating circuit generates a control signal for the read or write operation of the memory according to the received decoding signal. In this scheme, the time period for the decoding circuit to output the decoding signal is controlled, that is, the relevant operation is performed only after the activation command signal is received and before the precharge command signal is received, thereby consolidating the timing matching between the signals, and avoiding the timing changes of some signals in some scenarios, such as the activation command signal and the read / write command, which leads to the destruction of the timing relationship between the relevant signals in the subsequent read or write operation, thereby improving the accuracy and reliability of the memory operation.

[0112] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only.

[0113] It should be understood that the present application is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. A control circuit, characterized in that: include: enabling circuit, decoding circuit and signal generating circuit; The enabling circuit receives an activation command signal and a precharge command signal, and is used to generate an enabling signal based on the activation command signal and the precharge command signal; wherein the effective level of the enabling signal starts at an effective edge of the activation command signal and ends at an effective edge of the precharge command signal; The decoding circuit is connected to the enabling circuit, and is used to receive the instruction signal and the enabling signal, and when the enabling signal is at an effective level, output a decoding signal obtained by decoding the instruction signal; The signal generating circuit is connected to the decoding circuit and is used to generate a control signal based on the decoding signal; the control signal is used in the read or write operation of the memory.

2. The control circuit according to claim 1, characterized in that: The enabling circuit comprises: a first NAND gate and a second NAND gate; The first input end of the first NAND gate receives the precharge command signal, the second input end of the first NAND gate is connected to the output end of the second NAND gate, and the output end of the first NAND gate is connected to the decoding circuit for outputting the enable signal; The first input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, and the second input terminal of the second NAND gate receives the activation command signal.

3. The control circuit according to claim 1, characterized in that: The enabling circuit comprises: a first NOT gate, a second NOT gate, a third NAND gate and a fourth NAND gate; The input end of the first NOT gate receives the activation command signal, and the output end of the first NOT gate is connected to the first input end of the third NAND gate; the second input end of the third NAND gate is connected to the output end of the fourth NAND gate, and the output end of the third NAND gate is connected to the decoding circuit for outputting the enable signal; The first input terminal of the fourth NAND gate is connected to the output terminal of the third NAND gate; the input terminal of the second NAND gate receives the precharge command signal, and the output terminal of the second NAND gate is connected to the second input terminal of the fourth NAND gate.

4. The control circuit according to claim 1, characterized in that: The enabling circuit comprises: a first NOR gate, a second NOR gate and a third NOR gate; The first input end of the first NOR gate receives the activation command signal, the second input end of the first NOR gate is connected to the output end of the second NOR gate, the output end of the first NOR gate is connected to the input end of the third NOR gate; the output end of the third NOR gate is connected to the decoding circuit for outputting the enable signal; A first input terminal of the second NOR gate is connected to an output terminal of the first NOR gate, and a second input terminal of the second NOR gate receives the precharge command signal.

5. The control circuit according to claim 1, characterized in that: The decoding circuit comprises: a first NAND circuit and a NOR circuit; the first NAND circuit has n+1 input terminals, receiving the enable signal and n input signals; the n input signals are recorded as the first input signal, the second input signal, ... the ith input signal, ... the nth input signal, if the ith bit of the valid command corresponding to the decoding circuit is a high level, the ith input signal is the ith bit of the command signal, if the ith bit of the valid command corresponding to the decoding circuit is a low level, the ith input signal is the inverted signal of the ith bit of the command signal, wherein 1≤i≤n, i is an integer; An input end of the NOR circuit is connected to at least one output end of the first NAND circuit, and an output end of the NOR circuit is connected to the signal generating circuit.

6. The control circuit according to claim 1, characterized in that: The decoding circuit comprises: a first transmission gate and a first multi-input AND gate; The first multi-input AND gate has n input terminals, receiving n input signals; the n input signals are recorded as the first input signal, the second input signal, ... the ith input signal, ... the nth input signal, if the ith bit of the valid command corresponding to the decoding circuit is a high level, the ith input signal is the ith bit of the command signal, if the ith bit of the valid command corresponding to the decoding circuit is a low level, the ith input signal is the inverted signal of the ith bit of the command signal, wherein 1≤i≤n, i is an integer; The input end of the first transmission gate is connected to the output end of the first multi-input AND gate, the output end of the first transmission gate is connected to the signal generating circuit, and the control end of the first transmission gate receives the enable signal; the first transmission gate is used to turn on when the enable signal is at a valid level.

7. The control circuit according to any one of claims 1 to 6, characterized in that: The signal generating circuit comprises: two processing circuits, respectively denoted as a first processing circuit and a second processing circuit, and a delay circuit; The input end of the delay circuit is connected to the output end of the decoding circuit, and is used to output the decoded signal after delaying it for a preset time length; The first processing circuit is connected to the output end of the decoding circuit, and is used to use the decoding signal as the input signal of the first processing circuit to generate a corresponding control signal, and the control signal includes a first-in-first-out input pointer control signal; the second processing circuit is connected to the output end of the delay circuit, and is used to use the signal output by the delay circuit as the input signal of the second processing circuit to generate a corresponding control signal, and the control signal includes a first-in-first-out output pointer control signal.

8. The control circuit according to claim 7, characterized in that: Each of the processing circuits comprises: a preprocessing circuit, a pulse generating circuit, a multi-stage trigger circuit and an output circuit corresponding to each stage of the trigger circuit; The pre-processing circuit receives an input signal of the processing circuit, and is used to generate a clock signal that has undergone timing alignment processing, an inverted signal of the clock signal, and a gating signal according to the input signal of the processing circuit; The pulse generating circuit is used to generate a pulse input signal when the output signals of the first-stage trigger circuit and the last-stage trigger circuit are both in a reset state; the in-phase clock terminal of each stage trigger circuit receives the clock signal, the inverted clock terminal receives the inverted signal of the clock signal, and the reset terminal receives the reset signal of the trigger circuit, and outputs a signal in a reset state in response to the effective reset signal; the input terminal of the first-stage trigger circuit is connected to the output terminal of the pulse generating circuit for receiving the pulse input signal, and the input terminal of each stage trigger circuit except the first-stage trigger circuit is connected to the output terminal of the previous stage trigger circuit; The first input terminal of the output circuit receives the selection signal, the second input terminal of the output circuit is connected to the output terminal of the corresponding trigger circuit, and the output circuit is used to output the signal output by the corresponding trigger circuit when the selection signal is valid; the control signal includes the signal output by the output circuit corresponding to the multi-stage trigger circuit.

9. The control circuit according to claim 8, characterized in that: The signal in the reset state output by each stage of the trigger circuit except the last stage of the trigger circuit in response to the effective reset signal is a low level signal; the signal in the reset state output by the last stage of the trigger circuit in response to the effective reset signal is a high level signal; The pulse generating circuit comprises: a sixth NAND gate and an eighth NAND gate; The first input end of the sixth NAND gate receives the inverted signal of the output signal of the first-stage trigger circuit, and the second input end of the sixth NAND gate receives the output signal of the last-stage trigger circuit; the output end of the sixth NAND gate is connected to the input end of the eighth NAND gate; The output end of the eighth NOT gate is connected to the input end of the first-stage trigger circuit.

10. The control circuit according to claim 9, characterized in that: The output circuit includes: a ninth NOT gate, a tenth NOT gate, a seventh NAND gate and an eleventh NOT gate; The input end of the ninth NOT gate is connected to the in-phase output end of the corresponding trigger circuit, and the output end of the ninth NOT gate is connected to the input end of the tenth NOT gate; the output end of the tenth NOT gate is connected to the first input end of the seventh NAND gate; the second input end of the seventh NAND gate receives the selection signal, the output end of the seventh NAND gate is connected to the input end of the eleventh NOT gate, and the output end of the eleventh NOT gate outputs the control signal as the output end of the output circuit; Among them, the output end of the ninth NOT gate in the output circuit corresponding to the first-stage trigger circuit is used to output the inverted signal of the output signal of the first-stage trigger circuit; the output circuit corresponding to the last-stage trigger circuit also includes a twelfth NOT gate, and the input end of the twelfth NOT gate is connected to the output end of the ninth NOT gate in the output circuit corresponding to the last-stage trigger circuit, for outputting the output signal of the last-stage trigger circuit.

11. A memory, characterized in that: include: A storage array, a first-in-first-out circuit, and a control circuit as claimed in any one of claims 7 to 10; The control circuit receives an activation command signal and a precharge command signal for outputting a control signal; the control signal includes a first-in-first-out input pointer control signal and a first-in-first-out output pointer control signal; The FIFO circuit is connected to the control circuit and is used to store and output address information corresponding to the read or write operation of the memory in response to the FIFO input pointer control signal and the FIFO output pointer control signal.

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