Portable memory test system
Through the modularly designed portable memory test system, the signal delay circuit and relay circuit are used to generate delayed time pulse signals, which solves the problems of large size and high maintenance costs in the existing system, and realizes the use of multiple memory chips. Efficient testing and timing failure analysis reduce system maintenance costs.
Patent Information
- Application Number
- CN202311017528.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-10
- Filing Date
- 2023-08-14
- Publication Date
- 2025-01-10
AI Technical Summary
Existing memory test systems are bulky, expensive, and expensive to maintain, and it is difficult to effectively control the output and delay of clock signals to meet the analysis needs of different memory.
A modular portable memory test system is designed, including a memory connector, a signal delay device and a processor. The reference clock signal is received through the signal delay circuit and the relay circuit, and the delay clock signal is generated and passed through the The processor performs timing failure analysis and supports testing of multiple memory chips.
It realizes the reduction of the test system volume, which is easy to carry, and can test multiple memory chips. It conducts multiple timing failure analysis through the signal delay device, controls the delay time of the clock signal, and reduces the system maintenance cost and volume.
Smart Images
Figure CN119296624A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a test system. Specifically, the present invention relates to a modular portable memory test system. Background Art
[0002] Existing memory testers provide high-performance test signals, convenient test methods, and programmable test software. However, these traditional testers are bulky, expensive, and require time to maintain.
[0003] In addition, in order to avoid the difference and uncertainty of the clock signal distribution, it is necessary to control the output and delay of the clock signal so as to analyze the different conditions of each memory.
[0004] Therefore, the above technology still has many defects, and it is necessary for those skilled in the art to develop other suitable portable memory testing systems. Summary of the invention
[0005] One aspect of the present invention relates to a portable memory test system. A first memory connector, a signal delay device, and a processor. The first memory connector is used to connect a first chip to be tested. The signal delay device is coupled to the first memory connector. The processor is coupled to the signal delay device and is used to match the first pin definition of a plurality of first chip pins of the first chip to be tested with the second pin definition of the first memory connector. The signal delay device is used to receive a reference clock signal and delay the reference clock signal by a preset time to generate a delayed clock signal, so as to input the delayed clock signal into the first chip to be tested.
[0006] In some embodiments, the signal delay device includes a clock signal delay circuit coupled to the processor and configured to receive a reference clock signal and delay the reference clock signal by a preset time to generate an initial delayed clock signal.
[0007] In some embodiments, the signal delay device further comprises a clock signal relay circuit coupled to the first memory connector and configured to receive the initial delayed clock signal to eliminate multiple noises in the initial delayed clock signal to generate a delayed clock signal.
[0008] In some embodiments, the portable memory test system further comprises a second memory connector. The second memory connector is coupled to the clock signal relay circuit of the signal delay device and is used to connect to a second chip to be tested.
[0009] In some embodiments, the first memory connector is further used to be plugged into a plurality of first chip pins of the first chip to be tested. The second memory connector is further used to be plugged into a plurality of second chip pins of the second chip to be tested.
[0010] In some embodiments, the first chip under test includes one of a second-generation low-power double data rate synchronous dynamic random access memory to a fifth-generation low-power double data rate synchronous dynamic random access memory, a second-generation double data rate synchronous dynamic random access memory to a fifth-generation double data rate synchronous dynamic random access memory, an unbuffered dual in-line memory module, and a dual in-line memory module with a register.
[0011] In some embodiments, the second chip under test includes a small outline dual in-line memory module.
[0012] In some embodiments, the portable memory test system further comprises a clock generator which is coupled to the processor and used to generate a reference clock signal to the processor and the signal delay device.
[0013] In some embodiments, the processor is further configured to perform a timing failure analysis test process on the first chip under test and the second chip under test according to the delayed clock signal.
[0014] In some embodiments, the portable memory test system further comprises a test board on which the processor, the first memory connector, the second memory connector, the clock generator and the signal delay device are all disposed.
[0015] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present invention provides a portable memory test system, which can reduce the size of the memory test system to facilitate portability and can test multiple types of memory chips. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The content of this case can be better understood by referring to the embodiments in the subsequent paragraphs and the following drawings:
[0017] Figure 1 is a circuit block diagram of a portable memory testing system according to some embodiments of the present invention; and
[0018] Figure 2 FIG. 4 is a signal timing diagram of a reference clock signal and a delayed clock signal according to some embodiments of the present invention. DETAILED DESCRIPTION
[0019] The spirit of the present invention will be clearly illustrated below with accompanying drawings and detailed descriptions. After understanding the embodiments of the present invention, any person skilled in the art can make changes and modifications based on the techniques taught by the present invention without departing from the spirit and scope of the present invention.
[0020] The terms used herein are only for describing specific embodiments and are not intended to be limiting of the present invention. Singular forms such as "a", "an", "this", "this", and "the" as used herein also include plural forms.
[0021] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.
[0022] The terms used herein generally have the ordinary meaning of each term used in the field, in the context of the present invention, and in the specific context, unless otherwise noted. Certain terms used to describe the present invention will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the present invention.
[0023] Figure 1 FIG. 1 is a circuit block diagram of a portable memory testing system 100 according to some embodiments of the present invention. Figure 1 The portable memory test system 100 includes a test board 110, a plurality of memory connectors (for example, a memory connector 120 and a memory connector 130), a processor 140, a clock generator 150, a signal delay device 160, and a plurality of chips to be tested (for example, a chip to be tested 170 and a chip to be tested 180).
[0024] In some embodiments, the memory connector 120 is different from the memory connector 130. In some embodiments, the chip under test 170 is different from the chip under test 180.
[0025] In some embodiments, the clock generator 150 is coupled to the processor 140. The processor 140 is coupled to the signal delay device 160. The memory connector 120 is used to connect the chip under test 170. The memory connector 130 is used to connect the chip under test 180. The memory connector 120 is coupled to the signal delay device 160. The memory connector 130 is coupled to the signal delay device 160.
[0026] In some embodiments, the chip under test 170 and the chip under test 180 both include a plurality of chip pins. The plurality of chip pins of the chip under test 170 can be correspondingly plugged into the memory connector 120. The plurality of chip pins of the chip under test 180 can be correspondingly plugged into the memory connector 130.
[0027] It should be noted that the memory connector 120 and the memory connector 130 are arranged on the test board 110 by adjusting the interfaces of the memory connectors according to the chip pins of different types of memory chips.
[0028] In some embodiments, the memory connector 120 , the memory connector 130 , the processor 140 , the clock generator 150 , and the signal delay device 160 are all disposed on the test board 110 .
[0029] In some embodiments, the memory connector 120 , the memory connector 130 , the processor 140 , the clock generator 150 , and the signal delay device 160 can be removed and replaced on the test board 110 .
[0030] In some embodiments, the processor 140 is used to match the first pin definition of the plurality of first chip pins of the chip under test 170 with the second pin definition of the memory connector 120. The signal delay device 160 is used to receive a reference clock signal and delay the reference clock signal by a preset time to generate a delayed clock signal, thereby inputting the delayed clock signal to the chip under test 170.
[0031] In some embodiments, the test board 110 includes a development board of a field programmable gate array (FPGA). In some embodiments, the size and shape of the test board 110 can be designed according to actual needs. The test board 110 is mainly designed based on the principle of portability.
[0032] In some embodiments, the processor 140 includes but is not limited to a single processor and an integration of multiple microprocessors, such as a central processing unit (CPU) or a graphics processing unit (GPU).
[0033] In some embodiments, the clock generator 150 is used to generate a reference clock signal. The clock generator is a circuit (amplifier) for signal amplification. The clock generator is connected to components such as a quartz oscillator crystal and a capacitor (an electronic component that stores and releases electricity) to generate a fixed-period signal.
[0034] In some embodiments, the signal delay device 160 includes a clock signal delay circuit 161 and a clock signal relay circuit 162. The clock signal delay circuit 161 is coupled to the processor 140 and used to receive a reference clock signal to delay the reference clock signal by a preset time to generate an initial delayed clock signal. The clock signal relay circuit 162 is coupled to a plurality of memory connectors (e.g., the memory connector 120 and the memory connector 130) and used to receive the initial delayed clock signal to eliminate a plurality of noises in the initial delayed clock signal to generate a delayed clock signal. It should be noted that when the clock signal delay circuit 161 delays the reference clock signal, noise is generated, so that the noise affects the subsequent chip under test 170 or the chip under test 180. Therefore, the noise generated by the clock signal delay circuit 161 needs to be eliminated by the clock signal relay circuit 162 to enhance the reference clock signal and generate a delayed clock signal.
[0035] In some embodiments, the clock signal delay circuit 161 is a dual-channel programmable delay chip, which is mainly used for clock or data offset correction and timing adjustment, and its serial number is NB6L295M. It should be noted that the dual-channel design greatly reduces the delay, improves the efficiency of the memory chip and enhances the stability of the system integrating the memory chip. The dual-channel programmable delay chip has two working modes, namely dual-channel delay mode and extended delay mode. In dual-channel mode, the two delay paths are independent of each other and provide delay for the signals of the two channels respectively. In extended delay mode, the two delay paths are connected to expand the variable delay range of the signal, but it can only be used for one signal path.
[0036] In some embodiments, the clock signal delay circuit 161 is further used to switch between the dual-channel delay mode and the extended delay mode to change the reference clock signal generated by the clock generator 150 so as to input it to the chip under test 170 or the chip under test 180 .
[0037] In some embodiments, the chip under test 170 includes one of a second-generation low-power double-data-rate synchronous dynamic random access memory (Lower Power Double-Data-Rate Two Synchronous Dynamic Random Access Memory, LPDDR2) to a fifth-generation low-power double-data-rate synchronous dynamic random access memory (LPDDR5), a second-generation double-data-rate synchronous dynamic random access memory (DDR2) to a fifth-generation double-data-rate synchronous dynamic random access memory (DDR5), an unbuffered dual in-line memory module (Unbuffered Dual In-line Memory Module, UDIMM) and a registered dual in-line memory module (Registered Dual In-line Memory Module, RDIMM).
[0038] In some embodiments, the chip under test 180 includes a small outline dual in-line memory module (SO-DIMM).
[0039] Figure 2 FIG. 1 is a schematic diagram of the timing sequence of a reference clock signal and a delayed clock signal according to some embodiments of the present invention. Figure 1 and Figure 2 The clock signal delay circuit 161 of the signal delay device 160 is used to delay the reference clock signal CLK by a preset time T1 or a preset time T2 to generate a plurality of delayed clock signals (eg, a delayed clock signal CLK1 and a delayed clock signal CLK2).
[0040] It should be noted that a person skilled in the art can utilize the clock signal delay circuit 161 to generate a variety of delayed clock signals (for example, delayed clock signal CLK1 and delayed clock signal CLK2) to input into different types of memory chips, thereby analyzing the signal timing diagrams of various types of memory chips, and then searching for abnormal circuits or areas in the memory chip through the signal timing diagrams of the memory chip to correct the abnormal circuits or areas in the memory chip.
[0041] In some embodiments, the processor 140 is also used to perform a signal integrity (SI) test process on multiple command signals and multiple data signals. Signal integrity is defined as a series of metrics for detecting the quality of electronic signals transmitted by the chip under test 170 and the chip under test 180 or the command signal generated by the processor 140. Signal integrity means that a digital signal has clean and fast signal rising and falling edges, stable and valid logic position levels, accurate signal time positions, and the digital signal does not contain any transient signals. The main issues considered in signal integrity are ringing, crosstalk, ground bounce, skew, signal loss and noise in the power supply in the digital signal.
[0042] It should be noted that ringing refers to unwanted oscillations in voltage or current, which may be caused by the parasitic capacitance and parasitic inductance in the circuit (not components added in the design, but side effects caused by the materials or placement in the circuit) caused by the pulse wave resonating at its characteristic frequency. Crosstalk in electronics refers to the coupling phenomenon between two signal lines. Ground bounce refers to the phenomenon that when the transistor switches state, the threshold voltage presents a lower voltage than the ground loop at that time. Skew refers to the slight difference in time between different signal paths in a parallel bus (such as length), which leads to a slight time difference in the signal reaching the receiving end.
[0043] In some embodiments, the processor 140 is also used to perform a logic analyzer (LA) test process on multiple command signals and multiple data signals. The logic analysis is used to debug and verify whether the internal digital circuits of the chip under test 170 and the chip under test 180 are operating normally, and the electronic signals of the chip under test 170 and the chip under test 180 can be captured at the same time to analyze the timing relationship of the electronic signals.
[0044] In some embodiments, the processor 140 is also used to perform failure analysis (FA), reset, read and write operations on the chip under test 170 and the chip under test 180. Failure analysis refers to analyzing potential failure modes within the operating range of the memory chip so as to classify the memory chip according to the severity of abnormality, or determine the impact of the failure mode on the memory chip.
[0045] In some embodiments, the processor 140 is further used to copy a plurality of delayed clock signals (e.g., delayed clock signal CLK1 and delayed clock signal CLK2) to input to the same type but different memory chips for analysis. It should be noted that the purpose of copying the delayed clock signal is to select a normal memory chip from a batch of memory chips, and by inputting the delayed clock signal to the abnormal memory chip, the abnormal problems of the circuits and blocks in the memory chip can be found and corrected.
[0046] In some embodiments, the processor 140 is further used to generate system instructions and input them into the chips under test 170 and 180 through the memory connectors 120 and 130 , thereby defining and matching the functions of multiple pins of the chips under test 170 and 180 .
[0047] According to the aforementioned embodiments, the present invention provides a portable memory test system, which reduces the size of the memory test system to facilitate portability, and can test multiple types of memory chips through different types of memory connectors and printed circuit boards specially designed for corresponding memory types, thereby avoiding the use of bulky and expensive traditional machines.
[0048] In addition, through the design of the signal delay device of the portable memory test system of the present case, various timing failure analysis can be performed on the memory to extract the valid signal in the normal memory and apply it to the abnormal memory with the failure signal. In addition, through the design of the signal delay device of the portable memory test system of the present case, the clock signal of the clock generator can be controlled to adjust the fixed delay time.
[0049] Although the present invention is disclosed in detail with reference to the embodiments above, the present invention does not exclude other feasible implementations. Therefore, the protection scope of the present invention shall be determined by the appended claims, rather than being limited by the aforementioned embodiments.
[0050] For those skilled in the art, various changes and modifications can be made to the present invention without departing from the spirit and scope of the present invention. Based on the above embodiments, all changes and modifications made to the present invention are also included in the protection scope of the present invention.
[0051]
Explanation of symbols
[0052] 100: Portable storage test system
[0053] 110: Beta
[0054] 120~130: Memory connector
[0055] 140: Processor
[0056] 150: Clock generator
[0057] 160: Signal delay device
[0058] 161: Clock signal delay circuit
[0059] 162: Clock signal relay circuit
[0060] 170~180: Chip to be tested
[0061] CLK: reference clock signal
[0062] CLK1~CLK2: Delayed clock signal
[0063] T1~T2: preset time.
Claims
1. A portable memory testing system, characterized in that: Include: A first memory connector, used to connect to a first chip to be tested; A signal delay device coupled to the first memory connector; as well as The processor is coupled to the signal delay device and is used to match the first pin definition of multiple first chip pins of the first chip to be tested with the second pin definition of the first memory connector, wherein the signal delay device is used to receive a reference clock signal and delay the reference clock signal by a preset time to generate a delayed clock signal, thereby inputting the delayed clock signal into the first chip to be tested.
2. The portable memory testing system according to claim 1, characterized in that: The signal delay device comprises: The clock signal delay circuit is coupled to the processor and is used to receive the reference clock signal to delay the reference clock signal by the preset time to generate an initial delayed clock signal.
3. The portable memory testing system according to claim 2, characterized in that: The signal delay device also includes: The clock signal relay circuit is coupled to the first memory connector and is used to receive the initial delayed clock signal to eliminate multiple noises in the initial delayed clock signal to generate the delayed clock signal.
4. The portable memory testing system according to claim 3, characterized in that: Also includes: The second memory connector is coupled to the clock signal relay circuit of the signal delay device and is used to connect to a second chip to be tested.
5. The portable memory testing system according to claim 4, characterized in that: The first memory connector is also used for correspondingly plugging into the first chip pins of the first chip to be tested, wherein the second memory connector is also used for correspondingly plugging into a plurality of second chip pins of the second chip to be tested.
6. The portable memory testing system according to claim 5, characterized in that: The first chip to be tested includes one of a second-generation low-power double data rate synchronous dynamic random access memory to a fifth-generation low-power double data rate synchronous dynamic random access memory, a second-generation double data rate synchronous dynamic random access memory to a fifth-generation double data rate synchronous dynamic random access memory, an unbuffered dual in-line memory module, and a dual in-line memory module with a temporary register.
7. The portable memory testing system according to claim 5, characterized in that: The second chip to be tested includes a small-outline dual in-line memory module.
8. The portable memory testing system according to claim 6, characterized in that: Also includes: The clock generator is coupled to the processor and used to generate the reference clock signal to the processor and the signal delay device.
9. The portable memory testing system according to claim 8, characterized in that: The processor is also used for performing a timing failure analysis test process on the first chip to be tested and the second chip to be tested according to the delayed clock signal.
10. The portable memory testing system according to claim 9, characterized in that: The invention also comprises a test board, wherein the processor, the first memory connector, the second memory connector, the clock generator and the signal delay device are all arranged on the test board.