A method and system for reliability evaluation of a sidewall spacer oxide process and electronic device thereof

Abstract

This invention discloses a reliability assessment method, system, and electronic device for sidewall gate oxide (TDDB) processes. In the TDDB test structure, the gate length L of a single finger is adjusted by increasing or decreasing the number of fingers, and then a reliability test is performed to obtain the TDDB test results. Data fitting is performed using L, the TDDB test results, and the logarithm of the gate leakage current to finally obtain the TDDB lifetime of the overlap area between the LDD region and the gate, and the gate oxide quality between the lower source / drain and the gate near the sidewall. This invention proposes a new calculation method to fill the technical gap in the existing technology for reliability assessment of the gate oxide near the sidewall. By more accurately assessing the TDDB lifetime of the overlap area Sov of the LDD region and the gate, this invention helps process engineers to deeply understand and control the gate oxide manufacturing process, especially in the sidewall and poly regions, and helps optimize the manufacturing process of the gate oxide near the sidewall.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and in particular relates to a reliability assessment method and system for sidewall gate oxide processes and its electronic equipment. Background Technology

[0002] In semiconductor manufacturing, particularly in wafer testing, a testkey refers to a test structure or area on a wafer specifically designed to collect specific test data. These test structures are typically located in non-product areas of the wafer, such as scribe lines or scribe lanes at the wafer edge, to facilitate testing before the wafer is diced into individual chips (dies). See also: [Image of scribe lines]. Figure 1 (a)-(c).

[0003] The primary purpose of designing different testkeys is to monitor various process parameters during wafer fabrication, such as transistor performance, resistance and capacitance of metal wires, and contact resistance. This test data (WAT data) is crucial for evaluating whether the wafer meets predetermined electrical specifications and helps identify potential anomalies or problems in the manufacturing process. By designing the test structures within the testkey, engineers can monitor every step of wafer fabrication, thereby ensuring that the wafer product has the required performance and reliability. Because testkeys do not occupy chip area, they do not increase the cost of the chip.

[0004] In WAT testing, TDDB (Time-Dependent Dielectric Breakdown) testing is a common method for evaluating the electrical integrity of the gate oxide layer. It aims to detect potential defects in the gate oxide layer and monitor processes related to the gate oxide layer. Based on previous tape-out results, in S... ov The gate oxide layer exhibits a higher concentration of defects, leading to more severe leakage current. Multiple studies have shown that the lifetime of the gate oxide layer (TDDB) is closely related to factors such as the shape of the sidewall bottom, the shape of the edge gate oxide layer, the gate length, and the overlay accuracy. These key factors are primarily concentrated near the sidewalls at the gate edge. Therefore, current research urgently requires a testing method and a corresponding structure to accurately characterize the quality of this portion of the gate oxide layer.

[0005] In existing TDDB tests, the Testkeys used are typically of two structures: Bulk and Transistor Array, such as... Figure 2As shown. A Bulk transistor consists of a large-area gate and gate oxide layer, primarily used to evaluate the intrinsic lifetime of a large-area gate oxide layer. A Transistor Array divides the bulk gate oxide layer into multiple fingers, forming multiple transistor arrays, primarily used to evaluate the gate oxide quality at the gate edge. In the Transistor Array structure, the polysilicon gate (poly) employs a polygonal dense structure to characterize the impact of the poly edge gate oxide quality on dielectric breakdown. In the bulk structure, a complete MOSFET structure is tested, typically as shown... Figure 3 As shown. The test procedure was performed according to JEDEC standards. During testing, the source, drain, and substrate were connected together as one terminal of the capacitor. The gate was used as the other terminal of the capacitor, as shown. Figure 4 As shown.

[0006] After performing TDDB tests on both Bulk and Transistor Array structures, lifespan calculations under temperature and stress conditions are typically performed based on reliability standards. Under normal procedures, once the TDDB lifespan is obtained, the TDDB testing concludes.

[0007] Therefore, it is evident that: 1) Existing methods are insufficient to estimate the lifetime of local gate oxide, as TDDB estimates the lifetime of the overall gate oxide. 2) Using a bulk or transistor array as the testkey also has limitations: using a bulk structure makes it difficult to effectively eliminate the potential influence of gate oxide on experimental results under large poly areas; while a transistor array can qualitatively evaluate the gate oxide quality at the gate edge, it cannot effectively assess the overall gate oxide quality except for S... ov The gate oxide outside still occupies a larger area. 3) Existing reliability tests have relatively small transistor array sizes, resulting in weak correlation between gate edge and gate oxide quality in the obtained data.

[0008] To more comprehensively and accurately evaluate the reliability of sidewall gate oxide processes and to conduct in-depth research on the gate oxide quality and lifetime between the S / D and the gate near the sidewall, this invention proposes a novel reliability evaluation method for sidewall gate oxide processes. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of the prior art and provide a reliability assessment method, system, and electronic equipment for sidewall gate oxide processes. Based on the relationship between the ratio of the poly perimeter or area to the total poly area and the TDDB (Total Surface Area Depth), this invention proposes an extrapolation of the sensitivity of the gate oxide near the sidewall in the TDDB.

[0010] Firstly, the present invention provides a novel reliability assessment method for sidewall grate oxide processes, specifically:

[0011] In the TDDB test structure, the gate length of a single finger is adjusted by increasing or decreasing the number of fingers, and then reliability testing is performed to obtain the TDDB test results. During the adjustment of the gate length of a single finger, it is necessary to ensure that the total gate area S is maintained. poly The total effective gate length L remains unchanged. eff Get smaller;

[0012] Using the gate length L of a single finger as the x-axis and the TDDB test result as the y-axis, data fitting is performed; the TDDB test result corresponding to L approaching zero is extrapolated, and this TDDB test result is used as the overlap area S between the LDD region and the gate. ov TDDB lifetime;

[0013] Using the gate length L of a single finger as the x-axis, the logarithm of the gate leakage current lg(I) g Using ) as the ordinate, data fitting is performed; extrapolation is performed on the logarithm of the gate leakage current lg(I) when L approaches zero. g The logarithm of the gate leakage current is used as the leakage current value between the lower source drain and the gate near the sidewall, which is used to characterize the gate oxide quality.

[0014] Secondly, the present invention provides a reliability evaluation system for the sidewall grid oxide process implementing the method, comprising:

[0015] The reliability testing module is responsible for performing reliability tests on the TDDB test structure after adjusting the gate length of a single finger, and obtaining the TDDB test results.

[0016] The TDDB lifetime calculation module, which calculates the overlap area between the LDD region and the gate, is responsible for data fitting using the gate length L of a single finger as the x-axis and the TDDB test result as the y-axis. It extrapolates the TDDB test result corresponding to L approaching zero and uses this TDDB test result as the overlap area S between the LDD region and the gate. ov TDDB lifetime;

[0017] The module for calculating the gate oxide quality between the lower source / drain and the gate near the sidewall is responsible for using the gate length L of a single finger as the abscissa and the logarithm of the gate drain current lg(I) as the coordinate. g Using ) as the ordinate, data fitting is performed; extrapolation is performed on the logarithm of the gate leakage current lg(I) when L approaches zero. g The logarithm of the gate leakage current is used as the leakage current value between the lower source drain and the gate near the sidewall to characterize the gate oxide quality.

[0018] Thirdly, the present invention provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method when executing the program.

[0019] Fourthly, the present invention provides a machine-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method.

[0020] The beneficial effects of this invention are:

[0021] This invention proposes an overlap area S between the LDD region and the gate. ov A new calculation method for TDDB lifetime and gate oxide quality between the lower source / drain and gate near the wall is proposed to fill the technical gap in the existing technology for partial gate oxide reliability assessment near the sidewall, and provides an effective solution.

[0022] This invention achieves a more accurate evaluation of the overlap area S between the LDD region and the gate. ov The TDDB lifetime helps process engineers gain a deeper understanding and control of the gate oxide manufacturing process, especially in the sidewalls and poly regions. This helps optimize the manufacturing process of the gate oxide near the sidewalls, thereby improving the overall performance and reliability of semiconductor devices. Furthermore, because it provides rapid and accurate reliability assessment, it accelerates product development processes, speeds up process improvements and product iterations, shortens development cycles, and enhances product market competitiveness. Attached Figure Description

[0023] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a chip dicing groove, where (a) is a chip on a whole wafer, (b) is a magnified chip and dicing groove, and (c) is a chip dicing groove under a microscope;

[0025] Figure 2 These are schematic diagrams of the two testkey structures used in conventional TDDB testing: Bulk and Transistor Array. (a) is a top view of the Bulk type testkey structure, (b) is a side view of the Bulk type testkey structure, (c) is a top view of the Transistor Array type testkey structure, and (d) is a side view of the Transistor Array type testkey structure.

[0026] Figure 3 This is a schematic diagram of the Testkey structure (the red circle represents the gate oxide that needs to be characterized).

[0027] Figure 4 This is the wiring for the gate oxide layer integrity test;

[0028] Figure 5 This is a partial testkey schematic diagram used to characterize the gate oxide quality near the sidewalls, with a total gate area S. poly =25; where (a)-(d) are the gate lengths of different individual fingers, L=5, 1, 0.5, 0.25 respectively;

[0029] Figure 6 This is the principle of lifetime extrapolation method, where (a) L in MOSFET ov Schematic diagram, (b) S in MOSFET ov Schematic diagram, (c) As N increases, L decreases, S ov Increase, (d)L and S ov Relationship, (e) L and L eff Relationship (profile), (f) as N increases, L and L eff Changes (cross-sectional view);

[0030] Figure 7 It is a fitting and extrapolation of TDDB lifetime;

[0031] Figure 8 It involves fitting and extrapolating the leakage current;

[0032] Figure 9 This describes the handling of Testkeys with special dimensions, where (a) shows the case when L is large, and (b) shows the structural changes of the Testkey when L is large, reducing W to make S ov Keeping it unchanged, (c) is the case where L cannot be taken very precisely, and (d) is the case where L cannot be taken very precisely. When fitting, the actual L is used instead.

[0033] Figure 10 This is a partial Testkey layout file used to characterize the quality of the grid oxygen near the sidewall, where (a) is the testkey with finger=1 (bulk), (b) is the testkey with finger=5, (c) is the testkey with finger=10, (d) is the testkey with finger=10, and (e) is the single testkey connected to the pad.

[0034] Figure 11This is the V-ramp test procedure, including (a) the V-ramp test procedure flowchart, (b) the step signal applied during the V-ramp test, and (c) the graph of gate leakage current changing with time during the test.

[0035] Figure 12 This is the TDDB CVS test procedure, including (a) the TDDB test procedure flow and (b) the stress-time variation graph. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] The terms "comprising" and "having," and any variations thereof, used in the embodiments of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or devices.

[0038] In the semiconductor manufacturing field, the TDDB test method estimates the lifetime of the overall gate oxide, making it difficult to estimate the lifetime of local gate oxide. Furthermore, using a bulk structure makes it difficult to effectively eliminate the potential influence of gate oxide on experimental results under large poly areas. While Transistor Arrays can qualitatively evaluate the gate oxide quality at the gate edge, they are limited by factors other than S... ov The gate oxide outside the gate still occupies a larger area, and because the transistor array size is smaller, the correlation between the gate edge and gate oxide quality is weak in the obtained data. Therefore, there is a technical gap in the existing technology for evaluating the reliability of the gate oxide near the sidewalls, and it cannot solve the problem of calculating the lifetime of local gate oxide.

[0039] Based on this, embodiments of the present invention provide a reliability assessment method and system for sidewall gate oxide processes, as well as an electronic device thereof. This method can fill the technical gap in the reliability assessment of gate oxide near the sidewall. The method of the present invention enables testing to capture changes in gate oxide quality in this critical region of the sidewall edge, which is crucial for improving the overall reliability of semiconductor devices. This improvement in local sensitivity is not readily apparent, as it overcomes the limitations of traditional overall assessment, providing the possibility for accurately locating and improving reliability issues. Based on a lifetime estimation method, the present invention provides a series of Testkeys with different finger numbers and gate widths, making them strongly correlated with the gate oxide quality near the sidewall. This enhanced intrinsic correlation makes the test results more reflective of the device performance under actual operating conditions. The present invention solves the problem that existing TDDB tests cannot assess critical local gate oxide, providing a new perspective and method for the reliability assessment of semiconductor devices. With the increasing demand for local reliability assessment, the present invention helps to promote the reliability assessment system towards higher precision and greater comprehensiveness.

[0040] This invention provides a novel reliability assessment method for a sidewall epoxy coating process, specifically:

[0041] In the TDDB test structure, the gate length of a single finger is adjusted by increasing or decreasing the number of fingers, and then reliability testing is performed to obtain the TDDB test results. During the adjustment of the gate length of a single finger, it is necessary to ensure that the total gate area S is maintained. poly The total effective gate length L remains unchanged. eff Get smaller;

[0042] Using the gate length L of a single finger as the x-axis and the TDDB test result as the y-axis, data fitting is performed; the TDDB test result corresponding to L approaching zero is extrapolated, and this TDDB test result is used as the overlap area S between the LDD region and the gate. ov TDDB lifetime;

[0043] Using the gate length L of a single finger as the x-axis, the logarithm of the gate leakage current lg(I) g Using ) as the ordinate, data fitting is performed; extrapolation is performed on the logarithm of the gate leakage current lg(I) when L approaches zero. g The logarithm of the gate leakage current is used as the leakage current value between the lower source drain and the gate near the sidewall, which is used to characterize the gate oxide quality.

[0044] This invention also provides a reliability assessment system for the sidewall grate oxide process implementing the method, comprising:

[0045] The reliability testing module is responsible for performing reliability tests on the TDDB test structure after adjusting the gate length of a single finger, and obtaining the TDDB test results.

[0046] The TDDB lifetime calculation module, which calculates the overlap area between the LDD region and the gate, is responsible for data fitting using the gate length L of a single finger as the x-axis and the TDDB test result as the y-axis. It extrapolates the TDDB test result corresponding to L approaching zero and uses this TDDB test result as the overlap area S between the LDD region and the gate. ov TDDB lifetime;

[0047] The module for calculating the gate oxide quality between the lower source / drain and the gate near the sidewall is responsible for using the gate length L of a single finger as the abscissa and the logarithm of the gate drain current lg(I) as the coordinate. g Using ) as the ordinate, data fitting is performed; extrapolation is performed on the logarithm of the gate leakage current lg(I) when L approaches zero. g The logarithm of the gate leakage current is used as the leakage current value between the lower source drain and the gate near the sidewall, which is used to characterize the gate oxide quality.

[0048] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0049] Example 1:

[0050] Prepare a set of N-type and P-type transistor array samples with different numbers of fingers (N). Figure 5 (a)-5(d), where the gate width W=5um. Maintain the total gate area S. poly (S) poly= With the gate width (W × gate length (L × number of fingers (N)) remaining constant, the gate length of a single finger is adjusted by increasing or decreasing the number of fingers.

[0051] By reducing the gate length L and increasing the number of play cells, the total area between the gate and the substrate capacitor remains constant. As the number of gates increases, the total length L remains unchanged, but the total L... eff (Effective gate length) decreases, such as Figure 6 As shown in (e)-(f).

[0052] The geometry of the capacitor structure between the gate and the source / drain (S / D) is relatively fixed during manufacturing. As N increases, the total L... eff It is getting closer and closer to zero, and it is becoming more and more able to characterize the gate oxide between the gate and the S / D.

[0053] Gate oxide reliability (GOI) and time-delay breakdown (TDDB) tests were performed on each sample, along with V-ramp testing, and the leakage current (IL) of each sample under stress variation was recorded. g Data. CVS tests were performed under applied stress voltage, and the TDDB time data under stress conditions were recorded, extrapolated to 125℃ and 1.1V. OP TDDB lifetime (denoted as T) at a cumulative failure rate of 0.1% under the condition 0.1% ), calculate the TDDB T 0.1% The leakage current data is organized into the following format:

[0054] L and T 0.1% Calculate L, where L is the gate length of a single finger, and S poly This is the total gate area. For each finger number (N), L is compared with T. 0.1% By correlating these, a dataset is formed. Similarly, L is correlated with the logarithm of the leakage current, lg(I). g This forms another dataset. Using L as the x-axis and T as the y-axis... 0.1% Use the ordinate as the vertical axis for data fitting. Common fitting methods are linear or exponential fitting. Extrapolate T as L approaches zero. 0.1% Value, i.e., L eff TDDB lifetime T when (effective gate length) approaches zero 0.1% This can be obtained by observing the y-intercept (L=0), see... Figure 7 .

[0055] L and lg(I) g ): Using L as the x-axis, lg(I) g Using L as the ordinate, data fitting is performed. Common fitting methods are linear fitting or exponential fitting. Extrapolating the logarithm of the leakage current lg(I) as L approaches zero... g This is obtained by observing the y-intercept (L=0), see [link / reference]. Figure 8 .

[0056] L obtained through data fitting and extrapolation eff The TDDB lifetime approaching zero reflects the gate oxide lifetime between the lower S / D and gate near the sidewall. Similarly, L is obtained through data fitting and extrapolation. eff The logarithmic change of leakage current approaching zero is normalized to lg(l) by N. g ), thus obtaining the magnitude of the S / D and gate leakage current.

[0057] In addition to the four sizes of devices with L=5, 1, 0.5, and 0.25 mentioned above, there are also devices with L=0.28, 0.35, 0.6, and 15. For these devices, it is impossible to... poly=Divisible by 25 (N is not an integer), can be used as follows: Figure 9 Methods (a)-(d). The principle followed is ① to ensure that the overlap area S between the L and the LDD region-gate of all devices under test is guaranteed. ov To ensure the accuracy of the data to be fitted, S becomes a uniform functional relationship. ov =W×L ov (See Figure 6 (a), L ov (The length of the intersection between the source / drain and the gate); ② It is also necessary to ensure S poly =25 remains unchanged because the TDDB lifetime decreases as the area increases. L and S ov Inversely proportional, such as Figure 6 As shown in (a)-(d).

[0058] Example 2:

[0059] I. Drawing the map

[0060] like Figure 10 (a)-(d) are four types of MOSCAP and transistor arrytest keys with L=5, L=1, L=0.5, and L=0.25. There are two types, P-type and N-type, both of which are 1.2V devices.

[0061] TDDB testing is performed with a voltage applied to the gate while the source / drain and body are grounded. The pads for G (Gate), S / D (Source / Drain), and B (Bulk) are connected to the SMU (Source Measure Unit). Figure 10 (e) shows one of the devices.

[0062] The following procedures are performed in accordance with JEDEC standards:

[0063] II. Obtain I by conducting GOI testing g and V bd

[0064] See the V-ramp testing procedure. Figure 11 (a)-(c):

[0065] 1) First, perform a pre-test to test the output voltage V of the test machine. use The oxide leakage current I is applied across the capacitor and measured under the operating voltage of the corresponding component. use If I use Greater than the set breakdown current I bd If so, the capacitor is considered to have failed initially.

[0066] 2) If Iuse Less than I bd Then we begin the ramp-test, with the voltage starting from V. use The voltage increases gradually at a uniform pace until oxide layer breakdown is detected, or the set maximum voltage V is reached. max stop.

[0067] 3) Finally, perform a post-test (also called V) after passing the test. use This is used to verify whether the oxide layer has been broken down.

[0068] III. Conduct TDDB testing

[0069] TDDB CVS Testing Process:

[0070] The same voltage stress was applied to test keys with different structures at 125°C. The TDDB was tested using the constant voltage method (CVS), such as... Figure 12 As shown in (a)-(b):

[0071] 1) Apply a time-duration t to the gate int constant pressure stress V stress And monitor the gate current;

[0072] 2) Interruption stress: Applying a stress-induced leakage current (SILC) measurement voltage V to the gate. SILC Waiting time t wait Then, record the gate current I. SILC .

[0073] 3) Repeat steps 1 and 2 until the breakdown standard is reached.

[0074] 4) After testing, sweep the gate voltage to V. meas And measure the gate current;

[0075] If a sudden increase in gate current or an increase in low voltage stress induced leakage current (SILC) is detected during CVS, it is considered a breakdown and the corresponding time is recorded.

[0076] After the test is completed, the breakdown time is obtained under different testkey structure conditions. By going through the above process, the reliability of MOSFET under different stress conditions can be systematically evaluated, and its life under actual working conditions can be extrapolated.

[0077] IV. TDDB Lifespan Extrapolation

[0078] Based on the breakdown time of the samples, the failure time T when the cumulative failure rate is 63.5% is extrapolated using a Weibull distribution. 63% Then, use T 63%An E-model (anodic hole injection model) was fitted to obtain the electric field acceleration factor. The lifetime at an operating voltage of 1.1V was obtained by extrapolation from the E-model. All extrapolated lifetimes were fitted according to a Weibull distribution to calculate the lifetime at a cumulative failure rate of 0.1%. Finally, combined with an area scaling factor, the TDDB lifetime for a specific area was obtained, which is the final TBBD lifetime T. 0.1% .

[0079] IV. Extrapolated S / D gate oxide lifetime

[0080] Using logarithmic data of different TDDB lifetimes / leakage currents as y-axis data and L as x-axis data, a fitting algorithm is used to calculate the TDDB lifetime or lg(I) logarithmic data. g The gate oxide characteristics between the S / D and the gate (below the sidewall) are fitted and extrapolated.

[0081] This invention provides an electronic device, specifically, the electronic device includes a memory and a processor, the memory stores executable code, and when the processor executes the executable code, it implements the method described in any of the embodiments.

[0082] The memory may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk drive. Communication between this system network element and at least one other network element is achieved through at least one communication interface (which can be wired or wireless), such as the Internet, wide area network, local area network, or metropolitan area network.

[0083] The bus can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc.

[0084] The memory is used to store programs. After receiving an execution instruction, the processor executes the program. The method executed by the device for defining the flow process disclosed in any of the foregoing embodiments of the present invention can be applied to the processor or implemented by the processor.

[0085] The processor may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above methods can be completed by integrated logic circuits in the processor's hardware or by software instructions. The processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0086] The computer program product of the readable storage medium provided in the embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the foregoing method embodiments. For specific implementation, please refer to the foregoing method embodiments, which will not be repeated here.

[0087] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0088] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A reliability assessment method for a novel sidewall epoxy coating process, characterized in that... The method is specifically as follows: Adjust the gate length L of a single finger in the TDDB test structure, and then perform a reliability test to obtain the TDDB test results; Using the gate length L of a single finger as the x-axis and the TDDB test result as the y-axis, data fitting is performed; the TDDB test result corresponding to L approaching zero is extrapolated, and this TDDB test result is used as the overlap area S between the LDD region and the gate. ov TDDB lifetime; Using the gate length L of a single finger as the x-axis, the logarithm of the gate leakage current lg(I) g Using ) as the ordinate, data fitting is performed; extrapolation is performed on the logarithm of the gate leakage current lg(I) when L approaches zero. g The logarithm of the gate leakage current is used as the leakage current value between the lower source drain and the gate near the sidewall, which is used to characterize the gate oxide quality.

2. The method according to claim 1, characterized in that... The gate length of a single finger is adjusted by increasing or decreasing the number of fingers.

3. The method according to claim 1, characterized in that... When adjusting the gate length of a single finger, the total gate area S must be maintained. poly The total effective gate length L remains unchanged. eff It gets smaller.

4. A reliability assessment system for implementing the sidewall grate oxide process according to any one of claims 1-3, characterized in that... include: The reliability testing module is responsible for performing reliability tests on the TDDB test structure after adjusting the gate length of a single finger, and obtaining the TDDB test results. The TDDB lifetime calculation module, which calculates the overlap area between the LDD region and the gate, is responsible for data fitting using the gate length L of a single finger as the x-axis and the TDDB test result as the y-axis. It extrapolates the TDDB test result corresponding to L approaching zero and uses this TDDB test result as the overlap area S between the LDD region and the gate. ov TDDB lifetime; The module for calculating the gate oxide quality between the lower source / drain and the gate near the sidewall is responsible for using the gate length L of a single finger as the abscissa and the logarithm of the gate drain current lg(I) as the coordinate. g Using ) as the ordinate, data fitting is performed; extrapolation is performed on the logarithm of the gate leakage current lg(I) when L approaches zero. g The logarithm of the gate leakage current is used as the leakage current value between the lower source drain and the gate near the sidewall, which is used to characterize the gate oxide quality.

5. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method of any one of claims 1-3.

6. A machine-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1-3.

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