SIC chip and manufacturing method thereof

Abstract

The present invention provides a SIC chip and a manufacturing method thereof, belonging to the field of semiconductors. The SIC chip manufacturing method comprises providing a SIC chip, depositing a passivation layer on the inner wall and bottom of a through-hole, wherein the passivation layer extends to a metal covering layer surrounding the through-hole; forming a first PI layer on the surface of the passivation layer and filling the through-hole; forming a second PI layer on the surface of the first PI layer, wherein the first PI layer and the second PI layer have opposite adhesive properties; and forming a plastic encapsulation layer on the surface of the second PI layer, wherein the plastic encapsulation layer covers the second PI layer and the metal covering layer. The present invention forms two PI layers with opposite adhesive properties. Using two PI layers, a stress gradient structure can be formed on the surface of the SIC chip, effectively reducing the shear stress between the plastic encapsulation material and the SIC chip during thermal cycling, thereby reducing the shear stress at the edges and corners of the SIC chip, thereby preventing delamination of the SIC chip from the plastic encapsulation material and cracking of the SIC chip, and further preventing abnormal physical properties and electrical failure of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a SIC chip and a manufacturing method thereof. Background Art

[0002] SIC chip, or silicon carbide chip, is a semiconductor chip that uses silicon carbide (SiC) as the main material. Silicon carbide is a compound composed of carbon and silicon that has the characteristics of high temperature resistance, high frequency resistance, and high voltage resistance, which makes it widely used in the field of power electronic devices.

[0003] In SIC chips, the existing top metal layer (TM) and passivation layer (PA) structure is based on the sequential application of the top metal layer and the passivation layer. First, a through hole is formed in the top metal layer, and the TM / PA structure is formed on the sidewalls and top of the through hole. Next, a PI layer is applied to prevent direct contact between the metal and the external environment, thereby protecting the wafer from contamination and oxidation, and improving the reliability and stability of the wafer.

[0004] Ginseng Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a SIC chip comprising a TM / PA structure in one embodiment. Here, 10 is the PA layer; 20 is the PI material layer; 30 is the molding material layer; and 40 is the TM layer. The PI material layer 20 is made of polyimide (PI). During thermal cycling testing, significant stress differences exist between the TM layer 40 and the PA layer 10 on the surface of the SIC chip, along with the molding material layer 30. During cooling, the molding material layer 30 contracts more than the SIC chip, but the bonding force between the two prevents relative sliding, resulting in significant shear stress at the interface. This shear stress is concentrated at the edges and corners of the SIC chip. Repeated thermal cycling can cause delamination between the SIC chip and the molding material layer 30, and even cracking of the SIC chip, leading to abnormal physical properties and electrical failure of the device.

[0005] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0006] The present invention aims to provide a SIC chip and a method for manufacturing the same, so as to solve the problem that shear stress generated at the edges and corners of the SIC chip during thermal cycling tests may cause delamination between the SIC chip and the plastic packaging material, or even cracking of the SIC chip, thereby leading to abnormal physical properties and electrical failure of the device.

[0007] To solve the above technical problems, the present invention provides a SIC chip, comprising:

[0008] Active area, forming a device functional structure;

[0009] a terminal region, arranged around the periphery of the active region;

[0010] a semiconductor structure layer, located between the active area and the terminal area and disposed near the edge of the active area, the semiconductor structure layer comprising an epitaxial layer, a field oxide layer, a polysilicon layer, a dielectric layer and a metal cover layer sequentially deposited on the surface of the epitaxial layer;

[0011] The metal covering layer is provided with a through hole, a passivation layer is deposited on the inner wall and bottom of the through hole, the passivation layer extends to the metal covering layer around the through hole, a first PI layer and a second PI layer are sequentially provided on the surface of the passivation layer, the first PI layer covers the passivation layer and fills the through hole, the second PI layer covers the first PI layer, a plastic sealing layer is plastic-sealed on the surface of the second PI layer, and the plastic sealing layer covers the second PI layer and the metal covering layer;

[0012] The first PI layer and the second PI layer have opposite adhesive properties.

[0013] Preferably, the first PI layer is a positive-resist PI, and the second PI layer is a negative-resist PI.

[0014] Preferably, the first PI layer is a negative-resist PI, and the second PI layer is a positive-resist PI.

[0015] Preferably, the thickness of the positive PI is 4 μm to 7 μm, the thickness of the negative PI is 7 μm to 12 μm, and the total thickness of the positive PI and the negative PI is less than or equal to 20 μm.

[0016] Based on the same inventive concept, the present invention also provides a method for manufacturing a SIC chip, comprising:

[0017] A SIC chip is provided. The SIC chip includes an active area having a device functional structure, a terminal area disposed around the periphery of the active area, and a semiconductor structure layer located between the active area and the terminal area and disposed near an edge of the active area. The semiconductor structure layer includes an epitaxial layer, a field oxide layer, a polysilicon layer, a dielectric layer, and a metal cover layer sequentially deposited on a surface of the epitaxial layer, wherein a through hole is formed on a surface of the metal cover layer.

[0018] Depositing a passivation layer on the inner wall and bottom of the through hole, wherein the passivation layer extends to the metal covering layer around the through hole;

[0019] forming a first PI layer on the surface of the passivation layer and filling the through hole;

[0020] forming a second PI layer on the surface of the first PI layer, wherein the first PI layer and the second PI layer have opposite adhesive properties;

[0021] A plastic sealing layer is formed on the surface of the second PI layer, and the plastic sealing layer covers the second PI layer and the metal covering layer.

[0022] Preferably, the first PI layer is a positive-resist PI, and the second PI layer is a negative-resist PI.

[0023] Preferably, forming a first PI layer on the surface of the passivation layer and filling the through hole comprises:

[0024] Spin-coat positive resist PI on the wafer surface;

[0025] Expose the spin-coated positive photoresist PI and develop it to form the first PI layer;

[0026] The first PI layer is cured at a temperature of 200° C. to 400° C. for 30 min to 120 min.

[0027] Preferably, forming a second PI layer on the surface of the first PI layer includes:

[0028] Spin-coat negative photoresist PI on the wafer surface;

[0029] The spin-coated negative photoresist PI is exposed and developed to form a second PI layer;

[0030] The second PI layer is cured at a temperature of 300° C. to 500° C. for 30 min to 120 min.

[0031] Preferably, the first PI layer is a negative-resist PI, and the second PI layer is a positive-resist PI.

[0032] Preferably, the thickness of the positive PI is 4 μm to 7 μm, the thickness of the negative PI is 7 μm to 12 μm, and the total thickness of the positive PI and the negative PI is less than or equal to 20 μm.

[0033] Compared with the prior art, the SIC chip of the present invention has the following advantages:

[0034] The present invention forms a first PI layer on the surface of the passivation layer and fills the through hole. A second PI layer is formed on the surface of the first PI layer, wherein the first PI layer and the second PI layer have opposite adhesive properties. A plastic encapsulation layer is formed on the surface of the second PI layer, and the plastic encapsulation layer covers the second PI layer and the metal covering layer. Using two PI layers, a stress gradient structure on the surface of the SIC chip can be formed, which effectively reduces the shear stress between the plastic encapsulation material and the SIC chip during the thermal cycle, thereby protecting the electrical parameters of the device from being stable. Using two PI layers, after the first PI layer is formed, the position with the groove or hole structure on the surface of the passivation layer is completely filled with PI material. When the second PI layer is formed, the interface between the two PI layers is smoother, which can release more shear stress and reduce the stress on the bottom passivation layer and the metal covering layer, thereby reducing the shear stress at the edges and corners of the SIC chip, thereby avoiding delamination of the SIC chip and the plastic encapsulation material, as well as cracking of the SIC chip, and further avoiding abnormal physical properties of the device and electrical failure.

[0035] The SIC chip provided by the present invention and the SIC chip manufacturing method provided by the present invention belong to the same inventive concept. Therefore, the SIC chip provided by the present invention has at least all the advantages of the SIC chip manufacturing method provided by the present invention, by forming a first PI layer on the surface of the passivation layer and filling the through hole. A second PI layer is formed on the surface of the first PI layer, wherein the adhesive properties of the first PI layer and the second PI layer are opposite. A plastic sealing layer is plastic-sealed on the surface of the second PI layer, and the plastic sealing layer covers the second PI layer and the metal covering layer. The use of two PI layers can form a stress gradient structure on the surface of the SIC chip, effectively reducing the shear stress between the plastic sealing material and the SIC chip during the thermal cycle, thereby reducing the shear stress at the edges and corners of the SIC chip, thereby avoiding delamination of the SIC chip and the plastic sealing material, and cracking of the SIC chip, and further avoiding abnormal physical properties of the device and electrical failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 FIG. 1 is a schematic structural diagram of a SIC chip including a TM / PA in one embodiment.

[0037] Figure 2 FIG. 1 is a flow chart of a method for manufacturing a SIC chip according to an embodiment of the present invention.

[0038] Figure 3 It is a schematic diagram of a portion of the structure after a passivation layer is deposited on the metal covering layer in one embodiment of the present invention.

[0039] Figure 4 It is a schematic diagram of a partial structure in which the passivation layer covers the first PI layer in one embodiment of the present invention.

[0040] Figure 5This is a partial structural diagram of a second PI layer covering the surface of a first PI layer in one embodiment of the present invention.

[0041] Figure 6 It is a structural schematic diagram of forming a plastic sealing layer on the surface of the second PI layer and the metal covering layer in one embodiment of the present invention.

[0042] In the figure,

[0043] 10-PA layer; 20-PI material layer; 30-molding material layer; 40-TM layer; 100-epitaxial layer; 101-field oxide layer; 102-polysilicon layer; 103-dielectric layer; 104-metal cover layer; 105-passivation layer; 106-first PI layer; 107-second PI layer; 108-molding layer; 200-through hole. DETAILED DESCRIPTION

[0044] To further clarify the objectives, advantages, and features of the present invention, the SIC chip and its manufacturing method proposed in the present invention are described in further detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the objectives of the embodiments of the present invention. It should be understood that the drawings in this specification do not necessarily depict the specific structure of the present invention to scale, and that illustrative features used to illustrate certain principles of the present invention in the drawings may be slightly simplified. The specific design features of the present invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific intended application and use environment. Furthermore, in the embodiments described below, the same reference numerals may be used across different drawings to denote identical parts or parts having the same function, and repeated descriptions thereof may be omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0045] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0046] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0047] The core concept of the present invention is to provide a SIC chip manufacturing method that can reduce the interfacial stress of the SIC chip. This solves the problem of shear stress generated at the edges and corners of the SIC chip, which causes delamination between the SIC chip and the plastic packaging material, or even cracking of the SIC chip, leading to abnormal physical properties and electrical failure of the device.

[0048] In order to realize the above idea, the present invention provides a method for manufacturing a SIC chip. Figures 2 to 6 A specific embodiment of a SIC chip manufacturing method disclosed herein includes the following steps S1 to S5.

[0049] Step S1: Providing a SIC chip, the SIC chip including an active area (not shown) having a device functional structure, a terminal area disposed around the periphery of the active area, and a semiconductor structure layer located between the active area and the terminal area and disposed near the edge of the active area. The semiconductor structure layer includes an epitaxial layer 100, a field oxide layer 101, a polysilicon layer 102, a dielectric layer 103, and a metal cap layer 104 sequentially deposited on the surface of the epitaxial layer 100, and a through hole 200 is formed on the surface of the metal cap layer 104.

[0050] Specifically, refer to Figure 2 and Figure 3 As shown, a SIC chip is provided. The chip has an active area and a terminal area. The active area is formed with device functional structures, such as source, drain, gate structure and other functional structures. The terminal area is arranged around the periphery of the active area. The semiconductor structure layer includes an epitaxial layer 100. A field oxide layer 101 is deposited on the surface of the epitaxial layer 100. A polysilicon layer 102 is deposited on the surface of the field oxide layer 101. A dielectric layer 103 is deposited on the surface of the polysilicon layer 102. A metal capping layer 104 is deposited on the surface of the dielectric layer 103. The metal capping layer 104 is the top metal layer. The top metal layer can be used as metal interconnection, heat dissipation, etc. for different levels in the chip. Through holes 200 can be formed on the surface of the metal capping layer 104 by a photolithography process.

[0051] Step S2 : depositing a passivation layer 105 on the inner wall and bottom of the through hole 200 , and the passivation layer 105 extends to the metal covering layer 104 around the through hole 200 .

[0052] Specifically, refer to Figure 2 and Figure 3 As shown, a passivation layer 105 is deposited on the inner walls and bottom of through-hole 200. Passivation layer 105 extends to the metal capping layer 104 surrounding through-hole 200. Passivation layer 105 can be formed on the inner walls, bottom, and surrounding of through-hole 200 using silicon nitride (SiN) material via chemical vapor deposition, atomic layer deposition, or other methods. Passivation layer 105 protects the chip from environmental corrosion and leakage current. The formed passivation layer 105 extends to the terminal region.

[0053] Step S3 : forming a first PI layer 106 on the surface of the passivation layer 105 and filling the through hole 200 .

[0054] Specifically, refer to Figure 2 and Figure 4 As shown, the first PI layer 106 can be a positive PI or a negative PI. The first PI layer 106 is explained as a positive PI. The first PI layer 106 is formed on the surface of the passivation layer 105 and filled with the through hole 200, including:

[0055] First, a positive PI photoresist is spin-coated on the surface of the wafer. That is, the active area, the terminal area, and the surface of the semiconductor structure layer are all coated with the positive PI photoresist. When the positive PI photoresist is spin-coated, the through hole 200 is filled with the positive PI photoresist.

[0056] Next, the spin-coated positive photoresist PI is exposed and developed to form the first PI layer 106. The positive photoresist PI at the position covering the passivation layer 105 is blocked using a mask. At the same time, the remaining positive photoresist PI is exposed. After the exposure process, the exposed positive photoresist PI is developed to dissolve the exposed positive photoresist PI. The positive photoresist PI at the position covering the passivation layer 105 remains, thereby forming the first PI layer 106. The first PI layer 106 is a positive photoresist PI with a thickness d1 of 4μm to 7μm. That is, the thickness of the first PI layer 106 can be 4μm, 4.5μm, 4μm, 5.5μm, 6μm, 6.5μm, 7μm, or any value within the range of 4μm to 7μm. In this embodiment, preferably, the first PI layer 106 is a positive photoresist PI with a thickness of 5μm to 6μm.

[0057] Finally, the first PI layer 106 is cured at a temperature of 200°C to 400°C for a duration of 30 to 120 minutes. Specifically, the curing temperature of the first PI layer 106 can be 200°C, 250°C, 300°C, 350°C, 400°C, or any temperature within the range of 200°C to 400°C. The curing duration can be 30 minutes, 50 minutes, 80 minutes, 100 minutes, 120 minutes, or any time within the range of 30 to 120 minutes.

[0058] Step S4: forming a second PI layer 107 on the surface of the first PI layer 106 , wherein the first PI layer 106 and the second PI layer 107 have opposite adhesive properties.

[0059] Specifically, refer to Figure 2 and Figure 5 As shown, the second PI layer 107 can be either a positive or negative PI resist. If the first PI layer 106 is a positive PI resist, then the second PI layer 107 is a negative PI resist. If the first PI layer 106 is a negative PI resist, then the second PI layer 107 is a positive PI resist. In other words, the adhesive properties of the first PI layer 106 and the second PI layer 107 are opposite. In step S3, the first PI layer 106 is explained as a positive PI resist. In this embodiment, the second PI layer 107 is explained as a negative PI resist.

[0060] Forming the second PI layer 107 on the surface of the first PI layer 106 includes:

[0061] First, a negative PI photoresist is spin-coated on the surface of the wafer, that is, the surface of the active area, the terminal area, and the semiconductor structure layer are all coated with the negative PI photoresist.

[0062] Next, the spin-coated negative photoresist PI is exposed and developed to form a second PI layer 107. The negative photoresist PI covering the first PI layer 106 is exposed. The remaining negative photoresist PI is blocked using a mask. The negative photoresist PI is then developed. Since the non-exposed negative photoresist PI dissolves in the developer, the negative photoresist PI covering the first PI layer 106 remains, forming the second PI layer 107. The second PI layer 107 is a negative photoresist PI with a thickness d2 of 7μm to 12μm. That is, the thickness of the second PI layer 107 can be 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, or any value within the range of 7μm to 12μm. In this embodiment, preferably, the second PI layer 107 is a negative photoresist PI with a thickness of 8μm to 10μm. At this time, the sum of the thickness of the positive photoresist PI and the thickness of the negative photoresist PI does not exceed 20μm.

[0063] Finally, the second PI layer 107 is cured at a temperature of 300°C to 500°C for a duration of 30 to 120 minutes. Specifically, the curing temperature for the second PI layer 107 can be 300°C, 350°C, 400°C, 450°C, 500°C, or any temperature within the range of 300°C to 500°C. The curing duration can be 30 minutes, 50 minutes, 80 minutes, 100 minutes, 120 minutes, or any time within the range of 30 to 120 minutes. Both the first PI layer 106 and the second PI layer 107 extend to the terminal region.

[0064] Step S5: forming a plastic encapsulation layer 108 on the surface of the second PI layer 107 , wherein the plastic encapsulation layer 108 covers the second PI layer 107 and the metal covering layer 104 .

[0065] Specifically, refer to Figure 2 and Figure 6 As shown, a plastic encapsulation layer 108 is formed on the surface of the second PI layer 107. The plastic encapsulation layer 108 not only covers the second PI layer 107, but also covers the metal covering layer 104 to protect the chip.

[0066] It should be noted that Figures 3 to 6 This is a schematic diagram of the structure formed during the process of forming the first PI layer 106, the second PI layer 107, and the plastic encapsulation layer 108 on the surface of the wafer. This schematic diagram only shows a portion and does not depict the entire structure. For those skilled in the art, the specific structure of the chip is already familiar.

[0067] A first PI layer 106 is formed on the surface of the passivation layer 105 and fills the through-hole 200. A second PI layer 107 is formed on the surface of the first PI layer 106, wherein the first and second PI layers 106 and 107 have opposite adhesive properties. A molding layer 108 is molded onto the surface of the second PI layer 107, covering the second PI layer 107 and the metal cover layer 104. The thermal expansion coefficient of positive resin is 36 ppm / °C, and that of negative resin is 55 ppm / °C. The thermal expansion coefficient of the molding compound used in commonly used molding layers is 10 ppm / °C at the glass transition temperature (generally 180-190°C). Above the glass transition temperature, the thermal expansion coefficient increases to 45 ppm / °C. During thermal cycling reliability testing, significant stress is generated between the molding compound and the SIC chip. Using two PI layers creates a stress gradient structure on the SIC chip surface, effectively reducing shear stress between the molding compound and the SIC chip during thermal cycling, thereby maintaining stable device electrical parameters.

[0068] Using two PI layers, after the first PI layer 106 is formed, the positions with grooves or hole structures on the surface of the passivation layer 105 are completely filled with PI material. When the second PI layer 107 is formed, the interface between the two PI layers is smoother, which can release more shear stress and reduce the stress on the bottom passivation layer 105 and the metal cover layer 104. Therefore, the shear stress at the edges and corners of the SIC chip can be reduced, thereby preventing delamination of the SIC chip and the plastic packaging material, as well as cracking of the SIC chip, and further preventing abnormal physical properties and electrical failure of the device.

[0069] To realize the above idea, this embodiment also discloses a SIC chip, comprising: an active area, forming a device functional structure; a terminal area, arranged around the periphery of the active area; a semiconductor structure layer, located between the active area and the terminal area and arranged near the edge of the active area, the semiconductor structure layer comprising an epitaxial layer 100, a field oxide layer 101, a polysilicon layer 102, a dielectric layer 103 and a metal cover layer 104 sequentially deposited on the surface of the epitaxial layer 100; the metal cover layer 104 is provided with a through hole 200, and a passivation layer 105 is deposited on the inner wall and bottom of the through hole 200. The passivation layer 105 extends to the metal cover layer 104 surrounding the through-hole 200. A first PI layer 106 and a second PI layer 107 are sequentially formed on the surface of the passivation layer 105. The first PI layer 106 covers the passivation layer 105 and fills the through-hole 200. The second PI layer 107 covers the first PI layer 106. A plastic encapsulation layer 108 is formed on the surface of the second PI layer 107, which covers the second PI layer 107 and the metal cover layer 104. The first PI layer 106 and the second PI layer 107 have opposite adhesive properties. The first PI layer 106 is a positive PI layer, and the second PI layer 107 is a negative PI layer. Alternatively, the first PI layer 106 is a negative PI layer, and the second PI layer 107 is a positive PI layer. The thickness of the positive PI layer is 4 to 7 μm, and the thickness of the negative PI layer is 7 to 12 μm. The total thickness of the positive and negative PI layers is less than or equal to 20 μm.

[0070] The SIC chip provided in this embodiment and the SIC chip manufacturing method provided in this embodiment belong to the same inventive concept. Therefore, the SIC chip provided in this embodiment has at least all the advantages of the SIC chip manufacturing method provided in this embodiment, by forming a first PI layer 106 on the surface of the passivation layer 105 and filling the through hole 200. A second PI layer 107 is formed on the surface of the first PI layer 106, wherein the first PI layer 106 and the second PI layer 107 have opposite adhesive properties. A plastic layer 108 is plastic-sealed on the surface of the second PI layer 107, and the plastic layer 108 covers the second PI layer 107 and the metal cover layer 104. The use of two PI layers can form a stress gradient structure on the surface of the SIC chip, effectively reducing the shear stress between the plastic encapsulation material and the SIC chip during thermal cycling, thereby reducing the shear stress at the edges and corners of the SIC chip, thereby preventing delamination of the SIC chip from the plastic encapsulation material, and cracking of the SIC chip, further preventing abnormal physical properties and electrical failure of the device.

[0071] In summary, the above embodiments provide detailed descriptions of different configurations of SIC chips and methods for manufacturing the same. Of course, the above descriptions are merely descriptions of preferred embodiments of the present invention and do not limit the scope of the present invention. The present invention includes, but is not limited to, the configurations listed in the above embodiments. Those skilled in the art can draw inferences based on the above embodiments. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A SIC chip, characterized in that: include: Active area, forming a device functional structure; a terminal region, arranged around the periphery of the active region; a semiconductor structure layer, located between the active area and the terminal area and disposed near the edge of the active area, the semiconductor structure layer comprising an epitaxial layer, a field oxide layer, a polysilicon layer, a dielectric layer and a metal cover layer sequentially deposited on the surface of the epitaxial layer; The metal covering layer is provided with a through hole, and a passivation layer is deposited on the inner wall and bottom of the through hole. The passivation layer extends to the metal covering layer around the through hole. The surface of the passivation layer is sequentially provided with a first PI layer and a second PI layer. The first PI layer covers the passivation layer and fills the through hole. The second PI layer covers the first PI layer. A plastic sealing layer is plastic-sealed on the surface of the second PI layer. The plastic sealing layer covers the second PI layer and the metal covering layer. The first PI layer and the second PI layer have opposite adhesive properties, and the first PI layer and the second PI layer have different thermal expansion coefficients.

2. The SIC chip according to claim 1, characterized in that: The first PI layer is a positive PI layer, and the second PI layer is a negative PI layer.

3. The SIC chip according to claim 1, characterized in that: The first PI layer is a negative-resist PI, and the second PI layer is a positive-resist PI.

4. The SIC chip according to claim 2 or 3, characterized in that: The thickness of the positive PI is 4 μm to 7 μm, the thickness of the negative PI is 7 μm to 12 μm, and the total thickness of the positive PI and the negative PI is less than or equal to 20 μm.

5. A method for manufacturing a SIC chip according to any one of claims 1 to 4, characterized in that: include: A SIC chip is provided. The SIC chip includes an active area having a device functional structure, a terminal area disposed around the periphery of the active area, and a semiconductor structure layer located between the active area and the terminal area and disposed near an edge of the active area. The semiconductor structure layer includes an epitaxial layer, a field oxide layer, a polysilicon layer, a dielectric layer, and a metal cover layer sequentially deposited on a surface of the epitaxial layer, wherein a through hole is formed on a surface of the metal cover layer. Depositing a passivation layer on the inner wall and bottom of the through hole, wherein the passivation layer extends to the metal covering layer around the through hole; forming a first PI layer on the surface of the passivation layer and filling the through hole; forming a second PI layer on the surface of the first PI layer, wherein the first PI layer and the second PI layer have opposite adhesive properties, and the first PI layer and the second PI layer have different thermal expansion coefficients; A plastic sealing layer is formed on the surface of the second PI layer, and the plastic sealing layer covers the second PI layer and the metal covering layer.

6. The SIC chip according to claim 5, characterized in that: The first PI layer is a positive PI layer, and the second PI layer is a negative PI layer.

7. The SIC chip according to claim 6, characterized in that: The forming of a first PI layer on the surface of the passivation layer and filling the through hole comprises: Spin-coat positive resist PI on the wafer surface; Expose the spin-coated positive photoresist PI and develop it to form the first PI layer; The first PI layer is cured at a temperature of 200° C. to 400° C. for 30 min to 120 min.

8. The SIC chip according to claim 6, characterized in that: The forming of the second PI layer on the surface of the first PI layer comprises: Spin-coat negative photoresist PI on the wafer surface; The spin-coated negative photoresist PI is exposed and developed to form a second PI layer; The second PI layer is cured at a temperature of 300° C. to 500° C. for 30 min to 120 min.

9. The SIC chip according to claim 5, characterized in that: The first PI layer is a negative-resist PI, and the second PI layer is a positive-resist PI.

10. The SIC chip according to claim 6, characterized in that: The thickness of the positive PI is 4 μm to 7 μm, the thickness of the negative PI is 7 μm to 12 μm, and the total thickness of the positive PI and the negative PI is less than or equal to 20 μm.

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