High-voltage gate drive integrated circuit using galvanic isolator

Abstract

The present disclosure provides an apparatus that may include: a first region including a first integrated circuit on a substrate; a second region including a second integrated circuit on the substrate; and a third region on the substrate between the first region and the second region, at least one of the first region and the second region may include at least one pattern that provides galvanic isolation between the first integrated circuit and the second integrated circuit on the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0087259, filed on Jul. 5, 2023, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] The technical concept of the present disclosure relates to a high-voltage gate driver integrated circuit (IC) based on junction isolation, and more specifically, to a high-voltage gate driver IC using a current separator as a level shifter. Background Art

[0004] A high voltage gate drive circuit can be used to drive a switching device operating at a high voltage with a low drive voltage. The high voltage gate drive circuit can usually use a level shifter using a high voltage metal oxide semiconductor field effect transistor (MOSFET) device to convert a low voltage signal into a high voltage level signal. In order to reduce power consumption, if a level shifter is used to transmit only the rising / falling edge information of the input signal, and a latch circuit is used to reproduce the drive signal from the signal at a high voltage level, the information in the latch may be damaged by noise, resulting in serious erroneous operation.

[0005] When a latch circuit is eliminated by driving a current isolator with a modulator and receiving a signal with a demodulator, a gate drive circuit that satisfies high reliability can be implemented. However, a gate drive circuit based on a current isolator may not be easy to implement on a single wafer because the modulator circuit and the demodulator circuit must be electrically isolated to meet insulation requirements. Summary of the invention

[0006] The technical idea of ​​the present disclosure provides a high-voltage gate drive integrated circuit and a semiconductor package including the same, which utilizes the semiconductor technology of the high-voltage gate drive circuit to realize a low-voltage modulator part and a demodulator part operating under high voltage on a single chip, and uses a current isolator to transmit signals between the two circuits, thereby achieving high reliability.

[0007] According to one aspect of the technical concept of the present disclosure, a device may include: a first region, which includes a first integrated circuit on a substrate; a second region, which includes a second integrated circuit on the substrate; and a third region, which is located between the first region and the second region on the substrate, at least one of the first region and the second region may include at least one pattern, and the pattern provides galvanic isolation (galvanic isolation) between the first integrated circuit and the second integrated circuit on the substrate.

[0008] According to an exemplary embodiment of the present disclosure, it may include: a first pattern and a second pattern, which respectively correspond to the first electrode of the first capacitor and the first electrode of the second capacitor in the first conductive layer; and a third pattern and a fourth pattern, which respectively correspond to the second electrode of the first capacitor and the second electrode of the second capacitor in the second conductive layer.

[0009] According to an exemplary embodiment of the present disclosure, it may also include: a fifth pattern and a sixth pattern, which respectively correspond to the first electrode of the third capacitor and the first electrode of the fourth capacitor in the first conductive layer; and a seventh pattern and an eighth pattern, which respectively correspond to the second electrode of the third capacitor and the second electrode of the fourth capacitor in the second conductive layer, the first pattern to the fourth pattern may be included in the first region, the fifth pattern to the eighth pattern may be included in the second region, the first pattern and the fifth pattern may be electrically connected to each other via a pattern spanning the third region, and the second pattern and the sixth pattern may be electrically connected to each other via a pattern spanning the third region.

[0010] According to an exemplary embodiment of the present disclosure, the device may further include a first inductor and a second inductor connected in series between a first electrode of the first capacitor and a first electrode of the second capacitor, and a node to which the first inductor and the second inductor are connected may be biased to a first voltage.

[0011] According to an exemplary embodiment of the present disclosure, the device may further include: a third inductor inductively coupled to the first inductor; and a fourth inductor inductively coupled to the second inductor.

[0012] According to an exemplary embodiment of the present disclosure, the at least one pattern may include: a first pattern and a second pattern, which respectively correspond to a first electrode of a first capacitor and a second electrode of a second capacitor in the first conductive layer; and a third pattern and a fourth pattern, which respectively correspond to a second electrode of the first capacitor and a second electrode of the second capacitor in the second conductive layer.

[0013] According to an exemplary embodiment of the present disclosure, the at least one pattern may include: a first pattern and a second pattern, which respectively correspond to a first inductor and a second inductor connected in series in a first conductive layer; and a third pattern and a fourth pattern, which respectively correspond to a third inductor and a fourth inductor connected in series in the second conductive layer and inductively coupled to the first inductor and the second inductor, respectively.

[0014] According to an exemplary embodiment of the present disclosure, a node to which the first inductor and the second inductor are connected may be biased to a first voltage, and a node to which the third inductor and the fourth inductor are connected may be biased to a second voltage.

[0015] According to an exemplary embodiment of the present disclosure, the at least one pattern may also include: a fifth pattern and a sixth pattern, which respectively correspond to a fifth inductor and a sixth inductor connected in series in the first conductive layer; and a seventh pattern and an eighth pattern, which respectively correspond to a seventh inductor and an eighth inductor connected in series in the second conductive layer and inductively coupled to the fifth inductor and the sixth inductor, respectively. The first pattern to the fourth pattern may be included in the first region, and the fifth pattern to the eighth pattern may be included in the second region. The first pattern and the fifth pattern may be electrically connected to each other via a pattern spanning the third region, and the second pattern and the sixth pattern may be electrically connected to each other via a pattern spanning the third region.

[0016] According to an exemplary embodiment of the present disclosure, a node to which the first inductor and the second inductor are connected may be biased to a first voltage, and a node to which the fifth inductor and the sixth inductor are connected may be biased to a second voltage.

[0017] According to an exemplary embodiment of the present disclosure, the third region may surround the second region on the substrate.

[0018] According to an exemplary embodiment of the present disclosure, the third region may include: a first doped region, which surrounds the second region on the substrate; a second doped region, which surrounds the first doped region on the substrate; and a third doped region, which surrounds the second doped region on the substrate, wherein the second doped region and the third doped region can be biased to a first potential and the second doped region can be electrically floating. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

[0020] Figure 1 Detailed description is given of an example of a high voltage gate drive circuit using a high voltage MOSFET level shifter according to an exemplary embodiment of the present disclosure.

[0021] Figure 2is a block diagram of an apparatus according to an exemplary embodiment of the present disclosure.

[0022] Figure 3 According to an exemplary embodiment of the present disclosure Figure 2 Timing diagram of the signal.

[0023] Figure 4A and Figure 4B is a circuit diagram of an example of a current isolator according to an exemplary embodiment of the present disclosure.

[0024] Figure 5A and Figure 5B is a circuit diagram of an example of a current isolator according to an exemplary embodiment of the present disclosure.

[0025] Figure 6 is a layout diagram of a device according to an exemplary embodiment of the present disclosure.

[0026] Fig. 7A and Figure 7B is a layout diagram of a device according to an exemplary embodiment of the present disclosure.

[0027] Fig. 8A and Figure 8B is a layout diagram of a device according to an exemplary embodiment of the present disclosure.

[0028] 9A to 9C is a circuit diagram of an example of a current isolator according to an exemplary embodiment of the present disclosure.

[0029] Fig. 10A and Fig. 10B is a circuit diagram of an example of a current isolator according to an exemplary embodiment of the present disclosure.

[0030] Fig.11 is a layout diagram of a device according to an exemplary embodiment of the present disclosure.

[0031] Fig.12 is a layout diagram of a device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Below, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to explain the present invention more completely to those of ordinary skill in the art. The present invention can be variously modified and can have various forms, so specific embodiments will be shown in the drawings and described in detail. However, this is not intended to limit the present invention to a specific disclosed form, and it should be understood that any changes, equivalents and substitutes included in the spirit and technical scope of the present invention are included. In the description of each of the accompanying drawings, similar reference numerals are used for similar components. In the accompanying drawings, for the sake of clarity of the present invention, the size of the structure is shown as being enlarged or reduced than the actual size.

[0033] The terms used in this application are only used to describe specific embodiments and are not intended to limit the present invention. Unless the context clearly indicates otherwise, singular expressions include plural expressions. As used herein, the terms "including" or "having" etc. are intended to indicate the presence of features, numbers, steps, operations, components, parts or combinations thereof described in the specification, and it should be understood that this does not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0034] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by ordinary technicians in the technical field to which the present invention belongs. Terms defined in commonly used dictionaries should be interpreted as having the same meaning as in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless clearly defined in this application.

[0035] In this specification, the X-axis direction and the Y-axis direction may be referred to as the first horizontal direction and the second horizontal direction, respectively, and the Z-axis direction may be referred to as the vertical direction. The plane formed by the X-axis and the Y-axis may be referred to as a horizontal plane, the component positioned in the +Z direction relative to other components may be referred to as being located above the other components, and the component positioned in the -Z direction relative to other components may be referred to as being located below the other components. In addition, the area of ​​a component may refer to the size occupied by the component in a plane parallel to the horizontal plane, and the width of a component may refer to the length in a direction perpendicular to the direction in which the component extends. The surface exposed in the +Z direction may be referred to as the top surface, the surface exposed in the -Z direction may be referred to as the bottom surface, and the surface exposed in the ±X or ±Y direction may be referred to as the side surface. For ease of description, only some layers may be shown in the accompanying drawings, and patterns made of conductive materials, such as patterns of conductive layers such as wiring layers, may be referred to as conductive patterns, or simply patterns.

[0036] Figure 1Schematic diagram of a high voltage gate drive circuit 10 for driving a switching device M1 operating at a high potential using an input pulse signal according to an exemplary embodiment of the present disclosure. A rising edge pulse generator 11 and a falling edge pulse generator 12 can provide rising / falling edge information of an input pulse signal to two high voltage MOSFETs MA and MB, and the two high voltage MOSFETs Ma and MB can transmit the signal information to a high voltage circuit area (HSDC). Therefore, two high voltage MOSFETs are used as level shifter devices. In the high voltage circuit area (HSDC), a pulse input detector 13 detects signals of two high voltage MOSFETs MA and MB connected to two resistors R1 and R2, respectively, and according to the detected signal, a setting signal S or a reset signal R is used to determine the state of the SR latch 14 to a logic level 1 or 0. Thus, the input pulse signal can be reproduced in the high voltage circuit area (HSDC), and the gate driver 15 is used to convert the signal into a signal (Vgate) suitable for driving the switching device M1 to drive the switching device.

[0037] For example, Figure 6 As shown, it can be realized on a single chip using semiconductor technology Figure 1 For example, the low voltage gate drive circuit can be Figure 6 The first integrated circuit IC1 is implemented, and the high voltage drive circuit can be Figure 6 The first integrated circuit IC1 and the second integrated circuit IC2 are implemented in the second integrated circuit IC2. The ring structure between the first integrated circuit IC1 and the second integrated circuit IC2 is used as a region for maintaining a high voltage between the two regions. This method may be referred to as an isolation method using a silicon junction, for example, a drive signal may be generated in a high voltage direction or a low voltage direction based on the grounding of the wafer.

[0038] Accordingly, since all circuits can be implemented on one wafer, manufacturing is easy and cost-effective. However, when a very high level of noise is applied to the high voltage circuit region (HSDC), the state of the SR latch 14 may be changed by the noise. Since the SR latch 14 is determined by the edge information of the input pulse signal, if an erroneous operation occurs in the SR latch 14, the error cannot be corrected before a new input pulse is applied. However, since the reference Figure 2 The gate drive circuit using a current isolator described later does not require a latch circuit and is therefore relatively free from these erroneous operations, making it possible to drive the switching device with high reliability and to freely set the switching voltage by isolating the drive. However, since the modulator circuit and demodulator circuit must also be insulated, they are implemented as separate chips, and the assembly process is complicated, resulting in high costs.

[0039] The switch voltage can be higher than the input as long as unidirectional control can be performed. Therefore, it may be advantageous to use junction isolation technology. Accordingly, as described later with reference to the accompanying drawings, by using junction isolation technology and using a current isolator as a level shifter, a high-voltage gate drive semiconductor chip that meets low cost and high reliability can be implemented on a single wafer.

[0040] Figure 2 1 is a block diagram of an example 100 of the present disclosure. Figure 2 As shown, the device 100 may include a transmitter 120, a galvanic isolator 140, and a receiver 160. The transmitter 120 and the receiver 160 may each have a different reference potential, and the galvanic isolator 140 may transmit a signal including information between the transmitter 120 and the receiver 160.

[0041] In some embodiments, the device 100 may be: an electronic device, such as a television (TV), a personal computer (PC), etc.; a means of transportation, such as a vehicle, a personal mobility (PM), etc.; or a component thereof. In some embodiments, the device 100 may correspond to a chip (or die) prepared by a semiconductor process. For example, the transmitter 120, the galvanic isolator 140, and the receiver 160 may be included in one chip prepared by dicing a wafer, and the chip may be packaged. As described later with reference to the accompanying drawings, galvanic isolation may be provided in one chip, so that galvanic isolation may be easily adopted in various applications.

[0042] The transmitter 120 may include a modulator 122. The modulator 122 may receive an input signal IN and generate a modulation signal MOD by modulating the input signal IN. In some embodiments, the modulator 122 may generate the modulation signal MOD from the input signal IN based on on / offkeying (OOK). The input signal IN may include information to be provided to the receiver 160 and may be generated inside the transmitter 120 or received from outside the transmitter 120. In some embodiments, the galvanic isolator 140 may include an inductor, and the modulator 122 may generate the modulation signal MOD using a resonant frequency based on the inductor included in the galvanic isolator 140. Reference will be made to Figure 3 Examples of the input signal IN and the modulation signal MOD will be described later.

[0043] The galvanic isolator 140 may receive the modulation signal MOD from the transmitter 120, and may generate a sensing signal MOD' derived from the modulation signal MOD. In some embodiments, the sensing signal MOD' may correspond to a signal attenuated from the modulation signal MOD. As described later with reference to the accompanying drawings, the galvanic isolator 140 may include at least one pattern, which may form a capacitor and / or an inductor.

[0044] The receiver 160 may include a demodulator 162. The demodulator 162 may receive the sensing signal MOD' and may generate an output signal OUT by demodulating the sensing signal MOD'. In some embodiments, the demodulator 162 may generate the output signal OUT from the sensing signal MOD' based on OOK. The output signal OUT may include information included in the input signal IN. In some embodiments, a driver for amplifying the output signal OUT may be included in the receiver 160, or may be included in the device 100 outside the receiver 160.

[0045] The transmitter 120 and the receiver 160 may each be included in an isolated region of the chip. For example, the transmitter 120 may be included as an integrated circuit in a first region, the receiver 160 may be included as an integrated circuit in a second region, and the first region and the second region may be spaced apart. Figure 6 As described later, the third region between the first region and the second region may have a structure for isolating the high voltage between the first region and the second region. The current isolator 140 may provide current separation between the separated first region and the second region, so that the transmitter 120 and the receiver 160 may be implemented on one chip. In this specification, it is assumed that the first region includes the transmitter 120 and the second region includes the receiver 160, but it should be noted that the first region may include the receiver 160 and the second region may include the transmitter 120.

[0046] Figure 3 According to an exemplary embodiment of the present disclosure Figure 2 The timing diagram of the signal. It should be noted that Figure 3 are examples only, and Figure 2 The signal is not limited to Figure 3 For ease of description, Figure 3 The delay between signals is ignored. Figure 2 right Figure 3 Provide explanation.

[0047] Reference Figure 3 , the input signal IN can be a pulse signal with an active state or an inactive state. Figure 3As shown, the input signal IN may be in an active state at time t1 and time t3, and may be in an inactive state at time t2 and time t4. The modulator 122 may generate a modulation signal MOD that oscillates in response to the activation of the input signal IN. For example, Figure 3 As shown, the modulation signal MOD may oscillate between time t1 and time t2, and may oscillate between time t3 and time t4.

[0048] The current isolator 140 can generate an oscillating sensing signal MOD' from the oscillating modulation signal MOD. Figure 3 As shown, the sensing signal MOD' may oscillate between time t1 and time t2, and may oscillate between time t3 and time t4. Figure 3 As shown, the magnitude (ie, amplitude or peak value) of the sensing signal MOD' may be smaller than the modulation signal MOD. The demodulator 162 may generate an activated output signal OUT in response to the oscillating sensing signal MOD'. Figure 3 As shown, the output signal OUT may be activated between time t1 and time t2 , and may be activated between time t3 and time t4 .

[0049] Figure 4A and Figure 4B is a circuit diagram of an example of a current isolator according to an exemplary embodiment of the present disclosure. For example, Figure 4A and Figure 4B The circuit diagram shows Figure 2 The equivalent circuit of the current isolator 140 is shown in FIG. Figure 4A and Figure 4B As shown, the current isolator 140 may include a capacitor having a high withstand voltage. Figure 4A and Figure 4B Duplicate content in the description.

[0050] In some embodiments, Figure 2 The modulation signal MOD and the sensing signal MOD' may be differential signals, and the current isolators 300a and 300b may each include terminals T11 and T12 for receiving the modulation signal MOD, and terminals T21 and T22 for outputting the sensing signal MOD'. In some embodiments, the modulation signal MOD may be applied to the terminals T21 and T22, and the sensing signal MOD' may be output to the terminals T11 and T12. Figure 4A and Figure 4B As shown, galvanic isolators 300a and 300b may have a balanced structure for differential signals.

[0051] Reference Figure 4A, the current isolator 300a may include a first capacitor C1 and a second capacitor C2. The first capacitor C1 may be connected between the terminals T11 and T21, and the second capacitor C2 may be connected between the terminals T12 and T22. The transmitting side and the receiving side may be isolated from each other by the first capacitor C1 and the second capacitor C2, and the first capacitor C1 and the second capacitor C2 may each have an insulation withstand voltage as required. In some embodiments, referring to Fig. 7A As described later, the first capacitor C1 and the second capacitor C2 may be formed by a pattern included in one of the first region and the second region.

[0052] Reference Figure 4B , the current isolator 300b may include first to fourth capacitors C1 to C4. The first capacitor C1 and the third capacitor C3 may be connected in series between the terminals T11 and T21, and the second capacitor C2 and the fourth capacitor C4 may be connected in series between the terminals T12 and T22. In some embodiments, referring to Figure 7B As described later, the first capacitor C1 and the second capacitor C2 may be formed in one of the first region and the second region, and the third capacitor C3 and the fourth capacitor C4 may be formed in the other of the first region and the second region. In addition, the first capacitor C1 and the third capacitor C3 may be connected to each other through a pattern crossing the third region, and the second capacitor C2 and the fourth capacitor C4 may also be connected to each other through a pattern crossing the third region. Figure 4A Compared with the galvanic isolator 300a, Figure 4B The current isolator 300b can provide a higher withstand voltage between the first region and the second region while occupying a larger area.

[0053] Figure 5A and Figure 5B is a circuit diagram of an example of a current isolator according to an exemplary embodiment of the present disclosure. For example, Figure 5A and Figure 5B The circuit diagram shows Figure 2 The equivalent circuit of the current isolator 140 is shown in FIG. Figure 5A and Figure 5B As shown, the current isolator 140 may include a transformer with a high withstand voltage. Figure 5A and Figure 5B Duplicate content in the description.

[0054] In some embodiments, Figure 2The modulation signal MOD and the sensing signal MOD' may be differential signals, and the current isolators 400a and 400b may each include terminals T11 and T12 for receiving the modulation signal MOD, and terminals T21 and T22 for outputting the sensing signal MOD'. In some embodiments, the modulation signal MOD may be applied to the terminals T21 and T22, and the sensing signal MOD' may be output to the terminals T11 and T12. Figure 5A and Figure 5B As shown, galvanic isolators 400a and 400b may have a balanced structure for differential signals.

[0055] Reference Figure 5A , the current isolator 400a may include first inductors L11 and L12 connected in series between terminals T11 and T12, and second inductors L21 and L22 connected in series between terminals T21 and T22. The first inductors L11 and L12 may be inductively coupled to the second inductors L21 and L22 with a coupling coefficient k. The transmitting side and the receiving side may be isolated from each other by the first inductors L11 and L12 and the second inductors L21 and L22 that are insulated from each other, and the first inductors L11 and L12 and the second inductors L21 and L22 may have an insulation withstand voltage that meets the requirements. In some embodiments, refer to Fig. 8A As described later, the first inductors L11 and L12 and the second inductors L21 and L22 may be formed of a pattern included in one of the first region and the second region.

[0056] Reference Figure 5B , the current isolator 400b may include a plurality of inductors. The first inductors L11 and L12 may be connected in series between the terminals T11 and T12. The second inductors L21 and L22 connected in series with each other and the third inductors L31 and L32 connected in series with each other may be connected in parallel with each other. The fourth inductors L41 and L42 may be connected in series between the terminals T21 and T22. Figure 5B As shown, the first inductors L11 and L12 may be inductively coupled to the second inductors L21 and L22 with a coupling coefficient k, and the fourth inductors L41 and L42 may be inductively coupled to the third inductors L31 and L32 with a coupling coefficient k. Figure 8B As described later, the first inductors L11 and L12 and the second inductors L21 and L22 may be formed in one of the first region and the second region, and the third inductors L31 and L31 and the fourth inductors L41 and L42 may be formed in the other of the first region and the second region. In addition, the second inductors L21 and L22 and the third inductors L31 and L32 may be connected to each other through a pattern spanning the third region. Figure 5A Compared with the galvanic isolator 400a, Figure 5BThe current isolator 400b can provide a higher withstand voltage between the first region and the second region while occupying a larger area.

[0057] Figure 6 FIG. 5 is a diagram of a layout 500 of a device according to an exemplary embodiment of the present disclosure. For example, Figure 6 The upper portion shows a plan view of the layout 500, Figure 6 The lower part of FIG. 5 shows a cross-sectional view of the layout 500 taken along the line X1′-X1. As described above with reference to the accompanying drawings, the layout 500 can be prepared by a semiconductor process and can be included in a chip (or die). For ease of description, Figure 6 Only some components are shown.

[0058] Reference Figure 6 , the layout 500 may include a first region 51, a second region 52, and a third region 53. The first region 51 and the second region 52 may be isolated by the third region 53, and the third region 53 may surround the second region 52 on the substrate. The first region 51 may include a first integrated circuit IC1, and the second region 52 may include a second integrated circuit IC2. For example, the first integrated circuit IC1 may include Figure 2 The transmitter 120, the second integrated circuit IC2 may include Figure 2 On the other hand, the first integrated circuit IC1 may include Figure 2 The receiver 160, the second integrated circuit IC2 may include Figure 2 In the following, it is assumed that the first integrated circuit IC1 includes Figure 2 The transmitter 120 and the second integrated circuit IC2 include Figure 2 The receiver 160 may be a receiver 160, but it should be noted that the exemplary embodiments of the present disclosure are not limited thereto.

[0059] The third region 53 may have a structure that provides a high withstand voltage between the first region 51 and the second region 52. Figure 6 As shown, the third region 53 may include: a first doping region R1, which surrounds the second region 52 on the substrate; a second doping region R2, which surrounds the first doping region R1 on the substrate; and a third doping region R3, which surrounds the second doping region R2 on the substrate. In some embodiments, the first doping region R1 to the third doping region R3 may have a p-type.

[0060] like Figure 6As shown, the first doping region R1 can isolate an n-type region on the substrate, and the third doping region R3 can also isolate an n-type region on the substrate. The second doping region R2 and the third doping region R3 can be electrically connected through vias and metal patterns, and can be biased to a first potential (e.g., ground potential). The second doping region R2 can have a wider width than the first doping region R1 and the third doping region R3. The first doping region R1 can be electrically floating. It should be noted that the third region 53 is not limited to Figure 6 shown.

[0061] Fig. 7A and Figure 7B is a layout diagram of a device according to an exemplary embodiment of the present disclosure. For example, Fig. 7A Shown with Figure 4A A plan view of a layout 600a corresponding to the current isolator 300a and a cross-sectional view taken along line X2-X2', Figure 7B Shown with Figure 4B The plan view of the layout 600b corresponding to the current isolator 300b and the cross-sectional view taken along the line X3-X3' are shown below. Figure 4A , Figure 4B and Figure 6 To describe Fig. 7A and Figure 7B .

[0062] Reference Fig. 7A , the layout 600a may include patterns for forming the current isolator 300a. The first pattern P1 and the second pattern P2 of the conductive layer Mx may correspond to the first electrode of the first capacitor C1 and the first electrode of the second capacitor C2, respectively, and the third pattern P3 and the fourth pattern P4 of the conductive layer Mx may correspond to the second electrode of the first capacitor C1 and the second electrode of the second capacitor C2, respectively. Fig. 7A As shown, the first pattern P1 and the third pattern P3 may be spaced apart by a first distance D1, and may form a first capacitor C1 having a withstand voltage depending on the first distance D1.

[0063] The fifth pattern P5 of the conductive layer Mx may be connected to the first pattern P1 and may extend across the third region 63. In addition, the sixth pattern P6 of the conductive layer Mx may be connected to the second pattern P2 and may extend across the third region 63. When the first pattern P1 to the fourth pattern P4 are formed in the first region, the third pattern P3 and the fourth pattern P4 may be electrically connected to the first integrated circuit of the first region, and the fifth pattern P5 and the sixth pattern P6 may be electrically connected to the second integrated circuit of the second region. On the other hand, when the first pattern P1 to the fourth pattern P4 are formed in the second region, the third pattern P3 and the fourth pattern P4 may be electrically connected to the second integrated circuit of the second region, and the fifth pattern P5 and the sixth pattern P6 may be electrically connected to the first integrated circuit of the first region. In some embodiments, the conductive layer Mx may correspond to a top wiring layer.

[0064] Reference Figure 7B , the layout 600b may include patterns for forming the current isolator 300b. The first pattern P1 and the second pattern P2 of the conductive layer Mx may correspond to the first electrode of the first capacitor C1 and the first electrode of the second capacitor C2, respectively, and the third pattern P3 and the fourth pattern P4 of the conductive layer Ma may correspond to the second electrode of the first capacitor C1 and the second electrode of the second capacitor C2, respectively. In addition, the fifth pattern P5 and the sixth pattern P6 of the conductive layer Mx may correspond to the first electrode of the third capacitor C3 and the first electrode of the fourth capacitor C4, respectively, and the seventh pattern P7 and the eighth pattern P8 of the conductive layer Ma may correspond to the second electrode of the third capacitor C3 and the second electrode of the fourth capacitor C4, respectively. Figure 7B As shown, the first pattern P1 and the third pattern P3 may be spaced apart by a first distance D1, and may form a first capacitor C1 having a withstand voltage depending on the first distance D1. The fifth pattern P5 and the seventh pattern P7 may be spaced apart by a first distance D1, and may form a third capacitor C3 having a withstand voltage depending on the first distance D1.

[0065] The ninth pattern P9 of the conductive layer Mx may be connected to the first pattern P1 and the fifth pattern P5, and may extend across the third region 63. In addition, the tenth pattern P10 of the conductive layer Mx may be connected to the second pattern P2 and the sixth pattern P6, and may extend across the third region 63. When the first pattern P1 to the fourth pattern P4 are formed in the first region, and the fifth pattern P5 to the eighth pattern P8 are formed in the second region, the third pattern P3 and the fourth pattern P4 may be electrically connected to the first integrated circuit of the first region, and the seventh pattern P7 and the eighth pattern P8 may be electrically connected to the second integrated circuit of the second region. On the other hand, when the first pattern P1 to the fourth pattern P4 are formed in the second region, and the fifth pattern P5 to the eighth pattern P8 are formed in the first region, the third pattern P3 and the fourth pattern P4 may be electrically connected to the second integrated circuit of the second region, and the seventh pattern P7 and the eighth pattern P8 may be electrically connected to the first integrated circuit of the first region. In some embodiments, the conductive layer Mx may correspond to a top wiring layer.

[0066] Fig. 8A and Figure 8B is a layout diagram of a device according to an exemplary embodiment of the present disclosure. For example, Fig. 8A Shown with Figure 5A A plan view of a layout 700a corresponding to the current isolator 400a and a cross-sectional view taken along line X4-X4', Figure 8B Shown with Figure 5B The plan view of the layout 700b corresponding to the current isolator 400b and the cross-sectional view taken along the line X5-X5' are shown below. Figure 5A , Figure 5B and Figure 6 To describe Fig. 8A and Figure 8B .

[0067] Reference Fig. 8A , the layout 700a may include patterns for forming the current isolator 400a. The first pattern P1 and the second pattern P2 of the conductive layer Mx may correspond to first inductors L11 and L12 connected in series, respectively, and the third pattern P3 and the fourth pattern P4 of the conductive layer Ma may correspond to second inductors L21 and L22 connected in series, respectively. Fig. 8A As shown, the first pattern P1 and the third pattern P3 may overlap in the vertical direction, so the first inductor L11 and the second inductor L21 may be inductively coupled. The first pattern P1 and the seventh pattern P7 may be spaced apart by a second distance D2, and the first inductor L11 and the second inductor L21 may have a withstand voltage depending on the second distance D2.

[0068] The fifth pattern P5 of the conductive layer My may be connected to the first pattern P1 through a via and may extend across the third region 73. The sixth pattern P6 of the conductive layer My may be connected to the second pattern P2 through a via and may extend across the third region 73. The seventh pattern P7 of the conductive layer Mb may be connected to the third pattern P3 through a via, and the eighth pattern P8 of the conductive layer Mb may be connected to the fourth pattern P4 through a via. When the first pattern P1 to the fourth pattern P4 are formed in the first region, the seventh pattern P7 and the eighth pattern P8 may be electrically connected to the first integrated circuit of the first region, and the fifth pattern P5 and the sixth pattern P6 may be electrically connected to the second integrated circuit of the second region. On the other hand, when the first pattern P1 to the fourth pattern P4 are formed in the second region, the seventh pattern P7 and the eighth pattern P8 may be electrically connected to the second integrated circuit of the second region, and the fifth pattern P5 and the sixth pattern P6 may be electrically connected to the first integrated circuit of the first region.

[0069] Reference Figure 8B , the layout 700b may include patterns for forming the current isolator 400b. The first pattern P1 and the second pattern P2 of the conductive layer Mx may correspond to the first inductors L11 and L12 connected in series, respectively, and the third pattern P3 and the fourth pattern P4 of the conductive layer Ma may correspond to the second inductors L21 and L22 connected in series, respectively. In addition, the fifth pattern P5 and the sixth pattern P6 of the conductive layer Mx may correspond to the third inductors L31 and L32 connected in series, respectively, and the seventh pattern P7 and the eighth pattern P8 of the conductive layer Ma may correspond to the fourth inductors L41 and L42 connected in series, respectively. Figure 8B As shown, the first pattern P1 and the third pattern P3 may overlap in the vertical direction, so the first inductor L11 and the second inductor L21 may be inductively coupled. In addition, the fifth pattern P5 and the seventh pattern P7 may overlap in the vertical direction, so the third inductor L31 and the fourth inductor L41 may be inductively coupled. The first pattern P1 and the eleventh pattern P11 may be spaced apart by a second distance D2, and the first inductor L11 and the second inductor L12 may have a withstand voltage depending on the second distance D2. In addition, the fifth pattern P5 and the seventh pattern P7 may be spaced apart by a second distance D2, and the third inductor L31 and the fourth inductor L41 may have a withstand voltage depending on the second distance D2.

[0070] The ninth pattern P9 of the conductive layer My may be connected to the first pattern P1 and the fifth pattern P5 through a via hole, and may extend across the third region 73. The tenth pattern P10 of the conductive layer My may be connected to the second pattern P2 and the sixth pattern P6 through a via hole, and may extend across the third region 73. The eleventh pattern P11 of the conductive layer Mb may be connected to the third pattern P3 through a via hole, and the twelfth pattern P12 of the conductive layer Mb may be connected to the fourth pattern P4 through a via hole. The thirteenth pattern P13 of the conductive layer Mb may be connected to the seventh pattern P7 through a via hole, and the fourteenth pattern P14 of the conductive layer Mb may be connected to the eighth pattern P8 through a via hole. When the first pattern P1 to the fourth pattern P4 are formed in the first region, and the fifth pattern P5 to the eighth pattern P8 are formed in the second region, the eleventh pattern P11 and the twelfth pattern P12 may be electrically connected to the first integrated circuit of the first region, and the thirteenth pattern P13 and the fourteenth pattern P14 may be electrically connected to the second integrated circuit of the second region. On the other hand, when the first to fourth patterns P1 to P4 are formed in the second area and the fifth to eighth patterns P5 to P8 are formed in the first area, the eleventh pattern P11 and the twelfth pattern P12 can be electrically connected to the second integrated circuit of the second area, and the thirteenth pattern P13 and the fourteenth pattern P14 can be electrically connected to the first integrated circuit of the first area.

[0071] 9A to 9C is a circuit diagram of an example of a current isolator according to an exemplary embodiment of the present disclosure. For example, 9A to 9C The circuit diagram shows Figure 2 The equivalent circuit of the current isolator 140 is shown in FIG. 9A to 9C As shown, the current isolators 800a, 800b and 800c may each include a first capacitor C1 and a second capacitor C2 having a high withstand voltage. 9A to 9C Duplicate content in the description.

[0072] If the first capacitor C1 and the second capacitor C2 have high capacitance to improve the transmission characteristics of the signal, an erroneous operation may occur due to the first capacitor C1 and the second capacitor C2. Figure 2 When a large voltage change (i.e., high dv / dt) occurs in the receiver 160 and the driver operating based on the output of the receiver 160, a large current may be transmitted to the first capacitor C1 and / or the second capacitor C2. Figure 2 This may cause circuits included in the transmitter 120 to erroneously operate or even be destroyed.

[0073] Reference Fig. 9A, the current isolator 800a may include first inductors L11 and L12 connected in series between terminals T11 and T12, and second inductors L21 and L22 connected in series between terminals T21 and T22. In addition, the node to which the first inductors L11 and L12 are connected may be connected to terminal T13, and the node to which the second inductors L21 and L22 are connected may be connected to terminal T23. Terminals T13 and T23 may be referred to as center tap terminals. Terminals T13 and T23 may be connected to low impedance nodes, respectively. For example, terminal T13 may be biased to a first voltage, and terminal T23 may be biased to a second voltage. Therefore, due to the large change in the second voltage, the current flowing in through terminal T23 may be output through terminal T13, and an excessive amount of current may be prevented from flowing into transmitter 120.

[0074] Reference Fig. 9B , the current isolator 800b may include a first capacitor C1, a second capacitor C2, first inductors L11 and L12, second inductors L21 and L22, third inductors L31 and L32, and fourth inductors L41 and L42. The first inductors L11 and L12 may be connected in series between terminals T11 and T12, and may be inductively coupled to the second inductors L21 and L22 with a coupling coefficient k. The second inductors L21 and L22 may be connected in series between the first capacitor C1 and the second capacitor C2, and the node to which the second inductors L21 and L22 are connected may be connected to the terminal T13. The third inductors L31 and L32 may be connected in series between the first capacitor C1 and the second capacitor C2, and the node to which the second inductors L31 and L32 are connected may be connected to the terminal T23. The fourth inductor L41 and L42 can be connected in series between the terminals T21 and T22, and can be inductively coupled to the third inductor L31 and L32 with a coupling coefficient k. The terminals T13 and T23 can be connected to the low impedance node, respectively. For example, the terminal T13 can be biased to a first voltage, and the terminal T23 can be biased to a second voltage. Therefore, due to the large change of the second voltage, the current flowing in through the terminal T23 can be output through the terminal T13, and excessive current can be prevented from flowing into the transmitter 120.

[0075] Reference Fig. 9C, the current isolator 800c may include a first capacitor C1, a second capacitor C2, a first inductor L11 and L12, a second inductor L21 and L22, and a third inductor L31 and L32. The first inductor L11 and L12 may be connected in series between terminals T11 and T12, and the node to which the first inductors L11 and L12 are connected may be connected to terminal T13. The second inductors L21 and L22 may be inductively coupled to the third inductors L31 and L32 with a coupling coefficient k, and the node to which the second inductors L21 and L22 are connected may be connected to terminal T23. The third inductor L31 and L32 may be connected in series between terminals T21 and T22. Terminals T13 and T23 may be connected to low impedance nodes, respectively. For example, terminal T13 may be biased to a first voltage, and terminal T23 may be biased to a second voltage. Therefore, due to the large change in the second voltage, the current flowing in through the terminal T23 can be output through the terminal T13, and an excessive current can be prevented from flowing into the transmitter 120. In some embodiments, the transmitter 120 can be connected to the terminals T21 and T22, and the receiver 160 can be connected to the terminals T11 and T12.

[0076] Fig. 10A and Fig. 10B is a circuit diagram of an example of a current isolator according to an exemplary embodiment of the present disclosure. For example, Fig. 10A and Fig. 10B The circuit diagram shows Figure 2 The equivalent circuit of the current isolator 140 is shown in FIG. Fig. 10A and Fig. 10B As shown, the current isolators 900a and 900b may each include an inductor that is inductively coupled to each other. Fig. 10A and Fig. 10B Duplicate content in the description.

[0077] Reference Fig. 10A , the current isolator 900a may include first inductors L11 and L12 connected in series between terminals T11 and T12, and second inductors L21 and L22 connected in series between terminals T21 and T22. The first inductors L11 and L12 may be inductively coupled to the second inductors L21 and L22 with a coupling coefficient k. Fig. 10A As shown, the node to which the first inductors L11 and L12 are connected can be connected to the terminal T13, and the node to which the second inductors L21 and L22 are connected can be connected to the terminal T23. The terminals T13 and T23 can be connected to low impedance nodes, respectively. For example, the terminal T13 can be biased to a first voltage, and the terminal T23 can be biased to a second voltage. Therefore, due to the large change in the second voltage, the current flowing in through the terminal T23 can be output through the terminal T13, and an excessive current can be prevented from flowing into the transmitter 120.

[0078] Reference Fig. 10B , the current isolator 900b may include first inductors L11 and L12, second inductors L21 and L22, third inductors L31 and L32, and fourth inductors L41 and L42. The first inductors L11 and L12 may be connected in series between terminals T11 and T12, and may be inductively coupled to the second inductors L21 and L22 with a coupling coefficient k. The second inductors L21 and L22 may be connected in parallel with the third inductors L31 and L32, and the third inductors L31 and L32 may be inductively coupled to the fourth inductors L41 and L42 with a coupling coefficient k. The fourth inductors L41 and L42 may be connected in series between terminals T21 and T22. Fig. 10B As shown, the node to which the first inductors L11 and L12 are connected can be connected to the terminal T13, and the node to which the fourth inductors L41 and L42 are connected can be connected to the terminal T23. The terminals T13 and T23 can be connected to the low impedance nodes, respectively. For example, the terminal T13 can be biased to the first voltage, and the terminal T23 can be biased to the second voltage. Therefore, due to the large change of the second voltage, the current flowing in through the terminal T23 can be output through the terminal T13, and the excessive current can be prevented from flowing into the transmitter 120.

[0079] Fig.11 FIG. 1000 is a diagram of a layout of a device according to an exemplary embodiment of the present disclosure. For example, Fig.11 To correspond to Fig. 9A and Fig. 9C The first inductors L11 and L12 or Fig. 9A The plan view of the layout 1000 of the second inductor L21 and L22 is shown below. Fig. 9A right Fig.11 Provide explanation.

[0080] Reference Fig.11 , the layout 1000 may include patterns for forming first inductors L11 and L12 or second inductors L21 and L22 of the current isolator 800a. The first pattern P1 and the second pattern P2 of the conductive layer Mx may correspond to the first inductors L11 and L12 connected in series with each other or the second inductors L21 and L22 connected in series with each other, respectively. The third pattern P3 of the conductive layer Mx may be connected to the first pattern P1 and the second pattern P2, and may correspond to the terminal T13 or T23. The fourth pattern P4 of the conductive layer Mb may be connected to the first pattern P1 of the conductive layer Mx, and may be connected to the first capacitor C1 and the terminal T11. The fifth pattern P5 of the conductive layer Mb may be connected to the second pattern P2 of the conductive layer Mx, and may be connected to the second capacitor C2 and the terminal T12.

[0081] Fig.12FIG. 1100 is a diagram of a layout of a device according to an exemplary embodiment of the present disclosure. For example, Fig.12 For the corresponding Fig. 9B , Fig. 10A and Fig. 10B The first inductors L11 and L12 and the second inductors L21 and L22, Fig. 9B and Fig. 10B The third inductors L31 and L32 and the fourth inductors L41 and L42, or Fig. 9C The plan view of the layout 1100 of the second inductor L21 and L22 and the third inductor L31 and L32 is shown below. Fig. 10A right Fig.12 Provide explanation.

[0082] Reference Fig.12 , the layout 1100 may include patterns for forming first inductors L11 and L12 and second inductors L21 and L22 of the current isolator 900a. The first pattern P1 and the second pattern P2 of the conductive layer Mx may correspond to the first inductors L11 and L12 connected in series with each other, respectively. The third pattern P3 and the fourth pattern P4 of the conductive layer Ma may correspond to the second inductors L21 and L22 connected in series with each other, respectively. The fifth pattern P5 of the conductive layer Mx may be connected to the first pattern P1 and the second pattern P2, and may correspond to the terminal T13. The sixth pattern P6 of the conductive layer Ma may be connected to the third pattern P3 and the fourth pattern P4, and may correspond to the terminal T23. The seventh pattern P7 of the conductive layer My may be connected to the first pattern P1, and may correspond to the terminal T11. The eighth pattern P8 of the conductive layer My may be connected to the second pattern P2, and may correspond to the terminal T12. The ninth pattern P9 of the conductive layer Mb may be connected to the third pattern P3, and may correspond to the terminal T21. The tenth pattern P10 of the conductive layer Mb may be connected to the fourth pattern P4 and may correspond to the terminal T22.

[0083] According to the device of the exemplary embodiment of the present disclosure, when a high-voltage gate drive circuit is implemented with one chip, a current isolator can be used as a level shifter for signal transmission, and the problem of erroneous operation can be suppressed compared with a level shifter circuit using a high-voltage MOSFET, thereby being easily applicable to various high-power applications requiring high reliability.

[0084] In addition, according to the device of the exemplary embodiment of the present disclosure, erroneous operation due to a sudden change in a signal can be prevented, so that galvanic isolation with high reliability can be provided.

[0085] The effects that can be obtained from the exemplary embodiments of the present disclosure are not limited to the above effects, and those skilled in the art can clearly derive and understand other effects that are not mentioned from the following description to which the exemplary embodiments of the present disclosure belong. That is, those skilled in the art can also obtain unexpected effects produced by implementing the exemplary embodiments of the present disclosure from the exemplary embodiments of the present disclosure.

[0086] As described above, exemplary embodiments have been disclosed in the drawings and the specification. Although specific terms are used in this specification to describe the embodiments, this is only for the purpose of explaining the technical idea of ​​the present disclosure, and is not intended to limit the meaning or scope of the present disclosure set forth in the claims. It will be understood by those skilled in the art that various modifications and other equivalent embodiments may be made therefrom. Therefore, the true technical protection scope of the present disclosure should be determined by the technical ideas of the attached patent claims.

[0087] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to these embodiments, but is limited to the broader scope of the appended claims, and various obvious modifications and equivalent arrangements will be apparent to those of ordinary skill in the art.

Claims

1. A device, characterized in that: include: a first region including a first integrated circuit on a substrate; a second region comprising a second integrated circuit on the substrate; as well as a third region located between the first region and the second region on the substrate, At least one of the first region and the second region includes at least one pattern, and the pattern provides current isolation between the first integrated circuit and the second integrated circuit on the substrate.

2. The device according to claim 1, characterized in that The at least one pattern comprises: a first pattern and a second pattern corresponding to a first electrode of a first capacitor and a first electrode of a second capacitor in the first conductive layer, respectively; and A third pattern and a fourth pattern respectively correspond to the second electrode of the first capacitor and the second electrode of the second capacitor in the second conductive layer.

3. The device according to claim 2, characterized in that The at least one pattern further comprises: a fifth pattern and a sixth pattern corresponding to a first electrode of a third capacitor and a first electrode of a fourth capacitor in the first conductive layer, respectively; and a seventh pattern and an eighth pattern, which correspond to the second electrode of the third capacitor and the second electrode of the fourth capacitor in the second conductive layer, respectively, wherein the first pattern to the fourth pattern are included in the first region, The fifth to eighth patterns are included in the second region, The first pattern and the fifth pattern are electrically connected to each other through a pattern spanning the third region, The second pattern and the sixth pattern are electrically connected to each other through a pattern crossing the third region.

4. The device according to claim 2, characterized in that Also includes: a first inductor and a second inductor connected in series between the first electrode of the first capacitor and the first electrode of the second capacitor, A node to which the first inductor and the second inductor are connected is biased to a first voltage.

5. The device according to claim 4, characterized in that Also includes: a third inductor inductively coupled to the first inductor; as well as The fourth inductor is inductively coupled to the second inductor.

6. The device according to claim 1, characterized in that The at least one pattern comprises: a first pattern and a second pattern corresponding to a first electrode of a first capacitor and a second electrode of a second capacitor in the first conductive layer, respectively; and A third pattern and a fourth pattern respectively correspond to the second electrode of the first capacitor and the second electrode of the second capacitor in the second conductive layer.

7. The device according to claim 1, characterized in that The at least one pattern comprises: a first pattern and a second pattern corresponding to a first inductor and a second inductor connected in series in a first conductive layer, respectively; and The third pattern and the fourth pattern respectively correspond to a third inductor and a fourth inductor which are connected in series in the second conductive layer and are inductively coupled to the first inductor and the second inductor, respectively.

8. The device according to claim 7, characterized in that A node to which the first inductor and the second inductor are connected is biased to a first voltage, A node to which the third inductor and the fourth inductor are connected is biased to a second voltage.

9. The device according to claim 7, characterized in that The at least one pattern further comprises: a fifth pattern and a sixth pattern, which correspond to a fifth inductor and a sixth inductor connected in series in the first conductive layer, respectively; and a seventh pattern and an eighth pattern, which correspond to a seventh inductor and an eighth inductor respectively connected in series in the second conductive layer and inductively coupled to the fifth inductor and the sixth inductor respectively, The first to fourth patterns are included in the first region, The fifth to eighth patterns are included in the second region, The first pattern and the fifth pattern are electrically connected to each other through a pattern spanning the third region, The second pattern and the sixth pattern are electrically connected to each other through a pattern crossing the third region.

10. The device according to claim 9, characterized in that A node to which the first inductor and the second inductor are connected is biased to a first voltage, A node to which the fifth inductor and the sixth inductor are connected is biased to a second voltage.

11. The device according to claim 1, characterized in that The third region surrounds the second region on the substrate.

12. The device according to claim 11, characterized in that The third area includes: a first doped region surrounding the second region on the substrate; A second doped region surrounding the first doped region on the substrate; and A third doped region surrounding the second doped region on the substrate; and The second doping region and the third doping region are biased to a first potential, The second doped region is electrically floating.

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