Chip frequency control circuit, BUCK power supply and chip frequency control method

Abstract

The invention discloses a chip frequency control circuit, a BUCK power supply and a chip frequency control method, which are applied to the technical field of power electronics. The input end of the frequency reduction control unit is connected with an output voltage feedback signal of the BUCK power supply, the output end of the frequency reduction control unit is connected with the control end of the clock oscillator, the frequency reduction control unit is used for adjusting the frequency of a clock signal output by the clock oscillator according to the output voltage feedback signal, and the size of the output voltage feedback signal is in negative correlation with the frequency of the clock signal. The clock oscillator outputs a clock signal to the switching tube control unit, and the switching tube control unit drives the voltage to control the switching tube to be switched on according to the clock signal. Due to the fact that the circuit directly changes the clock signal frequency of the chip clock oscillator, FB voltages corresponding to the turn-on position and the turn-off position of the voltage control switch tube are relatively fixed, the difference of duty ratios of different periods is small, finally obtained inductive current pulse amplitudes are evenly distributed, and therefore linear smooth adjustment of the frequency is achieved.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a chip frequency control circuit, a BUCK power supply, and a chip frequency control method. Background Art

[0002] Figure 1 is a schematic diagram of the structure of a traditional chip frequency control circuit; As shown in Figure 1, the current frequency reduction control mode is a passive frequency reduction mode, which is characterized by the fact that the frequency of the clock signal CLK output by the clock oscillator OSC remains unchanged. When the frequency is a constant maximum frequency (that is, not in frequency reduction mode), the falling edge of the CLK pulse will set the output of the D flip-flop DFF to a high level, and provide a conduction signal to the MOS tube Q0 through the driver circuit Driver; and as long as the inductor current is in the resistor R CS When the voltage drop on the output voltage reaches the threshold voltage Vlimit, the MOS tube Q0 will be turned off. When the load decreases, the feedback signal FB (i.e., the output voltage feedback signal) generated by the output voltage increases, and the FB voltage is proportional to the first reference voltage V REF1 The output signal amplified by the operational amplifier EA1 is connected to the non-inverting input terminal of the feedback voltage comparator COMP1. The output signal of EA1 is connected to the second reference voltage V REF2 The frequency reduction signal generated after comparison is set to a high level, which will reset the D flip-flop DFF and make the output of the driver circuit Driver start to be set to a low level, thereby forcibly turning off the MOS tube Q0. At this time, the frequency reduction signal is generally maintained across the cycle until the FB voltage drops to V REF1 hour.

[0003] It can be seen that in the traditional solution, the operating frequency will decrease in the form of skipping cycles, and the frequency mutation will cause the inductor current to be unstable; and the FB signal has voltage ripples, which causes the width of the frequency reduction signal output by the feedback voltage comparator COMP1 to be inconsistent in different cycles, and the MOS tube Q0 shutdown time may be advanced or delayed. The manifestation is that the MOS tube Q0 conduction time is not fixed, and the inductor current is unstable with highs and lows.

[0004] It can be seen that how to achieve smooth linear frequency reduction and avoid the situation where the inductor current is unstable due to frequency mutation is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0005] The purpose of this application is to provide a chip frequency control circuit, a BUCK power supply and a chip frequency control method to solve the problem of unstable inductor current caused by frequency mutation when the traditional solution enters the frequency reduction mode.

[0006] In order to solve the above technical problems, the present application provides a chip frequency control circuit, including: a frequency reduction control unit, a clock oscillator, a switch tube control unit and a voltage-controlled switch tube;

[0007] The input end of the frequency reduction control unit is connected to the output voltage feedback signal of the BUCK power supply, and the output end of the frequency reduction control unit is connected to the control end of the clock oscillator, and is used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal, wherein the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal;

[0008] The output end of the clock oscillator is connected to the switch tube control unit to output the clock signal to the switch tube control unit, and the switch tube control unit is connected to the switch to drive the voltage-controlled switch tube to conduct according to the clock signal.

[0009] Preferably, it further comprises: a first operational amplifier;

[0010] The first input terminal of the first operational amplifier is connected to the output voltage feedback signal of the BUCK power supply, and the second input terminal of the first operational amplifier is connected to the first reference voltage; the output terminal of the first operational amplifier is connected to the input terminal of the frequency reduction control unit, so as to output the amplified output voltage feedback signal to the frequency reduction control unit.

[0011] Preferably, the frequency reduction control unit includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a first fixed current source and a second fixed current source;

[0012] The sources of the first PMOS tube and the second PMOS tube are both connected to a voltage source, and the gates and drains of the first PMOS tube and the second PMOS tube are connected to each other;

[0013] The common end of the gate and drain of the first PMOS tube is connected to the drain of the first NMOS tube, and the gate of the first NMOS tube is connected to the output end of the first operational amplifier;

[0014] The common end of the gate and the drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the gate of the second PMOS tube is connected to the second reference voltage;

[0015] The source of the first NMOS tube, the source of the second NMOS tube, the positive electrode of the first fixed current source and the gate of the third PMOS tube are connected to each other; the negative electrode of the first fixed current source and the drain of the third PMOS tube are grounded;

[0016] The positive electrode of the second fixed current source is connected to a voltage source; the negative electrode of the second fixed current source and the source of the third PMOS tube are connected to each other, and the common end of the connection is connected to the control end of the clock oscillator as the output end of the frequency reduction control unit.

[0017] Preferably, the clock oscillator comprises: a variable current source, a first capacitor, a switch, and an internal comparator;

[0018] The positive electrode of the variable current source is connected to a voltage source; the negative electrode of the variable current source, the first end of the first capacitor, the first end of the switch and the non-inverting input end of the internal comparator are connected to each other; the second end of the first capacitor and the second end of the switch are grounded;

[0019] The inverting input terminal of the internal comparator is connected to the output terminal of the frequency reduction control unit; the output terminal of the internal comparator is connected to the control terminal of the switch; wherein the output terminal of the internal comparator serves as the output terminal of the clock oscillator to output the clock signal.

[0020] Preferably, the variable current source is specifically a voltage-controlled current source;

[0021] The control end of the voltage-controlled current source is connected to the output end of the frequency reduction control unit.

[0022] Preferably, the switch tube control unit comprises: a D trigger and a drive circuit;

[0023] The clock oscillator is connected to the first input terminal of the D flip-flop, and is used to output the clock signal to the D flip-flop so as to set the output of the D flip-flop to a high level when the falling edge of the clock signal arrives;

[0024] The output end of the D flip-flop is connected to the input end of the driving circuit, and the output end of the driving circuit is connected to the voltage-controlled switch tube. After the D flip-flop outputs a high level, the driving circuit drives the voltage-controlled switch tube to turn on.

[0025] Preferably, it also includes: a current sampling circuit for obtaining a peak current sampling signal;

[0026] The current sampling circuit is connected to the second input terminal of the D flip-flop and is used to reset the D flip-flop according to the peak current sampling signal and the amplified output voltage feedback signal to turn off the voltage-controlled switch tube.

[0027] Preferably, the current sampling circuit comprises: a current sampling resistor, an adder, and an inductor current peak comparator;

[0028] The current sampling resistor and the voltage control switch tube are connected in series in the output loop, and the first end of the current sampling resistor is grounded;

[0029] The first input end of the adder is connected to the second end of the current sampling resistor; the second input end of the adder is connected to the output end of the first operational amplifier; the output end of the adder is connected to the first input end of the inductor current peak comparator;

[0030] The second input terminal of the inductor current peak comparator is connected to the threshold voltage, and the output terminal of the inductor current peak comparator is connected to the second input terminal of the D flip-flop, so as to output a signal to reset the D flip-flop after the output of the adder is greater than the threshold voltage.

[0031] In order to solve the above technical problems, the present application also provides a BUCK power supply, including the above chip frequency control circuit.

[0032] In order to solve the above technical problems, the present application also provides a chip frequency control method, which is applied to the above frequency reduction control unit; the method comprises:

[0033] Get the output voltage feedback signal of the BUCK power supply;

[0034] The frequency of the clock signal output by the clock oscillator is adjusted according to the output voltage feedback signal, wherein the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal.

[0035] A chip frequency control circuit provided in the present application includes: a frequency reduction control unit, a clock oscillator, a switch tube control unit and a voltage-controlled switch tube. The input end of the frequency reduction control unit is connected to the output voltage feedback signal of the BUCK power supply, and the output end of the frequency reduction control unit is connected to the control end of the clock oscillator, which is used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal, wherein the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal. It can be seen that this scheme is an active frequency reduction method, which is characterized in that the clock signal frequency of the clock oscillator is variable. The output end of the clock oscillator is connected to the switch tube control unit to output the clock signal to the switch tube control unit, and the switch tube control unit is connected to the switch to drive the voltage control switch tube to conduct according to the clock signal. Since this circuit directly changes the clock signal frequency of the chip clock oscillator, the FB voltage corresponding to the opening and closing of the voltage-controlled switch tube is relatively fixed, the duty cycle difference of different cycles is small, and the amplitude of the inductor current pulse obtained at the end is evenly distributed, thereby realizing linear and smooth frequency regulation.

[0036] The present application also provides a BUCK power supply and a chip frequency control method, which corresponds to the above-mentioned chip frequency control circuit, and thus has the same beneficial effects as the above-mentioned chip frequency control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] FIG1 is a schematic diagram of the structure of a conventional chip frequency control circuit;

[0039] FIG2 is a schematic diagram of the inductor current and frequency curve of a common BUCK power supply;

[0040] FIG3 is a schematic diagram of the operation of a conventional chip frequency control circuit in continuous mode;

[0041] FIG4 is a schematic diagram of an application circuit of a common high-voltage BUCK power supply;

[0042] FIG5 is a schematic diagram of a simulation waveform of a conventional Skip pulse frequency reduction method;

[0043] FIG6 is a schematic diagram of the structure of a chip frequency control circuit provided in an embodiment of the present application;

[0044] FIG7 is a schematic diagram of a specific circuit structure of a frequency reduction control unit and a clock oscillator provided in an embodiment of the present application;

[0045] FIG8 is a schematic diagram of a simulation waveform of a novel chip frequency control circuit in a frequency reduction region provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0047] The core of this application is to provide a chip frequency control circuit, a BUCK power supply and a chip frequency control method to solve the problem of unstable inductor current caused by frequency mutation when the traditional solution enters the frequency reduction mode.

[0048] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0049] BUCK power supply, also known as step-down converter, is a DC-DC conversion circuit whose output voltage is lower than the input voltage. In this circuit, the input current is pulsating, while the output current is continuous. The core component of the Buck power supply is the inductor, which is responsible for converting the input voltage into the output voltage. The voltage-controlled switch tube is the control element, which adjusts the output voltage by changing its on and off states. Figure 2 is a schematic diagram of the inductor current and frequency curve of a common BUCK power supply; the output current Iout represents the load change, and the smaller the Iout, the smaller the load. As shown in Figure 2, as the load decreases, the current I PK Will be reduced to I PK_MIN , then continue to reduce I PK , switching frequency F SW The frequency will start to decrease from the constant maximum frequency, that is, it will enter the frequency reduction mode. The frequency reduction mode is one of the important means to reduce switching losses and improve power efficiency.

[0050] Taking the chip frequency control circuit of FIG1 as an example, FIG3 is a schematic diagram of the operation of the conventional chip frequency control circuit in continuous mode; as shown in FIG3, the built-in clock oscillator OSC provides a fixed-frequency clock signal CLK. When the falling edge of CLK appears, the level of the driver circuit Driver of the driving voltage control switch tube (i.e., MOS tube Q0) is set to high through the output of the D flip-flop. At this time, Q0 is turned on, and the inductor current I IN_DUCTANCE When the frequency is the highest constant frequency, as long as the inductor current flows through the resistor R CS The voltage drop across the LIMIT When (i.e. the inductor current reaches I PK_LIMIT ), Q0 will be turned off.

[0051] When the load starts to decrease from full load, the switching frequency needs to decrease from the constant maximum frequency to reduce the loss of the switching device. Its working mechanism is to use the amplified output voltage feedback signal FB and the fixed second reference voltage V REF2 As the input of the feedback voltage comparator COMP1, the output level of the feedback voltage comparator COMP1 is used as the frequency reduction signal. When the frequency reduction signal is high, the D flip-flop DFF will be forced to clear. After clearing, the output of the D flip-flop is low, and the drive of the MOS tube Q0 will be turned off until the output voltage starts to drop. After the frequency reduction signal turns to a low level, the D flip-flop will output a high level generated by the falling edge of CLK. At this time, the drive of the MOS tube Q0 is reversed to a high level again. When the load continues to decrease, the amplified FB voltage is higher than the second reference voltage V REF2 The time that the frequency reduction signal is at a high level will continue to increase, thereby achieving a continuous decrease in frequency.

[0052] Figure 4 is a schematic diagram of the application circuit of a common high-voltage BUCK power supply; as shown in Figure 4, the FB signal and the output capacitor do not share a common ground. The FB voltage comes from the resistor divider of the sampling capacitor C5. Since the time constant of the C5 capacitor is different from the time constant of the resistor R1+R2 compared to the time constant of the output capacitor C3*load resistor, there is a difference in the voltage ripple on the two capacitors, so the FB signal can only approximately represent the output voltage signal. The circuit shown in Figure 1 adopts the Skip pulse mode. The clock pulse frequency of the clock oscillator OSC is fixed. When the frequency reduction circuit starts working, the frequency reduction is achieved by shielding part of the drive pulse generated by the clock signal, that is, reducing the drive pulse. And the more frequently the frequency shielding signal appears and the longer the duration of each time, the more the switching frequency will drop.

[0053] In the frequency reduction stage, the shutdown signal of MOS tube Q0 is generated by R CS The voltage drop and the frequency reduction signal are jointly determined. The FB signal is generated by the voltage obtained by charging the sampling capacitor C5 through the inductor L2 through the diode D2 during the MOS tube Q0 off period, and then through the voltage divider resistors R1 and R2. Since the FB signal and the output voltage signal do not share the same ground, this signal can only indirectly reflect the output voltage signal. The FB signal has voltage ripples, which causes the width of the frequency reduction signal output by the feedback voltage comparator COMP1 to be inconsistent in different cycles, and the MOS tube Q0 off time may be advanced or delayed. The manifestation is that the MOS tube Q0 conduction time is not fixed, and the inductor current is unstable with highs and lows.

[0054] Figure 5 is a schematic diagram of the simulation waveform of the traditional Skip pulse frequency reduction method; as shown in Figure 5, it includes the frequency reduction control signal Frequency reduction, the start signal MOSFET turn-on of the MOS tube Q0 inside the chip, the output voltage Vo on the output capacitor, the current Inductor current in the inductor L2, the clock frequency CLK inside the chip; the voltage FB (i.e., the output voltage feedback signal) after the voltage on the output sampling capacitor is divided by the resistor. Due to the difference in the FB ripple voltage, the width of the frequency reduction signal in different cycles is different, causing the conduction time of the MOS tube Q0 in different cycles to be quite different, and the corresponding peak value of the inductor current is high and low, which directly leads to an increase in the output voltage ripple.

[0055] The purpose of this application is to solve the problem of unstable duty cycle that occurs after the BUCK power supply frequency starts to decrease from a constant maximum frequency. For this purpose, a chip frequency control circuit is proposed, including: a frequency reduction control unit, a clock oscillator, a switch tube control unit, and a voltage-controlled switch tube. The input end of the frequency reduction control unit is connected to the output voltage feedback signal of the BUCK power supply, and the output end of the frequency reduction control unit is connected to the control end of the clock oscillator, which is used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal, wherein the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal. The output end of the clock oscillator is connected to the switch tube control unit to output a clock signal to the switch tube control unit, and the switch tube control unit is connected to the switch to drive the voltage control switch tube to conduct according to the clock signal.

[0056] The implementation of this application does not limit the specific types and structures of the above components. Here is a specific implementation method. Figure 6 is a structural diagram of a chip frequency control circuit provided in an embodiment of this application; as shown in Figure 6, the falling edge of the CLK pulse will set the output of the D flip-flop DFF to a high level, and provide an opening signal to the MOS tube Q0 through the driver circuit Driver. When the load decreases, the output voltage feedback signal FB will increase, and the FB voltage will be proportional to the first reference voltage V REF1 After passing through the first operational amplifier EA1, a frequency reduction control signal is generated (i.e., the signal level increases), and the clock frequency of the clock oscillator OSC will decrease proportionally with the increased level amplitude. In this mode, the output voltage feedback signal FB and the peak current sampling signal are input to the inverting input terminal of the inductor current peak comparator COMP2 after superposition operation, and the threshold voltage V LIMIT After comparison, the inductor current peak comparator COMP2 generates a high-level reset D flip-flop DFF. At this time, the driver circuit Driver output is set to a low level, and the MOS tube Q0 is turned off. When the output load decreases from full load, the switching frequency begins to decrease, that is, it enters the frequency reduction mode, and the output feedback voltage FB is equal to the first reference voltage V REF1 The compared voltage is then amplified and the frequency of the internal clock oscillator OSC of the chip is directly controlled. In this way, the frequency will not change suddenly and a smooth linear frequency reduction can be achieved.

[0057] FIG7 is a schematic diagram of a specific circuit structure of a frequency reduction control unit and a clock oscillator OSC provided by an embodiment of the present application; as shown in FIG7, the first PMOS tube Q1 and the second PMOS tube Q2 use the "diode connection" method in the analog circuit, the gate and the drain are short-circuited, and the transistor always works in the saturation region, which is equivalent to a load resistor, and is used to adjust the current flowing through the series NMOS tube. The first NMOS tube Q3 and the second NMOS tube Q4 implement output voltage following, and realize the switching of the input voltage of the inverting terminal of the internal comparator COMP3 when the maximum frequency is constant and the frequency is reduced.

[0058] When the system load decreases, the output voltage feedback signal FB is compared with the reference voltage and the error amplified signal triggers the frequency reduction function. The CLK clock frequency inside the chip can be achieved by changing the voltage comparison reference of the internal capacitor charge and discharge sawtooth wave, or by changing the charge and discharge current of the capacitor. The left half of the figure is the frequency reduction control unit, and the right half is the clock oscillator OSC.

[0059] Clock frequency: C1 is charged through the variable current source I3, and the switch S1 discharges the capacitor C1 to generate a sawtooth wave, which is then compared with the input voltage IN1 to generate a pulse width modulation CLK.

[0060] Constant operating frequency: by the second reference voltage V REF2 Control, at this time IN1 voltage = V REF2 -Vth4+ Vth5≈V REF2 , where Vth4 and Vth5 are the threshold voltages corresponding to the second NMOS tube Q4 and the third PMOS tube Q5.

[0061] The working frequency during frequency reduction is determined by the feedback voltage FB and the first reference voltage V REF1 After comparison, the Vout1 output by the first operational amplifier EA1 is used for control. At this time, the IN1 voltage = Vout1-Vth3+Vth5≈Vout1, where Vth3 and Vth5 are the threshold voltages of the first NMOS tube Q3 and the third PMOS tube Q5. REF2 , the voltage of IN1 increases, the sawtooth wave charging cycle on C1 becomes longer, and the operating frequency of the clock oscillator OSC will decrease. I3 is specifically a voltage-controlled current source, and its current is also controlled by the voltage of IN1. When the voltage of IN1 increases, the current of I3 will decrease. This design is to make the frequency range of OSC wider, which helps to further reduce the switching frequency under light load and improve system efficiency.

[0062] This solution uses a variable frequency clock signal. When the output load decreases from full load and the frequency enters the frequency reduction mode, the output voltage feedback signal FB is proportional to the first reference voltage V REF1 The compared voltage is amplified to directly reduce the frequency of the chip's internal clock oscillator OSC, and the frequency can be steadily and linearly reduced as the load decreases. FIG8 is a schematic diagram of the simulation waveform of the new chip frequency control circuit in the frequency reduction area provided by the embodiment of the present application; as shown in FIG8, the simulation results show that the duty cycle of the power supply in different cycles is relatively fixed, the amplitude of the inductor current is relatively stable, and the output ripple obtained is also uniform.

[0063] That is, in the traditional frequency reduction method, the clock frequency CLK of the clock oscillator OSC is fixed, and the frequency reduction is achieved by shielding part of the MOS tube Q0 drive pulse. Due to the voltage ripple of the FB signal, there is a difference in the voltage of the turn-off point FB, which causes the inductor current to show inconsistent amplitude in the frequency reduction area. The new frequency reduction method of the present application is that after the frequency reduction circuit starts to work, the frequency reduction signal does not clear the D flip-flop, and does not force the signal CLK emitted by the clock oscillator OSC to be pulled down. The FB voltage signal is compared with the reference to directly control the frequency of the clock oscillator OSC, that is, the switching frequency is reduced by reducing the frequency of the clock oscillator OSC to achieve linear frequency reduction.

[0064] A chip frequency control circuit provided in an embodiment of the present application includes: a frequency reduction control unit, a clock oscillator, a switch tube control unit and a voltage-controlled switch tube. The input end of the frequency reduction control unit is connected to the output voltage feedback signal of the BUCK power supply, and the output end of the frequency reduction control unit is connected to the control end of the clock oscillator, which is used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal, wherein the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal. It can be seen that this scheme is an active frequency reduction method, which is characterized in that the clock signal frequency of the clock oscillator is variable. The output end of the clock oscillator is connected to the switch tube control unit to output the clock signal to the switch tube control unit, and the switch tube control unit is connected to the switch to drive the voltage control switch tube to conduct according to the clock signal. Since this circuit directly changes the clock signal frequency of the chip clock oscillator, the FB voltage corresponding to the opening and closing of the voltage-controlled switch tube is relatively fixed, the duty cycle difference of different cycles is small, and the amplitude of the inductor current pulse obtained at the end is evenly distributed, thereby realizing linear and smooth frequency regulation.

[0065] As mentioned in the above embodiment, the present application does not limit the specific structure of the chip frequency control circuit. The circuit provided in this embodiment also includes a first operational amplifier EA1; the first input terminal of the first operational amplifier is connected to the output voltage feedback signal FB of the BUCK power supply, and the second input terminal of the first operational amplifier is connected to the first reference voltage V REF1 The output end of the first operational amplifier is connected to the input end of the frequency reduction control unit, and is used to output the amplified output voltage feedback signal to the frequency reduction control unit. The output voltage feedback signal is amplified by the first operational amplifier, so that the subsequent control is more accurate.

[0066] On the basis of the above implementation, this embodiment provides a specific frequency reduction control unit to realize the control of the clock frequency of the clock oscillator. The frequency reduction control unit of this embodiment is specifically composed of a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a first fixed current source and a second fixed current source. Among them, the source electrodes of the first PMOS tube and the second PMOS tube are both connected to the voltage source, and the gate and drain electrodes of the first PMOS tube and the second PMOS tube are connected to each other. The common end of the gate and drain of the first PMOS tube is connected to the drain electrode of the first NMOS tube, and the gate of the first NMOS tube is connected to the output end of the first operational amplifier. The common end of the gate and drain of the second PMOS tube is connected to the drain electrode of the second NMOS tube, and the gate of the second PMOS tube is connected to the second reference voltage. The source electrode of the first NMOS tube, the source electrode of the second NMOS tube, the positive electrode of the first fixed current source and the gate electrode of the third PMOS tube are connected to each other; the negative electrode of the first fixed current source and the drain electrode of the third PMOS tube are grounded. The positive electrode of the second fixed current source is connected to the voltage source; the negative electrode of the second fixed current source and the source electrode of the third PMOS tube are connected to each other, and the common end of the connection is connected to the control end of the clock oscillator as the output end of the frequency reduction control unit. Correspondingly, the clock oscillator is specifically composed of a variable current source, a first capacitor, a switch, and an internal comparator. The positive electrode of the variable current source is connected to the voltage source; the negative electrode of the variable current source, the first end of the first capacitor, the first end of the switch, and the in-phase input end of the internal comparator are connected to each other; the second end of the first capacitor and the second end of the switch are grounded; the inverting input end of the internal comparator is connected to the output end of the frequency reduction control unit; the output end of the internal comparator is connected to the control end of the switch; wherein the output end of the internal comparator is used as the output end of the clock oscillator to output the clock signal. Specifically, the variable current source is specifically a voltage-controlled current source; the control end of the voltage-controlled current source is connected to the output end of the frequency reduction control unit. By controlling the voltage-controlled switch tube Q0 provided by the specific structure of this embodiment, since the frequency of the clock oscillator will not change suddenly, a smooth linear frequency reduction can be achieved.

[0067] In practical applications, the switch tube control unit can be specifically composed of a D flip-flop and a driving circuit. The clock oscillator is connected to the first input terminal of the D flip-flop, and is used to output a clock signal to the D flip-flop so as to set the output of the D flip-flop to a high level when the falling edge of the clock signal arrives; the output terminal of the D flip-flop is connected to the input terminal of the driving circuit, and the output terminal of the driving circuit is connected to the voltage-controlled switch tube. After the D flip-flop outputs a high level, the driving circuit drives the voltage-controlled switch tube to turn on.

[0068] The above structure can drive the voltage-controlled switch tube to turn on, and after the voltage-controlled switch tube is turned on, it needs to be turned off to achieve complete control of the voltage-controlled switch tube. This embodiment provides a specific implementation scheme, and the chip frequency control circuit also includes a current sampling circuit for obtaining a peak current sampling signal. The current sampling circuit is connected to the second input end of the D trigger, and is used to reset the D trigger according to the peak current sampling signal and the amplified output voltage feedback signal to turn off the voltage-controlled switch tube. A specific structure of a current sampling circuit is provided here, including: a current sampling resistor, an adder, and an inductor current peak comparator; the current sampling resistor and the voltage-controlled switch tube are connected in series in the output loop, and the first end of the current sampling resistor is grounded; the first input end of the adder is connected to the second end of the current sampling resistor; the second input end of the adder is connected to the output end of the first operational amplifier; the output end of the adder is connected to the first input end (non-inverting input end) of the inductor current peak comparator; the second input end (inverting input end) of the inductor current peak comparator is connected to the threshold voltage, and the output end of the inductor current peak comparator is connected to the second input end of the D trigger, which is used to output a signal to reset the D trigger after the output of the adder is greater than the threshold voltage. The output voltage feedback signal FB and the peak current sampling signal are input to the inductor current peak comparator after superposition operation and the threshold voltage V LIMIT After comparison, the inductor current peak comparator generates a high-level reset D flip-flop. At this time, the drive circuit output is set to a low level, and the voltage-controlled switch tube Q0 is turned off.

[0069] In order to solve the above technical problems, an embodiment of the present application provides a BUCK power supply, including the chip frequency control circuit in the above embodiment.

[0070] Since the embodiments of the BUCK power supply part correspond to the embodiments of the chip frequency control circuit part, the embodiments of the BUCK power supply part refer to the description of the embodiments of the chip frequency control circuit part, which will not be described here.

[0071] The BUCK power supply provided in this embodiment corresponds to the above-mentioned chip frequency control circuit, and thus has the same beneficial effects as the above-mentioned chip frequency control circuit.

[0072] In order to solve the above technical problems, the embodiment of the present application also provides a chip frequency control method, which is applied to the frequency reduction control unit in the above embodiment; the method comprises the following steps: S1: obtaining the output voltage feedback signal of the BUCK power supply. S2: adjusting the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal. Among them, the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal.

[0073] Since the embodiments of the method part correspond to the embodiments of the chip frequency control circuit part, the embodiments of the method part refer to the description of the embodiments of the chip frequency control circuit part, which will not be repeated here.

[0074] The method provided in this embodiment corresponds to the above-mentioned chip frequency control circuit, and thus has the same beneficial effects as the above-mentioned chip frequency control circuit.

[0075] The above is a detailed introduction to a chip frequency control circuit, BUCK power supply and chip frequency control method provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can refer to each other. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the present application.

[0076] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method, article or device including the above elements.

Claims

1. A chip frequency control circuit, characterized in that: include: Frequency reduction control unit, clock oscillator, switch tube control unit and voltage control switch tube; The input end of the frequency reduction control unit is connected to the output voltage feedback signal of the BUCK power supply, and the output end of the frequency reduction control unit is connected to the control end of the clock oscillator, and is used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal, wherein the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal; The output end of the clock oscillator is connected to the switch tube control unit to output the clock signal to the switch tube control unit, and the switch tube control unit is connected to the switch to drive the voltage-controlled switch tube to conduct according to the clock signal.

2. The chip frequency control circuit according to claim 1, characterized in that: Also includes: a first operational amplifier; The first input terminal of the first operational amplifier is connected to the output voltage feedback signal of the BUCK power supply, and the second input terminal of the first operational amplifier is connected to the first reference voltage; the output terminal of the first operational amplifier is connected to the input terminal of the frequency reduction control unit, so as to output the amplified output voltage feedback signal to the frequency reduction control unit.

3. The chip frequency control circuit according to claim 2, characterized in that: The frequency reduction control unit includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, a second NMOS tube, a first fixed current source and a second fixed current source; The sources of the first PMOS tube and the second PMOS tube are both connected to a voltage source, and the gates and drains of the first PMOS tube and the second PMOS tube are connected to each other; The common end of the gate and drain of the first PMOS tube is connected to the drain of the first NMOS tube, and the gate of the first NMOS tube is connected to the output end of the first operational amplifier; A common end of the gate and drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the gate of the second PMOS tube is connected to a second reference voltage; The source of the first NMOS tube, the source of the second NMOS tube, the positive electrode of the first fixed current source and the gate of the third PMOS tube are connected to each other; the negative electrode of the first fixed current source and the drain of the third PMOS tube are grounded; The positive electrode of the second fixed current source is connected to a voltage source; the negative electrode of the second fixed current source and the source of the third PMOS tube are connected to each other, and the common end of the connection is connected to the control end of the clock oscillator as the output end of the frequency reduction control unit.

4. The chip frequency control circuit according to claim 3, characterized in that: The clock oscillator comprises: a variable current source, a first capacitor, a switch, and an internal comparator; The positive electrode of the variable current source is connected to a voltage source; the negative electrode of the variable current source, the first end of the first capacitor, the first end of the switch and the non-inverting input end of the internal comparator are connected to each other; the second end of the first capacitor and the second end of the switch are grounded; The inverting input terminal of the internal comparator is connected to the output terminal of the frequency reduction control unit; the output terminal of the internal comparator is connected to the control terminal of the switch; wherein the output terminal of the internal comparator serves as the output terminal of the clock oscillator to output the clock signal.

5. The chip frequency control circuit according to claim 4, characterized in that: The variable current source is specifically a voltage-controlled current source; The control end of the voltage-controlled current source is connected to the output end of the frequency reduction control unit.

6. The chip frequency control circuit according to any one of claims 2 to 5, characterized in that: The switch tube control unit includes: a D trigger and a drive circuit; The clock oscillator is connected to the first input terminal of the D flip-flop, and is used to output the clock signal to the D flip-flop so as to set the output of the D flip-flop to a high level when the falling edge of the clock signal arrives; The output end of the D trigger is connected to the input end of the driving circuit, and the output end of the driving circuit is connected to the voltage-controlled switch tube. After the D trigger outputs a high level, the driving circuit drives the voltage-controlled switch tube to turn on.

7. The chip frequency control circuit according to claim 6, characterized in that: Also includes: A current sampling circuit for obtaining a peak current sampling signal; The current sampling circuit is connected to the second input terminal of the D flip-flop and is used to reset the D flip-flop according to the peak current sampling signal and the amplified output voltage feedback signal to turn off the voltage-controlled switch tube.

8. The chip frequency control circuit according to claim 7, characterized in that: The current sampling circuit includes: a current sampling resistor, an adder, and an inductor current peak comparator; The current sampling resistor and the voltage control switch tube are connected in series in the output loop, and the first end of the current sampling resistor is grounded; The first input end of the adder is connected to the second end of the current sampling resistor; the second input end of the adder is connected to the output end of the first operational amplifier; the output end of the adder is connected to the first input end of the inductor current peak comparator; The second input terminal of the inductor current peak comparator is connected to the threshold voltage, and the output terminal of the inductor current peak comparator is connected to the second input terminal of the D flip-flop, so as to output a signal to reset the D flip-flop after the output of the adder is greater than the threshold voltage.

9. A BUCK power supply, characterized in that: A chip frequency control circuit comprising any one of claims 1 to 8.

10. A chip frequency control method, characterized in that: The method is applied to the frequency reduction control unit according to any one of claims 1 to 8; the method comprises: Get the output voltage feedback signal of the BUCK power supply; The frequency of the clock signal output by the clock oscillator is adjusted according to the output voltage feedback signal, wherein the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal.

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