Output drive circuit, impedance calibration circuit and memory

Abstract

The present disclosure discloses an output drive circuit, an impedance calibration circuit, and a memory. The output drive circuit includes a pull-up main transistor and a pull-down main transistor. Both the pull-up main transistor and the pull-down main transistor are N-type MOS transistors. The source of the pull-up main transistor and the drain of the pull-down main transistor are both connected to a bus. The drain of the pull-up main transistor is connected to a power supply, and the gate of the pull-up main transistor receives a pull-up main control signal. The source of the pull-down main transistor is grounded, and the gate of the pull-down main transistor receives a pull-down main control signal. The pull-up main control signal and the pull-down main control signal are in opposite phases. The substrate and source of the pull-up main transistor are short-circuited.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, an output driving circuit, an impedance calibration circuit, and a memory. Background Art

[0002] In semiconductor memory, data can be stored as physical signals (e.g., charge on a capacitor) in individual memory cells. Memory cells can be arranged in a memory array consisting of rows (e.g., word lines) and columns (e.g., bit lines). Furthermore, these can be organized into memory arrays (matrix), memory banks (banks), and memory bank groups (bank groups).

[0003] Signals are transmitted between the memory and external devices using a communication bus (such as an address bus or a data bus). However, there is a risk of signal distortion during transmission. Therefore, a driving circuit is required to drive the signal to reduce the risk of signal distortion. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide an output drive circuit, an impedance calibration circuit, and a memory, which can improve performance and save process costs.

[0005] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] An embodiment of the present disclosure provides an output drive circuit, which includes: a pull-up main transistor and a pull-down main transistor; the pull-up main transistor and the pull-down main transistor are both N-type MOS transistors; the source of the pull-up main transistor and the drain of the pull-down main transistor are both connected to a bus; the drain of the pull-up main transistor is connected to a power supply, and the gate of the pull-up main transistor receives a pull-up main control signal; the source of the pull-down main transistor is grounded, and the gate of the pull-down main transistor receives a pull-down main control signal; the pull-up main control signal and the pull-down main control signal are in antiphase with each other; and the substrate and source of the pull-up main transistor are short-circuited.

[0007] In the above solution, the pull-up main transistor is arranged in a deep N-well region; the voltage on the deep N-well region is greater than or equal to the voltage on the substrate and source of the pull-up main transistor.

[0008] In the above solution, the voltage on the substrate and source of the pull-up main transistor is 0-0.5V; the voltage on the gate of the pull-up main transistor is 0-1.05V; the voltage on the drain of the pull-up main transistor is 0.5V; and the voltage on the deep N-well region is 0.5V.

[0009] In the above solution, the output drive circuit also includes: a first protection resistor and a second protection resistor; the first protection resistor is connected between the source of the pull-up main transistor and the bus; the second protection resistor is connected between the drain of the pull-down main transistor and the bus.

[0010] An embodiment of the present disclosure also provides an impedance calibration circuit, which includes: the output drive circuit described in the above scheme, and a pull-up adjustable resistance unit and a pull-down adjustable resistance unit; the pull-up adjustable resistance unit is connected between the power supply and the bus, and is configured to receive and respond to a multi-bit pull-up adjustable control signal to adjust its own equivalent impedance; the pull-down adjustable resistance unit is connected between the ground terminal and the bus, and is configured to receive and respond to a multi-bit pull-down adjustable control signal to adjust its own equivalent impedance.

[0011] In the above solution, the pull-up adjustable resistance unit includes: multiple pull-up adjustable transistors; the drains of the multiple pull-up adjustable transistors are all connected to the power supply, and the sources of the multiple pull-up adjustable transistors are all connected to the bus; the gate of each pull-up adjustable transistor receives one of the pull-up adjustable control signals.

[0012] In the above solution, the pull-up adjustable resistor unit further includes: a third protection resistor; one end of the third protection resistor is connected to the sources of the plurality of pull-up adjustable transistors; and the other end of the third protection resistor is connected to the bus.

[0013] In the above scheme, the pull-down adjustable resistance unit includes: multiple pull-down adjustable transistors; the drains of the multiple pull-down adjustable transistors are all connected to the ground end, and the sources of the multiple pull-down adjustable transistors are all connected to the bus; the gate of each pull-down adjustable transistor receives one of the pull-down adjustable control signals.

[0014] In the above solution, the pull-down adjustable resistor unit further includes: a fourth protection resistor; one end of the fourth protection resistor is connected to the sources of the plurality of pull-down adjustable transistors; and the other end of the fourth protection resistor is connected to the bus.

[0015] An embodiment of the present disclosure further provides a memory, which includes the output driving circuit as described in the above solution, or the memory includes the impedance calibration circuit as described in the above solution.

[0016] It can be seen that the embodiments of the present disclosure provide an output drive circuit, an impedance calibration circuit, and a memory, wherein the output drive circuit includes: a pull-up main transistor and a pull-down main transistor. The pull-up main transistor and the pull-down main transistor are both N-type MOS transistors; the source of the pull-up main transistor and the drain of the pull-down main transistor are both connected to the bus; the drain of the pull-up main transistor is connected to the power supply, and the gate of the pull-up main transistor receives the pull-up main control signal; the source of the pull-down main transistor is grounded, and the gate of the pull-down main transistor receives the pull-down main control signal; the pull-up main control signal and the pull-down main control signal are in opposite phases; the substrate and source of the pull-up main transistor are short-circuited. In this way, the substrate and source of the pull-up main transistor are short-circuited, and a dynamic bias voltage is applied to the substrate, thereby reducing the threshold voltage of the pull-up main transistor, making it easier for the pull-up main transistor to be turned on, and further, accelerating the speed at which the bus voltage is pulled up, thereby improving the performance of the output drive circuit. At the same time, the embodiment of the present disclosure only designs the wires outside the device, without changing the manufacturing process of the device, thereby improving the performance of the output drive circuit and saving process costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the output drive circuit provided in the embodiment of the present disclosure Figure 1 ;

[0018] Figure 2 A schematic structural diagram of a pull-up main transistor provided in an embodiment of the present disclosure;

[0019] Figure 3 Schematic diagram of the effect of the output drive circuit provided by the embodiment of the present disclosure Figure 1 ;

[0020] Figure 4 Schematic diagram of the effect of the output drive circuit provided by the embodiment of the present disclosure Figure 2 ;

[0021] Figure 5 Schematic diagram of the effect of the output drive circuit provided by the embodiment of the present disclosure Figure 3 ;

[0022] Figure 6 Schematic diagram of the output drive circuit provided in the embodiment of the present disclosure Figure 2 ;

[0023] Figure 7 The structure of the impedance calibration circuit provided by the embodiment of the present disclosure is shown as follows: Figure 1 ;

[0024] Figure 8 The structure of the impedance calibration circuit provided by the embodiment of the present disclosure is shown as follows: Figure 2 ;

[0025] Figure 9 The structure of the impedance calibration circuit provided by the embodiment of the present disclosure is shown as follows: Figure 3 ;

[0026] Figure 10 Schematic diagram of the memory structure provided by the embodiment of the present disclosure Figure 1 ;

[0027] Figure 11 Schematic diagram of the memory structure provided in the embodiment of the present disclosure Figure 2 . DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0029] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0030] If similar descriptions of "first / second" appear in the invention document, the following explanation is added. In the following description, the terms "first\second\third" involved are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0032] To meet the demand for higher performance operating characteristics, designers continue to strive to increase the operating speeds for transmitting data across these communication buses. However, one problem with increased data transfer rates is maintaining signal integrity during these data bursts on the various bus signal lines. As these transfer rates increase, the impedance characteristics of the data bus become more pronounced. The capacitance and inductance characteristics of the signal lines may begin to distort the signal waveform on the data bus at these higher data rates. For example, the waveform may begin to spread and / or reflections may occur at locations of mismatched impedance on the data bus signal lines. When the impedance (e.g., output impedance) of one or more external terminals (e.g., data DQ terminals) of a memory device is not properly matched to the impedance of the communication bus, signal integrity (e.g., data integrity) may be affected. For example, impedance mismatch can be caused by process variations, temperature variations, and voltage (e.g., power supply potential) variations in the memory device. Therefore, it is necessary to reduce these effects in order to reduce the likelihood of data being corrupted when transmitted on the data bus.

[0033] Figure 1 is an optional structural diagram of the output drive circuit provided by the embodiment of the present disclosure, such as Figure 1 As shown, the output drive circuit 10 includes: a pull-up main transistor 101 and a pull-down main transistor 102. Both the pull-up main transistor 101 and the pull-down main transistor 102 are N-type MOS transistors. The source S of the pull-up main transistor 101 and the drain D of the pull-down main transistor 102 are both connected to the bus 60. The drain D of the pull-up main transistor 101 is connected to the power supply VDD, and the gate G of the pull-up main transistor 101 receives the pull-up main control signal Pum. The source S of the pull-down main transistor 102 is grounded, and the gate G of the pull-down main transistor 102 receives the pull-down main control signal Pdm. The pull-up main control signal Pum and the pull-down main control signal Pdm are in opposite phases. The substrate B and source S of the pull-up main transistor 101 are short-circuited.

[0034] In the embodiments of the present disclosure, reference Figure 1 , bus 60 can be used to transmit command address signals CA, data signals DQ, etc. A pull-up main transistor 101 is connected between the power supply VDD and bus 60. Furthermore, when triggered by the pull-up main control signal Pum, the source S and drain D of the pull-up main transistor 101 can be conductive, i.e., the pull-up main transistor 101 is turned on. In this way, the power supply VDD and bus 60 can be conductive, thereby pulling up the voltage of bus 60. Correspondingly, a pull-down main transistor 102 is connected between the ground terminal VSS and bus 60. Furthermore, when triggered by the pull-down main control signal Pdm, the source S and drain D of the pull-down main transistor 102 can be conductive, i.e., the pull-down main transistor 102 is turned on. In this way, the ground terminal VSS and bus 60 can be conductive, thereby pulling down the voltage of bus 60.

[0035] Continue to refer Figure 1 The pull-up main transistor 101 and the pull-down main transistor 102 are both N-type MOS transistors, and the pull-up main control signal Pum and the pull-down main control signal Pdm are in opposite phases. Therefore, the pull-up main transistor 101 and the pull-down main transistor 102 will not be turned on at the same time. In other words, when the pull-up main control signal Pum is "1" (i.e., a high level) and the pull-down main control signal Pdm is "0" (i.e., a low level), the pull-up main transistor 101 is turned on, while the pull-down main transistor 102 is turned off, and the voltage of the bus 60 is pulled up; on the other hand, when the pull-up main control signal Pum is "0" (i.e., a low level) and the pull-down main control signal Pdm is "1" (i.e., a high level), the pull-up main transistor 101 is turned off, while the pull-down main transistor 102 is turned on, and the voltage of the bus 60 is pulled down.

[0036] In some embodiments, reference Figure 1 The levels of the pull-up main control signal Pum and the pull-down main control signal Pdm can represent the comparison result between the voltage of bus 60 and a reference voltage; the reference voltage is used to determine the level state of the signal transmitted on bus 60. For example, if the voltage of bus 60 is greater than the reference voltage, it indicates that the signal transmitted on bus 60 is "1" (i.e., a high level). In this case, the pull-up main control signal Pum is "1" (i.e., a high level) and the pull-down main control signal Pdm is "0" (i.e., a low level). As a result, the voltage of bus 60 is pulled up, which can prevent the signal transmitted on bus 60 from decaying from "1" to "0", thus avoiding signal distortion. For another example, if the voltage of bus 60 is lower than the reference voltage, the signal transmitted on bus 60 is "0" (i.e., low level). In this case, the pull-up main control signal Pum is "0" (i.e., low level), and the pull-down main control signal Pdm is "1" (i.e., high level). Thus, the voltage of bus 60 is pulled down, which can prevent the signal transmitted on bus 60 from attenuating from "0" to "1", that is, avoid signal distortion.

[0037] In other embodiments, reference Figure 1The pull-up main control signal Pum and the pull-down main control signal Pdm come from the external control module and are used to set the voltage on the bus 60 to a specific value to shield the signal transmitted on the bus 60. For example, the external control module can output a high-level pull-up main control signal Pum and a low-level pull-down main control signal Pdm, thereby controlling the pull-up main transistor 101 to be turned on and the pull-down main transistor 102 to be turned off. In this way, the voltage of the bus 60 is pulled up, and the bus 60 remains in a high-level state, thereby shielding the signal transmitted on the bus 60. Correspondingly, the external control module can also output a low-level pull-up main control signal Pum and a high-level pull-down main control signal Pdm, thereby controlling the pull-up main transistor 101 to be turned off and the pull-down main transistor 102 to be turned on. In this way, the voltage of the bus 60 is pulled down, and the bus 60 remains in a low-level state, thereby shielding the signal transmitted on the bus 60.

[0038] It should be noted that a MOS transistor (metal-oxide semiconductor field-effect transistor, MOSFET) is a four-terminal device consisting of a source (S), a drain (Drain), a gate (G), and a bulk (B). For an N-type MOS transistor, when the gate-source voltage Vgs (i.e., the voltage difference between the gate G and the source S) reaches the threshold voltage Vth, a conductive channel is formed between the source S and the drain D, and conduction is established between the source S and the drain D, turning the MOS transistor on.

[0039] Figure 2 shows the structure of the pull-up main transistor 101, referring to Figure 2 Different doped regions are formed in the semiconductor material. N-type doping is performed in the P-well (P well) to form two N+ regions, which form the source S and drain D of the pull-up main transistor 101. P-type doping is performed in the P-well to form a P+ region, which forms the substrate B of the pull-up main transistor 101. The substrate B and source S of the pull-up main transistor 101 are short-circuited by a wire outside the device. In other words, the same voltage is applied to the substrate B and source S of the pull-up main transistor 101. Because the voltage on the source S of the pull-up main transistor 101 changes dynamically during the process of pulling up the voltage on the bus 60, the substrate B and source S of the pull-up main transistor 101 are short-circuited, which means that a dynamic bias voltage is applied to the substrate B.

[0040] The threshold voltage Vth of the NMOS tube is directly proportional to the thickness of the MOS depletion layer. When the substrate bias voltage increases, the depletion layer thickness decreases. Therefore, the threshold voltage Vth at this time is smaller than the threshold voltage Vth when the substrate terminal B is connected to 0V voltage.

[0041] In the disclosed embodiment, it is understood that the substrate B and source S of the pull-up main transistor 101 are short-circuited by a wire outside the device. This applies a dynamic bias voltage to the substrate B, which can reduce the threshold voltage of the pull-up main transistor 101, making it easier to turn on the pull-up main transistor 101. This can accelerate the speed at which the voltage of the bus 60 is pulled up, thereby improving the performance of the output drive circuit 10. Furthermore, since the initial voltage of the source S and substrate B is 0V after the substrate B and source S are short-circuited, it does not cause an increase in NMOS leakage current.

[0042] At the same time, the embodiment of the present disclosure only designs the wires outside the device, and there is no need to change the manufacturing process of the device, which improves the performance of the output drive circuit 10 and thus saves process costs.

[0043] Figures 3 to 5 A schematic diagram of the effects provided by an embodiment of the present disclosure.

[0044] Figure 3 The curve of the voltage Vdq on the bus 60 changing with time t during the voltage pull-up process is shown. Curve 3 is the voltage pull-up curve after the output drive circuit 10 provided by the embodiment of the present disclosure is adopted, and curves 1 and 2 are the voltage pull-up curves after the drive circuit in the related art is adopted. Figure 3 It can be seen that the pull-up speed of the voltage Vdq of curve 3 is better than that of curves 1 and 2. That is, the drain current Id corresponding to curve 3 is amplified, so that the voltage Vdq on the bus 60 can be pulled up more quickly, and the voltage pull-up effect is better.

[0045] Figure 4 The figure shows the curve of the drain current Id of the pull-up main transistor 101 and the voltage Vdq on the bus 60 during the voltage pull-up process. The expected result (the bold solid line) is the curve corresponding to the output drive circuit 10 provided by the embodiment of the present disclosure, and the other dotted lines are the corresponding curves under other different conditions. Figure 4 It can be seen that the output drive circuit 10 provided in the embodiment of the present disclosure can make the drain current Id change faster, so that the voltage Vdq on the bus 60 can be pulled up more quickly, and the voltage pull-up effect is better.

[0046] Figure 5 The figure shows the curve of the drain current Id and drain voltage Vd of the pull-up main transistor 101 during the voltage pull-up process. Curve 2 corresponds to the pull-up main transistor 101 provided by the embodiment of the present disclosure, and curve 1 corresponds to a common transistor. Figure 5It can be seen that the pull-up main transistor 101 provided in the embodiment of the present disclosure can dynamically adjust the bias voltage of the substrate electrode B, so its threshold voltage is lower and it is easier to be turned on. As a result, the drain current Id rises faster, that is, the slope of the change of curve 2 is larger. In this way, the voltage on the bus 60 can be pulled up more quickly, and the voltage pull-up effect is better.

[0047] In some embodiments of the present disclosure, reference Figure 2 The pull-up main transistor 101 is disposed in a deep N-well region (DNW). The voltage on the deep N-well region is greater than or equal to the voltage on the substrate B and the source S of the pull-up main transistor.

[0048] In the present disclosure, continue to refer to Figure 2 A PN junction is formed between the P-well region and the deep N-well region. If the voltage in the P-well region is higher than that in the deep N-well region, the PN junction will conduct, affecting the performance of the pull-up main transistor 101. Therefore, the voltage applied to the deep N-well region must be greater than or equal to the voltage across the substrate B and source S of the pull-up main transistor. This prevents the PN junction from conducting, thereby ensuring the normal operation of the pull-up main transistor 101.

[0049] In some embodiments of the present disclosure, reference Figure 2 The voltages on the substrate B and source S of the pull-up main transistor 101 are 0 to 0.5 V, for example, 0, 0.125 V, or 0.5 V. The voltage on the gate G of the pull-up main transistor 101 is 0 to 1.05 V, for example, 0, 0.6 V, or 1.05 V. The voltage on the drain D of the pull-up main transistor 101 is 0.5 V. The voltage on the deep N-well region is 0.5 V.

[0050] In some embodiments of the present disclosure, Figure 6 As shown, the output drive circuit 10 further includes a first protection resistor 103 and a second protection resistor 104. The first protection resistor 103 is connected between the source S of the pull-up main transistor 101 and the bus 60; the second protection resistor 104 is connected between the drain D of the pull-down main transistor 102 and the bus 60.

[0051] It is understood that the first protection resistor 103 can limit the current in the pull-up main transistor 101 during the process of pulling up the voltage of the bus 60, thereby preventing damage to the pull-up main transistor 101 caused by excessive current. Correspondingly, the second protection resistor 104 can limit the current in the pull-down main transistor 102 during the process of pulling down the voltage of the bus 60, thereby preventing damage to the pull-down main transistor 102 caused by excessive current.

[0052] The present disclosure also provides an impedance calibration circuit. Figure 7As shown, the impedance calibration circuit 20 includes: an output driver circuit 10, a pull-up adjustable resistor unit 21, and a pull-down adjustable resistor unit 22. The pull-up adjustable resistor unit 21 is connected between the power supply VDD and the bus 60. The pull-up adjustable resistor unit 21 is configured to receive and adjust its own equivalent impedance in response to a multi-bit pull-up adjustable control signal Pup. The pull-down adjustable resistor unit 22 is connected between the ground terminal VSS and the bus 60. The pull-down adjustable resistor unit 22 is configured to receive and adjust its own equivalent impedance in response to a multi-bit pull-down adjustable control signal Pdn.

[0053] It should be noted that Figure 7 The output driving circuit 10 shown may include the technical features in the aforementioned embodiments, which will not be described in detail here.

[0054] In the embodiments of the present disclosure, reference Figure 7 The pull-up adjustable control signal Pup and the pull-down adjustable control signal Pdn may be ZQ calibration commands in the memory. The ZQ calibration command is used to calibrate the output driver impedance between process, temperature, and voltage. The frequency of the ZQ calibration command depends on the system temperature and voltage drift rate.

[0055] In the disclosed embodiment, the ZQ calibration command is initiated by the MPC command and includes two calibration modes: ZQCal Start (ZQ calibration start) and ZQCal Latch (ZQ calibration latch). Among them, the ZQCal Start mode starts the calibration program in the memory, and the ZQCal Latch mode captures the results and loads them into the driver of the memory.

[0056] Further, a ZQCal Start command can be issued as long as the memory is not in a power-off state. There are two timing parameters associated with ZQ calibration. tZQCAL is the time from when the ZQCal Start MPC command is sent to the host that the ZQCal Latch MPC command can be sent. tZQLAT is the time from when the host sends the ZQCal Latch MPC command to when the CA bus (and subsequently the DQ bus) can be used for normal operation. After tZQCAL expires and all DQ bus operations are completed, the ZQCal Latch command can be issued at any time other than power-off. During tZQLAT, the CA bus must remain deselected to allow the CAODT calibration settings to be updated. After ZQCal starts, neither another ZQCal start nor a ZQCal latch is allowed until tZQCAL ends.

[0057] It should be noted that to use the ZQ calibration function, a 240 ohm ±1% tolerance external resistor must be connected between the ZQ pin and the power supply VDD. Furthermore, the pull-up adjustable resistor unit 21 and the pull-down adjustable resistor unit 22 can adjust their equivalent impedance to a desired value, such as 240 ohms, under the adjustment of the ZQ calibration command.

[0058] It is understood that the pull-up adjustable resistor unit 21 and the pull-down adjustable resistor unit 22 adjust their equivalent impedances under the control of the control signal. This allows for more reasonable control of the speed and amplitude of the pull-up or pull-down operation on the bus 60, thereby improving the driving capability of the signal on the bus 60.

[0059] In some embodiments of the present disclosure, reference Figure 8 The pull-up adjustable resistance unit 21 includes: a plurality of pull-up adjustable transistors 211. The drains of the plurality of pull-up adjustable transistors 211 are connected to the power supply VDD, and the sources of the plurality of pull-up adjustable transistors 211 are connected to the bus 60. The gate of each pull-up adjustable transistor 211 receives a corresponding pull-up adjustable control signal Pup.

[0060] In some embodiments of the present disclosure, reference Figure 8 The pull-down adjustable resistance unit 22 includes a plurality of pull-down adjustable transistors 221. The drains of the plurality of pull-down adjustable transistors 221 are connected to the ground terminal VSS, and the sources of the plurality of pull-down adjustable transistors 221 are connected to the bus 60. The gate of each pull-down adjustable transistor 221 receives a corresponding pull-down adjustable control signal Pdn.

[0061] In some embodiments of the present disclosure, reference Figure 9 The pull-up adjustable resistor unit 21 further includes a third protection resistor 212 . One end of the third protection resistor 212 is connected to the sources of the plurality of pull-up adjustable transistors 211 ; the other end of the third protection resistor 212 is connected to the bus 60 .

[0062] In some embodiments of the present disclosure, reference Figure 9 The pull-down adjustable resistor unit 22 further includes a fourth protection resistor 222 . One end of the fourth protection resistor 222 is connected to the sources of the plurality of pull-down adjustable transistors 221 ; the other end of the fourth protection resistor 222 is connected to the bus 60 .

[0063] In the embodiments of the present disclosure, reference Figure 8 or Figure 9 The gate of each pull-up adjustable transistor 211 receives the pull-up adjustable control signal Pup <0> ~Pup <n>Furthermore, each pull-up adjustable transistor 211 is turned on or off in response to the pull-up adjustable control signal it receives. For example, if the pull-up adjustable control signal Pup <0> If the value of the pull-up adjustable control signal Pup is "0", the first pull-up adjustable transistor 211 can be controlled to turn on; <0> If the value of is "1", the first pull-up adjustable transistor 211 can be controlled to be turned off. <0> ~Pup <n>The number of "0"s or "1"s in the pull-up resistor 21 is determined by the number of pull-up adjustable transistors 211 that need to be turned on. Since the impedance between the source and drain of a transistor is different when it is turned on or off, the equivalent impedance of the pull-up adjustable resistor unit 21 can be adjusted by controlling the number of pull-up adjustable transistors 211 that are turned on.

[0064] Correspondingly, the gate of each pull-down adjustable transistor 221 receives the pull-down adjustable control signal Pdn. <0> ~Pdn <n>Furthermore, each pull-down adjustable transistor 221 is turned on or off in response to the pull-down adjustable control signal it receives. For example, if the pull-down adjustable control signal Pdn <0> If the value of the pull-down adjustable control signal Pdn is "1", the first pull-down adjustable transistor 221 can be controlled to turn on; <0> If the value of is "0", the first pull-down adjustable transistor 221 can be controlled to be turned off. <0> ~Pdn <n>The number of "0" or "1" in the pull-down adjustable resistor 22 is determined by the number of pull-down adjustable transistors 221 that need to be turned on. In this way, the equivalent impedance of the pull-down adjustable resistor unit 22 can be adjusted by controlling the number of pull-down adjustable transistors 221 that are turned on.

[0065] In the embodiments of the present disclosure, reference Figure 9 The third protection resistor 212 is connected between the sources of the multiple pull-up adjustable transistors 211 and the connection bus 60; the fourth protection resistor 222 is connected between the sources of the multiple pull-down adjustable transistors 221 and the bus 60. In this way, the current in the pull-up adjustable transistors 211 or the pull-down adjustable transistors 221 can be limited to prevent damage to the transistors due to excessive current.

[0066] It is understood that by controlling the number of pull-up adjustable transistors 211 or pull-down adjustable transistors 221 that are turned on, the equivalent impedance of the pull-up adjustable resistor unit 21 or the pull-down adjustable resistor unit 22 can be adjusted. In this way, the speed and amplitude of the pull-up or pull-down operation can be more reasonably controlled during the process of pulling up or pulling down the voltage on the bus 60, thereby improving the driving capability of the signal on the bus 60.

[0067] The embodiment of the present disclosure also provides a memory.

[0068] In some embodiments of the present disclosure, Figure 10 As shown, the memory 80 includes an output driving circuit 10. The output driving circuit 10 includes the technical features of the aforementioned embodiment, which will not be described in detail here.

[0069] In some embodiments of the present disclosure, Figure 11 As shown, the memory 80 includes an impedance calibration circuit 20. The impedance calibration circuit 20 includes the technical features of the aforementioned embodiments, which will not be described in detail here.

[0070] In some embodiments of the present disclosure, reference Figure 10 or Figure 11 The memory 80 may be a DRAM (dynamic random access memory). The DRAM may be any one of DDR4 (4th generation double data rate synchronous dynamic random access memory), DDR5 (5th generation double data rate synchronous dynamic random access memory), LPDDR4 (4th generation low power double data rate synchronous dynamic random access memory), and LPDDR5 (5th generation low power double data rate synchronous dynamic random access memory).

[0071] It should be noted that, in this document, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a..." does not preclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0072] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments when there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments when there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments when there is no conflict.

[0073] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.< / n> < / n> < / n> < / n>

Claims

1. An output drive circuit, characterized in that: The output drive circuit includes: a pull-up main transistor and a pull-down main transistor; The pull-up main transistor and the pull-down main transistor are both N-type MOS transistors; The source of the pull-up main transistor and the drain of the pull-down main transistor are both connected to a bus; The drain of the pull-up main transistor is connected to a power supply, and the gate of the pull-up main transistor receives a pull-up main control signal; the source of the pull-down main transistor is grounded, and the gate of the pull-down main transistor receives a pull-down main control signal; the pull-up main control signal and the pull-down main control signal are in opposite phases; The substrate and source of the pull-up main transistor are short-circuited.

2. The output drive circuit according to claim 1, wherein: The pull-up main transistor is arranged in a deep N-well region; The voltage on the deep N-well region is greater than or equal to the voltage on the substrate and the source of the pull-up main transistor.

3. The output drive circuit according to claim 2, wherein: The voltage on the substrate and source of the pull-up main transistor is 0-0.5V; The voltage on the gate of the pull-up main transistor is 0 to 1.05V; The voltage on the drain of the pull-up main transistor is 0.5V; The voltage on the deep N-well region is 0.5V.

4. The output drive circuit according to any one of claims 1 to 3, characterized in that: The output drive circuit further includes: a first protection resistor and a second protection resistor; The first protection resistor is connected between the source of the pull-up main transistor and the bus; The second protection resistor is connected between the drain of the pull-down main transistor and the bus.

5. An impedance calibration circuit, characterized in that: The impedance calibration circuit comprises: the output driving circuit according to any one of claims 1 to 4, and a pull-up adjustable resistance unit and a pull-down adjustable resistance unit; The pull-up adjustable resistance unit is connected between the power supply and the bus, and is configured to receive and respond to a multi-bit pull-up adjustable control signal to adjust its own equivalent impedance; The pull-down adjustable resistance unit is connected between the ground terminal and the bus, and is configured to receive and respond to a multi-bit pull-down adjustable control signal to adjust its own equivalent impedance.

6. The impedance calibration circuit according to claim 5, characterized in that: The pull-up adjustable resistance unit includes: a plurality of pull-up adjustable transistors; The drains of the plurality of pull-up adjustable transistors are all connected to the power supply, and the sources of the plurality of pull-up adjustable transistors are all connected to the bus; The gate of each pull-up adjustable transistor receives one bit of the pull-up adjustable control signal accordingly.

7. The impedance calibration circuit according to claim 6, wherein: The pull-up adjustable resistor unit further includes: a third protection resistor; One end of the third protection resistor is connected to the sources of the plurality of pull-up adjustable transistors; the other end of the third protection resistor is connected to the bus.

8. The impedance calibration circuit according to claim 5, wherein: The pull-down adjustable resistance unit includes: a plurality of pull-down adjustable transistors; The drains of the plurality of pull-down adjustable transistors are all connected to the ground terminal, and the sources of the plurality of pull-down adjustable transistors are all connected to the bus; The gate of each pull-down adjustable transistor receives one bit of the pull-down adjustable control signal accordingly.

9. The impedance calibration circuit according to claim 8, characterized in that: The pull-down adjustable resistor unit further includes: a fourth protection resistor; One end of the fourth protection resistor is connected to the sources of the plurality of pull-down adjustable transistors; the other end of the fourth protection resistor is connected to the bus.

10. A memory, characterized in that: The memory includes the output driving circuit according to any one of claims 1 to 4, or the memory includes the impedance calibration circuit according to any one of claims 5 to 9.

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