Low-stray low-jitter frequency synthesizer circuit

Abstract

The invention discloses a low-stray and low-jitter frequency synthesizer which is composed of a phase error averaging circuit, a notch filter circuit and a local oscillator and feedback clock generating circuit. According to the circuit, a notch filter is added behind a loop filter, and notch is carried out at a reference frequency to suppress periodic modulation of the reference frequency on a voltage-controlled oscillator, so that reference spurious is suppressed; meanwhile, the invention provides a phase error averaging circuit for averaging quantization errors generated by an error summation modulator module in an instantaneous state, and suppressing quantization noise, thereby reducing decimal stray and decimal jitter.

Description

Technical Field

[0001] The invention relates to a frequency synthesizer circuit, belonging to the technical field of integrated circuits, and in particular to a frequency synthesizer circuit with low spurious and low jitter. Background Art

[0002] With the rapid development of communication systems and the increasing scale of integrated circuit usage, systems on chip have become ubiquitous. The clock generation module plays a vital role in the communication system, which determines the bit error rate of the entire communication system. The frequency synthesizer has been widely used in the communication system due to its high frequency accuracy, wide adjustable range and narrow frequency step.

[0003] In traditional frequency synthesizer circuits, an external reference clock is generally connected, and the frequency synthesizer is periodically adjusted at the clock frequency. This will cause the voltage-controlled oscillator to be periodically modulated, resulting in reference spurious, which in turn causes interference with adjacent channels.

[0004] In terms of fractional frequency division, an error sum modulator is generally used to periodically modulate the frequency divider to achieve fractional frequency division. However, in each reference clock cycle, the frequency divider's division coefficient is still an integer, not a true fraction, and there is still a phase error with the reference clock, which is reflected in the output of the frequency synthesizer as large jitter and fractional spurs. Summary of the invention

[0005] The object of the present invention is to overcome the above-mentioned disadvantages and provide a low-spurious and low-jitter frequency synthesizer circuit, which has the advantages of low integer spurious, fractional spurious, low integer jitter and fractional jitter.

[0006] In view of the existing technology and the above-mentioned shortcomings, the present invention adopts the following design scheme to achieve:

[0007] A low-spurious and low-jitter frequency synthesizer circuit comprises a local oscillator and feedback clock generating circuit, a notch filter circuit, a local oscillator and feedback clock generating circuit, a phase error averaging circuit, an input end of which is connected to the output end of the local oscillator and feedback clock generating circuit, and an output end of which is connected to the input end of the notch filter circuit, and is used to retain 32 divided phases, and compare the 32 divided phases with a reference clock through a frequency detector and phase detector array, generate corresponding lead-lag signals, and control the charging and discharging of a charge pump array, and finally average at a loop filter to generate a control signal for a voltage-controlled oscillator; the notch filter circuit, an input end of which is connected to the output end of the phase error averaging circuit, and an output end of which is connected to the input end of the local oscillator and feedback clock generating circuit, and is used to suppress the periodic modulation of the reference clock on the voltage-controlled oscillator, thereby suppressing the reference spurious; the local oscillator and feedback clock generating circuit, an input end of which is connected to the output end of the notch filter circuit, and an output end of which is connected to the input end of the local oscillator and feedback clock generating circuit, and is used to generate an oscillation signal and realize the fractional frequency division function of the overall circuit.

[0008] Furthermore, the phase error averaging circuit includes a fixed delay unit DF, a coarse delay unit DL1, a DL2 unit, a two-to-one selector MUX1, fine delay units D1, D2, D3, D4, D5, D6, D7, D8, an eight-to-one selector MUX2, and a reference clock delay unit Dref composed of them, 32 reference clock delay units form a 32-bit matrix cyclic right shift circuit, a frequency detector array, a charge pump array, and a loop filter; the input of the fixed delay unit DF is connected to the output of the frequency divider, and the output end of DF is connected to the input end of the coarse delay unit DL1; the output end of DL1 is connected to the 1 input end of the two-to-one selector MUX1, and is connected to the output end of the coarse delay unit DL2. The output end of DL2 is connected to the 2 input end of the selector MUX1; the output end of MUX1 is connected to the fine-tuning delay unit D1; the output end of the fine-tuning delay unit D1 is connected to the input end of the fine-tuning delay unit D2, and is also connected to the 1 input end of the eight-to-one selector MUX2; the output end of the fine-tuning delay unit D2 is connected to the input end of the fine-tuning delay unit D3, and is also connected to the 2 input end of the eight-to-one selector MUX2; the output end of the fine-tuning delay unit D3 is connected to the input end of the fine-tuning delay unit D4, and is also connected to the 3 input end of the eight-to-one selector MUX2; the output end of the fine-tuning delay unit D4 is connected to the input end of the fine-tuning delay unit D5, and is also connected to the 4 input end of the eight-to-one selector MUX2 ; The output end of the fine-tuning delay unit D5 is connected to the input end of the fine-tuning delay unit D6, and is also connected to the 5 input end of the eight-choose-one selector MUX2; the output end of the fine-tuning delay unit D6 is connected to the input end of the fine-tuning delay unit D7, and is also connected to the 6 input end of the eight-choose-one selector MUX2; the output end of the fine-tuning delay unit D7 is connected to the input end of the fine-tuning delay unit D8, and is also connected to the 7 input end of the eight-choose-one selector MUX2; the output end of the fine-tuning delay unit D8 is connected to the 8 input end of the eight-choose-one selector MUX2; fixed delay unit DF, coarse delay unit fine delay unit DL1, DL2 unit, two-choose-one selector MUX1, fine delay unit D1, D2, D3, D4, D5, D6, D7, D8, and eight-to-one selector MUX2 form a reference clock delay unit Dref; 32 Dref inputs and outputs are connected, and the connection point is used as an output port. The whole is a 32-bit matrix cyclic right shift circuit with a total of 32 output ports. The output terminals Fdiv<31:0> of the 32-bit matrix cyclic right shift circuit are respectively connected to the DIV terminals of the frequency detector array; the Fref terminal of the frequency detector array is connected to the external reference clock, the output terminal UP is connected to the upper input terminal of the charge pump array, and the output terminal DN is connected to the lower input terminal of the charge pump array; the output terminals of the charge pump array are short-circuited together and connected to the input terminal of the loop filter; the output terminal of the loop filter is connected to the input terminal of the notch filter.

[0009] Furthermore, the notch filter circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, and a third capacitor C3; one end of the first resistor R1 is connected to the output end of the loop filter, and the other end is interconnected with the first resistor R2 and the third capacitor C3; one end of the second resistor R2 is connected to one end of the first resistor R1, is interconnected with the third capacitor C3, and the other end is connected to the second capacitor C2, and is interconnected with the input end of the voltage-controlled oscillator; one end of the third resistor R3 is connected to one end of the first capacitor C1, is interconnected with the second capacitor C2, and the other end is connected to the ground terminal GND; one end of the first capacitor C1 is connected to the output end of the loop filter, and the other end is connected to the second capacitor C2, and is interconnected with the third resistor R3; one end of the second capacitor C2 is connected to the first capacitor C1, is interconnected with the third resistor R3, and the other end is connected to the second resistor R2, and is interconnected with the input end of the voltage-controlled oscillator; one end of the third capacitor C3 is connected to the first resistor R1, is interconnected with the second resistor R2, and the other end is connected to the third resistor R3, and is interconnected with the ground terminal GND.

[0010] Furthermore, the local oscillator and feedback clock generating circuit includes a voltage-controlled oscillator, a high-speed buffer, a PS divider, an error sum modulator module, and a division by seven remainder circuit; the input end of the voltage-controlled oscillator is connected to the second resistor R2 of the notch filter, and is interconnected with the second capacitor C2 of the notch filter, and the output end is connected to the input end of the high-speed buffer, and is interconnected with the input end of the PS divider; the input end of the high-speed buffer is connected to the output end of the voltage-controlled oscillator, and is interconnected with the input end of the PS divider, and the output end serves as the output of the frequency synthesizer; the input end of the PS divider The input end is connected to the input end of the high-speed buffer, connected to the output end of the voltage-controlled oscillator, interconnected to the output end of the division by seven remainder circuit, and the output end is connected to the input end of the 32-bit matrix circulation circuit; the first input end of the error sum modulator module is a 7-bit integer control word Integer<6:0>, the second input end is a 4-bit integer control word Fraction<3:0>, and the output end is connected to the output end of the division by seven remainder circuit; the input of the division by seven remainder circuit is connected to the output end of the error sum modulator module, and the output end is connected to the lower input end of the PS divider.

[0011] The present invention has the following advantages: first, the present invention adopts a notch filter at the reference clock to suppress the periodic modulation of the reference clock on the voltage-controlled oscillator, which can significantly improve the reference spurious performance of the frequency synthesizer; second, the present invention proposes a phase error averaging circuit for averaging the phase error between the feedback clock and the reference clock, which can significantly reduce the fractional jitter and fractional spurious of the frequency synthesizer; third, the present invention proposes a digitally controlled adjustable delay unit for adjusting the delay fluctuation caused by temperature process changes to accurately delay a reference clock cycle, which can significantly improve the accuracy of the delay unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The present invention is a schematic diagram of the circuit structure of a low-spurious and low-jitter frequency synthesizer circuit.

[0013] Figure 2 It is a diagram of integer jitter simulation results of the low-spurious and low-jitter frequency synthesizer circuit of the present invention.

[0014] Figure 3 It is a diagram of integer spurious simulation results of the low-spurious and low-jitter frequency synthesizer circuit of the present invention.

[0015] Figure 4 It is a diagram of the fractional jitter simulation result of the low-spurious and low-jitter frequency synthesizer circuit of the present invention.

[0016] Figure 5 It is a diagram of the fractional spurious simulation results of the low-spurious and low-jitter frequency synthesizer circuit of the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. Examples of these embodiments are illustrated in the accompanying drawings. The embodiments of the present invention shown in the accompanying drawings and described according to the accompanying drawings are merely exemplary and are not limited to these embodiments.

[0018] In addition, it should be noted that in order to avoid obscuring the present invention due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the accompanying drawings, while other details that are not very relevant to the present invention are omitted.

[0019] Also, in the description of the present invention, the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0020] See also Figures 1 to 5 , the embodiment of the present invention includes:

[0021] like Figure 1 As shown, an embodiment of the present invention includes: a low-spurious and low-jitter frequency synthesizer provided by the present invention includes a phase error averaging circuit, a notch filter circuit, a local oscillator and feedback clock generating circuit, and its functions and implementation methods are described below respectively.

[0022] The phase error averaging circuit is used to average the phase error between the frequency-divided signal and the reference signal to reduce digital jitter and fractional spurious signals and provide a control voltage for the voltage-controlled oscillator; the notch filter circuit is used to suppress the energy at the reference clock frequency, thereby reducing the periodic modulation of the reference clock on the voltage-controlled oscillator and thus reducing the reference spurious signals; the local oscillator and feedback clock generation are used to generate an oscillation signal and realize the fractional frequency division function of the overall circuit.

[0023] Continue reading Figure 1As shown, in an embodiment of the present invention, the phase error averaging circuit includes a fixed delay unit DF, a coarse delay unit, a fine delay unit DL1, a DL2 unit, a two-to-one selector MUX1, fine delay units D1, D2, D3, D4, D5, D6, D7, D8, an eight-to-one selector MUX2, and a reference clock delay unit Dref composed of them, 32 reference clock delay units form a 32-bit matrix cyclic right shift circuit, a frequency detector array, a charge pump array, and a loop filter; the input of the fixed delay unit DF is connected to the output of the divider, and the output end of DF is connected to the input end of the coarse delay unit DL1; the output end of DL1 is connected to the 1 input end of the two-to-one selector MUX1, and The output end of DL2 is connected to the input end of the coarse-tuning delay unit DL2; the output end of DL2 is connected to the input end 2 of the selector MUX1; the control end of the selector MUX1 is controlled by the outside world, and the output end of MUX1 is connected to the fine-tuning delay unit D1; the output end of the fine-tuning delay unit D1 is connected to the input end of the fine-tuning delay unit D2, and is also connected to the input end 1 of the eight-to-one selector MUX2; the output end of the fine-tuning delay unit D2 is connected to the input end of the fine-tuning delay unit D3, and is also connected to the input end 2 of the eight-to-one selector MUX2; the output end of the fine-tuning delay unit D3 is connected to the input end of the fine-tuning delay unit D4, and is also connected to the input end 3 of the eight-to-one selector MUX2; the output end of the fine-tuning delay unit D4 is connected to the fine-tuning delay unit D5 The input end of the fine-tuning delay unit D5 is connected to the input end of the fine-tuning delay unit D6, and is also connected to the 5 input end of the eight-to-one selector MUX2; the output end of the fine-tuning delay unit D6 is connected to the input end of the fine-tuning delay unit D7, and is also connected to the 6 input end of the eight-to-one selector MUX2; the output end of the fine-tuning delay unit D7 is connected to the input end of the fine-tuning delay unit D8, and is also connected to the 7 input end of the eight-to-one selector MUX2; the output end of the fine-tuning delay unit D8 is connected to the 8 input end of the eight-to-one selector MUX2; the fixed delay unit DF, the coarse delay unit, the fine delay unit DL1, DL2 unit, the two-to-one selector MUX1, fine-tuning delay units D1, D2, D3, D4, D5, D6, D7, D8, and eight-to-one selector MUX2 form a reference clock delay unit Dref; 32 Dref inputs and outputs are connected, and the connection point is used as an output port. The whole is a 32-bit matrix cyclic right shift circuit, with a total of 32 output ports (Fdiv<31:0>). The output end Fdiv<31:0> of the 32-bit matrix cyclic right shift circuit is respectively connected to the DIV end of the phase frequency detector array; the Fref end of the phase frequency detector array (PFD) is connected to the external reference clock, the output end UP is connected to the upper input end of the charge pump array (CP), and the output end DN is connected to the lower input end of the charge pump array (CP);The output ends of the charge pump array (CP) are short-circuited together and connected to the input end of the loop filter (LPF); the output end of the loop filter (LPF) is connected to the input end of the notch filter (Notch Filter). ;

[0024] The notch filter circuit of the present invention comprises a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, and a third capacitor C3; one end of the first resistor R1 is connected to the output end of the loop filter, and the other end is interconnected with the first resistor R2 and the third capacitor C3; one end of the second resistor R2 is connected to one end of the first resistor R1 and is interconnected with the third capacitor C3, and the other end is connected to the second capacitor C2 and is interconnected with the input end of a voltage controlled oscillator (VCO); one end of the third resistor R3 is connected to one end of the first capacitor C1, The first capacitor C1 is connected to the output terminal of the loop filter (LPF), and the other end is connected to the second capacitor C2, and is interconnected to the third resistor R3; the second capacitor C2 is connected to the first capacitor C1, is interconnected to the third resistor R3, and the other end is connected to the second resistor R2, and is interconnected to the input terminal of the voltage controlled oscillator (VCO); the third capacitor C3 is connected to the first resistor R1, is interconnected to the second resistor R2, and the other end is connected to the third resistor R3, and is interconnected to the ground terminal GND.

[0025] The local oscillator and feedback clock generating circuit of the present invention comprises a voltage controlled oscillator (VCO), a high speed buffer (Buffer), a PS divider (PSdivider), an error sum modulator module (DSM), and a divide-by-seven remainder circuit; the input end of the voltage controlled oscillator (VCO) is connected to the second resistor R2 of the notch filter (Notch Filter), and the input end of the voltage controlled oscillator (VCO) is connected to the second resistor R2 of the notch filter (Notch Filter). The second capacitor C2 of the filter is interconnected, and the output end is connected to the input end of the high-speed buffer (Buffer) and the input end of the PS divider (PSdivider); the input end of the high-speed buffer (Buffer) is connected to the output end of the voltage-controlled oscillator (VCO), and is interconnected with the input end of the PS divider (PSdivider), and the output end is used as the output of the frequency synthesizer; the input end of the PS divider (PSdivider) is connected to the input end of the high-speed buffer (Buffer), is connected to the output end of the voltage-controlled oscillator (VCO), is interconnected with the output end of the division-by-seven remainder circuit, and the output end is connected to the input end of the 32-bit matrix circulation circuit; the first input end of the error sum modulator module (DSM) is a 7-bit integer control word Integer<6:0>, the second input end is a 4-bit integer control word Fraction<3:0>, and the output end is connected to the output end of the division-by-seven remainder circuit; the input of the division-by-seven remainder circuit is connected to the output end of the error sum modulator module (DSM), and the output end is connected to the lower input end of the PS divider (PSdivider).

[0026] Below Figure 1 The specific working principle and performance of the low-spurious and low-jitter frequency synthesizer shown are introduced in detail.

[0027] The phase error averaging circuit of the present invention is used for averaging the phase difference between the reference frequency and the frequency divider caused by the quantization error of the error sum modulator module (DSM). The phase error averaging circuit is composed of a fixed delay unit DF, a coarse adjustment delay unit DL1, a DL2 unit, a two-choice selector MUX1, a fine adjustment delay unit D1, D2, D3, D4, D5, D6, D7, D8, an eight-choice selector MUX2, and a reference clock delay unit Dref composed of them, 32 reference clock delay units form a 32-bit matrix cyclic right shift circuit, a frequency detector array, a charge pump array, and a loop filter. The fixed delay unit DF provides a fixed delay. The coarse adjustment delay unit and the fine adjustment delay unit DL1, DL2 provide a wide delay adjustment range. The two-choice selector MUX1 selects whether to output at the coarse adjustment delay unit DL1 or the coarse adjustment delay unit DL2. Fine-tuning delay units D1, D2, D3, D4, D5, D6, D7, and D8 provide a narrow delay adjustment range. The eight-to-one selector MUX2 selects the outputs of the fine-tuning delay units D1 to D8. The fixed delay unit DF, the coarse-tuning delay unit DL1, and the DL2 unit, the two-to-one selector MUX1, the fine-tuning delay unit D1, D2, D3, D4, D5, D6, D7, and D8, and the eight-to-one selector MUX2 form a reference clock delay unit Dref. The reference clock delay unit Dref provides a reference clock delay and outputs it to each sub-phase frequency detector (PFD). The 32 reference clock delay units form a 32-bit matrix cyclic right shift circuit, which delays the waveform generated by the PS divider (PSdivider) by 32 reference clock cycles. The phase frequency detector (PFD) array is used to compare the phase difference between the signal of the 32-bit output port (Fdiv<31:0>) of the 32-bit matrix cyclic right shift circuit and the reference clock signal (Fref). If the reference signal (Fref) is ahead of the 32-bit matrix cyclic right shift circuit signal, the UP signal of the phase frequency detector (PFD) array is 1 and the DN signal is 0. If the reference signal is ahead of the 32-bit matrix cyclic right shift circuit signal, the UP signal of the phase frequency detector array is 0 and the DN signal is 1. The charge pump (CP) array is used to charge and discharge the loop filter (LPF). If the input UP signal is 1 and the DN signal is 0, the charge pump (CP) array is used to charge the loop filter (LPF). If the input UP signal is 0 and the DN signal is 1, the charge pump (CP) array is used to discharge the loop filter (LPF). The loop filter (LPF) is used to adjust the loop parameters of the entire frequency synthesizer to stabilize the entire frequency synthesizer loop.

[0028] The notch filter of the present invention is used to suppress the periodic modulation of the reference frequency on the voltage controlled oscillator (VCO), thereby reducing the reference spurious. The notch filter is composed of a resistor R 1 -R3 , capacitor C 1 -C 3 Composition. Resistor R 1 , resistor R 2 , capacitor C 1 To form a low-pass filter, the resistor R 1 , capacitor C 1 , capacitor C 2 The low-pass filter and the high-pass filter are combined to form a notch filter, and the notch frequency of the notch filter is the reference frequency, thereby suppressing the periodic modulation of the reference frequency on the voltage-controlled oscillator (VCO).

[0029] The local oscillator and feedback clock generating circuit of the present invention includes a circuit for generating a local oscillator signal and a frequency division signal. The circuit is composed of a voltage controlled oscillator (VCO), a high-speed buffer (Buffer), a PS frequency divider (PSdivider), an error sum modulator module (DSM), and a seven-remainder circuit. The voltage controlled oscillator (VCO) generates a local oscillator signal under a VTUNE control signal, and the high-speed buffer (Buffer) serves as an output buffer to prevent the influence of external load capacitance on the voltage controlled oscillator (VCO). The PS frequency divider (PSdivider) divides the local oscillator signal, and the error sum modulator module (DSM) is used to generate a dynamic frequency division coefficient, the average value of the dynamic frequency division coefficient is the set Integer<6:0>+Fraction<3:0>, Integer<6:0> is used as the integer part of the frequency division coefficient, and Fraction<3:0> is used as the decimal part of the frequency division coefficient. The seven-remainder circuit converts the dynamic frequency division coefficient generated by the error sum modulator module (DSM) into a control signal of the PS frequency divider (PSdivider).

[0030] Figure 2 This is the integer jitter simulation result of a low-spurious and low-jitter frequency synthesizer circuit of the present invention. As can be seen from the figure, in integer mode, the fractional root mean square jitter (RMS Jitter) of the frequency synthesizer is 130fs.

[0031] Figure 3 This is a reference spurious simulation result diagram of a low spurious and low jitter frequency synthesizer circuit of the present invention. It can be seen from the figure that when the frequency synthesizer operates at a frequency of 1.571GHz, the difference between the frequency energy of the reference frequency (16.368MHz) deviation and the center oscillation frequency is 83.9dB, that is, the reference spurious is -83.9dBc.

[0032] Figure 3This is the fractional jitter simulation result of a low-spurious and low-jitter frequency synthesizer circuit of the present invention. As can be seen from the figure, in the fractional mode, the fractional root mean square jitter (RMS Jitter) of the frequency synthesizer is 537.59fs.

[0033] Figure 4 This is a simulation result diagram of integer spurious signals of a low spurious and low jitter frequency synthesizer circuit of the present invention. It can be seen from the figure that when the frequency synthesizer operates at a frequency of 1.572346 GHz, the difference between the frequency energy of the fractional frequency (1.0000061 MHz) deviation and the center oscillation frequency is about 65.29 dB, that is, the fractional spurious signal is -65.29 dBc.

[0034] In addition, it should be noted that in this specification, "includes", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0035] It should be understood that although this specification is described according to implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A low spurious and low jitter frequency synthesizer circuit, characterized in that: The invention comprises a phase error averaging circuit, a notch filter circuit, and a local oscillator and feedback clock generating circuit. The phase error averaging circuit has an input end connected to an output end of a local oscillator and feedback clock generating circuit, and an output end connected to an input end of a notch filter circuit. The phase error averaging circuit is used to retain 32 divided phases, and compare the 32 divided phases with a reference clock through a frequency detector and phase detector array to generate corresponding lead-lag signals, and control the charging and discharging of a charge pump array, and finally average the phases at a loop filter to generate a control signal for a voltage-controlled oscillator. The notch filter circuit has an input end connected to an output end of the phase error averaging circuit, and an output end connected to an input end of a local oscillator and feedback clock generating circuit. The notch filter circuit is used to suppress periodic modulation of the reference clock on the voltage-controlled oscillator, thereby suppressing reference spurious. The local oscillator and feedback clock generating circuit has an input end connected to an output end of a notch filter circuit, and an output end connected to an input end of a local oscillator and feedback clock generating circuit. The local oscillator and feedback clock generating circuit is used to generate an oscillation signal and realize the fractional frequency division function of the overall circuit.

2. The low-spurious and low-jitter frequency synthesizer circuit according to claim 1, characterized in that: The phase error averaging circuit comprises a fixed delay unit DF, a coarse delay unit DL1, a DL2 unit, a two-to-one selector MUX1, fine delay units D1, D2, D3, D4, D5, D6, D7, D8, an eight-to-one selector MUX2, and a reference clock delay unit Dref composed of the same, 32 reference clock delay units Dref form a 32-bit matrix cyclic right shift circuit, a frequency detector array, a charge pump array, and a loop filter; the input of the fixed delay unit DF is connected to the output of the frequency divider, and the output end of DF is connected to the input end of the coarse delay unit DL1; the output end of DL1 is connected to the 1 input end of the two-to-one selector MUX1, and is connected to the input end of the coarse delay unit DL2; D The output end of L2 is connected to the 2 input end of the selector MUX1; the control end of the selector MUX1 is controlled by the outside world, and the output end of MUX1 is connected to the fine-tuning delay unit D1; the output end of the fine-tuning delay unit D1 is connected to the input end of the fine-tuning delay unit D2, and is also connected to the 1 input end of the eight-to-one selector MUX2; the output end of the fine-tuning delay unit D2 is connected to the input end of the fine-tuning delay unit D3, and is also connected to the 2 input end of the eight-to-one selector MUX2; the output end of the fine-tuning delay unit D3 is connected to the input end of the fine-tuning delay unit D4, and is also connected to the 3 input end of the eight-to-one selector MUX2; the output end of the fine-tuning delay unit D4 is connected to the input end of the fine-tuning delay unit D5, and is also connected to the 4 input terminals; the output terminal of the fine-tuning delay unit D5 is connected to the input terminal of the fine-tuning delay unit D6, and is also connected to the 5 input terminal of the eight-to-one selector MUX2; the output terminal of the fine-tuning delay unit D6 is connected to the input terminal of the fine-tuning delay unit D7, and is also connected to the 6 input terminal of the eight-to-one selector MUX2; the output terminal of the fine-tuning delay unit D7 is connected to the input terminal of the fine-tuning delay unit D8, and is also connected to the 7 input terminal of the eight-to-one selector MUX2; the output terminal of the fine-tuning delay unit D8 is connected to the 8 input terminal of the eight-to-one selector MUX2; the fixed delay unit DF, the coarse delay unit, the fine delay unit DL1, DL2 units, the two-to-one selector MUX1, the fine delay unit D1, D2, D3, D4, D 5, D6, D7, D8, and eight-to-one selector MUX2 form a reference clock delay unit Dref; 32 Dref inputs and outputs are connected end to end, and the connection point is used as an output port. The whole is a 32-bit matrix cyclic right shift circuit with a total of 32 output ports. The output terminals Fdiv<31:0> of the 32-bit matrix cyclic right shift circuit are respectively connected to the DIV terminals of the frequency detector array; the Fref terminal of the frequency detector array is connected to the external reference clock, the output terminal UP is connected to the upper input terminal of the charge pump array, and the output terminal DN is connected to the lower input terminal of the charge pump array; the output terminals of the charge pump array are short-circuited together and connected to the input terminal of the loop filter; the output terminal of the loop filter is connected to the input terminal of the notch filter.

3. The low-spurious and low-jitter frequency synthesizer circuit according to claim 1, characterized in that: The notch filter circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, and a third capacitor C3; one end of the first resistor R1 is connected to the output end of the loop filter, and the other end is interconnected with the first resistor R2 and the third capacitor C3; one end of the second resistor R2 is connected to one end of the first resistor R1, is interconnected with the third capacitor C3, and the other end is connected to the second capacitor C2 and is interconnected with the input end of the voltage-controlled oscillator; one end of the third resistor R3 is connected to one end of the first capacitor C1, is interconnected with the second capacitor C2, and the other end is connected to the ground terminal GND; one end of the first capacitor C1 is connected to the output end of the loop filter, and the other end is connected to the second capacitor C2 and is interconnected with the third resistor R3; one end of the second capacitor C2 is connected to the first capacitor C1, is interconnected with the third resistor R3, and the other end is connected to the second resistor R2 and is interconnected with the input end of the voltage-controlled oscillator; one end of the third capacitor C3 is connected to the first resistor R1, is interconnected with the second resistor R2, and the other end is connected to the third resistor R3 and is interconnected with the ground terminal GND.

4. The low-spurious and low-jitter frequency synthesizer circuit according to claim 1, characterized in that: The local oscillator and feedback clock generating circuit comprises a voltage controlled oscillator, a high-speed buffer, a PS frequency divider, an error sum modulator module, and a division by seven remainder circuit; the input end of the voltage controlled oscillator is connected to the second resistor R2 of the notch filter, is interconnected with the second capacitor C2 of the notch filter, and the output end is connected to the input end of the high-speed buffer, and is interconnected with the input end of the PS frequency divider; the input end of the high-speed buffer is connected to the output end of the voltage controlled oscillator, is interconnected with the input end of the PS frequency divider, and the output end serves as the output of the frequency synthesizer; the input end of the PS frequency divider is connected to the input end of the high-speed buffer, is connected to the output end of the voltage controlled oscillator, is interconnected with the output end of the division by seven remainder circuit, and the output end is connected to the input end of the 32-bit matrix circulation circuit; the first input end of the error sum modulator module is a 7-bit integer control word Integer<6:0>, the second input end is a 4-bit integer control word Fraction<3:0>, and the output end is connected to the output end of the division by seven remainder circuit; the input of the division by seven remainder circuit is connected to the output end of the error sum modulator module, and the output end is connected to the lower input end of the PS frequency divider.

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