Reference voltage generation circuit and memory

Abstract

The present disclosure relates to the field of semiconductor circuit design, and in particular to a reference voltage generating circuit and a memory. The reference voltage generating circuit includes: an initial reference voltage generating module, which generates a first initial reference voltage, a second initial reference voltage, a third initial reference voltage, and a fourth initial reference voltage based on an original code, a first code, and a second code; a first selection circuit, which is configured to select, based on a first voltage selection signal, to output a first reference voltage based on the first initial reference voltage or the second initial reference voltage, and to select, based on the first voltage selection signal, to output a second reference voltage based on the third initial reference voltage or the fourth initial reference voltage; and a second selection circuit, which is configured to select, based on a second voltage selection signal, to output a reference voltage based on the first reference voltage or the second reference voltage, so as to improve the accuracy of data sampling in the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a reference voltage generating circuit and a memory. Background Art

[0002] In the design of memory receiver circuits, the data to be sampled is usually sampled based on the valid edge of the sampling clock. The sampling of the data to be sampled is to compare the level of the data to be sampled with a reference voltage. If the level of the data to be sampled is greater than the reference voltage, the output data "1" is the sampling result, that is, the sampling result is a high level. If the level of the data to be sampled is less than the reference voltage, the output data "0" is the sampling result, that is, the sampling result is a low level.

[0003] In high-speed computer links, as data signal transmission speeds increase, significant inter-symbol interference (ISI) is unavoidable. ISI can cause the sampled data level to fail to rise above the reference voltage, resulting in a receiver mis-sampling and outputting a "0" value. Alternatively, it can cause the sampled data level to fail to fall below the reference voltage, resulting in a receiver mis-sampling and outputting a "1" value. Summary of the Invention

[0004] Embodiments of the present disclosure provide a reference voltage generating circuit and a memory to improve the accuracy of data sampling performed by the memory.

[0005] An embodiment of the present disclosure provides a reference voltage generating circuit, comprising: an initial reference voltage generating module, configured to receive an original code, a first code, and a second code, and to generate a first initial reference voltage based on the original code + the first code + the second code, to generate a second initial reference voltage based on the original code + the first code - the second code, to generate a third initial reference voltage based on the original code - the first code + the second code, and to generate a fourth initial reference voltage based on the original code - the first code - the second code; a first selection circuit, configured to receive the first initial reference voltage, the second initial reference voltage, the third initial reference voltage, the fourth initial reference voltage, and a first voltage selection signal, and to generate a first reference voltage based on the first voltage. The selection signal selects to output the first reference voltage based on the first initial reference voltage or the second initial reference voltage; the first selection circuit is further configured to select to output the second reference voltage based on the third initial reference voltage or the fourth initial reference voltage based on the first voltage selection signal; the second selection circuit is used to receive the first reference voltage, the second reference voltage and the second voltage selection signal, and is configured to select to output the reference voltage based on the first reference voltage or the second reference voltage based on the second voltage selection signal; wherein the output value of the first voltage selection signal is used to consider the influence of the previous second bit data on the current data to be sampled, and the output value of the second voltage selection signal is used to consider the influence of the previous first bit data on the current data to be sampled.

[0006] The reference voltage generating circuit provided in this embodiment generates four reference voltages based on the sampling effect of the previous second bit data on the current data to be sampled DQ, as well as the sampling effect of the previous first bit data on the current data to be sampled DQ. Then, based on the control of the first voltage selection signal and the second voltage selection signal, the adaptive reference voltages are output for sampling by the memory, so as to comprehensively consider the sampling effect of the previous second bit data and the previous first bit data on the current data to be sampled DQ, thereby improving the accuracy of data sampling by the memory.

[0007] Optionally, the initial reference voltage generating module includes: a voltage divider circuit including N voltage output terminals, and each voltage output terminal outputs a different voltage, where N is an integer greater than 1; a decoding circuit for receiving an original code, a first code, and a second code, and configured to generate a first processing signal based on the original code + the first code + the second code, generate a second processing signal based on the original code + the first code - the second code, generate a third processing signal based on the original code - the first code + the second code, and generate a fourth processing signal based on the original code - the first code - the second code; a first processing circuit connected to the voltage divider circuit and the decoding circuit , configured to select the corresponding voltage output terminal in the voltage divider circuit to output the first initial reference voltage based on the first processing signal; the second processing circuit, connected to the voltage divider circuit and the decoding circuit, is configured to select the corresponding voltage output terminal in the voltage divider circuit to output the second initial reference voltage based on the second processing signal; the third processing circuit, connected to the voltage divider circuit and the decoding circuit, is configured to select the corresponding voltage output terminal in the voltage divider circuit to output the third initial reference voltage based on the third processing signal; the fourth processing circuit, connected to the voltage divider circuit and the decoding circuit, is configured to select the corresponding voltage output terminal in the voltage divider circuit to output the fourth initial reference voltage based on the fourth processing signal.

[0008] Optionally, the voltage divider circuit includes: N-1 first resistors connected in series, wherein the first end of the first first resistor is used to receive a first internal voltage, the second end of the last first resistor is used to receive a second internal voltage, and the second end of each first resistor is connected to the first end of the next first resistor; the voltage value of the first internal voltage is greater than the voltage value of the second internal voltage; and the two ends of each first resistor serve as output ports to form N voltage output ends.

[0009] Optionally, the voltage value of the first initial reference voltage is greater than the voltage value of the second initial reference voltage, and the voltage value of the third initial reference voltage is greater than the voltage value of the fourth initial reference voltage.

[0010] Optionally, the original encoded value>the first encoded value>the second encoded value.

[0011] Optionally, the first processing signal includes N first sub-signals, and the N first sub-signals include only one valid signal. The first processing circuit includes: N first switching transistors, and the control end of each first switching transistor receives the corresponding first sub-signal; the first terminal of each first switching transistor is connected to a corresponding voltage output end of the N voltage output ends, and the second terminal is connected to the output end of the first processing circuit to output a first initial reference voltage.

[0012] Optionally, the first selection circuit includes: a first selection unit for receiving a first initial reference voltage, a second initial reference voltage and a first voltage selection signal, and is configured to select, based on the first voltage selection signal, to output the first reference voltage based on the first initial reference voltage or the second initial reference voltage; a second selection unit for receiving a third initial reference voltage, a fourth initial reference voltage and the first voltage selection signal, and is configured to select, based on the first voltage selection signal, to output the second reference voltage based on the third initial reference voltage or the fourth initial reference voltage.

[0013] Optionally, the size of the first code is configured to measure the influence parameter of the previous first bit data on the current data to be sampled, and the size of the second code is configured to measure the influence parameter of the previous second bit data on the current data to be sampled.

[0014] Optionally, the first voltage selection signal is set based on the previous second bit data, and the second voltage selection signal is set based on the previous first bit data.

[0015] Another embodiment of the present disclosure further provides a memory, comprising the reference voltage generating circuit and sampling circuit provided in the above embodiment, wherein a first input terminal of the sampling circuit is used to receive data to be sampled, and a second input terminal is connected to an output terminal of the reference voltage generating circuit for receiving a reference voltage. The sampling circuit is configured to sample the data to be sampled based on the reference voltage to improve the accuracy of data sampling in the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 A schematic diagram showing the influence of the first bit of data and the first two bits of data on the DQ of the sampled data provided in one embodiment of the present disclosure;

[0018] Figure 2 A schematic diagram illustrating the principle of sampling data DQ using different reference voltages provided in an embodiment of the present disclosure;

[0019] Figure 3 A schematic diagram of the structure of a reference voltage generating circuit provided in one embodiment of the present disclosure;

[0020] Figure 4A schematic structural diagram of an initial reference voltage generating module provided in one embodiment of the present disclosure;

[0021] Figure 5 A schematic structural diagram of a voltage divider circuit and a first processing circuit provided in one embodiment of the present disclosure;

[0022] Figure 6 A schematic structural diagram of a first selection circuit provided in one embodiment of the present disclosure;

[0023] Figure 7 A schematic structural diagram of a memory provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] As the background art indicates, in high-speed computer links, as data signal transmission speeds increase, significant inter-symbol interference (ISI) is unavoidable. ISI can cause the level of the sampled data to fail to rise above a reference voltage, leading to a receiver erroneous sampling and output of data "0." Alternatively, it can cause the level of the sampled data to fail to fall below the reference voltage, leading to a receiver erroneous sampling and output of data "1."

[0025] An embodiment of the present disclosure provides a reference voltage generating circuit to improve the accuracy of data sampling in a memory.

[0026] Those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments may be combined and referenced with each other as long as there is no contradiction.

[0027] Figure 1 Schematic diagram of the influence of the first bit data and the first two bits data on the DQ of the sampled data provided in this embodiment, Figure 2 Schematic diagram of the principle of sampling the data DQ to be sampled using different reference voltages provided in this embodiment, Figure 3 This is a schematic diagram of the structure of the reference voltage generating circuit provided in this embodiment, Figure 4 Schematic diagram of the structure of the initial reference voltage generation module provided in this embodiment Figure 5 This is a schematic structural diagram of the voltage divider circuit and the first processing circuit provided in this embodiment. Figure 6 This is a schematic diagram of the structure of the first selection circuit provided in this embodiment. The reference voltage generating circuit provided in this embodiment is described in detail below in conjunction with the accompanying drawings, as follows:

[0028] For the memory, the signal sampling of the memory is implemented based on a comparator. Specifically, the comparator compares the voltage of the data to be sampled DQ with the reference voltage based on the valid edge of the sampling signal. If the voltage of the data to be sampled DQ is greater than the reference voltage, the comparator outputs a high level, that is, data "1". If the voltage of the data to be sampled DQ is less than the reference voltage, the comparator outputs a low level, that is, data "0".

[0029] In high-speed computer links, data signal transmission speeds are getting faster and faster, and the time interval between the effective edges of the sampling clock is getting smaller and smaller to collect more data per unit time. However, this operation causes significant inter-symbol interference (ISI) in the memory sampling.

[0030] For ISI, refer to Figure 1 In one example, when the data DQ to be sampled changes from "0" to "1", due to the decrease in the time interval between the valid edges of the sampling clock, when the valid edge of the sampling clock arrives, the actual level of the data DQ to be sampled has not risen to a sufficient level, which may cause the actual voltage of the data DQ to be sampled to still be lower than the reference voltage at this time, and the comparator may perform erroneous sampling, thereby outputting data "0"; when the data DQ to be sampled changes from "1" to "0", due to the decrease in the time interval between the valid edges of the sampling clock, when the valid edge of the sampling clock arrives, the actual level of the data DQ to be sampled has not dropped to a sufficient level, which may cause the actual voltage of the data DQ to be sampled to still be higher than the reference voltage at this time, and the comparator may perform erroneous sampling, thereby outputting data "1".

[0031] A common solution to the impact of ISI is to set the reference voltages to a high reference voltage (VCH) and a low reference voltage (VCL). Based on the data of the previous bit, the reference voltage used by the comparator to sample the current data DQ to be sampled is adjusted. For example, if the current data bit is "0," the comparator is set to sample the current data DQ to be sampled based on the low reference voltage (VCL). If the current data DQ to be sampled changes from "0" to "1," although the actual level of the data DQ to be sampled has not risen sufficiently, the use of the low reference voltage (VCL) as the reference voltage reduces the likelihood that the actual level of the data DQ to be sampled will be less than the reference voltage, thereby alleviating the impact of ISI to a certain extent. Similarly, if the current data bit is "1," the comparator is set to sample the current data DQ to be sampled based on the high reference voltage (VCL). If the current data DQ to be sampled changes from "1" to "0," although the actual level of the data DQ to be sampled has not fallen sufficiently, the use of the high reference voltage (VCH) as the reference voltage reduces the likelihood that the actual level of the data DQ to be sampled will be greater than the reference voltage, thereby alleviating the impact of ISI to a certain extent.

[0032] However, this solution only considers the impact of the first bit of data on the current data to be sampled DQ, while the second bit of data, the third bit of data, etc. also have a certain impact on the sampling of the current data to be sampled DQ. If only the impact of the first bit of data on the sampling of the current data to be sampled DQ is considered, the comparator will still have the problem of incorrect sampling in actual applications.

[0033] For the influence of the first bit data and the second bit data on the DQ of the sampled data, please refer to Figure 1 , assuming that under ideal conditions, the high level of the data to be sampled DQ is set to 1 and the low level is set to 0; the current one-bit data is "0", the current data to be sampled DQ is about to jump to "1", when the valid edge of the sampling clock arrives, the level of the data to be sampled rises to 0.7, if the previous second bit data is also "0", when the valid edge of the sampling clock arrives, the level of the data to be sampled only rises to 0.6, if the previous second bit data is "1", when the valid edge of the sampling clock arrives, the level of the data to be sampled rises to 0.8; the current one-bit data is "1", when The previous data to be sampled, DQ, is about to jump to "0." When the valid edge of the sampling clock arrives, the level of the data to be sampled drops to 0.3. If the second bit of data before is also "1," the level of the data to be sampled only drops to 0.4 when the valid edge of the sampling clock arrives. If the second bit of data before is "0," the level of the data to be sampled drops to 0.2 when the valid edge of the sampling clock arrives. Therefore, it can be seen that after combining the influence of the second bit of data before and the third bit of data before, etc., the variation range of the current data to be sampled, DQ, is larger, and the memory still has the problem of incorrect sampling.

[0034] In order to consider the influence of the first bit data and the second bit data on the sampled data DQ, refer to Figure 2 In this embodiment, the one reference voltage V is adjusted into two reference voltages V+ and V- in consideration of the influence of the first bit data on the data to be sampled DQ. In addition, the two reference voltages V+ and V- are expanded into four reference voltages V++, V+-, V-+, and V-- in consideration of the influence of the second bit data on the data to be sampled DQ, so as to improve the accuracy of data sampling by the memory.

[0035] Specifically, refer to Figure 3 The reference voltage generating circuit 100 provided in this embodiment includes:

[0036] The initial reference voltage generating module 103 is configured to receive the original code code, the first code c1 and the second code c2, and generate the reference voltage based on the original code code. <a:0>+First code c1 <a:0>+Second code c2 <a:0>Generate a first initial reference voltage Vr1 based on the original code code <a:0>+First code c1 <a:0>-Second code c2 <a:0>Generate a second initial reference voltage Vr2 based on the original code code <a:0>-First code c1 <a:0>+Second code c2 <a:0>Generate a third initial reference voltage Vr3 based on the original code code <a:0>-First code c1 <a:0>-Second code c2 <a:0>A fourth initial reference voltage Vr4 is generated.

[0037] For the initial reference voltage generating module 103, in one example, the larger the code used to generate the initial reference voltage, the larger the initial reference voltage generated; in another example, it can also be set that the larger the code used to generate the initial reference voltage, the smaller the initial reference voltage generated; in the subsequent description of this embodiment, the initial reference voltage generating module 103 is described in detail by taking the example that the larger the code used to generate the initial reference voltage, the larger the initial reference voltage generated.

[0038] Specifically, the initial reference voltage generating module 103 is based only on the original code code <a:0>The generated voltage is the reference voltage V mentioned above, that is, the original code code <a:0>The size of the reference voltage V is used to measure the size of the first code c1 <a:0>The size of the first bit data is used to measure the influence parameter of the current data to be sampled DQ. The initial reference voltage generation module 103 is based on the original code code <a:0>+First code c1 <a:0>The generated voltage is the reference voltage V+△V1, namely the V+ mentioned above; the initial reference voltage generating module 103 is based on the original code code <a:0>-First code c1 <a:0>The generated voltage is the reference voltage V-△V1, which is the V- mentioned above; the second code c2 <a:0>The size of the second bit data is used to measure the influence parameter of the current data to be sampled DQ. The initial reference voltage generation module 103 is based on the original code code <a:0>+First code c1 <a:0>+Second code c2 <a:0>The generated voltage is the reference voltage V+△V1+△V2, that is, the first initial reference voltage Vr1, that is, the V++ mentioned above; the initial reference voltage generating module 103 is based on the original code code <a:0>+First code c1 <a:0>-Second code c2 <a:0>The generated voltage is the reference voltage V+△V1-△V2, that is, the second initial reference voltage Vr2, that is, the V+- mentioned above; the initial reference voltage generating module 103 is based on the original code code <a:0>-First code c1 <a:0>+Second code c2 <a:0>The generated voltage is the reference voltage V-△V1+△V2, that is, the third initial reference voltage Vr3, that is, the V-+ mentioned above; the initial reference voltage generating module 103 is based on the original code code <a:0>-First code c1 <a:0>-Second code c2 <a:0>The generated voltage is the reference voltage V-ΔV1-ΔV2, ie, the fourth initial reference voltage Vr4, ie, the V-- mentioned above.

[0039] As can be seen from the foregoing, under this setting, the voltage value of the first initial reference voltage Vr1 > the voltage value of the second initial reference voltage Vr2 > the voltage value of the third initial reference voltage Vr3 > the voltage value of the fourth initial reference voltage Vr4 .

[0040] Since the original code <a:0>The size of the reference voltage V is used to measure the size of the first code c1 <a:0>The size of the first bit of data is used to measure the impact of the previous first bit of data on the current data to be sampled DQ. The second code c2 <a:0>The size of is used to measure the influence parameter of the previous second bit data on the current data to be sampled DQ, and the influence of the previous first bit data on the current data to be sampled DQ is greater than the influence of the previous second bit data on the current data to be sampled DQ, that is, the original code code <a:0>The value of > first code c1 <a:0>The value of > second code c2 <a:0>value.

[0041] Continue to refer Figure 3 The reference voltage generating circuit 100 further includes: a first selection circuit 101, which is used to receive the first initial reference voltage Vr1, the second initial reference voltage Vr2, the third initial reference voltage Vr3, the fourth initial reference voltage Vr4 and the first voltage selection signal sel1, and is configured to select the first initial reference voltage Vr1 or the second initial reference voltage Vr2 to output the first reference voltage Vref1 based on the first voltage selection signal sel1. The first selection circuit 101 is also configured to select the third initial reference voltage Vr3 or the fourth reference voltage Vr4 to output the second reference voltage Vref2 based on the first voltage selection signal sel1, wherein the output value of the first voltage selection signal sel1 is used to consider the influence of the previous second bit data on the current data to be sampled.

[0042] Specifically, when the previous second-bit data is "0", the first voltage selection signal sel1 is used to control the first selection circuit 101 to output the first reference voltage Vref1 at the second initial reference voltage Vr2, and to output the second reference voltage Vref2 at the fourth initial reference voltage Vr4; that is, it is selected to reduce the influence of the second coding c2 on the basis of the reference voltage V, so as to offset the influence of the previous second-bit data on the sampling of the current data DQ to be sampled; when the previous second-bit data is "1", the first voltage selection signal sel1 is used to control the first selection circuit 101 to output the first reference voltage Vref1 at the first initial reference voltage Vr1, and to output the second reference voltage Vref2 at the third initial reference voltage Vr3; that is, it is selected to increase the influence of the second coding c2 on the basis of the reference voltage V, so as to offset the influence of the previous second-bit data on the sampling of the current data DQ to be sampled.

[0043] In some embodiments, the first voltage selection signal sel1 may be directly set based on the previous second-bit data, so as to feedback-control the selection result of the first selection circuit 101 directly based on the value of the previous second-bit data.

[0044] The second selection circuit 102 is used to receive the first reference voltage Vref1, the second reference voltage Vref2 and the second voltage selection signal sel2, and is configured to select the output reference voltage V based on the first reference voltage Vref1 or the second reference voltage Vref2 based on the second voltage selection signal sel2, wherein the output value of the second voltage selection signal sel2 is used to consider the influence of the previous first bit data on the current data to be sampled.

[0045] Specifically, when the previous first bit data is "0", the second voltage selection signal sel2 is used to control the second selection circuit 102 to output the reference voltage V at the second reference voltage Vref2, wherein the second reference voltage Vref2 is the third initial reference voltage Vr3 or the fourth initial reference voltage Vr4, that is, the influence of the first coding c1 is reduced based on the reference voltage V to offset the sampling influence of the previous first bit data on the current data to be sampled DQ; when the previous first bit data is "1", the second voltage selection signal sel2 is used to control the second selection circuit 102 to output the reference voltage V at the first reference voltage Vref1, wherein the second reference voltage Vref2 is the first initial reference voltage Vr1 or the second initial reference voltage Vr2, that is, the influence of the first coding c1 is increased based on the reference voltage V to offset the sampling influence of the previous first bit data on the current data to be sampled DQ.

[0046] In some embodiments, the second voltage selection signal sel2 may be directly set based on the previous first bit data, so as to directly feedback-control the selection result of the second selection circuit 102 based on the value of the previous first bit data.

[0047] The reference voltage generating circuit provided in this embodiment generates four reference voltages based on the sampling influence of the previous second-bit data on the current data to be sampled DQ, as well as the sampling influence of the previous first-bit data on the current data to be sampled DQ. Then, based on the control of the first voltage selection signal sel1 and the second voltage selection signal sel2, the adapted reference voltages are output for sampling by the memory, so as to comprehensively consider the sampling influence of the previous second-bit data and the previous first-bit data on the current data to be sampled DQ, thereby improving the accuracy of data sampling by the memory.

[0048] For the initial reference voltage generating module 103, in some embodiments, the reference voltage Figure 4 , the initial reference voltage generating module 103 includes:

[0049] The voltage divider circuit 200 includes N voltage output terminals, and each voltage output terminal outputs a different voltage, where N is an integer greater than 1.

[0050] For the voltage divider circuit 200, refer to Figure 5 In one example, the voltage divider circuit 200 includes: N-1 first resistors connected in series, the first end of the first first resistor is used to receive the first internal voltage V1, the second end of the last first resistor is used to receive the second internal voltage V2, and the second end of each first resistor is connected to the first end of the next first resistor; the voltage value of the first internal voltage V1 is greater than the voltage value of the second internal voltage V2, and the two ends of each first resistor serve as output ports to form N voltage output ends.

[0051] Specific reference Figure 5 , N voltage output terminals are used to output voltage Q <0> ~Q <n>, since the resistors for voltage division are all first resistors, the voltage difference between two adjacent voltage output terminals is the same, that is, Q <x>=(V1-V2) / N*x, where x is any integer from 0 to N.

[0052] It should be noted that, in other embodiments, the resistance values ​​of different first resistors may be different. In this case, the voltage difference between two adjacent voltage output terminals is different, but it still meets the Q <n> ＞Q <n-1>>… >Q <1> >Q <0> .

[0053] In some embodiments, the first internal voltage V1 is implemented based on an internal power supply voltage VDD of the memory, and the second internal voltage V2 is implemented based on an internal ground voltage VSS of the memory.

[0054] Continue to refer Figure 4 , decoding circuit 201, for receiving the original code code <a:0>, first code c1 <a:0>and the second code c2 <a:0>The decoding circuit 201 is configured to be based on the original code <a:0>+First code c1 <a:0>+Second code c2 <a:0>Generate a first processed signal based on the original code <a:0>+First code c1 <a:0>-Second code c2 <a:0>Generate a second processed signal based on the original code <a:0>-First code c1 <a:0>+Second code c2 <a:0>Generate a third processed signal based on the original code <a:0>-First code c1 <a:0>-Second code c2 <a:0>A fourth processed signal is generated.

[0055] In an example, assuming a=3, the original code code<3:0>="1000", the first code c1<3:0>="0010", and the second code c2<3:0>="0001", then the first processed signal is "1011", the second processed signal is "1001", the third processed signal is "0111", and the fourth processed signal is "0101".

[0056] The first processing circuit 210 is connected to the voltage divider 200 and the decoding circuit 201 and is configured to select, based on the first processing signal, a corresponding voltage output terminal in the voltage divider 200 to output a first initial reference voltage Vr1. The second processing circuit 220 is connected to the voltage divider 200 and the decoding circuit 201 and is configured to select, based on the second processing signal, a corresponding voltage output terminal in the voltage divider 200 to output a second initial reference voltage Vr2. The third processing circuit 230 is connected to the voltage divider 200 and the decoding circuit 201 and is configured to select, based on the third processing signal, a corresponding voltage output terminal in the voltage divider 200 to output a third initial reference voltage Vr3. The fourth processing circuit 240 is connected to the voltage divider 200 and the decoding circuit 201 and is configured to select, based on the fourth processing signal, a corresponding voltage output terminal in the voltage divider 200 to output a fourth initial reference voltage Vr4.

[0057] For the first processing circuit 210, refer to Figure 5 In some embodiments, the first processed signal includes N first sub-signals (X1 <0> ~X1 <n>), and the N first sub-signals include only one valid signal, the first processing circuit 210 includes: N first switching transistors, the control end of each first switching transistor receives the corresponding first sub-signal, the first terminal of each first switching transistor is connected to the corresponding voltage output end of the N voltage output ends, and the second terminal is connected to the output end of the first processing circuit 210 to output the first initial reference voltage Vr1.

[0058] Specifically, based on the above example, when a=3, the first processed signal, the second processed signal, the third processed signal, and the fourth processed signal are all 4-bit signals, and the 4-bit signal corresponds to 16 binary combinations. At this time, N=15, and the binary signal "0000" corresponds to the first sub-signal X1 <0> To output the corresponding Q <0> , the binary signal "0001" corresponds to the first sub-signal X1 <1> To output the corresponding Q <1> ...the binary signal "1110" corresponds to the first sub-signal X1 <14> To output the corresponding Q <14> , the binary signal "1111" corresponds to the first sub-signal X1 <15> To output the corresponding Q <15> In addition, there is only one valid signal among the N first sub-signals included in the first processed signal, that is, when X1 <0> When output "1" is valid, X1 <1> ~X1 <15> Output is "0" invalid; when X1 <d>When the output is "1", X1 <0> ~X1 <d-1>and X1<d+1> ~X1 <15> An output of "0" is invalid.

[0059] It should be noted that the above example uses X1 <0> ~X1 <n>When the output is "1", it is valid. <0> ~X1 <n>The output is invalid when it is "0". This is just an example and does not limit this embodiment. In other embodiments, it can also be set to X1. <0> ~X1 <n>When the output is "0", it is valid. <0> ~X1 <n>Invalid when output is "1".

[0060] More specifically, in this embodiment, the first processed signal "1011" corresponds to the first sub-signal X1 <11> To output the corresponding Q <11> As the first initial reference voltage Vr1.

[0061] Similarly, for the second processing circuit 220, in some embodiments, the second processed signal includes N second sub-signals (X2 <0> ~X2 <n>), and the N second sub-signals include only one valid signal, the second processing circuit 220 includes: N second switching transistors, the control end of each second switching transistor receives the corresponding second sub-signal, the first terminal of each second switching transistor is connected to the corresponding voltage output end among the N voltage output ends, and the second terminal is connected to the output end of the second processing circuit 220 to output the second initial reference voltage Vr2.

[0062] Accordingly, in this embodiment, the second processed signal "1001" corresponds to the second sub-signal X2 <9> To output the corresponding Q <9> As the second initial reference voltage Vr2.

[0063] Similarly, for the third processing circuit 230, in some embodiments, the third processed signal includes N third sub-signals (X3 <0> ~X3 <n>), and the N third sub-signals include only one valid signal, the third processing circuit 230 includes: N third switching transistors, the control end of each third switching transistor receives the corresponding third sub-signal, the first terminal of each third switching transistor is connected to the corresponding voltage output end among the N voltage output ends, and the second terminal is connected to the output end of the third processing circuit 230 to output the third initial reference voltage Vr3.

[0064] Accordingly, in this embodiment, the third processed signal "0111" corresponds to the third sub-signal X3 <7> To output the corresponding Q <7> As the third initial reference voltage Vr3.

[0065] Similarly, for the fourth processing circuit 240, in some embodiments, the fourth processed signal includes N fourth sub-signals (X4 <0> ~X4 <n>), and the N fourth sub-signals include only one valid signal, the fourth processing circuit 240 includes: N fourth switching transistors, the control end of each fourth switching transistor receives the corresponding fourth sub-signal, the first terminal of each fourth switching transistor is connected to the corresponding voltage output end among the N voltage output ends, and the second terminal is connected to the output end of the fourth processing circuit 240 to output the fourth initial reference voltage Vr4.

[0066] Accordingly, in this embodiment, the fourth processed signal "0101" corresponds to the fourth sub-signal X4 <5> To output the corresponding Q <5> As the fourth initial reference voltage Vr4.

[0067] It should be noted that the relationship between the second processing circuit 220, the third processing circuit 230, the fourth processing circuit 240, the decoding circuit 201 and the voltage divider circuit 200 is the same as that of the first processing circuit 210. Figure 5 The example is directly replaced.

[0068] For the first selection circuit 101, in some embodiments, reference Figure 6 The first selection circuit 101 includes: a first selection unit 110, which is used to receive the first initial reference voltage Vr1, the second initial reference voltage Vr2 and the first voltage selection signal sel1, and is configured to select the first initial reference voltage Vr1 or the second initial reference voltage Vr2 to output the first reference voltage Vref1 based on the first voltage selection signal sel1; a second selection unit 120, which is used to receive the third initial reference voltage Vr3, the fourth initial reference voltage Vr4 and the second voltage selection signal sel2, and is configured to select the third initial reference voltage Vr3 or the fourth initial reference voltage Vr4 to output the second reference voltage Vref2 based on the first voltage selection signal sel1.

[0069] The reference voltage generating circuit provided in this embodiment generates four reference voltages based on the sampling influence of the previous second-bit data on the current data to be sampled DQ, as well as the sampling influence of the previous first-bit data on the current data to be sampled DQ. Then, based on the control of the first voltage selection signal sel1 and the second voltage selection signal sel2, the adapted reference voltages are output for sampling by the memory, so as to comprehensively consider the sampling influence of the previous second-bit data and the previous first-bit data on the current data to be sampled DQ, thereby improving the accuracy of data sampling by the memory.

[0070] It should be noted that the features disclosed in the reference voltage generating circuits provided in the above embodiments can be arbitrarily combined without conflict to obtain new reference voltage generating circuit embodiments.

[0071] Another embodiment of the present disclosure provides a memory, comprising the reference voltage generating circuit and sampling circuit provided by the above embodiments, so as to improve the accuracy of data sampling of the memory.

[0072] Figure 7 This is a schematic diagram of the structure of the memory provided in this embodiment. The memory provided in this embodiment is further described in detail below with reference to the accompanying drawings, as follows:

[0073] refer to Figure 7 The first input terminal of the sampling circuit 400 is used to receive the data to be sampled DQ, and the second input terminal is connected to the output terminal of the reference voltage generating circuit 100 for receiving the reference voltage V. The sampling circuit 400 is configured to sample the data to be sampled DQ based on the reference voltage V.

[0074] Specifically, for the reference voltage generating circuit 100, the reference voltage Figure 3 When the previous second bit data is "0", the first voltage selection signal sel1 is used to control the first selection circuit 101 to output the first reference voltage Vref1 at the second initial reference voltage Vr2, and to output the second reference voltage Vref2 at the fourth initial reference voltage Vr4; that is, the influence of the second coding c2 is reduced based on the reference voltage V to offset the influence of the previous second bit data on the sampling of the current data to be sampled DQ; when the previous second bit data is "1", the first voltage selection signal sel1 is used to control the first selection circuit 101 to output the first reference voltage Vref1 at the first initial reference voltage Vr1, and to output the second reference voltage Vref2 at the third initial reference voltage Vr3; that is, the influence of the second coding c2 is increased based on the reference voltage V to offset the influence of the previous second bit data on the sampling of the current data to be sampled DQ. When the previous first bit data is "0", the second voltage selection signal sel2 is used to control the second selection circuit 102 to output the reference voltage V at the second reference voltage Vref2, where the second reference voltage Vref2 is the third initial reference voltage Vr3 or the fourth initial reference voltage Vr4. That is, the influence of the first coding c1 is reduced based on the reference voltage V to offset the influence of the previous first bit data on the sampling of the current data to be sampled DQ. When the previous first bit data is "1", the second voltage selection signal sel2 is used to control the second selection circuit 102 to output the reference voltage V at the first reference voltage Vref1, where the second reference voltage Vref2 is the first initial reference voltage Vr1 or the second initial reference voltage Vr2. That is, the influence of the first coding c1 is increased based on the reference voltage V to offset the influence of the previous first bit data on the sampling of the current data to be sampled DQ.

[0075] In some embodiments, the first voltage selection signal sel1 can be set directly based on the previous second-bit data to feedback-control the selection result of the first selection circuit 101 directly based on the value of the previous second-bit data. The second voltage selection signal sel2 can be set directly based on the previous first-bit data to feedback-control the selection result of the second selection circuit 102 directly based on the value of the previous first-bit data.

[0076] For the memory provided in this embodiment, four reference voltages are generated based on the sampling influence of the previous second bit data on the current data to be sampled, and the sampling influence of the previous first bit data on the current data to be sampled. Then, based on the control output of the first voltage selection signal and the second voltage selection signal, the adapted reference voltage is provided for sampling by the memory to comprehensively consider the sampling influence of the previous second bit data and the previous first bit data on the current data to be sampled, thereby improving the accuracy of data sampling by the memory.

[0077] It should be noted that the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphic double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it may be a non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0078] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / d> < / n> < / n> < / x> < / n>

Claims

1. A reference voltage generating circuit, characterized in that: include: an initial reference voltage generating module, configured to receive an original code, a first code, and a second code, and generate a first initial reference voltage based on the original code + the first code + the second code, generate a second initial reference voltage based on the original code + the first code - the second code, generate a third initial reference voltage based on the original code - the first code + the second code, and generate a fourth initial reference voltage based on the original code - the first code - the second code; a first selection circuit, configured to receive the first initial reference voltage, the second initial reference voltage, the third initial reference voltage, the fourth initial reference voltage, and a first voltage selection signal, and configured to select, based on the first voltage selection signal, to output a first reference voltage based on the first initial reference voltage or the second initial reference voltage; The first selection circuit is further configured to select, based on the first voltage selection signal, to output a second reference voltage based on the third initial reference voltage or the fourth initial reference voltage; a second selection circuit, configured to receive the first reference voltage, the second reference voltage, and a second voltage selection signal, and configured to select, based on the second voltage selection signal, an output reference voltage based on the first reference voltage or the second reference voltage; The output value of the first voltage selection signal is used to consider the influence of the previous second bit data on the current data to be sampled, and the output value of the second voltage selection signal is used to consider the influence of the previous first bit data on the current data to be sampled; The size of the first code is configured to measure the influence parameter of the previous first bit data on the current data to be sampled, and the size of the second code is configured to measure the influence parameter of the previous second bit data on the current data to be sampled; the size of the original code is used to measure the size of the reference voltage.

2. The reference voltage generating circuit according to claim 1, wherein: The initial reference voltage generating module includes: The voltage divider circuit includes N voltage output terminals, each of which outputs a different voltage, where N is an integer greater than 1; a decoding circuit, configured to receive the original code, the first code, and the second code, and configured to generate a first processed signal by decoding the original code + the first code + the second code, generate a second processed signal by decoding the original code + the first code - the second code, generate a third processed signal by decoding the original code - the first code + the second code, and generate a fourth processed signal by decoding the original code - the first code - the second code; a first processing circuit connected to the voltage divider circuit and the decoding circuit, and configured to select the corresponding voltage output terminal in the voltage divider circuit to output the first initial reference voltage based on the first processing signal; a second processing circuit connected to the voltage divider circuit and the decoding circuit, and configured to select the corresponding voltage output terminal in the voltage divider circuit to output the second initial reference voltage based on the second processed signal; a third processing circuit, connected to the voltage divider circuit and the decoding circuit, and configured to select the corresponding voltage output terminal in the voltage divider circuit to output the third initial reference voltage based on the third processing signal; The fourth processing circuit is connected to the voltage divider circuit and the decoding circuit, and is configured to select the corresponding voltage output terminal in the voltage divider circuit to output the fourth initial reference voltage based on the fourth processing signal.

3. The reference voltage generating circuit according to claim 2, wherein: The voltage divider circuit comprises: N-1 first resistors connected in series, wherein a first end of a first first resistor is used to receive a first internal voltage, a second end of a last first resistor is used to receive a second internal voltage, and the second end of each first resistor is connected to the first end of the next first resistor; A voltage value of the first internal voltage is greater than a voltage value of the second internal voltage; Both ends of each first resistor serve as output ports to form the N voltage output ends.

4. The reference voltage generating circuit according to claim 2, wherein: The voltage value of the first initial reference voltage is greater than the voltage value of the second initial reference voltage, and the voltage value of the third initial reference voltage is greater than the voltage value of the fourth initial reference voltage.

5. The reference voltage generating circuit according to claim 4, wherein: The value of the original code>the value of the first code>the value of the second code.

6. The reference voltage generating circuit according to claim 2, wherein: The first processed signal includes N first sub-signals, and the N first sub-signals include only one valid signal. The first processing circuit includes: N first switch transistors, each first switch transistor having a control terminal corresponding to receiving the corresponding first sub-signal; The first terminal of each first switch transistor is connected to a corresponding one of the N voltage output terminals, and the second terminal is connected to the output terminal of the first processing circuit to output the first initial reference voltage.

7. The reference voltage generating circuit according to claim 1, wherein: The first selection circuit includes: a first selection unit, configured to receive the first initial reference voltage, the second initial reference voltage, and the first voltage selection signal, and configured to select, based on the first voltage selection signal, to output a first reference voltage based on the first initial reference voltage or the second initial reference voltage; The second selection unit is used to receive the third initial reference voltage, the fourth initial reference voltage and the first voltage selection signal, and is configured to select and output a second reference voltage based on the third initial reference voltage or the fourth initial reference voltage based on the first voltage selection signal.

8. The reference voltage generating circuit according to any one of claims 1 to 7, wherein: The first voltage selection signal is set based on the previous second bit data, and the second voltage selection signal is set based on the previous first bit data.

9. A memory, characterized in that: include: The reference voltage generating circuit and sampling circuit according to any one of claims 1 to 8, wherein a first input terminal of the sampling circuit is used to receive data to be sampled, a second input terminal is connected to an output terminal of the reference voltage generating circuit, and is used to receive the reference voltage, and the sampling circuit is configured to sample the data to be sampled based on the reference voltage.

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