METHOD AND APPARATUS FOR FACILITATING DETERMINATION OF LEADERS AND followers OF A SHARED INTERFACE

Abstract

Methods and apparatus for facilitating determining leaders and followers of a shared interface. Methods, apparatus, systems, and articles of manufacture are described for facilitating determining leaders and followers of a shared interface. An example first physical layer includes interface circuitry (300) configured to transmit a first signal to a second physical layer; comparator circuitry (306) configured to compare a second signal from the second physical layer with the first signal; and configuration circuitry (310) configured to facilitate operation as a leader or follower based on the comparison.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of and priority to U.S. Provisional Patent Application No. 63 / 525,729, filed on July 10, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present description relates generally to circuits and, more particularly, to methods and apparatus that facilitate determining leaders and followers of a shared interface. Background Art

[0004] Devices connected via a shared interface transmit and receive data using the shared interface. To facilitate transmission and reception of data via the same shared interface, the connected devices may perform an initialization and / or link training protocol. During the initialization and / or link training protocol, the physical layer of one of the connected devices operates as a leader, while the other connected devices operate as followers. The leader generates a clock signal, performs synchronization operations, and performs framing for the follower devices. The follower devices obtain data from the leader device and are configured based on information from the leader device. Summary of the invention

[0005] Examples of the present specification include a first physical layer, which includes an interface circuit system configured to transmit a first signal to a second physical layer; a comparator circuit system configured to compare a second signal from the second physical layer with the first signal; and a configuration circuit system configured to facilitate operation as a leader or a follower based on the comparison. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 An example system for implementing a physical layer in conjunction with the examples described herein.

[0007] Figure 2 is an example implementation of the physical layer in a vehicle.

[0008] Figure 3 for Figure 1 and / or a block diagram of a circuit system for automatically determining 2.

[0009] Figure 4 To indicate that it is executable to achieve Figure 1-3 A method and / or flowchart of an operation of an automatic determination circuit system.

[0010] Figures 5A-5C Description means executable to achieve Figure 1-3 A method and / or flowchart of an operation of an automatic determination circuit system.

[0011] Figure 6 To illustrate the Figure 1 Timing diagram of two example toning signals output by the physical layer

[0012] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0013] The drawings are not necessarily drawn to scale. Generally, the same reference numerals in the drawings and the specification refer to the same or similar parts. Although the drawings show regions with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In practice, boundaries and / or lines may be unobservable, mixed, and / or irregular.

[0014] In some systems such as automotive systems, devices communicate with each other via network connections. The network connection may include an Ethernet connection, a wired bus, or any other wired or wireless connection. Some network connections include a physical full-duplex interface that facilitates transmission and reception of data on the same shared interface, rather than dedicating one interface to data transmission and a second interface to data reception. For example, connections corresponding to the Institute of Electrical and Electronics Engineers (IEEE) 802.3bw standard and / or the 100BASE-T1 standard utilize a physical full-duplex Ethernet shared interface. Using a shared interface reduces total cable weight, which can reduce material costs, system weight, complexity, and improve fuel efficiency. In order to facilitate the use of a shared interface, a physical layer (PHY) device of a connected device performs a link drain and / or connection establishment protocol. After the PHY is connected, the PHY performs a link training process and the establishment of transmission parameters (frequency, phase, etc.) so that the device can communicate and / or perform mixing or echo cancellation. In order to perform link training, one of the PHY devices is configured to operate as a leader PHY, and the other PHY devices are configured to operate as follower PHY devices. The leader PHY is the PHY of the first device that provides training sequences to the follower device for use during training during link training and / or initialization. After the follower is trained, the follower PHY provides training sequences to the leader PHY for use during training.

[0015] In some systems, the connected PHY is pre-started with a leader / follower role. For example, when the system is first put into use, the user and / or manufacturer will pre-select and program a PHY to always operate as a leader during link training and / or initialization, and will select other PHYs to always operate as followers during link training and / or initialization. However, such systems do not have a protocol for selecting a follower or leader. Therefore, new equipment with a PHY cannot be connected and / or added to the system because the previously set leader-follower relationship has been configured and cannot be reconfigured. The examples described herein facilitate the leader-follower determination protocol for determining which PHY will operate as a leader and which (which) PHYs will operate as followers, so that link training and / or initialization can occur when adding, removing or adjusting components in the system.

[0016] During the leader follower determination protocol, the examples described herein cause each connected PHY to output a tuning signal. The tuning signal is structured to attempt to be unique for each PHY. For example, each PHY may generate a random number and / or utilize a unique identifier or other unique feature of the PHY or a device implementing the PHY. The PHY then generates a tuning signal having characteristics based on the random number and / or unique identifier. For example, the tuning signal may include a delay, amplitude, frequency, etc. based on the random number and / or unique identifier. In this way, each tuning signal of each connected PHY should be different. During the leader follower determination protocol, the PHYs each output the generated tuning signal. In this way, each PHY may obtain one or more tuning signals from other PHYs, and compare the obtained tuning signals with the generated tuning signals to determine whether the PHY should operate as a leader or a follower. For example, if the delay is compared, the PHY may compare the amount of delay in the obtained signal from another PHY with the amount of delay in the locally generated tuning signal. In this way, the PHY may determine whether to operate as a leader or a follower based on the comparison. For example, if the delay of the locally generated signal is less than the delay of the obtained tuning signals, the PHY may configure itself to operate as a leader. If the delay of the locally generated signal is greater than the delay of one of the obtained tuning signals, the PHY may configure itself to operate as a follower. Using the examples described herein, a system utilizing a shared interface including automotive Ethernet may be configured and / or reconfigured to operate in different configurations corresponding to topology changes, modulation replacements, recovery via redundant connections, and the like. In addition, the leader-follower determination protocol described herein is fully effective for legacy devices that are not capable of executing the leader-follower determination protocol. Although the examples described herein are described in conjunction with an automotive Ethernet interface, the examples described herein may be used in any technology where it is desired to determine leaders and followers.

[0017] Figure 1 An example system 100 for facilitating a leader-follower determination protocol is illustrated. The example system 100 includes example controller units 102, 112, example physical layers (PHYs) 104, 114, example automatic determination circuitry 106, 116, example processing units 108, 118, example media access control (MAC) layers 110, 120, and an example network 122. Although Figure 1 The system 100 includes two controller units, but there may be any number of controller units having PHYs and automatic determination circuitry connected via the network 122 .

[0018] Figure 1 The controller units 102, 112 are processing devices including corresponding PHYs 104, 114 that communicate with each other. The controller units 102, 112 may be computers, servers, edge or cloud nodes, electronic control units, electronic control modules, and / or any other processing devices. The controller units 102, 112 may be implemented in a wired or wireless system. In some examples, the controller units 102, 112 are implemented as devices within the vehicle, as described below in conjunction with Figure 2 Also described.

[0019] Figure 1 The PHYs 104, 114 transmit and / or receive data from other connected devices via the network 122 based on instructions from the controller unit 102. During startup and / or after a device is connected to the network 122 and / or removed from the network, the PHYs 104, 114 perform an initialization and / or link training protocol. As described above, in order to perform an initialization and / or link training protocol between two PHYs 104, 114, one of the PHYs will operate as a leader and one of the PHYs will operate as a follower. Therefore, the PHYs 104, 114 include automatic determination circuitry 106, 116 to perform a leader-follower determination protocol to determine which PHY will operate as a leader and which PHY will operate as a follower.

[0020] Figure 1The automatic determination circuit system 106, 116 performs a leader follower determination protocol by generating a tuning signal. For example, the automatic determination circuit system 106 generates a first tuning signal and the automatic determination circuit system 116 generates a second tuning signal. The automatic determination circuit system 106, 116 generates a tuning signal that is unique to the corresponding PHY 104, 114. For example, the automatic determination circuit system 106 may generate a random number, or may utilize a number corresponding to a unique identifier of the physical layer 104 and / or the controller unit 102. The automatic determination circuit system 106 uses the generated number to define the characteristics of the tuning signal. For example, the number may correspond to an amount of delay before outputting a periodic portion of the tuning signal. Additionally or alternatively, the number may correspond to an amplitude, frequency, offset, etc. of the tuning signal. In addition, the automatic determination circuit system 116 generates a unique tuning signal using the same technique. In this way, the tuning signal generated by the automatic determination circuit system 106 will be different from the tuning signal generated by the automatic determination circuit system 116 with a high probability.

[0021] After generating the tuning signal, Figure 1The automatic determination circuit systems 106, 116 cause the generated tuning signals to be transmitted to each other via the network 122. The automatic determination circuit systems 106, 116 may perform some echo cancellation and / or filtering so that the tuning signals can be obtained via the network 122 while removing the tuning signals transmitted on the network. Therefore, each of the automatic determination circuit systems 106, 116 will transmit a locally generated tuning signal and obtain a tuning signal. The automatic determination circuit systems 106, 116 compare the locally generated tuning signal with the obtained tuning signal to determine the difference between the two signals. The automatic determination circuit systems 106, 116 will operate as followers and / or leaders based on the determined differences. For example, if the tuning signal generated by the automatic determination circuit system 106 includes a shorter delay, then the automatic determination circuit system 106 will determine that the locally generated signal at the PHY 104 has a shorter delay than the obtained signal, and the automatic determination circuit system 116 will determine that the locally generated signal at the PHY 114 has a longer delay. If the leader-follower determination protocol specifies that the PHY that generates the shorter delay will operate as the leader, then the automatic determination circuit system 106 will determine that PHY 104 should operate as a leader by setting a value in a register that defines whether to operate as a leader or a follower, and the automatic determination circuit system 116 will determine that PHY 114 should operate as a follower by setting a value in a register that defines whether to operate as a leader or a follower. The leader-follower determination protocol may specify a leader and / or follower based on any characteristic of the tuning signal such as maximum delay, minimum delay, highest amplitude, lowest amplitude, longest duration, shortest duration, longest frequency, shortest frequency, highest offset, lowest offset, etc. In addition, the automatic determination circuit system 106 performs a verification protocol to ensure that the two PHYs 114, 104 agree to the follower leader role before executing the startup and / or link training protocol. If during the verification protocol, the automatic determination circuit system 106 does not agree on the determined role, then the leader-follower determination protocol is repeated. The following is combined with Figure 3 The automatic determination circuitry 106 is further described.

[0022] Figure 1The processing units 108, 118 of the physical layer 104 execute instructions to perform functions and / or operations based on the data communicated between the two physical layers 104. When the processing units 108, 118 have an external device, the processing units 108, 118 transmit instructions to send information and / or obtain received information from the corresponding MAC layer 110, 120. The MAC layer 110, 120 interfaces between the processing units 108, 118 and the corresponding PHY layer 104, 114. For example, the MAC layer 110, 120 inserts a MAC header and / or a cyclic redundancy check (CRC) in an Internet Protocol (IP) packet output by the processing units 108, 118. In addition, the MAC layer 110, 120 incorporates one or more protocols for retransmission in the event of an error in transmitting and / or receiving information. The MAC layer 110, 120 instructs the corresponding PHY 104, 114 to transmit information to the external device based on the instructions from the corresponding processing unit 108, 118. In addition, the MAC layer 110 , 120 transfers information corresponding to the obtained packet received from the external device via the corresponding PHY 104 , 114 .

[0023] Figure 1 An example network 122 is a system that interconnects systems to exchange data. For example, network 122 may be a shared interface or medium such as an Ethernet connection. Figure 1 In the example of , network 122 represents a physical full-duplex interface that enables transmission and reception over the same connection using a single twisted pair cable. However, network 122 may correspond to different connections (eg, different wired or wireless connections).

[0024] Figure 2 An example vehicle 200 is illustrated for implementing the examples described herein. The example vehicle 200 includes Figure 1 The first component 202 is connected to the second component 204 via a network 122 (e.g., Ethernet twisted pair). The first component 202 includes Figure 1 The controller unit 102, PHY 104 and automatic determination circuit system 106 of the second component 204 include Figure 1 The controller unit 112, PHY 114 and automatic determination circuit system 116 are provided.

[0025] exist Figure 2In the example of , the first component 202 is an advanced driver assistance system (ADAS) and the second component 204 may be a camera, a sensor, a lidar system, a central gateway, etc. The first component 202 obtains data and / or transmits data to the second component 204 to perform operations related to driver assistance. However, the first component 202 and / or the second component 204 may be any computing device within the vehicle 200, such as an infotainment system, a speaker, a display, etc. The components 202, 204 are connected via the network 122. If any other components are added to the network 122 and / or if one or more of the components 202, 204 are replaced, the automatic determination circuit system 106, 116 may execute a follower leader determination protocol to establish a follower leader role for startup and / or link training.

[0026] Figure 3 for Figure 1 and / or 2 is a block diagram of the automatic determination circuit system 106. Although combined Figure 1 and / or 2 automatic determination circuit system 106 describes Figure 3 , but can be combined Figure 1 and / or 2 automatic determination circuit system 116 describes Figure 3 The example automatic determination circuit system 106 includes an example interface circuit system 300, example differential circuit systems 301a, 301b, an example random number generator circuit system 302, an example timer circuit system 303, an example tuning signal generation circuit system 304, an example count measurement circuit system 307, an example comparator circuit system 308, an example configuration circuit system 310, and an example configuration timer circuit system 312.

[0027] Figure 3 The interface circuit system 300 transmits the locally generated tuning signal using the components of PHY 104. For example, the interface circuit system 300 can communicate with the hybrid transmitter receiver component of PHY 104. In addition, the interface circuit system 300 can receive the locally generated tuning signal from the connected device (e.g., Figure 1 The interface circuit system 300 obtains the tuning signal generated locally from the tuning signal generating circuit system 304. The interface circuit system 300 forwards the tuning signal obtained from the connected device to the comparator circuit system 308. In some examples, the interface circuit 300 includes an output differential circuit system 301a and an input differential circuit system 301b. The output differential circuit system 301 converts the tuning signal generated by the tuning signal generating circuit system 304 into two differential output signals. The input differential circuit system 301b converts the differential input tuning signal into a single tuning signal.

[0028] Figure 3The random number generator circuit system 302 generates a number. For example, the random number generator circuit system 302 may generate a random number within a range of numbers. Additionally or alternatively, the random number generator circuit system 302 may utilize a unique identifier as the number. For example, the random number generator circuit system 302 may utilize a unique identifier of the PHY 104 and / or the controller unit 102 to generate the number. The random number generator circuit system 302 may utilize the entire unique identifier, a portion of the unique identifier (e.g., the first X digits, the last X digits, etc.), and / or a function of the unique identifier (e.g., a modulo function corresponding to the unique identifier) ​​to generate the number. The random number generator circuit system 302 generates the number during the leader follower determination protocol. As further described below, the generated number is used to set one or more characteristics of the tuning signal to make the tuning signal unique.

[0029] Figure 3 The example timer circuit system 303 generates a digital clock signal (e.g., a square wave) using a reference clock. The digital clock signal corresponds to a logic high voltage that lasts for a period of time and a logic low or zero voltage signal that lasts for a period of time. In some examples, where the tuning signal is based on the duration between pulses (e.g., a delay), the timer circuit system 303 generates the digital clock signal based on a random number generated by the random number generation circuit system 302. For example, if the random number is a first number, then the timer circuit system 303 will generate a first tuning signal corresponding to a first delay, and if the random number is a second number, then the timer circuit system 303 will generate a second tuning signal corresponding to a second delay. The timer circuit system 303 outputs the digital clock signal to the tuning signal generation circuit system 304 to generate a tuning signal based on the digital clock signal. In addition, the timer circuit system outputs a digital value corresponding to a local digital interval value to the comparator circuit system 308. In some examples, where the characteristics of the tuning signal for the leader follower protocol are not based on delay, the timer circuit system 303 can be removed. In such examples, tuning signal generation circuitry 304 may output a digital value corresponding to a unique characteristic of the locally generated tuning signal to comparator circuitry 308 .

[0030] Figure 3The tuning signal generation circuit system 304 obtains the digital clock signal from the timer circuit system 303 and / or the number generated by the random number generator circuit system 302. The tuning signal generation circuit system 304 generates a tuning signal based on the digital clock signal and / or the generated number. For example, the tuning signal generation circuit system 304 generates a tuning signal having one or more characteristics based on the generated number. In some examples, the tuning signal generation circuit system 304 generates a tuning signal corresponding to the delay amount. In such examples, the tuning signal generation circuit system 304 uses the digital clock from the timer circuit system 303 to generate a tuning signal that oscillates only when the digital clock signal is high. However, the generated number and / or digital clock signal may affect the delay amount of the tuning signal, the duration of the tuning signal, the amplitude of the tuning signal, the frequency of the tuning signal, the offset of the tuning signal, and / or any other characteristics of the tuning signal. Therefore, the generated tuning signal will be unique to the PHY 104 with a high probability. After generating the tuning signal, the tuning signal generation circuitry 304 outputs the generated tuning signal to the interface circuitry 300 for transmission of the generated tuning signal to a connected device via the network 122 .

[0031] In some examples, to accommodate legacy devices, Figure 3 The tuning signal generating circuit system 304 can generate a tuning signal to ensure that a legacy device configured as a leader will result in a leader designation during a leader follower determination protocol. For example, if the leader follower protocol designates a device as a leader when the signal output by the device has a minimum delay between tuning signals, then the tuning signal generating circuit system 304 generates a tuning signal with a certain delay, which corresponds to a generated number that is larger than the delay of the signal output by the legacy device. In this way, during the training protocol, if the legacy device is pre-configured as a leader, the delay of the signal from the legacy device will already be minimal because the legacy device will not have any delay when sending the training synchronization mode, and the legacy device will be designed as a leader during the leader follower protocol, even if the legacy device does not generate a tuning signal based on the generated number. In addition, a legacy device that is pre-configured to operate as a follower will not output any signal. Therefore, such a legacy device will have a maximum delay, which will result in such a legacy device not being incorrectly marked as a leader.

[0032] Figure 3Count measurement circuitry 307 of the comparator circuitry 308 may use a reference clock to convert an obtained (e.g., external) tuning signal into a digital value corresponding to a delay of the obtained tuning signal. For example, count measurement circuitry 307 may count how many reference clock pulses are spent between oscillations of the obtained tuning signal, which corresponds to the delay of the obtained external tuning signal. Count measurement circuitry 307 outputs an external digital interval value corresponding to the count of reference clock pulses between oscillations to comparator circuitry 308. In some examples, count measurement circuitry 307 may be removed or replaced with a different circuitry for a different tuning signal characteristic. For example, if the only tuning signal characteristic corresponds to the amplitude of the tuning signal, then count measurement circuitry 307 may be replaced with circuitry that determines the amplitude of the tuning signal and converts the amplitude into a digital value.

[0033] Figure 3 The example comparator circuit system 308 compares one or more characteristics of the generated tuning signal to one or more characteristics of the acquired tuning signal. As described above, because each automatic determination circuit system 106 generates a unique tuning signal, there is a high probability that the comparator circuit system 308 can determine a difference in one or more characteristics of the acquired tuning signal and the locally generated tuning signal. For example, if the leader follower determination protocol is based on an amount of delay in the tuning signal, then the comparator circuit system 208 compares the amount of delay in the generated tuning signal to the amount of delay in the acquired tuning signal to determine which tuning signal has a longer or shorter delay. For example, in Figure 3 , comparator circuitry 308 obtains (a) a local digital interval value corresponding to a delay of a locally generated tuning signal, and (b) an external digital interval value corresponding to a delay of an obtained external tuning signal. Comparator 308 compares the two digital values ​​to determine which delay is greater and / or less. However, comparator 308 may compare a value corresponding to any characteristic of the locally generated tuning signal to the obtained external tuning signal. Comparator 308 outputs a comparison output to configuration circuitry 310.

[0034] Figure 3In an example configuration circuit system 310 determines whether to cause PHY 104 to operate as a leader or a follower based on the result of the comparison. For example, if the leader follower determination protocol is designated as a leader based on the tuning signal with the lowest delay, and all other PHYs are designed as followers, then the configuration circuit system 310 determines whether the generated signal has a shorter delay than the obtained tuning signal. In such an example, if the configuration circuit system 310 determines that the generated tuning signal has a smaller delay than the obtained tuning signal, then the configuration circuit system 310 configures PHY 104 to operate as a leader by setting a value corresponding to leader operation into a register. If the configuration circuit system 310 determines that the generated tuning signal has a greater delay than at least one obtained tuning signal, then the configuration circuit system 310 configures PHY 104 to operate as a follower by setting a value corresponding to follower operation into a register. Additionally or alternatively, the leader-follower determination protocol may specify leader and / or follower roles based on any characteristic of the tuning signal (e.g., maximum delay corresponding to the leader, minimum amplitude corresponding to the leader, maximum amplitude corresponding to the leader, minimum frequency corresponding to the leader, maximum frequency corresponding to the leader, etc.).

[0035] Additionally, after configuring to operate as a leader or follower, Figure 3The configuration circuit system 310 performs a confirmation protocol to ensure that all components agree on the leader follower role. For example, the configuration circuit system 310 may cause the interface circuit system 300, when configured to operate as a leader, to output a tuning signal and / or a training sequence after a follower designation to confirm to other devices that the PHY 104 has been configured to operate as a leader. In such examples, the configuration circuit system 310 monitors the interface circuit system 300 to determine whether a tuning signal and / or a training sequence has been obtained from another PHY. If the leader follower role is correctly designated, then the tuning signal and / or training sequence from the other PHY will not be obtained because the other PHY will operate as a follower to listen for signals and will not output signals. If the leader follower role is not correctly designated, then the tuning signal and / or training sequence from the PHY will be obtained, and the configuration circuit system 310 may determine that an error has occurred and will re-trigger the leader follower determination protocol. In some examples, if the configuration circuit system 310 determines that a training sequence from another PHY is obtained when operating as a leader, the configuration circuit system 310 may switch to a follower and continue to operate as a follower PHY. In another example, the configuration circuit system 310 may monitor the interface circuit system 300 when configured to operate as a follower to determine whether a tuning signal and / or a training sequence has been obtained from another PHY. If the leader follower role is correctly specified, then the tuning signal from the other PHY will be obtained because the other PHY will operate as a leader to output signals to PHY 104. If the leader follower role is not correctly specified, then the tuning signal and / or training sequence from the other PHY will not be obtained, and the configuration circuit system 310 may determine that an error has occurred and will re-trigger the leader follower determination protocol.

[0036] Figure 3 An example configuration timer circuit system 312 tracks the duration used during the confirmation protocol. For example, when the confirmation protocol begins, the configuration circuit system 310 monitors the tone signal on the network 122, which will be obtained within a threshold amount of time tracked by the configuration timer circuit system 312. In some examples, the configuration timer circuit system 312 can be implemented by a counter that counts clock pulses.

[0037] Figure 4 For Figure 1-3 The flowchart representation of the method and / or example operations 400 of the automatic determination circuit system 106 processor circuit system and / or any other circuit system executed and / or instantiated to perform the leader follower determination protocol. Figure 1-3 The automatic determination circuit system 106 describes Figure 4 instructions and / or operations, but can be combined with Figure 1The automatic determination circuit system 116 and / or any other PHY device describes instructions and / or operations.

[0038] Figure 4 The machine-readable instructions and / or operations 400 of the configuration begin at block 402, where the tuning signal generation circuit system 304 causes the interface circuit system 300 to output a tuning signal to a connected device via the network 122. The interface circuit system 300 may use one or more components of the PHY 104 to transmit the tuning signal. As described above, the tuning signal generation circuit system 304 generates the tuning signal based on a number (e.g., randomly generated and / or based on an identifier). Therefore, the tuning signal is different from other tuning signals with a high probability. At block 404, the configuration circuit system 310 determines whether a tuning signal has been obtained from another device via the interface circuit system 300. If the configuration circuit system 310 determines that a tuning signal from another device has not been obtained (block 404: No), then control continues to block 410, as further described below. If the configuration circuit system 310 determines that a tuning signal from another device has been obtained (block 404: Yes), then control continues to block 406. At block 406, the comparator circuitry 308 compares the obtained tuning signal to the locally generated output tuning signal. Depending on the leader-follower determination protocol, the comparator circuitry 308 may compare one or more characteristics of the generated tuning signal to one or more characteristics of the obtained tuning signal to determine a difference. At block 408, the example configuration circuitry 310 configures the PHY 104 to operate as a leader or a follower based on the comparison of the characteristics.

[0039] At block 410 (e.g., if no tuning signal is obtained from another device), the configuration circuit system 310 configures the PHY 104 to operate as a leader. For example, if the device that should transmit the tuning signal is a legacy device, then the legacy device will not output the tuning signal, so the PHY 104 can act as a leader. At block 412, the configuration circuit system 310 determines whether a response from a follower has been obtained. For example, if the initial tuning signal is not obtained from another device at block 404, then this may be because the device is a legacy follower device, or this may be due to an error. Therefore, if the device is a legacy follower device, then it will transmit a response as part of the startup and / or link training protocol. If there is an error, then the other device will not transmit a response. Therefore, if the configuration circuit system 310 determines that a response from a follower has been obtained (block 412: No), then the instruction ends, and the startup and / or link training protocol continues. If the configuration circuit system 310 determines that no response from a follower has been obtained (block 412: No), then control returns to block 402 to restart the leader follower protocol.

[0040] Figures 5A-5C Description can be Figure 1-3 The flowchart representation of the method and / or example operations 400 of the processor circuitry and / or any other circuitry executed and / or instantiated by the automatic determination circuitry 106 to perform the leader follower determination protocol and confirmation protocol. Figure 1-3 The automatic determination circuit system 106 describes Figures 5A-5C instructions and / or operations, but can be combined with Figure 1 The automatic determination circuit system 116 and / or any other PHY device describes instructions and / or operations.

[0041] The machine-readable instructions and / or operations 500 of FIG. 5 begin at block 502, where the random number generator circuitry 302 generates a random number. Alternatively, the random number generator circuitry 302 may alternatively select a number from a preset set of numbers and / or may utilize and / or generate a number based on an identifier. At block 504, the example tuning signal generation circuitry 304 generates a tuning signal based on the generated number. For example, the tuning signal generation circuitry 304 generates a tuning signal having a characteristic (e.g., delay, frequency, phase, offset, duration, etc.) based on the generated number. In some examples, as described above in conjunction with Figure 3 As described, the tuning signal generation circuit system 304 generates the tuning signal by oscillating the signal based on the digital clock signal corresponding to the random delay amount generated by the timer circuit system 303. At block 506, the tuning signal generation circuit system 304 causes the interface circuit system 300 to output the tuning signal to the connected device via the network 122. The interface circuit system 300 may use one or more components of the PHY 104 to transmit the tuning signal.

[0042] At block 508, configuration circuitry 310 determines whether a tuning signal has been obtained from another device via interface circuitry 300. If configuration circuitry 310 determines that a tuning signal from another device has not been obtained (block 508: No), control continues to block 515, as further described below. If configuration circuitry 310 determines that a tuning signal from another device has been obtained (block 508: Yes), control continues to block 512. In some examples, count measurement circuitry 307 generates a digital value corresponding to a characteristic of the obtained tuning signal. For example, count measurement circuitry 307 may count the number of reference clock pulses between oscillations of the tuning signal to determine an amount of delay of the obtained tuning signal, and generate a digital value corresponding to the count. However, count measurement circuitry 307 may generate a value for any characteristic of the obtained tuning signal. At block 512, comparator circuitry 308 compares the obtained tuning signal to the locally generated output tuning signal. Depending on the leader-follower determination protocol, the comparator circuit system 308 may compare one or more characteristics of the generated tuning signal with one or more characteristics of the acquired tuning signal to determine a difference. In some examples, the comparator circuit system 308 compares the delay of the locally generated tuning signal and the acquired tuning signal by comparing a first digital value from the timer circuit system 303 and a second digital value from the count measurement circuit system 207, as described above in conjunction with Figure 3 At block 514, the example configuration circuitry 310 configures the PHY 104 to operate as a leader or a follower based on the comparison of the characteristics. At block 515 (e.g., if a tuning signal is not obtained from another device), the configuration circuitry 310 configures the PHY 104 to operate as a leader. For example, if the device that should transmit the tuning signal is a legacy device, the legacy device will not output the tuning signal, so the PHY 104 can operate as a leader.

[0043] If the configuration circuitry 310 configures the PHY 104 to operate as a follower (block 516: Follower), control passes to Figure 5C530. If the configuration circuit system 310 configures the PHY 104 to operate as a leader (block 516: Leader), then control continues to block 518. At block 518, the configuration circuit system 310 begins to configure the timer circuit system 312. At block 520, the tuning signal generation circuit system 340 outputs a tuning signal or any other signal via the interface circuit system 300. The output tuning signal indicates to other connected devices that the PHY 104 operates as a leader. At block 522, the configuration circuit system 310 determines whether a tuning signal has been obtained from another connected device via the interface circuit system 300. For example, if an error occurs during the initial leader / follower protocol, then another PHY device may transmit a subsequent tuning signal even if the leader / follower protocol has ended. Therefore, the configuration circuit system 310 monitors the obtained tuning signal to determine that the previous leader / follower protocol caused an error, and restarts the leader / follower protocol.

[0044] If the configuration circuit system 310 determines that a tuning signal has been obtained from another computing device (block 522: yes), then control continues to block 528, as further described below. If the configuration circuit system 310 determines that a tuning signal has not been obtained from another computing device (block 522: no), then control continues to block 524. At block 523, the configuration circuit system 310 determines whether a training sequence has been obtained from another computing device. Because only one device can operate as a leader, if the configuration circuit system 310 determines that a tuning signal has been obtained, then the configuration circuit system 310 will determine that the leader follower determination protocol has failed because at least two devices are configured to operate as leaders. Therefore, the configuration circuit system 310 will determine that the other device operates as a leader. If the configuration circuit system 310 determines that a training sequence has not been obtained from another computing device (block 523: no), then control continues to block 524. If the configuration circuit system 310 determines that a training sequence has been obtained from another computing device (block 523: yes), then control continues to block 527.

[0045] At block 524, configuration circuitry 310 determines whether configuration timer circuitry 312 has reached a threshold amount of time. If configuration circuitry 310 determines that configuration timer circuitry 312 has not reached a threshold amount of time (block 524: No), control returns to block 522. If configuration circuitry 310 determines that configuration timer circuitry 312 has reached a threshold amount of time (block 524: Yes), control continues to block 526. At block 526, PHY 104 initiates initialization and / or link training as a leader. At block 528, after obtaining a tuning signal from another computing device, random number generator circuitry 302 generates a new number, and control returns to Figure 5AAt block 504. At block 527 (eg, if the training sequence was obtained from another computing device), the configuration circuitry 310 reconfigures the PHY 104 to operate as a follower and continues training as a follower based on the obtained training sequence.

[0046] At block 530, after configuration circuitry 310 configures PHY 104 to operate as a follower, configuration circuitry 310 begins configuring timer circuitry 312. At block 532, configuration circuitry 310 determines whether a training sequence has been obtained from another connected device via interface circuitry 300. Because one device is operating as a leader, if configuration circuitry 310 determines that a training sequence has not been obtained, then configuration circuitry 310 will determine that the leader follower determination protocol has failed because no device is structured to operate as a leader. Therefore, configuration circuitry 310 will determine that the leader follower protocol should be restarted.

[0047] If the configuration circuitry 310 determines that a training sequence has been obtained from another computing device (block 532: YES), control continues to block 538, as further described below. If the configuration circuitry 310 determines that a tuning signal has not been obtained from another computing device (block 532: NO), control continues to block 534. At block 534, the configuration circuitry 310 determines whether the configuration timer circuitry 312 has reached a threshold amount of time. If the configuration circuitry 310 determines that the configuration timer circuitry 312 has not reached a threshold amount of time (block 534: NO), control returns to block 532. If the configuration circuitry 310 determines that the configuration timer circuitry 312 has reached a threshold amount of time (block 534: YES), control continues to block 536. At block 536, after the threshold amount of time has been reached, the random number generator circuitry 302 generates a new number, and control returns to block 537. Figure 5A At block 504. At block 338, upon determining that a tuning signal has been obtained from another device, the PHY 104 initiates initialization and / or link training as a follower.

[0048] Figure 6 To illustrate the Figure 11. The timing diagram 600 is an example timing diagram of two tuning signals generated by the PHYs 104, 114 of the embodiment of the present invention. The timing diagram 600 includes a first example tuning signal 602 and a second example tuning signal 604. The first tuning signal 602 is a signal that may be output by the PHY 104, and the second tuning signal 604 is a signal that may be output by the PHY 114. The timing diagram 600 is described in conjunction with a leader-follower determination protocol, in which the PHY that outputs the tuning signal with a shorter delay will be the leader, and the remaining PHYs will be followers. However, the leader-follower determination protocol may correspond to any characteristics corresponding to a leader or a follower.

[0049] As shown in the timing diagram 600, the delay amount between the periodic pulses of the first tone signal 602 is shorter than the delay amount between the periodic pulses of the second tone signal 604. The PHY 104 outputs the first tone signal 602, and obtains the second tone signal 604 via the network 122. Therefore, the PHY 104 determines that the locally generated tone signal 602 has a smaller delay than the obtained tone signal 604. Similarly, the PHY 114 outputs the second tone signal 604, and obtains the first tone signal 602 via the network 122. Therefore, the PHY 114 determines that the locally generated tone signal 604 has a larger delay than the obtained tone signal 602. Therefore, the PHY 104 operates as a leader, and the PHY 114 operates as a follower.

[0050] The periodic portion of the first tuning signal 602 and / or the second tuning signal 604 can be any type of periodic signal. In some examples, the periodic portion of the tuning signal corresponds to a slow transition time (e.g., such as a triangle wave or a sine wave). In this way, if link training is not performed to train the echo cancellation circuit including the cancellation of reflected signals from the channel, then the echo cancellation can eliminate the signal from the local transmitter. Therefore, the tuning signal with a slow transition time can minimize the reflection. However, any periodic signal can be used.

[0051] accomplish Figure 1 An example of an automatic determination circuit system 106 is Figure 3 However, Figure 3 One or more of the elements, processes, and / or devices described in the drawings may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner.

[0052] in addition, Figure 3The interface circuit system 300, random number generator circuit system 302, example timer circuit system 303, tuning signal generation circuit system 304, count measurement circuit system 307, comparator circuit system 308, configuration circuit system 310 and / or configuration timer circuit system 312 may be implemented by hardware, software, firmware and / or any combination of hardware, software and / or firmware. As a result, for example, Figure 3 Any of the interface circuit system 300, the random number generator circuit system 302, the example timer circuit system 303, the tuning signal generation circuit system 304, the count measurement circuit system 307, the comparator circuit system 308, the configuration circuit system 310 and / or the configuration timer circuit system 312 can be implemented by one or more analog or digital circuits, logic circuits, programmable processors, programmable controllers, graphics processing units (GPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable logic devices (PLDs) and / or field programmable logic devices (FPLDs).

[0053] When any of the apparatus or system claims of this patent are read to cover pure software and / or firmware implementations, Figure 3 At least one of the interface circuit system 300, random number generator circuit system 302, example timer circuit system 303, tuning signal generation circuit system 304, count measurement circuit system 307, comparator circuit system 308, configuration circuit system 310 and / or configuration timer circuit system 312 is expressly defined herein as comprising a non-transitory computer-readable storage device or storage disk, such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc., including software and / or firmware. In addition, Figure 3 The interface circuit system 300, the random number generator circuit system 302, the example timer circuit system 303, the tuning signal generation circuit system 304, the count measurement circuit system 307, the comparator circuit system 308, the configuration circuit system 310 and / or the configuration timer circuit system 312 may include one or more elements, processes or devices as Figure 3 The present invention may be in addition to or in place of those described in, and / or may include one or more of any or all of the described elements, processes, and devices. As used herein, the phrase "communication" (including variations thereof) includes direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but also includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals, and / or one-time events.

[0054] Figure 4-5C Shown for implementation Figure 1 , 2The flowchart representation of example hardware logic, machine readable instructions, hardware-implemented state machines, and / or any combination thereof of the automatic determination circuit system 106 of and / or 3. The machine readable instructions may be one or more executable programs or portions of executable programs for execution by a computer processor. The programs may be embodied in software stored on a non-transitory computer-readable storage medium such as a CD-ROM, floppy disk, hard drive, DVD, Blu-ray disk, or memory associated with a processor, but the entire program and / or portions thereof may alternatively be executed by a device other than a processor and / or embodied in firmware or dedicated hardware.

[0055] In addition, although the reference Figure 4-5C The flowcharts illustrated in the description of the example procedures describe an example process, but many other methods of implementing the automatic determination circuit system 106 may be used alternatively. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are structured to perform corresponding operations without executing software or firmware.

[0056] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, and the like. The machine-readable instructions as described herein may be stored as data (e.g., portions of instructions, code, representations of code, and the like) that can be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices and / or computing devices (e.g., servers). The machine-readable instructions may require one or more of installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, redistribution, compilation, and the like so that they can be directly read, interpreted, and / or executed by a computing device and / or other machine. For example, the machine-readable instructions may be stored in multiple parts that are separately compressed, encrypted, and stored on separate computing devices, where the parts, when decrypted, decompressed, and combined, form an executable instruction set that implements a program such as described herein.

[0057] In another example, the machine-readable instructions may be stored in a state that is readable by a computer, but requires the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the instructions on a particular computing device or another device. In another example, the machine-readable instructions and / or corresponding programs may be configured before the machine-readable instructions and / or corresponding programs can be executed in whole or in part (e.g., stored settings, data inputs, recorded network addresses, etc.). As a result, the described machine-readable instructions and / or corresponding programs include such machine-readable instructions and / or programs regardless of the particular format or state of the machine-readable instructions and / or programs when stored or otherwise at rest or in transit.

[0058] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented by any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0059] As mentioned above, Figure 4-5C The example processes of may be implemented using executable instructions (e.g., computer and / or machine readable instructions) stored on a non-transitory computer and / or machine readable medium such as a hard drive, flash memory, read-only memory, compact disk, digital versatile disk, cache, random access memory, and / or any other storage device or storage disk in which information is stored for any duration (e.g., for an extended period of time, permanently, for transient situations, for temporary buffering, and / or for caching information). As used herein, the term non-transitory computer readable medium is expressly defined to include any type of computer readable storage device and / or storage disk, and to exclude propagating signals and to exclude transmission media.

[0060] Although certain example methods, apparatus, and articles of manufacture are described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus, and articles of manufacture fairly falling within the scope of the claims of this patent.

[0061] Descriptors "first", "second", "third", etc. are used herein when identifying multiple elements or components that can be mentioned separately. Unless otherwise specified or known based on the context of their use, such descriptors do not confer any meaning of priority, physical order, or arrangement in a list or chronological order, but are merely used as labels to refer to multiple elements or components respectively to facilitate understanding of the described examples. In some examples, the descriptor "first" can be used to refer to an element in the detailed description, while the same element can be referred to using different descriptors such as "second" or "third" in the claims. In this case, such descriptors are only used for convenient reference to multiple elements or components.

[0062] In the specification and claims, unless otherwise stated, the terms "including" and "having" and variations thereof are included in a manner similar to the term "comprising". Unless otherwise stated, "about", "approximately" or "substantially" before a value means + / -10% of the value. In another example, "about", "approximately" or "substantially" before a value means + / -5% of the value. In another example, "about", "approximately" or "substantially" before a value means + / -1% of the value.

[0063] As used herein, the terms "couple", "coupled", "couples" and variations thereof may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then in the first example, device A is coupled to device B, or in the second example, if the intermediate component C does not substantially change the functional relationship between device A and device B, then device A is coupled to device B through the intermediate component C, such that device B is controlled by device A via the control signal generated by device A. In addition, the terms "couple", "coupled", "couples" or variations thereof include indirect or direct electrical or mechanical connections.

[0064] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be programmable through the device's firmware and / or software, through the construction and / or layout of the device's hardware components and interconnects, or a combination thereof.

[0065] Despite Figure 1-6Although not all are individually labeled, the components or elements of the systems and circuits described therein have one or more conductors or terminals that allow signals to enter and / or leave the components or elements. Conductors or terminals (or portions thereof) may be referred to herein as pins, pads, terminals (including, for example, input terminals, output terminals, reference terminals, and ground terminals), inputs, outputs, nodes, and interconnects.

[0066] As used herein, the "terminal" of a component, device, system, circuit, integrated circuit or other electronic or semiconductor component generally refers to a conductor such as a wire, trace, pin, pad or other connector or interconnect, which enables a component, device, system, etc. to be electrically connected and / or mechanically connected to another component, device, system, etc. For example, a terminal can be used to receive or provide an analog or digital electrical signal (or simply referred to as a signal), or to be electrically connected to a common or ground reference. Therefore, an input terminal or input is used to receive a signal from another component, device, system, etc. An output terminal or output is used to provide a signal to another component, device, system, etc. Other terminals can be used to connect to a common, ground or voltage reference, such as a reference terminal or a ground terminal. The terminal of an IC or PCB may also be referred to as a pin (longitudinal conductor) or a pad (planar conductor). A node refers to a connection point or interconnection point of two or more terminals. An example number of terminals and nodes may be shown. However, depending on a specific circuit or system topology, there may be more or fewer terminals and nodes. However, in some cases, "terminals", "nodes", "interconnects", "pads" and "pins" may be used interchangeably.

[0067] Described herein are example methods, apparatus, systems, and articles of manufacture corresponding to facilitating determining a leader and a follower of a shared interface. Additional examples and combinations thereof include the following: a first physical layer comprising an interface circuitry configured to transmit a first signal to a second physical layer, a comparator circuitry configured to compare a second signal from the second physical layer to the first signal, and a configuration circuitry configured to facilitate operation as a leader or a follower based on the comparison.

[0068] Example 2 includes the first physical layer of Example 1, further comprising signal generator circuitry configured to generate a first signal based on at least one of a generated number or a characteristic of the first physical layer or a device implementing the first physical layer.

[0069] Example 3 includes the first physical layer of Example 1, wherein the first signal corresponds to a first characteristic and the second signal corresponds to a second characteristic different from the first characteristic, and the comparator circuitry compares the first characteristic to the second characteristic.

[0070] Example 4 includes the first physical layer of Example 1, wherein the interface circuitry is to obtain the second signal via the shared wired bus and transmit the first signal via the shared wired bus.

[0071] Example 5 includes the first physical layer of Example 1, wherein when operating as a leader, the interface circuit system is configured to output a third signal to the second physical layer, and the configuration circuit system is configured to initiate training configured as a leader when no signal is obtained from the second physical layer within a threshold amount of time.

[0072] Example 6 includes the first physical layer of Example 1, wherein when operating as a leader, the interface circuit system is configured to output a third signal to the second physical layer, and the configuration circuit system is configured to redetermine operation as a leader or a follower when a signal has been obtained from the second physical layer within a threshold amount of time.

[0073] Example 7 includes the first physical layer of Example 1, wherein when operating as a follower, the configuration circuitry is configured to initiate training configured as a follower when a signal has been obtained from the second physical layer within a threshold amount of time.

[0074] Example 8 includes the first physical layer of Example 1, wherein when operating as a follower, the configuration circuitry is configured to re-determine operation as a leader or a follower when a signal is not obtained from the second physical layer within a threshold amount of time.

[0075] Example 9 includes a method comprising generating a first signal by using a first physical layer to execute instructions, transmitting the first signal to a second physical layer, comparing a second signal from the second physical layer with the first signal by using the first physical layer to execute instructions, and configuring the first physical layer to operate as a leader or a follower based on the comparison by using the first physical layer to execute instructions.

[0076] Example 10 includes the method of Example 9, further comprising generating the first signal based on at least one of a generated number or a characteristic of the first physical layer or a device implementing the first physical layer.

[0077] Example 11 includes the method of Example 9, wherein the first signal corresponds to a first characteristic and the second signal corresponds to a second characteristic different from the first characteristic, wherein the comparison of the first signal and the second signal includes comparing the first characteristic to the second characteristic.

[0078] Example 12 includes the method of Example 9, further comprising obtaining the second signal via the shared wired bus, and transmitting the first signal via the shared wired bus.

[0079] Example 13 includes the method of Example 9, further comprising, when operating as a leader, outputting a third signal to the second physical layer, and when no signal is obtained from the second physical layer within a threshold amount of time, initiating training configured as a leader.

[0080] Example 14 includes the method of Example 9, further comprising, when operating as a leader, outputting a third signal to a second physical layer, and when a signal has been obtained from the second physical layer within a threshold amount of time, re-determining operation as a leader or a follower.

[0081] Example 15 includes the method of Example 9, further comprising, when operating as a follower and having obtained a signal from a second physical layer within a threshold amount of time, initiating training configured as a follower.

[0082] Example 16 includes the method of Example 9, further comprising, when operating as a follower and not obtaining a signal from the second physical layer within a threshold amount of time, re-determining operation as a leader or a follower.

[0083] Example 17 includes a non-transitory computer-readable storage medium comprising instructions that cause a first physical layer to at least transmit a first signal to a second physical layer, compare a second signal from the second physical layer to the first signal, and configure the first physical layer as a leader or a follower based on the comparison.

[0084] Example 18 includes the non-transitory computer-readable storage medium of Example 17, wherein the instructions cause the first physical layer to generate the first signal based on at least one of a generated number or a characteristic of the first physical layer or a device implementing the first physical layer.

[0085] Example 19 includes the non-transitory computer-readable storage medium of Example 17, wherein the first signal corresponds to a first characteristic and the second signal corresponds to a second characteristic different from the first characteristic, and the instructions cause the first physical layer to compare the first characteristic to the second characteristic.

[0086] Example 20 includes the non-transitory computer readable storage medium of Example 17, wherein the instructions cause the first physical layer to obtain the second signal via the shared wired bus and cause the first signal to be transmitted via the shared wired bus.

[0087] Modifications may be made in the described embodiments, and other embodiments may be modified, within the scope of the claims.

Claims

1. A first physical layer, comprising: an interface circuit system configured to transmit the first signal to a second physical layer; comparator circuitry configured to compare a second signal from the second physical layer with the first signal; and Circuitry is configured to facilitate operation as a leader or a follower based on the comparison.

2. The first physical layer of claim 1, further comprising a signal generator circuit system configured to generate the first signal based on at least one of a generated number or a characteristic of the first physical layer or a device implementing the first physical layer.

3. The first physical layer of claim 1, wherein the first signal corresponds to a first characteristic and the second signal corresponds to a second characteristic different from the first characteristic, the comparator circuitry comparing the first characteristic to the second characteristic.

4. The first physical layer of claim 1 , wherein the interface circuitry is configured to: obtaining the second signal via a shared wired bus; and The first signal is transmitted via the shared wired bus.

5. The first physical layer of claim 1 , wherein when operating as the leader: The interface circuitry is configured to output a third signal to the second physical layer; and The configuration circuitry is configured to initiate training configured as the leader when a signal is not obtained from the second physical layer within a threshold amount of time.

6. The first physical layer of claim 1 , wherein when operating as the leader: The interface circuitry is configured to output a third signal to the second physical layer; and The configuration circuitry is configured to re-determine operation as the leader or the follower when a signal has been obtained from the second physical layer within a threshold amount of time.

7. The first physical layer of claim 1, wherein when operating as the follower, the configuration circuitry is configured to initiate training configured as the follower when a signal has been obtained from the second physical layer within a threshold amount of time.

8. The first physical layer of claim 1, wherein when operating as the follower, the configuration circuit system is configured to re-determine operation as the leader or the follower when no signal is obtained from the second physical layer within a threshold amount of time.

9. A method comprising: generating a first signal by executing an instruction using a first physical layer; transmitting the first signal to a second physical layer; comparing a second signal from the second physical layer with the first signal by executing instructions using the first physical layer; and The first physical layer is configured to operate as a leader or a follower based on the comparison by executing instructions using the first physical layer.

10. The method of claim 9, further comprising generating the first signal based on at least one of a generated number or a characteristic of the first physical layer or a device implementing the first physical layer.

11. The method of claim 9, wherein the first signal corresponds to a first characteristic and the second signal corresponds to a second characteristic different from the first characteristic, wherein the comparison of the first signal and the second signal comprises comparing the first characteristic to the second characteristic.

12. The method according to claim 9, further comprising: obtaining the second signal via a shared wired bus; and The first signal is transmitted via the shared wired bus.

13. The method of claim 9, further comprising, when operating as the leader: outputting a third signal to the second physical layer; and When a signal is not obtained from the second physical layer within a threshold amount of time, training configured as the leader is initiated.

14. The method of claim 9, further comprising, when operating as the leader: outputting a third signal to the second physical layer; and When a signal has been obtained from the second physical layer within a threshold amount of time, operation as the leader or the follower is re-determined.

15. The method of claim 9, further comprising, when operating as the follower and having obtained a signal from the second physical layer within a threshold amount of time, initiating training configured as the follower.

16. The method of claim 9, further comprising, when operating as the follower and not obtaining a signal from the second physical layer within a threshold amount of time, re-determining operation as the leader or the follower.

17. A non-transitory computer-readable storage medium comprising instructions that cause a first physical layer to at least: causing the first signal to be transmitted to a second physical layer; comparing a second signal from the second physical layer to the first signal; and The first physical layer is configured as a leader or a follower based on the comparison.

18. The non-transitory computer-readable storage medium of claim 17, wherein the instructions cause the first physical layer to generate the first signal based on at least one of a generated number or a characteristic of the first physical layer or a device implementing the first physical layer.

19. The non-transitory computer-readable storage medium of claim 17, wherein the first signal corresponds to a first characteristic and the second signal corresponds to a second characteristic different from the first characteristic, the instructions causing the first physical layer to compare the first characteristic to the second characteristic.

20. The non-transitory computer-readable storage medium of claim 17, wherein the instructions cause the first physical layer to: obtaining the second signal via a shared wired bus; and The first signal is caused to be transmitted via the shared wired bus.

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