System and method for remotely reading and writing PHY chip register

Abstract

The invention discloses a system and method for remotely reading and writing a PHY chip register, and relates to the technical field of communication, and the system comprises an Ethernet switch which is in communication connection with a remote computer; the Ethernet switch comprises an FPGA (Field Programmable Gate Array) chip unit, a serial port module and a plurality of PHY (Physical Layer) chip modules which are in communication connection, the PHY chip module is used for receiving or sending network data; the remote computer is used for sending a serial port instruction; the serial port instruction is a read instruction or a write instruction; the serial port module is used for forwarding a serial port instruction to the FPGA chip unit; the FPGA chip unit is used for reading or writing a register of the corresponding PHY chip module according to the serial port instruction and generating a prompt signal when the reading or writing operation is completed; and the serial port module is also used for sending the prompt signal to a remote computer. And the overall compatibility and reliability of the system are improved.

Description

Technical Field

[0001] The present application generally relates to the field of communication technology, and specifically to a system and method for remotely reading and writing PHY chip registers. Background Art

[0002] An Ethernet switch is a network device that is responsible for forwarding data packets between multiple devices in the network. The core components of an Ethernet switch generally include a switching chip and a physical layer transceiver (PHY) chip. The switching chip mainly completes the core function of Ethernet data exchange, and the PHY chip mainly completes the Ethernet physical layer connection status detection and Ethernet data transceiver function. If you need to check the status of each port of the Ethernet switch or set each port, you need to read and write the registers of the PHY chip. At present, the register parameters of the PHY chip cannot be directly read externally. Therefore, we propose a system and method for remotely reading and writing PHY chip registers to solve the above problems. Summary of the invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a system and method for remotely reading and writing PHY chip registers with improved compatibility and reliability.

[0004] In a first aspect, the present application provides a system for remotely reading and writing PHY chip registers, comprising: an Ethernet switch connected to a remote computer for communication; the Ethernet switch comprises: an FPGA chip unit, a serial port module and a plurality of PHY chip modules connected to the communication; The PHY chip module is used to receive or send network data; The remote computer is used to send a serial port instruction; the serial port instruction is a read instruction or a write instruction; The serial port module is used to forward the serial port instruction to the FPGA chip unit; The FPGA chip unit is used to read or write the register of the corresponding PHY chip module according to the serial port instruction, and generate a prompt signal when the read or write operation is completed; The serial port module is also used to send the prompt signal to the remote computer.

[0005] According to the technical solution provided in the embodiment of the present application, the FPGA chip unit includes: A serial port receiving module, the serial port receiving module is used to receive the serial port instruction forwarded by the serial port module; A data processing module, the data processing module is used to generate a read / write signal according to the serial port instruction; A smi read / write module, the smi read / write module is used to convert the read / write signal into a smi interface protocol, read or write the corresponding register of the PHY chip module, and generate a prompt signal when the read or write operation is completed, and feed it back to the data processing module; A serial port sending module, the serial port sending module is used to receive the prompt signal forwarded by the data processing module, and send the prompt signal to the serial port module.

[0006] According to the technical solution provided in the embodiment of the present application, the Ethernet switch further includes: A switching chip module is communicatively connected to each of the PHY chip modules and is used to transmit network data to each of the PHY chip modules.

[0007] According to the technical solution provided in the embodiment of the present application, the switching chip module is communicatively connected to the PHY chip module via the rgmii interface.

[0008] According to the technical solution provided in the embodiment of the present application, the Ethernet switch further includes: The network port module has a corresponding number and a one-to-one communication connection with the PHY chip module, and the network port module is used to transmit the data received from the external device to the corresponding PHY chip module.

[0009] According to the technical solution provided in the embodiment of the present application, the FPGA chip unit is connected to all the PHY chip modules through the smi interface.

[0010] In a second aspect, the present application provides a method for remotely reading and writing a PHY chip register, based on the above system implementation, the method comprises the following steps: receiving a serial port instruction forwarded by the serial port module; the serial port instruction is issued by the remote computer; the serial port instruction is a read instruction or a write instruction; Read or write the corresponding register of the PHY chip module according to the serial port instruction, and generate a prompt signal when the read or write operation is completed; The prompt signal is sent to the serial port module; the serial port module is used to forward the prompt signal to the remote computer.

[0011] According to the technical solution provided in the embodiment of the present application, according to the serial port instruction, the register of the corresponding PHY chip module is read or written, and a prompt signal is generated when the read or write operation is completed, which specifically includes the following steps: When the serial port receiving module receives data from the rx of the serial port module, it parses it according to the serial port protocol and stores the received serial port data in rx_data[7:0]. After receiving the 8-bit data, the serial port receiving module sets the rx_valid connected to the data processing module to 1. When the data processing module writes PHY chip data, it writes the chip address, register address, write request, and write data to the SMI read / write module. After the write operation is completed, the SMI read / write module sets the prompt signal to 1. When the data processing module reads the PHY chip register, it outputs the PHY chip address, register address, and read request to the SMI read-write module. The SMI read-write module outputs the read data to the data processing module, and after sending, sets the data valid signal to 1 and the prompt information to 1; When tx_valid sent by the data processing module is 1, the serial port sending module sends the 8-bit data tx_data[7:0] to be sent bit by bit from the tx interface of the serial port module according to the serial port protocol, and after the 8-bit data is sent, the serial port sending module sets tx_rdy of the data processing module to 1.

[0012] It can be seen from the above technical solution that the present application has at least the following beneficial effects: The present application discloses a system for remotely reading and writing PHY chip registers, which includes: an Ethernet switch connected to a remote computer for communication; wherein the Ethernet switch includes: an FPGA chip unit, a serial port module and a plurality of PHY chip modules connected to each other for communication; specifically, the PHY chip module receives or sends network data; the remote computer sends a serial port instruction; here, the serial port instruction is a read instruction or a write instruction; the serial port module forwards the serial port instruction to the FPGA chip unit; the FPGA chip unit reads or writes the register of the corresponding PHY chip module according to the serial port instruction, and generates a prompt signal when the read or write operation is completed; the serial port module then sends the prompt signal to the remote computer.

[0013] This application will design an Ethernet switch, using an FPGA chip unit, a serial port module and multiple PHY chip modules to form the core structure of the Ethernet switch. The serial port instructions and feedback prompt signals are mainly received through the FPGA chip unit and the serial port module, so that the remote computer can read and write the registers of the PHY chip module in the Ethernet switch, thereby improving the overall compatibility and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Other features, objects and advantages of the present application will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings.

[0015] Figure 1A schematic diagram of the structure of a system for remotely reading and writing PHY chip registers.

[0016] Figure 2 It is a structural diagram of the FPGA chip unit.

[0017] Figure 3 Application block diagram of a system for remotely reading and writing PHY chip registers.

[0018] Figure 4 This is a diagram of the internal structure of the FPGA chip unit when in use.

[0019] Figure 5 Schematic diagram of the data processing module.

[0020] Figure 6 A flowchart of a method for remotely reading and writing PHY chip registers.

[0021] Numbers in the figure: 1. Remote computer; 2. Ethernet switch; 3. FPGA chip unit; 4. Serial port module; 5. PHY chip module; 6. Serial port receiving module; 7. Data processing module; 8. SMI read-write module; 9. Serial port sending module; 10. Switch chip module; 11. Network port module. DETAILED DESCRIPTION

[0022] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0023] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0024] In order to make the description of the following embodiments clear and concise, a brief introduction to the related technology is first given: An Ethernet switch is a network device that is responsible for forwarding data packets between multiple devices in a network. It ensures that data packets are forwarded to the target device in the most efficient way by learning and storing Media Access Control (MAC) addresses. A remote computer usually refers to a computer connected through a network, which can be a client or a server. In network management, remote computers are used to perform tasks such as data processing, storage, application running, and network monitoring. Remote read and write interaction between Ethernet switches and remote computers is a key link in modern network management. At present, the register parameters of PHY chips cannot be directly read externally. Therefore, we propose a system and method for remotely reading and writing PHY chip registers to solve the above problems.

[0025] In order to make the system for remotely reading and writing PHY chip registers provided by the embodiment of the present application clearer and easier to understand, the system is introduced below in conjunction with the accompanying drawings. Figure 1 As shown, the figure is a schematic diagram of the structure of a system for remotely reading and writing PHY chip registers provided in an embodiment of the present application, the system comprising: an Ethernet switch 2 connected to a remote computer 1 for communication; the Ethernet switch 2 comprises: an FPGA chip unit 3, a serial port module 4 and a plurality of PHY chip modules 5 connected for communication; PHY chip module 5, used for receiving or sending network data; Remote computer 1, used for sending serial port commands; the serial port commands are read commands or write commands; The serial port module 4 is used to forward the serial port instructions to the FPGA chip unit 3; The FPGA chip unit 3 is used to read or write the register of the corresponding PHY chip module 5 according to the serial port instruction, and generate a prompt signal when the read or write operation is completed; wherein the FPGA chip unit 3 is connected to all PHY chip modules 5 through the smi interface. The registers of the PHY chip module 5 generally include: control registers, status registers, statistics registers, test registers and other types.

[0026] The serial port module 4 is also used to send the prompt signal to the remote computer 1 .

[0027] Here, the remote computer is a computer connected via a network, which can be a client or a server. The FPGA chip unit 3 is, for example, an FPGA chip. The PHY chip module 5 is, for example, a PHY chip; and the serial port module 4 is a serial port with connection and communication functions.

[0028] Furthermore, if Figure 2 As shown, the FPGA chip unit 3 includes: The serial port receiving module 6 is used to receive the serial port instructions forwarded by the serial port module 4; here, the serial port receiving module 6 is a serial port with a data receiving function.

[0029] Data processing module 7, data processing module 7 is used to generate read and write signals according to serial port instructions; The SMI read / write module 8 is used to convert the read / write signal into the SMI interface protocol, read or write the register of the corresponding PHY chip module 5, and generate a prompt signal when the read or write operation is completed, and feed it back to the data processing module 7; The serial port sending module 9 is used to receive the prompt signal forwarded by the data processing module 7 and send the prompt signal to the serial port module 4. Here, the serial port sending module 9 is a serial port with a data sending function.

[0030] Furthermore, if Figure 1 As shown, the Ethernet switch 2 also includes: The switching chip module 10 is connected to each PHY chip module 5 for transmitting network data to each PHY chip module 5. Here, the switching chip module 10 is, for example, a switching chip; it is a core component of the Ethernet switch 2 and is responsible for processing the forwarding and routing of data packets. It determines how to forward the data packet to the corresponding port according to the target MAC address of the data packet. The switching chip usually has a high-speed cache and parallel processing capability to support multiple concurrent data streams. Among them, the switching chip module 10 is connected to the PHY chip module 5 through the rgmii interface.

[0031] Furthermore, if Figure 1 As shown, the Ethernet switch 2 also includes: The network port module 11 has a corresponding number and one-to-one communication connection with the PHY chip module 5. The network port module 11 is used to transmit the received data sent by the external device to the corresponding PHY chip module 5. Here, the network port module 11 is, for example, a network port of an Ethernet switch, which is responsible for connecting with the external device and processing the reception and forwarding of data. In addition, the Ethernet network port supports multiple network protocols (such as Ethernet, VLAN, QoS, etc.) and can be configured according to network requirements to achieve efficient data transmission.

[0032] Specifically, Figure 3 As shown, the switching chip is connected to the PHY chip through the RGMII interface to transmit network data, and the registers of the PHY chip are read and written through the SMI interface. Here, the SMI interface includes two signal lines, MDC and MDIO. Each network port of the Ethernet switch 2 requires a PHY chip to send and receive network data, and each PHY chip has its own chip address. The FPGA chip is connected to the remote computer 1 through the serial port module 4 to send and receive serial port instructions of the remote computer 1. At the same time, the FPGA chip is connected to the SMI interface bus of all PHY chips inside the Ethernet switch 1 through the MDC and MDIO signal lines, so that the registers of all PHY chips can be read and written through the PHY chip address. The FPGA chip completes the conversion of the serial port read and write instructions into the read and write signals of the SMI interface, thereby reading and writing the registers of each PHY chip.

[0033] Among them, Figure 4As shown, the FPGA chip at least includes four parts: a serial port receiving module 6, a serial port sending module 9, a data processing module 7, and a smi read / write module 8. When the tx_valid sent by the data processing module 7 is 1, the serial port sending module 9 sends the 8-bit data tx_data[7:0] to be sent bit by bit from the tx interface of the serial port module 4 according to the serial port protocol. After the 8-bit data is sent, the serial port sending module 9 sets the tx_rdy connected to the data processing module 7 to 1. After the serial port receiving module 6 receives the data from the rx of the serial port module 4, it parses it according to the serial port protocol and stores the received serial data in rx_data[7:0]. After the 8-bit data is received, the serial port receiving module 6 sets the rx_valid connected to the data processing module 7 to 1.

[0034] The main function of the smi read / write module 8 is to convert the read / write signals of the data processing module into the smi interface protocol, and read / write the PHY chip register from the mdio interface. When the data processing module 7 wants to write PHY chip data, it writes the chip address (phy_addr), register address (reg_addr), write request (write_req), and write data (write_data) to the smi read / write module 8. After writing, the smi read / write module 8 sets the transmission completion signal (done) to 1; when the data processing module 7 needs to read the PHY chip register, it outputs the PHY chip address (phy_addr), register address (reg_addr), and read request (read_req) to the smi read / write module 8. The smi read / write module 8 outputs the read data (read_data) to the data processing module 7. After sending, the data valid signal (data_valid) is set to 1, and the transmission completion signal (done) is set to 1.

[0035] The data processing module 7 mainly completes the parsing of the serial port instructions, and completes the read and write operations of the PHY chip according to the instructions. The module implements related functions through a state machine. In addition, the present application designs a set of serial port instruction protocols for the read and write operations of the PHY chip. The serial port read instructions are the start frame (16 bits, the value is 55aa in hexadecimal), read instructions (3 bits, the value is 111), PHY chip address (5 bits) register address (8 bits, the lower 5 bits are valid). The write instructions are the start frame (16 bits, the value is 55aa in hexadecimal), read instructions (3 bits, the value is 111), PHY chip address (5 bits), register address (8 bits, the lower 5 bits are valid), write data high 8 bits, write data low 8 bits.

[0036] like Figure 5As shown, after the system is powered on, it enters the idle state. When it detects that the serial port has received the 16-bit start frame 16'h55aa, it enters the read and write instruction state. At this time, if the high 3 bits of the received 8-bit serial port data are 3'b111, it jumps to the read address receiving state. If they are 3'b000, it jumps to the write address receiving state. In this state, the low 5 bits of the 8-bit serial port data received are the phy chip address, which is stored in phy_addr[4:0].

[0037] In the read address receiving state, the lower 5 bits of the 8-bit data received by the serial port are the register address, which is stored in reg_addr[4:0], and then jumps to the smi read state. In the smi read state, read_req is set to 1, so that the smi read-write module 8 starts to send read instructions to the PHY chip. Detecting that data_valid is 1 indicates that the read is complete. At this time, read_data[15:0] is the read PHY chip register data, and then jumps to the smi read completion state. In the smi read completion state, the data in read_data[15:0] is sent to the remote computer 1 through the serial port sending module. After the serial port transmission is completed, that is, when tx_rdy is 1, it jumps to the idle state to complete the reading process. Here, the serial port read instruction is shown in Table 1, and the x in Table 1 represents an invalid bit.

[0038] Table 1 Serial port read instructions

[0039] In the write address receiving state, the lower 5 bits of the 8-bit data received by the serial port are the register address, which are stored in reg_addr[4:0], and then jump to the smi write data receiving state. In the smi write smi write data receiving state, the two consecutive 8-bit data received by the serial port are the upper 8 bits and lower 8 bits of the write data, which are stored in write_data[15:0], and then jump to the smi write state. In the smi write state, write_req is set to 1, so that the smi read-write module 8 starts to send write instructions to the PHY chip. Detecting done as 1 indicates that the write is completed, and then jumps to the smi write completion state. In the smi write completion state, the "ok" character is sent to the remote computer 1 through the serial port. After the serial port sends the data, that is, when tx_rdy is 1, it jumps to the idle state to complete the write process. Here, the serial port write instruction is shown in Table 2, where x represents an invalid bit.

[0040] Table 2 Serial port write instructions

[0041] like Figure 6As shown, the figure is a flowchart of a method for remotely reading and writing a PHY chip register provided by an embodiment of the present application, the method comprising the following steps: Receive serial port instructions forwarded by the serial port module 4; the serial port instructions are sent by the remote computer 1; the serial port instructions are read instructions or write instructions; Read or write the register of the corresponding PHY chip module 5 according to the serial port instruction, and generate a prompt signal when the read or write operation is completed; The prompt signal is sent to the serial port module 4 ; the serial port module 4 is used to forward the prompt signal to the remote computer 1 .

[0042] This application will design an Ethernet switch 2, using an FPGA chip unit 3, a serial port module 4 and multiple PHY chip modules 5 to form the core structure of the Ethernet switch, mainly receiving serial port instructions and feedback prompt signals through the FPGA chip unit 3 and the serial port module 4, so that the remote computer 1 can read and write the registers of the PHY chip module 5 in the Ethernet switch 2, thereby improving the overall compatibility and reliability of the system.

[0043] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A system for remotely reading and writing PHY chip registers, characterized in that: include: An Ethernet switch (2) connected to the remote computer (1); The Ethernet switch (2) comprises: a communication-connected FPGA chip unit (3), a serial port module (4) and a plurality of PHY chip modules (5); The PHY chip module (5) is used to receive or send network data; The remote computer (1) is used to send a serial port instruction; the serial port instruction is a read instruction or a write instruction; The serial port module (4) is used to forward the serial port instruction to the FPGA chip unit (3); The FPGA chip unit (3) is used to read or write the corresponding register of the PHY chip module (5) according to the serial port instruction, and generate a prompt signal when the read or write operation is completed; The serial port module (4) is also used to send the prompt signal to the remote computer (1).

2. A system for remotely reading and writing PHY chip registers according to claim 1, characterized in that: The FPGA chip unit (3) comprises: A serial port receiving module (6), the serial port receiving module (6) being used to receive the serial port instruction forwarded by the serial port module (4); A data processing module (7), the data processing module (7) being used to generate a read / write signal according to the serial port instruction; an SMI read / write module (8), the SMI read / write module (8) being used to convert the read / write signal into an SMI interface protocol, read or write the corresponding register of the PHY chip module (5), and generate a prompt signal when the read or write operation is completed, and feed it back to the data processing module (7); A serial port sending module (9), the serial port sending module (9) is used to receive the prompt signal forwarded by the data processing module (7), and send the prompt signal to the serial port module (4).

3. A system for remotely reading and writing PHY chip registers according to claim 1, characterized in that: The Ethernet switch (2) further comprises: A switching chip module (10), the switching chip module (10) being communicatively connected to each of the PHY chip modules (5), and being used for transmitting network data to each of the PHY chip modules (5).

4. A system for remotely reading and writing PHY chip registers according to claim 3, characterized in that: The switching chip module (10) is communicatively connected to the PHY chip module (5) via an RGMII interface.

5. A system for remotely reading and writing PHY chip registers according to claim 1, characterized in that: The Ethernet switch (2) further comprises: The network port modules (11) correspond in number to the PHY chip modules (5) and are communicatively connected in a one-to-one correspondence, and the network port modules (11) are used to transmit data received from an external device to the corresponding PHY chip module (5).

6. A system for remotely reading and writing PHY chip registers according to claim 1, characterized in that: The FPGA chip unit (3) is connected to all the PHY chip modules (5) via a smi interface.

7. A method for remotely reading and writing a PHY chip register, implemented based on the system according to any one of claims 1 to 6, characterized in that: The method comprises the following steps: receiving a serial port instruction forwarded by the serial port module (4); the serial port instruction is issued by the remote computer (1); the serial port instruction is a read instruction or a write instruction; Reading or writing the corresponding register of the PHY chip module (5) according to the serial port instruction, and generating a prompt signal when the reading or writing operation is completed; The prompt signal is sent to the serial port module (4); the serial port module (4) is used to forward the prompt signal to the remote computer (1).

8. A method for remotely reading and writing a PHY chip register according to claim 7, characterized in that: According to the serial port instruction, the register of the corresponding PHY chip module (5) is read or written, and a prompt signal is generated when the read or write operation is completed, specifically comprising the following steps: When the serial port receiving module (6) receives data from the rx of the serial port module (4), it parses the data according to the serial port protocol and stores the received serial port data in rx_data[7:0]. After receiving the 8-bit data, the serial port receiving module (6) sets the rx_valid connected to the data processing module (7) to 1. When the data processing module (7) writes the PHY chip data, the chip address, register address, write request, and write data are written to the SMI read / write module (8), and after the write operation is completed, the SMI read / write module (8) sets the prompt signal to 1; When the data processing module (7) reads the PHY chip register, it outputs the PHY chip address, register address, and read request to the SMI read / write module (8); the SMI read / write module (8) outputs the read data to the data processing module (7), and after the transmission is completed, sets the data valid signal to 1 and sets the prompt information to 1; When tx_valid sent by the data processing module (7) is 1, the serial port sending module (9) sends the 8-bit data tx_data[7:0] to be sent bit by bit from the tx interface of the serial port module (4) according to the serial port protocol, and after the 8-bit data is sent, the serial port sending module (9) sets tx_rdy of the data processing module (7) to 1.

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