System and method for remotely reading and writing phy chip registers

Abstract

The application discloses a system and method for remotely reading and writing a PHY chip register, and relates to the technical field of communication.The system comprises an Ethernet switch in communication connection with a remote computer; the Ethernet switch comprises an FPGA chip unit, a serial port module and a plurality of PHY chip modules in communication connection; the PHY chip module is used for receiving or sending network data; the remote computer is used for sending a serial port instruction; the serial port instruction is a read instruction or a write instruction; the serial port module is used for forwarding the serial port instruction to the FPGA chip unit; the FPGA chip unit is used for reading or writing a register of the corresponding PHY chip module according to the serial port instruction, and generating a prompt signal when the reading or writing operation is completed; and the serial port module is further used for sending the prompt signal to the remote computer.The system improves the overall compatibility and reliability.

Description

Technical Field

[0001] The present application generally relates to the field of communication technology, and more specifically to a system and method for remotely reading and writing PHY chip registers. Background Art

[0002] An Ethernet switch is a network device responsible for forwarding data packets between multiple devices on a network. The core components of an Ethernet switch generally include a switching chip and a physical layer transceiver (PHY) chip. The switching chip primarily performs the core function of Ethernet data exchange, while the PHY chip primarily performs Ethernet physical layer connection status detection and Ethernet data transmission and reception. To check the status of individual Ethernet switch ports or configure individual port settings, it is necessary to read and write registers in the PHY chip. Currently, PHY chip register parameters cannot be directly read externally. Therefore, we propose a system and method for remotely reading and writing PHY chip registers to address this issue. Summary of the Invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a system and method for remotely reading and writing PHY chip registers with improved compatibility and reliability.

[0004] In a first aspect, the present application provides a system for remotely reading and writing PHY chip registers, comprising: an Ethernet switch connected to a remote computer for communication; the Ethernet switch comprising: an FPGA chip unit, a serial port module, and a plurality of PHY chip modules connected for communication;

[0005] The PHY chip module is used to receive or send network data;

[0006] The remote computer is used to send serial port instructions; the serial port instructions are read instructions or write instructions;

[0007] The serial port module is used to forward the serial port instruction to the FPGA chip unit;

[0008] The FPGA chip unit is used to read or write the register of the corresponding PHY chip module according to the serial port instruction, and generate a prompt signal when the read or write operation is completed;

[0009] The serial port module is further configured to send the prompt signal to the remote computer.

[0010] According to the technical solution provided in the embodiment of the present application, the FPGA chip unit includes:

[0011] A serial port receiving module, configured to receive the serial port instruction forwarded by the serial port module;

[0012] A data processing module, configured to generate a read / write signal according to the serial port instruction;

[0013] an SMI read / write module, configured to convert the read / write signals into an SMI interface protocol, read or write the corresponding register of the PHY chip module, and generate a prompt signal upon completion of the read or write operation, which is fed back to the data processing module;

[0014] A serial port sending module is used to receive the prompt signal forwarded by the data processing module and send the prompt signal to the serial port module.

[0015] According to the technical solution provided in the embodiment of the present application, the Ethernet switch further includes:

[0016] A switching chip module is communicatively connected to each of the PHY chip modules and is used to transmit network data to each of the PHY chip modules.

[0017] According to the technical solution provided in the embodiment of the present application, the switching chip module is communicatively connected to the PHY chip module via the rgmii interface.

[0018] According to the technical solution provided in the embodiment of the present application, the Ethernet switch further includes:

[0019] The network port module has a corresponding number of network port modules and a one-to-one communication connection with the PHY chip module. The network port module is used to transmit the data received from the external device to the corresponding PHY chip module.

[0020] According to the technical solution provided in the embodiment of the present application, the FPGA chip unit is connected to all the PHY chip modules through the smi interface.

[0021] In a second aspect, the present application provides a method for remotely reading and writing PHY chip registers, based on the above-mentioned system implementation, the method includes the following steps:

[0022] receiving a serial port instruction forwarded by the serial port module; the serial port instruction is issued by the remote computer; the serial port instruction is a read instruction or a write instruction;

[0023] Read or write the corresponding register of the PHY chip module according to the serial port instruction, and generate a prompt signal when the read or write operation is completed;

[0024] The prompt signal is sent to the serial port module; the serial port module is used to forward the prompt signal to the remote computer.

[0025] According to the technical solution provided in the embodiment of the present application, according to the serial port instruction, the register of the corresponding PHY chip module is read or written, and a prompt signal is generated when the read or write operation is completed, which specifically includes the following steps:

[0026] When the serial port receiving module receives data from the rx of the serial port module, it parses it according to the serial port protocol and stores the received serial port data in rx_data[7:0]. After receiving the 8-bit data, the serial port receiving module sets the rx_valid connected to the data processing module to 1.

[0027] When the data processing module writes PHY chip data, it writes the chip address, register address, write request, and write data to the SMI read / write module. After the write operation is completed, the SMI read / write module sets the prompt signal to 1.

[0028] When the data processing module reads the PHY chip register, it outputs the PHY chip address, register address, and read request to the SMI read / write module. The SMI read / write module outputs the read data to the data processing module, and after sending, sets the data valid signal to 1 and the prompt information to 1;

[0029] When the tx_valid sent by the data processing module is 1, the serial port sending module sends the 8-bit data tx_data[7:0] to be sent bit by bit from the tx interface of the serial port module according to the serial port protocol. After the 8-bit data is sent, the serial port sending module sets the tx_rdy of the data processing module to 1.

[0030] It can be seen from the above technical solution that this application has at least the following beneficial effects:

[0031] The present application discloses a system for remotely reading and writing PHY chip registers, which includes: an Ethernet switch communicatively connected to a remote computer; wherein the Ethernet switch includes: an FPGA chip unit, a serial port module, and multiple PHY chip modules communicatively connected; specifically, the PHY chip module receives or sends network data; the remote computer sends a serial port instruction; here, the serial port instruction is a read instruction or a write instruction; the serial port module forwards the serial port instruction to the FPGA chip unit; the FPGA chip unit reads or writes the register of the corresponding PHY chip module according to the serial port instruction, and generates a prompt signal when the read or write operation is completed; the serial port module then sends the prompt signal to the remote computer.

[0032] This application will design an Ethernet switch, using an FPGA chip unit, a serial port module, and multiple PHY chip modules to form the core structure of the Ethernet switch. Serial port commands and feedback prompt signals are mainly received through the FPGA chip unit and the serial port module, allowing remote computers to read and write the registers of the PHY chip module in the Ethernet switch, thereby improving the overall compatibility and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features, objects and advantages of the present application will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings.

[0034] Figure 1 A schematic diagram of the system for remotely reading and writing PHY chip registers.

[0035] Figure 2 This is a structural diagram of the FPGA chip unit.

[0036] Figure 3 This is an application block diagram of a system for remotely reading and writing PHY chip registers.

[0037] Figure 4 This is a diagram of the internal structure of the FPGA chip unit when in use.

[0038] Figure 5 Schematic diagram of the data processing module.

[0039] Figure 6 A flowchart of a method for remotely reading and writing PHY chip registers.

[0040] Numbers in the figure: 1. Remote computer; 2. Ethernet switch; 3. FPGA chip unit; 4. Serial port module; 5. PHY chip module; 6. Serial port receiving module; 7. Data processing module; 8. SMI read / write module; 9. Serial port sending module; 10. Switch chip module; 11. Network port module. DETAILED DESCRIPTION

[0041] The present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. It should also be noted that, for ease of description, only portions relevant to the invention are shown in the accompanying drawings.

[0042] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0043] To make the description of the following embodiments clear and concise, a brief introduction to the related technologies is first given:

[0044] An Ethernet switch is a network device responsible for forwarding data packets between multiple devices on a network. It learns and stores Media Access Control (MAC) addresses to ensure that data packets are forwarded to their destination devices in the most efficient manner. A remote computer typically refers to a computer connected via a network, which can be either a client or a server. In network management, remote computers perform tasks such as data processing, storage, application execution, and network monitoring. Remote read and write interactions between Ethernet switches and remote computers are critical to modern network management. Currently, the register parameters of physical layer (PHY) chips cannot be directly read externally. Therefore, we propose a system and method for remotely reading and writing PHY chip registers to address this issue.

[0045] In order to make the system for remotely reading and writing PHY chip registers provided by the embodiment of the present application clearer and easier to understand, the system is introduced below with reference to the accompanying drawings. Figure 1 As shown, this figure is a structural diagram of a system for remotely reading and writing PHY chip registers provided by an embodiment of the present application, the system comprising: an Ethernet switch 2 connected to a remote computer 1 for communication; the Ethernet switch 2 comprising: an FPGA chip unit 3, a serial port module 4, and multiple PHY chip modules 5 connected for communication;

[0046] PHY chip module 5, used to receive or send network data;

[0047] Remote computer 1 is used to send serial port commands; the serial port commands are read commands or write commands;

[0048] Serial port module 4, used for forwarding serial port instructions to FPGA chip unit 3;

[0049] The FPGA chip unit 3 is used to read or write registers of the corresponding PHY chip module 5 according to serial port instructions and generate a prompt signal when the read or write operation is completed. The FPGA chip unit 3 is connected to all PHY chip modules 5 via the SMI interface. The registers of the PHY chip module 5 generally include control registers, status registers, statistics registers, test registers, etc.

[0050] The serial port module 4 is also used to send the prompt signal to the remote computer 1.

[0051] Here, the remote computer is a computer connected via a network, which can be a client or a server. The FPGA chip unit 3 is, for example, an FPGA chip. The PHY chip module 5 is, for example, a PHY chip. The serial port module 4 is a serial port with connection and communication functions.

[0052] Furthermore, if Figure 2As shown, the FPGA chip unit 3 includes:

[0053] The serial port receiving module 6 is used to receive the serial port instructions forwarded by the serial port module 4; here, the serial port receiving module 6 is a serial port with a data receiving function.

[0054] Data processing module 7, data processing module 7 is used to generate read and write signals according to serial port instructions;

[0055] SMI read / write module 8, which is used to convert read / write signals into SMI interface protocols, read or write registers of the corresponding PHY chip module 5, and generate a prompt signal when the read or write operation is completed, and feed it back to the data processing module 7;

[0056] The serial port sending module 9 is used to receive the prompt signal forwarded by the data processing module 7 and send the prompt signal to the serial port module 4. Here, the serial port sending module 9 is a serial port with a data sending function.

[0057] Further, if Figure 1 As shown, the Ethernet switch 2 further includes:

[0058] The switch chip module 10 is communicatively connected to each PHY chip module 5 and is used to transmit network data to each PHY chip module 5. Here, the switch chip module 10 is, for example, a switch chip; it is a core component of the Ethernet switch 2 and is responsible for forwarding and routing data packets. It determines how to forward the data packet to the corresponding port based on the packet's destination MAC address. Switch chips typically have high-speed caching and parallel processing capabilities to support multiple concurrent data streams. The switch chip module 10 is communicatively connected to the PHY chip module 5 via the RGMII interface.

[0059] Further, if Figure 1 As shown, the Ethernet switch 2 further includes:

[0060] The network port modules 11 correspond in number to the PHY chip modules 5 and are connected in a one-to-one communication relationship. The network port modules 11 are used to transmit data received from external devices to the corresponding PHY chip modules 5. Here, the network port modules 11 are, for example, Ethernet switch ports, which are responsible for connecting to external devices and processing data reception and forwarding. Furthermore, Ethernet ports support multiple network protocols (such as Ethernet, VLAN, and QoS) and can be configured according to network requirements to achieve efficient data transmission.

[0061] Specifically, if Figure 3As shown, the switch chip connects to the PHY chip via the RGMII interface to transmit network data and reads and writes the PHY chip's registers via the SMI interface. The SMI interface includes two signal lines, MDC and MDIO. Each network port on Ethernet switch 2 requires a PHY chip to send and receive network data, and each PHY chip has its own chip address. The FPGA chip connects to remote computer 1 via serial port module 4, sending and receiving serial port commands from remote computer 1. Simultaneously, the FPGA chip connects to the SMI interface bus of all PHY chips within Ethernet switch 1 via the MDC and MDIO signal lines, allowing it to read and write registers of all PHY chips using the PHY chip addresses. The FPGA chip converts serial port read and write commands into SMI interface read and write signals, thereby reading and writing registers of each PHY chip.

[0062] Among them, such as Figure 4 As shown, the FPGA chip comprises at least four parts: a serial port receiving module 6, a serial port transmitting module 9, a data processing module 7, and an SMI read / write module 8. When the tx_valid flag sent by the data processing module 7 is 1, the serial port transmitting module 9 transmits the 8-bit data to be transmitted, tx_data[7:0], bit by bit, from the tx interface of the serial port module 4 according to the serial port protocol. After the 8-bit data is transmitted, the serial port transmitting module 9 sets the tx_rdy flag connected to the data processing module 7 to 1. After receiving data from the rx port of the serial port module 4, the serial port receiving module 6 parses the data according to the serial port protocol and stores the received serial data in rx_data[7:0]. After receiving the 8-bit data, the serial port receiving module 6 sets the rx_valid flag connected to the data processing module 7 to 1.

[0063] The main function of SMI read / write module 8 is to convert the read / write signals from the data processing module into the SMI interface protocol and read / write the PHY chip registers from the MDIO interface. When data processing module 7 writes PHY chip data, it writes the chip address (phy_addr), register address (reg_addr), write request (write_req), and write data (write_data) to SMI read / write module 8. After the write is complete, SMI read / write module 8 sets the transfer completion signal (done) to 1. When data processing module 7 needs to read PHY chip registers, it outputs the PHY chip address (phy_addr), register address (reg_addr), and read request (read_req) to SMI read / write module 8. SMI read / write module 8 then outputs the read data (read_data) to data processing module 7. After the data is sent, it sets the data valid signal (data_valid) to 1 and the transfer completion signal (done) to 1.

[0064] The data processing module 7 mainly completes the parsing of serial port instructions and completes the read and write operations of the PHY chip according to the instructions. This module implements related functions through a state machine. In addition, this application designs a set of serial port instruction protocols for the read and write operations of the PHY chip. The serial port read instruction is the start frame (16 bits, the value is 55aa in hexadecimal), the read instruction (3 bits, the value is 111), the PHY chip address (5 bits) and the register address (8 bits, the lower 5 bits are valid). The write instruction is the start frame (16 bits, the value is 55aa in hexadecimal), the read instruction (3 bits, the value is 111), the PHY chip address (5 bits), the register address (8 bits, the lower 5 bits are valid), the write data high 8 bits, and the write data low 8 bits.

[0065] like Figure 5 As shown, after the system is powered on, it enters the idle state. When it detects that the serial port has received the 16-bit start frame 16'h55aa, it enters the read and write instruction state. At this time, if the upper 3 bits of the 8-bit serial port data received are 3'b111, it jumps to the read address receiving state. If they are 3'b000, it jumps to the write address receiving state. In this state, the lower 5 bits of the 8-bit serial port data received are the phy chip address, which is stored in phy_addr[4:0].

[0066] In the read address receiving state, the lower 5 bits of the 8-bit data received by the serial port are the register address, which is stored in reg_addr[4:0], and then jumps to the smi read state. In the smi read state, read_req is set to 1, so that the smi read-write module 8 starts sending a read instruction to the PHY chip. Detecting that data_valid is 1 indicates that the read is complete. At this time, read_data[15:0] is the read PHY chip register data, and then jumps to the smi read completion state. In the smi read completion state, the data in read_data[15:0] is sent to the remote computer 1 through the serial port sending module. After the serial port transmission is completed, that is, when tx_rdy is 1, it jumps to the idle state to complete the reading process. Here, the serial port read instruction is shown in Table 1, for example, and the x in Table 1 represents an invalid bit.

[0067] Table 1 Serial port read instructions

[0068]

[0069] In the write address receiving state, the lower 5 bits of the 8-bit data received by the serial port are the register address, which are stored in reg_addr[4:0], and then jump to the smi write data receiving state. In the smi write data receiving state, the two consecutive 8-bit data received by the serial port are the upper 8 bits and lower 8 bits of the write data, which are stored in write_data[15:0], and then jump to the smi write state. In the smi write state, write_req is set to 1, so that the smi read-write module 8 starts sending write instructions to the PHY chip. When done is detected as 1, it indicates that the write is completed, and then jumps to the smi write completion state. In the smi write completion state, the "ok" character is sent to the remote computer 1 through the serial port. After the serial port transmission is completed, that is, when tx_rdy is 1, it jumps to the idle state to complete the write process. Here, the serial port write instruction is shown in Table 2, where x represents an invalid bit.

[0070] Table 2 Serial port write instructions

[0071]

[0072] like Figure 6 As shown in the figure, this figure is a flowchart of a method for remotely reading and writing PHY chip registers provided in an embodiment of the present application, the method comprising the following steps:

[0073] Receive serial port commands forwarded by the serial port module 4; the serial port commands are issued by the remote computer 1; the serial port commands are read commands or write commands;

[0074] Read or write the register of the corresponding PHY chip module 5 according to the serial port instruction, and generate a prompt signal when the read or write operation is completed;

[0075] The prompt signal is sent to the serial port module 4 ; the serial port module 4 is used to forward the prompt signal to the remote computer 1 .

[0076] This application will design an Ethernet switch 2, using an FPGA chip unit 3, a serial port module 4 and multiple PHY chip modules 5 to form the core structure of the Ethernet switch. The serial port instructions and feedback prompt signals are mainly received through the FPGA chip unit 3 and the serial port module 4, so that the remote computer 1 can read and write the registers of the PHY chip module 5 in the Ethernet switch 2, thereby improving the overall compatibility and reliability of the system.

[0077] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention herein is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A system for remotely reading and writing PHY chip registers, characterized in that: include: An Ethernet switch (2) connected to a remote computer (1); The Ethernet switch (2) comprises: a communication-connected FPGA chip unit (3), a serial port module (4), and a plurality of PHY chip modules (5); The PHY chip module (5) is used to receive or send network data; The remote computer (1) is used to send serial port instructions; the serial port instructions are read instructions or write instructions; The serial port module (4) is used to forward the serial port instruction to the FPGA chip unit (3); The FPGA chip unit (3) is used to read or write the register of the corresponding PHY chip module (5) according to the serial port instruction, and generate a prompt signal when the read or write operation is completed; The serial port module (4) is further used to send the prompt signal to the remote computer (1); the FPGA chip unit (3) includes: A serial port receiving module (6), the serial port receiving module (6) is used to receive the serial port instruction forwarded by the serial port module (4); A data processing module (7), the data processing module (7) is used to generate a read / write signal according to the serial port instruction; an SMI read / write module (8), the SMI read / write module (8) being used to convert the read / write signal into an SMI interface protocol, read or write the corresponding register of the PHY chip module (5), and generate a prompt signal when the read or write operation is completed, and feed it back to the data processing module (7); A serial port sending module (9) is used to receive the prompt signal forwarded by the data processing module (7) and send the prompt signal to the serial port module (4).

2. A system for remotely reading and writing PHY chip registers according to claim 1, characterized in that: The Ethernet switch (2) further comprises: A switching chip module (10) is communicatively connected to each of the PHY chip modules (5) and is used to transmit network data to each of the PHY chip modules (5).

3. A system for remotely reading and writing PHY chip registers according to claim 2, characterized in that: The switching chip module (10) is communicatively connected to the PHY chip module (5) via an RGMII interface.

4. A system for remotely reading and writing PHY chip registers according to claim 1, characterized in that: The Ethernet switch (2) further comprises: The network port modules (11) correspond in number to the PHY chip modules (5) and are communicatively connected in a one-to-one manner. The network port modules (11) are used to transmit data received from an external device to the corresponding PHY chip module (5).

5. The system for remotely reading and writing PHY chip registers according to claim 1, characterized in that: The FPGA chip unit (3) is connected to all the PHY chip modules (5) via an SMI interface.

6. A method for remotely reading and writing PHY chip registers, implemented based on the system according to any one of claims 1 to 5, characterized in that: The method comprises the following steps: receiving a serial port instruction forwarded by the serial port module (4); the serial port instruction is issued by the remote computer (1); the serial port instruction is a read instruction or a write instruction; Reading or writing the corresponding register of the PHY chip module (5) according to the serial port instruction, and generating a prompt signal when the read or write operation is completed; The prompt signal is sent to the serial port module (4); the serial port module (4) is used to forward the prompt signal to the remote computer (1).

7. A method for remotely reading and writing PHY chip registers according to claim 6, characterized in that: According to the serial port instruction, the register of the corresponding PHY chip module (5) is read or written, and a prompt signal is generated when the read or write operation is completed, specifically comprising the following steps: When the serial port receiving module (6) receives data from the rx of the serial port module (4), it parses it according to the serial port protocol and stores the received serial port data in rx_data[7:0]. After receiving the 8-bit data, the serial port receiving module (6) sets the rx_valid connected to the data processing module (7) to 1. When the data processing module (7) writes data to the PHY chip, the chip address, register address, write request, and write data are written to the SMI read / write module (8), and after the write operation is completed, the SMI read / write module (8) sets the prompt signal to 1; When the data processing module (7) reads the PHY chip register, it outputs the PHY chip address, register address, and read request to the SMI read / write module (8). The SMI read / write module (8) outputs the read data to the data processing module (7), and after the transmission is completed, sets the data valid signal to 1 and sets the prompt information to 1; When the tx_valid sent by the data processing module (7) is 1, the serial port sending module (9) sends the 8-bit data tx_data[7:0] to be sent from the tx interface of the serial port module (4) bit by bit according to the serial port protocol, and after the 8-bit data is sent, the serial port sending module (9) sets the tx_rdy of the data processing module (7) to 1.

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