Systems, apparatus, and methods for utilizing surface mount techniques on metal substrates

Abstract

A method for forming a circuit pattern on an integrated substrate structure includes providing an insulating surface including a pattern forming portion. An activation ink is deposited only on the pattern forming portion to form a non-conductor isolation layer. A first metal layer is formed on the non-conductor isolation layer by electroless plating. A patterned portion of the first metal layer is isolated from a remaining portion of the first metal layer to form the circuit pattern. A non-conductive mask layer is applied over the first metal layer. A second metal layer is formed on the non-conductor mask layer. A surface mount land pattern and a pad configuration are determined. A solder mask layer is applied to the patterned portion. A protective layer is applied to protect the pad region not covered by the solder mask layer. The electrical component may then be mounted to the pad (s).

Description

This application is a divisional application of the Chinese invention patent application with the application date of June 15, 2017, application number 201780092153.5, and invention name “Systems, devices and methods for utilizing surface mounting technology on a metal substrate”. Technical Field

[0001] The present disclosure relates generally to the formation of electronic circuits and electronic devices, and particularly to methods using surface mount technology on metal substrates. Background Art

[0002] As electronics and process equipment develop, the demand for miniaturized and integrated electronic components continues to increase. Currently, many conventional device components are assembled using soldering techniques. For these techniques, components are typically soldered to a rigid or flexible printed circuit substrate to form a printed circuit board assembly (PCBA), which has a typical lead-free process temperature range of 220 to 250°C or higher, or a typical tin-lead process temperature range of 180 to 220°C. Once the PCBA is formed, it is then attached or integrated into a device, device part, or product chassis, for example, to form a final product.

[0003] With the advent of 3-dimensional (3D) printing and structural electronics, devices or products (often relatively miniature) of various and / or unique shapes, sizes, and / or dimensions are being manufactured, and these unique devices and products often require dedicated cavities, spaces, and / or areas to accommodate the aforementioned PCBA circuits. Among various disadvantages (such as the at least partially inflexible nature of most conventional PCBA circuit arrangements), inserting electronic devices into these devices can incur significant costs in terms of space requirements, which is highly undesirable given the aforementioned unique and often miniature nature of these products and devices. Summary of the invention

[0004] A system and method for placing a surface mount technology component directly onto a metal substrate having a circuit pattern is described herein. The method for forming a circuit pattern on a metal substrate structure includes providing a metal substrate structure having an insulating surface, the insulating surface including a pattern forming portion. Depositing (i.e., printing and other similar techniques) activated ink only on the pattern forming portion of the insulating surface to form a non-conductive isolation layer on the pattern forming portion of the insulating surface. A first metal layer is formed on the non-conductive isolation layer by electroless plating. The patterned portion of the first metal layer is isolated from the remaining portion of the first metal layer to form a circuit pattern. A non-conductor mask layer is applied to the first metal layer. A second metal layer is formed on the non-conductor mask layer. A surface mount land pattern and a pad configuration are determined. A solder mask layer is applied to the patterned portion to protect the circuit pattern. A protective layer is applied to protect the pad area not covered by the solder mask layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0006] Figure 1 is a flow chart illustrating a method for placing a surface mount technology component on a metal substrate having a circuit pattern according to certain embodiments;

[0007] Figure 2 is an example metal substrate according to certain embodiments;

[0008] Figure 3 is a flow chart for preparing an insulated metal substrate according to certain embodiments;

[0009] Figure 4 is a schematic diagram showing forming an activation layer or a circuit layer on a portion of an insulating surface on an insulating metal substrate according to certain embodiments;

[0010] Figure 5 is a pad structure for placing a surface mount technology component according to certain embodiments;

[0011] Fig. 6A and 6B is a schematic diagram showing a surface mount technology component mounted on a metal substrate having a circuit pattern according to certain embodiments;

[0012] Figure 7 is an example photograph of a surface mount technology component lead soldered to a pad structure on a metal substrate having a circuit pattern according to certain embodiments;

[0013] Figure 8 is an example photograph of a surface mount technology component lead soldered to a pad structure on a metal substrate having a circuit pattern according to certain embodiments;

[0014] Fig. 9 is a thermal map of a conventional arrangement of surface mount technology components on a printed circuit board which are then mounted on a metal substrate; and

[0015] Fig.10 is a thermal map of a surface mount technology component on a metal substrate having a circuit pattern according to certain embodiments. DETAILED DESCRIPTION

[0016] The accompanying drawings and descriptions provided herein may have been simplified to illustrate the aspects related to the device, system and method described herein, and for the sake of clarity, other aspects that can be found in typical similar devices, systems and methods have been eliminated. Therefore, those skilled in the art will recognize that other elements and / or operations may be desirable and / or necessary for realizing the equipment, system and method described herein. But because such elements and operations are known in the art, and because they will not promote a better understanding of the present disclosure, the discussion of such elements and operations may not be provided here. However, the present disclosure is considered to still include all such elements, variations and modifications to the described aspects known to those of ordinary skill in the art.

[0017] Exemplary embodiments are provided throughout so that this disclosure will be thorough and will fully convey the scope of the disclosed embodiments to those skilled in the art. Numerous specific details are set forth, such as examples of specific components, devices, and methods, to provide a thorough understanding of the embodiments of the present disclosure.

[0018] However, it is obvious to those skilled in the art that the specific disclosed details need not be adopted, and the exemplary embodiments may be implemented in different forms. Therefore, the exemplary embodiments should not be interpreted as limiting the scope of the present disclosure. In some exemplary embodiments, well-known processes, well-known device structures, and well-known technologies may not be described in detail.

[0019] The terms used herein are only for describing specific exemplary embodiments, rather than for limiting. As used herein, the singular forms "one", "an" and "the" may also be intended to include plural forms, unless the context clearly indicates otherwise. The terms "include", "comprise", and "have" are inclusive, and therefore specify the existence of stated features, integers, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or their combinations. The steps, processes and operations described herein should not be interpreted as necessarily requiring them to be performed in the particular order discussed or shown, unless specifically identified as a preferred or required execution order. It should also be understood that additional or alternative steps may be used to replace the disclosed aspects or to be combined with the disclosed aspects.

[0020] When an element or layer is referred to as being "on," "engaged to," "connected to," or "coupled to" another element or layer, it may be directly on, engaged to, connected to, or coupled to another element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on," "directly engaged to," "directly connected to," or "directly coupled to" another element or layer, there may be no intermediate elements or layers. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0021] Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts here, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Unless the context clearly indicates, the terms such as "first", "second" and other numerical terms do not imply order or sequence when used herein. Therefore, without departing from the teaching of exemplary embodiments, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part.

[0022] A system and method for placing surface mount technology (SMT) directly onto a metal substrate or similar substrate having a circuit pattern is described herein. For purposes of illustration only, an integrated substrate may include a metal substrate covered by a thin layer of dielectric and a copper layer.

[0023] Figure 1 1 is an assembly process flow or flowchart 100 showing a method for placing surface mount technology components on a metal substrate having a circuit pattern. An integrated substrate structure is provided that can be processed for placement of SMT components (block 102). The integrated substrate structure can be 2-dimensional, 2.5-dimensional, or 3-dimensional for use in electronic devices and systems. The integrated substrate structure can be formed using various techniques known to those of ordinary skill in the art, such as one of the insulated metal substrate technologies developed by ON Semiconductor. Figure 2 An exemplary metal base heat sink 200 is shown in FIG.

[0024] according to Figure 3 The integrated substrate structure is processed using printed laser selective plating (PLSP), which is described in U.S. Patent Application Publication 2016 / 0186327, filed on December 23, 2015, and which is incorporated herein by reference as if fully set forth. In particular, Figure 3is an exemplary method or flow chart 300 for forming a circuit pattern on a metal structure. Figure 2 , 4 and 5 description Figure 3 . Figure 4 An exemplary process integrated substrate structure 400 is shown, Figure 5 An exemplary pad structure 500 is shown.

[0025] As described above, an integrated substrate structure (also referred to herein as a substrate) is provided (block 305). For example, the integrated substrate structure may be part of a product (such as a cellular phone, a touch panel, a watch, eyeglasses, etc.) that uses the heat sink 200. Referring now also to Figure 4 , the integrated substrate structure is schematically shown as layer 405, which can be a metal, dielectric and copper structure. Where an insulating layer 410 is required, this can be formed by spraying, screen printing, transfer printing, etc., and can be made of an insulating paint or ink (box 310). The insulating surface 410 is not limited to being planar, i.e. the insulating surface 410 can follow the structure of the integrated substrate structure.

[0026] An activation ink is printed on a portion 415 (pattern forming area) of the insulating surface 410 so as to form a nonconductor isolation layer or activation layer 420 on the portion 415 of the insulating surface 410 (block 315). Note that before the processing described herein, the nonconductor isolation layer 420 initially has the same size as the portion 415. In some embodiments, the nonconductor isolation layer 420 may include a catalyst metal element selected from the group consisting of palladium, rhodium, platinum, silver, and combinations thereof. In some embodiments, the nonconductor isolation layer 420 may be made of a nonconductive metal oxide compound. The activation ink printing may be performed by digital printing, screen printing, pad printing, transfer printing, coating, spraying, or powder coating techniques. These techniques are illustrative and non-limiting. The activation ink may include, but is not limited to, N-methyl-2-pyrrolidone (NMP), which may slightly etch the insulating surface 410 when applied to the insulating surface 410. In this way, the conventional step of roughening the insulating surface 410 to increase the bonding strength between the activation layer 420 and the insulating surface 410 may be omitted.

[0027] A first metal layer 425 is formed on the activation layer 420 by electroless plating (block 320). In some embodiments, this can be performed by placing the substrate with the non-conductor isolation layer 420 in an electroless plating solution for a predetermined period of time in order to perform an electroless plating reaction. In some embodiments, the first metal layer 425 may have a thickness ranging from 0.1 μm to 0.25 μm. In some embodiments, the first metal layer 425 may be made of nickel, but is not limited thereto. For example, in some embodiments, the first metal layer 425 may be made of copper.

[0028] The patterned portion 422 (also referred to as a circuit or trace pattern) is isolated from the remaining portion 423 (block 325), wherein the portion 415 is equal to the patterned portion 422 plus the remaining portion 423. In some embodiments, the method may include removing a portion of the first metal layer 425 so as to form a gap (not shown) along the periphery of the patterned portion 422 to isolate the patterned portion 422 of the first metal layer 425. The removal of the portion of the first metal layer 425 may be performed by laser ablation. In some embodiments, the patterned portion 422 of the first metal layer 425 may be surrounded by the remaining portion 423 of the first metal layer 425. In some embodiments, the patterned portion of the non-conductor isolation layer 420 may be isolated, for example, by laser ablation, wherein the patterned portion of the non-conductor isolation layer 420 corresponds in position to the patterned portion 422 of the first metal layer 425 as described herein. In some embodiments, in the case where the activation layer 420 is non-conductive, the gap does not need to extend into the non-conductor isolation layer 420 in consideration of the subsequent electroplating process.

[0029] The second metal layer 430 is formed on the patterned portion 422 of the first metal layer 425 by electroplating (block 330). In some embodiments, the second metal layer 430 may be made of copper, i.e., a copper-containing electroplating solution and a copper electrode are used during the electroplating process. In some embodiments, the second metal layer 430 may have a thickness ranging from 0.2 μm to 0.5 μm. Since the patterned portion 422 of the first metal layer 425 is isolated from the remaining portion 423, the second metal layer 430 may be formed only on the patterned portion 422 of the first metal layer 425 during the electroplating process.

[0030] In some embodiments, the method may further include a step of removing the remaining portion 423 of the first metal layer 425. According to the present disclosure, such a step may be performed by wet etching technology or laser ablation, and is not limited thereto.

[0031] In some embodiments, the method may further include a step of removing a portion of the non-conductor isolation layer 420 located outside the patterned portion 422. This step may be performed by applying a stripping solution to the substrate, such as by spraying the stripping solution onto the substrate or by immersing the substrate in the stripping solution. In this way, the non-conductor isolation layer 420 is softened by the stripping solution, and the bond between the non-conductor isolation layer 420 and the insulating surface 410 of the substrate is weakened, thereby allowing it to be removed from the insulating surface 410 of the substrate. In some embodiments, the step of removing the non-conductor isolation layer 420 may be performed by laser ablation.

[0032] Determine the surface mount connection pad pattern (one or more) for welding, and then determine the pad configuration for the determined pattern (box 335). In order to provide the desired connectivity and increase the reliability of the attachment of the surface mount component, the specific pad layout on the integrated substrate structure can be designed to increase and / or maximize the amount of contact between the integrated substrate structure and the pad surface area. Such a structure should promote a stronger bond through mechanical and chemical bonding, and can also help absorb at least some of the forces generated by the potential mismatch of CTE between the traces, substrates, interconnect materials, and component terminals. Figure 5 An exemplary pad configuration 500 is shown, specifically, an integrated substrate structure 505 having pads 510 and components 515 mounted on pads 510. Those skilled in the art will appreciate that other pad configurations / geometries are contemplated in the present disclosure to allow for soldering applications to contact pads and integrated substrate structures.

[0033] A solder mask layer may be applied to cover the copper traces (e.g., patterned portion 422) to prevent corrosion and electrical shorts, oxidation, and environmental impacts (block 340). If a solder mask is not applied, the pad configuration design may be reconsidered. Test points and fiducial markers may or may not be required for the bonding pads. In addition, a silk screen may be applied as a reference designator and pin marker for each SMT component designed for the integrated substrate structure. Figure 6B An exemplary solder mask is shown in FIG.

[0034] A protective layer is applied to protect the pad areas not covered by the solder mask layer and prevent oxidation (block 345). For example, a surface finishing / plating layer may be applied, which may be a resin laminated with multiple metal layers, which may include copper (Cu), nickel (Ni) and / or gold (Au), etc. Organic solderability preservatives (OSP) may be used for high temperature / normal temperature integrated substrate structure configurations. Preferably, a smooth, glossy plating should be used instead of matte surface finishes, because a rough plating surface may form inconsistent intermetallic compound thickness, which may affect bonding reliability performance.

[0035] Return to reference Figure 1, perform material inspection and measurement manually or by using machine vision technology (box 104). Once the inspection is successfully completed, the SMT component is placed on the pad of the integrated substrate structure (box 106). In an exemplary embodiment, for example, for a 2D structure, a conventional SMT machine can use a typical SMT pick and place process. For a 2.5D or 3D structure, a special 3D capable placement machine can be used. In an exemplary embodiment, solder or similar bonding materials are used to attach the SMT components to the integrated substrate structure. In particular, solder paste materials and online reflow technology can be used for the component-substrate bonding process.

[0036] Once the SMT layout is determined, a reflow and / or curing process (if necessary) is performed (in block 108), followed by electrical testing (block 110) and inspection (block 112). Inspection can be performed manually or automatically, for example using machine vision technology.

[0037] As mentioned above, Figure 2 is an example of a bare metal structure according to certain embodiments. Fig. 6A and 6B Is using about Figure 1 and 3 An example of an integrated substrate structure following the described method, Fig. 6A An integrated substrate structure 600 populated with surface mount components 610 is shown. Figure 6B An exploded view is shown showing an isolation layer 615 (see box 315 ), a copper layer 620 (see box 330 ), a solder mask 625 (see box 340 ), surface mount components such as LEDs 630 , and connectors 635 .

[0038] Figure 7 is an exemplary photograph of surface mount technology component leads 705 soldered to pad structures 710 on integrated substrate structure 700 in accordance with certain embodiments. Figure 8 is an exemplary photograph of surface mount technology component leads 805 soldered to pad structures 810 on an integrated substrate structure in accordance with certain embodiments.

[0039] Fig. 9 is a thermal diagram of a conventional arrangement of surface mount technology components on a printed circuit board mounted on a metal substrate. Fig.10 is a thermal map of a surface mount technology component on an integrated substrate structure according to certain embodiments. It is evident from the thermal map that there is greater and more uniform heat dissipation in the integrated substrate structure processed according to the methods described herein. The copper thickness and size need to be evaluated from an early stage to meet the specific application requirements of the final product, for example, for high power product applications, thicker and larger copper sizes may be required for better heat dissipation.

[0040] Users are able to assemble SMT components directly onto 3D structures to form the final product, and are able to integrate mechanical and electronic functions into a single device. Other advantages include, but are not limited to, enabling device miniaturization, integration, rationalization, and feature advancement; providing shape flexibility and hybrid configurations that can shorten the process chain; providing greater design flexibility to further improve portability and functionality; reducing the number of components and substrates and the total assembly time through integration. There are a variety of industrial applications, including but not limited to automotive lighting applications, consumer applications (e.g., wireless chargers, power transmission touch sensors, camera modules, etc.), industrial applications (e.g., sensors, power controllers, battery containers, switch modules, OLEDs, etc.) and microelectronics, especially power electronics applications with high heat dissipation requirements, i.e., LED lighting, power conversion, motor drives, and semiconductor modules, etc.

[0041] While the present disclosure has been described in connection with what are considered to be exemplary embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.

Claims

1. A method for forming a circuit pattern on a substrate, comprising the following steps: providing a substrate having an insulating surface including a pattern forming portion; printing only on the pattern-forming portion of the insulating surface using an activated ink to form a non-conductive insulating layer on the pattern-forming portion of the insulating surface; forming a first metal layer on the non-conductive isolation layer by electroless plating; isolating the patterned portion of the first metal layer from a remaining portion of the first metal layer to form the circuit pattern; forming a second metal layer on the patterned portion of the first metal layer; removing a remaining portion of the first metal layer; Determining a surface mount land pattern and land configuration to maximize contact between the substrate and the surface mount land pattern and land area, thereby increasing reliability of attachment of the surface mount component and mitigating mismatches in coefficients of thermal expansion between the circuit pattern, the substrate, interconnect material, and surface mount component terminals; applying a solder mask layer to cover the patterned portion; applying a silk screen layer as a reference designator and pin marker for the surface mount component; applying a protective layer to protect the pad areas not covered by the solder mask layer, wherein the protective layer comprises a glossy plating layer; and The substrate is reflowed or cured.

2. The method according to claim 1, wherein: The step of printing using the activated ink is performed by one of digital printing, screen printing, pad printing, transfer printing, coating, spraying, and powder coating. 3 . The method of claim 1 , wherein the step of isolating the patterned portion of the first metal layer is performed by laser ablation.

4. The method of claim 3, wherein the step of isolating the patterned portion of the first metal layer comprises: Portions of the first metal layer are removed along a periphery of the patterned portion to isolate the patterned portion of the first metal layer.

5. The method of claim 3, further comprising the step of isolating a patterned portion of the non-conductor isolation layer, the patterned portion of the non-conductor isolation layer being formed in the pattern forming region and corresponding in position to the patterned portion of the first metal layer. The method of claim 1 , wherein the nonconductor isolation layer is nonconductive. 7 . The method according to claim 1 , wherein the substrate comprises a metal base layer and an insulating layer formed on the metal base layer to provide the insulating surface. 8 . The method of claim 1 , wherein the step of forming the second metal layer on the patterned portion of the first metal layer is performed by electroplating. 9 . The method of claim 1 , wherein the patterned portion of the first metal layer is surrounded by the remaining portion of the first metal layer.

10. The method of claim 1, wherein the activated ink comprises N-methyl-2-pyrrolidone.

11. The method according to claim 1, further comprising: The surface mount components are soldered to pads on the substrate.

12. An electronic circuit, comprising: An integrated substrate structure comprising one or more conductive traces, the one or more conductive traces comprising: a non-conductor insulating layer formed from an activated ink printed in a pattern forming area of ​​the insulating surface of the integrated base structure; a first metal layer formed on the non-conductive isolation layer; and a second metal layer formed on the laser-etched patterned portion of the first metal layer, wherein the laser-etched patterned portion is isolated from a remainder of the patterned region of the insulating surface; one or more conductive pads located at one or more predetermined locations along the one or more conductive traces, wherein the one or more conductive pads maximize a surface area between the integrated substrate structure and the one or more conductive pads to absorb at least some forces generated by a potential mismatch in coefficient of thermal expansion between the one or more conductive traces and the integrated substrate structure; a solder mask layer covering the one or more conductive traces and leaving the one or more conductive pads exposed; a silk screen configured as a reference designator and a pin marker for an electrical component; a protective layer covering the one or more conductive pads left exposed by the solder mask layer, wherein the protective layer comprises a glossy plating layer; and an electrical component surface mounted to the one or more conductive pads using interconnect and bonding materials, Wherein the integrated substrate structure is 2.5-dimensional or 3-dimensional.

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