Semiconductor device structure and manufacturing method thereof

Abstract

The embodiment of the invention relates to the technical field of semiconductors, and provides a semiconductor device structure and a manufacturing method thereof, and the semiconductor device structure comprises a substrate which is provided with a source electrode region and a drain electrode region which are spaced from each other; the gate structure is arranged on the upper surface of the substrate; the plurality of conductive columns are respectively contacted with the source electrode region and / or the drain electrode region; wherein the gate structure comprises a gate of which the length extends along a first direction and a gate oxide layer arranged between the gate and the substrate; the source electrode region and / or the drain electrode region are / is provided with at least one sunken structure, and the at least one conductive column is arranged in the sunken structure; and in the plurality of conductive columns in contact with one of the source electrode region or the drain electrode region, the heights of the positions, in contact with the substrate, of two adjacent conductive columns in the thickness direction of the substrate are different. The embodiment of the invention is at least beneficial to reducing the coupling influence between different conductive columns and improving the integration density of the semiconductor device structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor device structure and a method for manufacturing the same. Background Art

[0002] In dynamic random access memory (DRAM), it is hoped that the layout area of ​​various circuits can be further reduced so that DRAM can be further scaled. However, as the integration density of DRAM is further improved, the performance of each electrical device in the circuit, such as a transistor, will be reduced, and the reduction in the spacing between electrical devices will increase the coupling effect on each other, which will limit the scaling of DRAM. Summary of the invention

[0003] The embodiments of the present disclosure provide a semiconductor device structure and a method for manufacturing the same, which are at least beneficial for reducing the coupling effect between different conductive pillars and improving the integration density of the semiconductor device structure.

[0004] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor device structure, including: a substrate provided with a source region and a drain region spaced apart from each other; a gate structure arranged on the upper surface of the substrate; and a plurality of conductive pillars respectively contacting the source region and / or the drain region; wherein the gate structure includes a gate whose length extends along a first direction and a gate oxide layer arranged between the gate and the substrate; the source region and / or the drain region has at least one recessed structure, and at least one of the conductive pillars is arranged in the recessed structure; among the plurality of conductive pillars contacting one of the source region or the drain region, the positions where two adjacent conductive pillars contact the substrate have different heights in the thickness direction of the substrate.

[0005] In some embodiments, the source region and / or the drain region has a plurality of the recess structures arranged at intervals along the first direction.

[0006] In some embodiments, the substrate further includes a channel region disposed between the source region and the drain region, and the channel region also has a plurality of the recess structures arranged at intervals along the first direction.

[0007] In some embodiments, the plurality of recessed structures disposed on the substrate are arranged in an array.

[0008] In some embodiments, a plurality of the recess structures spaced apart along the first direction form a column of recess groups, and the recess structures in two adjacent columns of the recess groups are staggered.

[0009] In some embodiments, the substrate further includes a channel region disposed between the source region and the drain region, and a groove having a length extending along the first direction is disposed in the substrate, and the groove is at least partially located in the channel region.

[0010] In some embodiments, the source region has a first portion close to the channel region and a second portion away from the channel region, and the thickness of the first portion in the second direction gradually decreases along the direction from the source region to the drain region; and / or, the drain region has a third portion close to the channel region and a fourth portion away from the channel region, and the thickness of the third portion in the second direction gradually increases along the direction from the source region to the drain region; wherein the second direction is the thickness extension direction of the gate.

[0011] In some embodiments, along the second direction, the first portion has a relative first side and a second side, the first side is inclined toward the second side, and the second side is inclined toward the first side; and / or, along the second direction, the third portion has a relative third side and a fourth side, the third side is inclined toward the fourth side, and the fourth side is inclined toward the third side.

[0012] In some embodiments, at least a portion of the gate is located in the groove, the first direction and the second direction constitute a reference plane, and in the second direction, the length of the overlapping area of ​​the gate and the positive projection of any of the conductive columns on the reference plane is less than the thickness of the gate, wherein the second direction is the thickness extension direction of the gate.

[0013] In some embodiments, the gate and the gate oxide layer both have shapes matching a surface of the channel region.

[0014] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a semiconductor device structure, comprising: providing a substrate, the substrate comprising an initial substrate and a first doping region and a second doping region arranged in the initial substrate; forming a mask layer on the substrate, the mask layer having at least one first opening directly opposite to the first doping region and / or the second doping region to expose a portion of the surface of the first doping region and / or the second doping region; performing oxidation treatment on the substrate based on the mask layer to form an oxide layer; removing the mask layer and the oxide layer to leave the initial substrate as a substrate, The remaining first doped region is a source region, and the remaining second doped region is a drain region, so that the source region and / or the drain region has at least one recessed structure; a gate structure whose length extends along a first direction is formed based on the substrate; a dielectric layer at least covering the source region and the drain region is formed, and the dielectric layer has a plurality of vias; conductive columns are formed in the plurality of vias, and at least one conductive column is arranged in the recessed structure; wherein, among the plurality of conductive columns contacting one of the source region or the drain region, the positions at which two adjacent conductive columns contact the substrate are different in height in the thickness direction of the substrate.

[0015] In some embodiments, the mask layer directly opposite to the first doping region and / or the second doping region has a plurality of first openings arranged at intervals along the first direction.

[0016] In some embodiments, the mask layer has a middle portion directly opposite to the first doping region and the second doping region, and the middle portion also has a plurality of first openings arranged at intervals along the first direction to expose a portion of the surface of the initial substrate located between the first doping region and the second doping region.

[0017] In some embodiments, the plurality of first openings of the mask layer are arranged in an array.

[0018] In some embodiments, the mask layer has a middle portion directly opposite to the first doping region and the second doping region, and the middle portion has a second opening extending along the first direction.

[0019] In some embodiments, the second opening further exposes a portion of the surface of the first doping region and a portion of the surface of the second doping region.

[0020] In some embodiments, after forming the mask layer and before forming the oxide layer, the manufacturing method further includes: patterning the substrate using the mask layer as a mask so that the surface of the remaining substrate exposed by the first opening is recessed toward the interior of the substrate.

[0021] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0022] At least one of the source region and the drain region has at least one recessed structure. It can be understood that the surface of the source region or the drain region having the recessed structure will present an uneven morphology. On this basis, at least one of the multiple conductive pillars in contact with one of the source region or the drain region is arranged in the recessed structure, which is conducive to making the positions of the two adjacent conductive pillars in contact with the substrate in the thickness direction of the substrate different in height, that is, in the thickness direction of the substrate, the conductive pillars located in different areas of the substrate surface are staggered, which is conducive to reducing the facing area between adjacent conductive pillars, thereby helping to reduce the coupling effect between different conductive pillars. In addition, on the basis of reducing the coupling effect between adjacent conductive pillars, the spacing between adjacent conductive pillars can be further reduced to improve the integration density of the semiconductor device structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic diagram of a partial top view of a semiconductor device structure provided by an embodiment of the present disclosure;

[0025] Figure 2 A schematic diagram of a partial cross-sectional structure of a semiconductor device structure provided by an embodiment of the present disclosure along a first cross-sectional direction AA1;

[0026] Figure 3 A schematic diagram of a partial cross-sectional structure of a semiconductor device structure provided by an embodiment of the present disclosure along a second cross-sectional direction BB1;

[0027] Figure 4 A schematic diagram of a partial top view of a substrate in a semiconductor device structure provided by an embodiment of the present disclosure;

[0028] Figure 5 5a is another partial top view schematic diagram of a substrate in a semiconductor device structure provided by an embodiment of the present disclosure;

[0029] Figure 5 5b is a schematic diagram of a partial cross-sectional structure of a semiconductor device structure provided by an embodiment of the present disclosure along a third cross-sectional direction CC1;

[0030] Figures 6 to 9 Four other partial top view structural schematic diagrams of a substrate in a semiconductor device structure provided in an embodiment of the present disclosure;

[0031] Figures 10 to 12 Three partial cross-sectional structural schematic diagrams of a semiconductor device structure provided by an embodiment of the present disclosure along a fourth cross-sectional direction DD1;

[0032] Fig.13 A flow chart of a method for manufacturing a semiconductor device structure provided by another embodiment of the present disclosure;

[0033] Figures 14 to 25 A schematic structural diagram corresponding to each step in a method for manufacturing a semiconductor device structure provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] As can be seen from the background technology, the performance of semiconductor device structures needs to be improved, and the integration density needs to be improved.

[0035] The present disclosure provides a semiconductor device structure and a manufacturing method thereof. In the semiconductor device structure, at least one of the source region and the drain region has at least one recessed structure. It can be understood that the surface of the source region and the drain region having the recessed structure will present an uneven morphology. On this basis, at least one of the multiple conductive pillars in contact with one of the source region or the drain region is arranged in the recessed structure, which is conducive to making the positions of the two adjacent conductive pillars in contact with the substrate in the thickness direction of the substrate different in height, that is, in the thickness direction of the substrate, the conductive pillars located on different areas of the substrate surface are staggered, which is conducive to reducing the facing area between adjacent conductive pillars, thereby helping to reduce the coupling effect between different conductive pillars. In addition, on the basis of reducing the coupling effect between adjacent conductive pillars, the spacing between adjacent conductive pillars can be further reduced to improve the integration density of the semiconductor device structure.

[0036] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0037] An embodiment of the present disclosure provides a semiconductor device structure, which will be described in detail below with reference to the accompanying drawings. Figure 1 A schematic diagram of a partial top view of a semiconductor device structure provided by an embodiment of the present disclosure; Figure 2 A schematic diagram of a partial cross-sectional structure of a semiconductor device structure provided by an embodiment of the present disclosure along a first cross-sectional direction AA1; Figure 3 A schematic diagram of a partial cross-sectional structure of a semiconductor device structure provided by an embodiment of the present disclosure along a second cross-sectional direction BB1; Figure 4 A schematic diagram of a partial top view of a substrate in a semiconductor device structure provided by an embodiment of the present disclosure; Figure 5 5a is another partial top view schematic diagram of a substrate in a semiconductor device structure provided by an embodiment of the present disclosure;

[0038] Figure 5 5b is a schematic diagram of a partial cross-sectional structure of a semiconductor device structure provided by an embodiment of the present disclosure along a third cross-sectional direction CC1; Figures 6 to 9 Four other partial top view structural schematic diagrams of a substrate in a semiconductor device structure provided in an embodiment of the present disclosure; Figures 10 to 12 Schematic diagrams of three partial cross-sectional structures of a semiconductor device structure along a fourth cross-sectional direction DD1 provided by an embodiment of the present disclosure.

[0039] refer to Figures 1 to 12 The semiconductor device structure includes: a substrate 100 provided with a source region 110 and a drain region 120 spaced apart from each other; a gate structure 101 provided on the upper surface of the substrate 100; and a plurality of conductive pillars 102 respectively contacting the source region 110 and / or the drain region 120; wherein the gate structure 101 includes a gate 111 whose length extends along a first direction X and a gate oxide layer 121 provided between the gate 111 and the substrate 100; the source region 110 and / or the drain region 120 has at least one recessed structure 104, and at least one conductive pillar 102 is provided in the recessed structure 104; among the plurality of conductive pillars 102 contacting one of the source region 110 or the drain region 120, the positions where two adjacent conductive pillars 102 contact the substrate 100 have different heights in the thickness direction of the substrate 100.

[0040] It should be noted that at least one conductive pillar 102 is disposed in the recessed structure 104 in at least the following two situations:

[0041] In some embodiments, reference Figure 1 and Figure 2All the conductive pillars 102 are located in the recessed structure 104, but different conductive pillars 102 may be located in different areas of the same recessed structure 104 or in different recessed structures 104, so that among the multiple conductive pillars 102 contacting one of the source region 110 or the drain region 120, the positions where two adjacent conductive pillars 102 contact the substrate 100 are at different heights in the thickness direction of the substrate 100.

[0042] In some embodiments, the substrate 100 further includes a shallow trench isolation structure 180 embedded therein, and the region of the substrate 100 other than the source region 110, the drain region 120 and the shallow trench isolation structure 180 is a base plate 190. It is understood that the channel region 130 in the subsequent description is a partial thickness of the base plate 190 along the second direction Y.

[0043] In some other embodiments, reference Figure 3 Part of the conductive pillars 102 may be located in the recessed structure 104, and other parts of the conductive pillars 102 may be located in an area of ​​the source region 110 or the drain region 120 where there is no recessed structure 104, so that among the multiple conductive pillars 102 contacting one of the source region 110 or the drain region 120, the positions where two adjacent conductive pillars 102 contact the substrate 100 have different heights in the thickness direction of the substrate 100.

[0044] In addition, the thickness direction of the substrate 100 is the second direction Y, the first direction X and the second direction Y constitute a reference plane, and the different heights of the positions where two adjacent conductive pillars 102 contact the substrate 100 in the thickness direction of the substrate 100 means that: in the second direction, the height of the overlapping area of ​​the orthographic projections of the two adjacent conductive pillars 102 on the reference plane is less than the height of at least one of the two adjacent conductive pillars 102. In other words, taking the flat surface of the side of the substrate 100 away from the gate structure 101 as the reference plane, the different heights of the positions where two adjacent conductive pillars 102 contact the substrate 100 in the thickness direction of the substrate 100 means that: the vertical distances between the two adjacent conductive pillars 102 and the reference plane are different.

[0045] The positional relationship between the plurality of conductive pillars 102 and the source region 110 and the drain region 120 includes at least the following three situations:

[0046] In some embodiments, reference Figure 2 The source region 110 has at least one recessed structure 104 , and the plurality of conductive pillars 102 are all in contact with the source region 110 . The positions where two adjacent conductive pillars 102 contact the source region 110 are at different heights in the second direction Y.

[0047] In other embodiments, reference Figure 3The drain region 120 has at least one recessed structure 104 , and the plurality of conductive pillars 102 are all in contact with the drain region 120 . The positions where two adjacent conductive pillars 102 contact the drain region 120 are at different heights in the second direction Y.

[0048] In some other embodiments, reference Figure 4 , at least one recessed structure 104 is provided in each of the source region 110 and the drain region 120, part of the plurality of conductive pillars 102 are in contact with the source region 110, and the remaining part of the conductive pillars 102 are in contact with the drain region 120. Among the plurality of conductive pillars 102 in contact with the source region 110, the positions where two adjacent conductive pillars 102 are in contact with the source region 110 are at different heights in the second direction Y; and among the plurality of conductive pillars 102 in contact with the drain region 120, the positions where two adjacent conductive pillars 102 are in contact with the drain region 120 are at different heights in the second direction Y.

[0049] It should be noted that the positional relationship between the plurality of conductive pillars 102 and the recessed structure 104 will be described in detail later. In order to facilitate the distinction between the conductive pillars 102 in contact with the source region 110 and the drain region 120, the conductive pillars 102 in contact with the source region 110 are referred to as first conductive pillars 112, and the conductive pillars 102 in contact with the drain region 120 are referred to as second conductive pillars 122.

[0050] It can be understood that whichever of the source region 110 and the drain region 120 has the recessed structure 104, its surface will present an uneven morphology. On this basis, at least one of the multiple conductive pillars 102 in contact with one of the source region 110 or the drain region 120 is disposed in the recessed structure 104, which is conducive to making the positions of the two adjacent conductive pillars 102 in contact with the substrate 100 in the thickness direction of the substrate 100 different in height, that is, in the thickness direction of the substrate 100, the conductive pillars 102 located in different areas of the surface of the substrate 100 are staggered, which is conducive to reducing the facing area between adjacent conductive pillars 102, thereby helping to reduce the coupling effect between different conductive pillars 102. In addition, on the basis of reducing the coupling effect between adjacent conductive pillars 102, the spacing between adjacent conductive pillars 102 can be further reduced to improve the integration density of the semiconductor device structure.

[0051] An embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0052] In some embodiments, reference Figure 2The source region 110 has a plurality of recessed structures 104 arranged at intervals along the first direction X. It is understandable that in practical applications, the source region 110 may also have only one recessed structure 104 , and the plurality of conductive pillars 102 contacting the source region 110 are located at different positions of the recessed structure 104 .

[0053] In other embodiments, reference Figure 3 The drain region 120 has a plurality of recessed structures 104 arranged at intervals along the first direction X. It is understandable that in practical applications, the drain region 120 may also have only one recessed structure 104 , and the plurality of conductive pillars 102 contacting the source region 110 are located at different positions of the recessed structure 104 .

[0054] It should be noted that, in order to clearly illustrate the concave structure 104, Figure 2 and Figure 3 The dotted line in FIG. 1 shows the approximate area of ​​the recessed structure 104. Figure 1 The recess structure 104 is not shown, and the shallow trench isolation structure 180 in the substrate 100 is not drawn.

[0055] In some other embodiments, reference Figure 4 , the source region 110 and the drain region 120 both have a plurality of recess structures 104 arranged at intervals along the first direction X, combined with reference Figures 2 to 4 , some of the conductive pillars 102 are in contact with the source region 110, and the remaining conductive pillars 102 are in contact with the drain region 120. It can be understood that in practical applications, the source region 110 and the drain region 120 may each have only one recessed structure 104, and the plurality of conductive pillars 102 in contact with one of the source region 110 and the drain region 120 are located at different positions of the recessed structure 104 corresponding thereto.

[0056] It should be noted that, in order to clearly illustrate the concave structure 104, Figure 4 The approximate area of ​​the recessed structure 104 is indicated by an ellipse, and the recessed structure 104 is not filled and drawn in the same manner as the source region 110 or the drain region 120. Figure 4 The shallow trench isolation structure 180 in the substrate 100 is not depicted.

[0057] It can be understood that in the various embodiments described above, in the thickness direction of the substrate 100, that is, in the second direction Y, the conductive pillars 102 located in different regions of the surface of the substrate 100 can be arranged in a staggered manner, so that among the multiple conductive pillars 102 that contact one of the source region 110 or the drain region 120, the positions where two adjacent conductive pillars 102 contact the substrate 100 have different heights in the thickness direction of the substrate 100, which is conducive to reducing the facing area between adjacent conductive pillars 102, thereby helping to reduce the coupling effect between different conductive pillars 102. In addition, on the basis of reducing the coupling effect between adjacent conductive pillars 102, the spacing between adjacent conductive pillars 102 can be further reduced to improve the integration density of the semiconductor device structure.

[0058] In some embodiments, reference Figure 5 The substrate 100 may further include a channel region 130 disposed between the source region 110 and the drain region 120 , and the channel region 130 also has a plurality of recess structures 104 arranged at intervals along the first direction X.

[0059] The channel region 130 has a plurality of recessed structures 104 arranged at intervals along the first direction X, and the surface of the channel region 130 presents an uneven morphology, for example, the surface of the channel region 130 presents a wave shape, and the wave fluctuates along the first direction X. It can be understood that, compared with a channel region with a flat surface, the channel width of the channel region 130 provided in an embodiment of the present disclosure is larger, and the width of the channel region 130 along the first direction X will not be increased. Therefore, without increasing the channel length of the channel region 130, it is beneficial to increase the width-to-length ratio of the channel region 130. The source region 110, the drain region 120, the channel region 130 and the gate structure 101 together constitute a transistor, and the on-resistance of the transistor decreases as the width-to-length ratio of the channel region 130 increases, thereby facilitating the increase of the on / off speed of the transistor, so as to improve the performance of the transistor without increasing the size of the transistor.

[0060] It should be noted that the channel width of the channel region 130 refers to the extension width of the uneven surface of the channel region 130 along the first direction X; the channel length of the channel region 130 refers to the extension length of the uneven surface of the channel region 130 along the third direction Z. The third direction Z is the direction from the source region 110 to the drain region 120.

[0061] In some embodiments, reference Figure 6 and Figure 7 , a plurality of recessed structures 104 disposed on the substrate 100 are arranged in an array.

[0062] In some embodiments, reference Figure 6, the multiple recessed structures 104 in the substrate 100 are arranged in a quadrilateral arrangement, that is, the multiple recessed structures 104 are arranged at intervals along the first direction X and also arranged at intervals along the third direction Z. In one example, the first direction X and the third direction Z may be perpendicular to each other. In practical applications, the first direction X and the third direction Z may also be other intersecting situations.

[0063] In other embodiments, reference Figure 7 , a plurality of recess structures 104 arranged at intervals along the first direction X constitute a row of recess groups 114, and the recess structures 104 in two adjacent rows of recess groups 114 are arranged in a staggered manner. Figure 7 , the recess structures 104 in two adjacent rows of recess groups 114 are not arranged at intervals along the third direction Z, and the recess structures 104 in the two recess groups 114 on both sides of the recess group 114 in the middle row of three adjacent rows of recess groups 114 are arranged at intervals along the third direction Z. It should be noted that, Figure 7 This is only one case where the recess structures 104 in two adjacent rows of recess groups 114 are staggered. An embodiment of the present disclosure does not limit the specific case of the staggered arrangement of the recess structures 104 in two adjacent rows of recess groups 114. It only needs to ensure the staggered arrangement, and the specific degree of the staggered arrangement is not limited.

[0064] It should be noted that Figure 7 The plurality of recess structures 104 framed by a dotted frame constitutes a row of recess groups 114 , and only two dotted frames are used to illustrate two adjacent recess groups 114 .

[0065] In the above two embodiments, the multiple recessed structures 104 arranged in an array and provided in the substrate 100 may refer to the multiple recessed structures 104 provided only in the source region 110 and the channel region 130; or, may refer to the multiple recessed structures 104 provided only in the drain region 120 and the channel region 130; or, may refer to the multiple recessed structures 104 provided in the source region 110, the drain region 120 and the channel region 130.

[0066] In this way, the width-to-length ratio of the channel region 130 is increased while reducing the coupling effect between adjacent conductive pillars 102 , thereby improving the electrical performance of the semiconductor device structure.

[0067] It should be noted that, in order to clearly illustrate the arrangement of the plurality of recessed structures 104 in the substrate 100, Figure 6 and Figure 7 In the figure, different filling methods are used for the recessed structure 104 and the substrate 100, and Figure 6 and Figure 7 The source region 110 (reference Figure 5 ), the drain region 120 (reference Figure 5 ) and the channel region 130 (reference Figure 5 ) to distinguish. In addition, Figure 6 and Figure 7 The recessed structure 104 is schematically shown as a rectangle. It is understandable that the top view of the recessed structure 104 has various shapes. The specific shape of the recessed structure 104 will be described later.

[0068] In some embodiments, reference Figure 8 and Fig.12 The substrate 100 may further include a channel region 130 disposed between the source region 110 and the drain region 120 . A groove 105 extending along the first direction X is disposed in the substrate 100 . The groove 105 is at least partially located in the channel region 130 .

[0069] It should be noted that Figure 8 and Fig.12 In the figure, the groove 105 is not only located in the channel region 130, but also located in the portion of the source region 110 in contact with the channel region 130 and the portion of the drain region 120 in contact with the channel region 130. In actual applications, the groove 105 may be located only in the channel region 130, or only in the channel region 130 and the portion of the source region 110 in contact with the channel region 130, or only in the channel region 130 and the portion of the drain region 120 in contact with the channel region 130.

[0070] It should be noted that Figure 8 The thicker dotted line in the figure indicates the approximate area where the groove 105 is located. Fig.12 The dotted line in the figure indicates the approximate area where the groove 105 is located.

[0071] In other embodiments, reference Fig. 9 The substrate 100 may further include a channel region 130 disposed between the source region 110 and the drain region 120 , and a plurality of grooves 105 extending along the first direction X are disposed in the substrate 100 , the plurality of grooves 105 are arranged at intervals along the third direction Z, and each groove 105 is at least partially located in the channel region 130 .

[0072] It should be noted that Fig. 9 The groove 105 is schematically shown as a long rectangle, and the groove 105 and the channel region 130 without the groove 105 are drawn in different ways. Fig. 9 The number of the grooves 105 is taken as 3 as an example. In actual applications, the number of the grooves 105 can be adjusted according to actual needs.

[0073] It should be noted that an embodiment of the present disclosure does not limit the number of recesses 105 in the channel region 130 .

[0074] Understandably, Figure 8 and Fig. 9 In the example shown, the channel region 130 has at least one groove 105 extending along the second direction Y, and the surface of the channel region 130 presents an uneven morphology, for example, the surface of the channel region 130 presents a wave shape, and the wave fluctuates along the third direction Z. In this way, compared with a channel region with a flat surface, the channel length of the channel region 130 provided in an embodiment of the present disclosure is larger, and the layout area of ​​the channel region 130 as a whole in the semiconductor device structure is not increased. Moreover, the smaller the channel length of the channel region 130 in the transistor, the more serious the mismatch between the same transistors, thereby increasing the channel length of the channel region 130 and reducing the mismatch of the transistor.

[0075] In some embodiments, reference Fig.10 The source region 110 has a first portion 110a close to the channel region 130 and a second portion 110b away from the channel region 130. In the direction from the source region 110 to the drain region 120, that is, along the third direction Z, the thickness of the first portion 110a in the second direction Y gradually decreases.

[0076] It can be understood that the source region 110 of the transistor has doped ions, and along the third direction Z, the thickness of the first part 110a in the second direction Y gradually decreases. The number of doped ions in the first part 110a closer to the channel region 130 is smaller, so as to suppress the hot carrier effect and improve the performance of the transistor.

[0077] In some embodiments, along the second direction Y, an average thickness of the second portion 110 b is greater than a maximum thickness of the first portion 110 a .

[0078] In other embodiments, reference Fig.11 The drain region 120 has a third portion 120a close to the channel region 130 and a fourth portion 120b away from the channel region 130. In the direction from the source region 110 to the drain region 120, that is, along the third direction Z, the thickness of the third portion 120a in the second direction Y gradually increases.

[0079] It can be understood that the drain region 120 of the transistor has doped ions, and along the third direction Z, the thickness of the third part 120a in the second direction Y gradually increases. The number of doped ions in the third part 120a closer to the channel region 130 is smaller, so as to suppress the hot carrier effect and improve the performance of the transistor.

[0080] In some embodiments, along the second direction Y, an average thickness of the fourth portion 120 b is greater than a maximum thickness of the third portion 120 a .

[0081] In some other embodiments, reference Fig.12The source region 110 has a first portion 110a close to the channel region 130 and a second portion 110b far from the channel region 130, and the drain region 120 has a third portion 120a close to the channel region 130 and a fourth portion 120b far from the channel region 130. Along the third direction Z, the thickness of the first portion 110a in the second direction Y gradually decreases, and the thickness of the third portion 120a in the second direction Y gradually increases. In this way, the hot carrier effect can be suppressed by both the first portion 110a and the third portion 120a, which is conducive to further improving the performance of the transistor.

[0082] In some embodiments, along the second direction Y, the average thickness of the second portion 110 b is greater than the maximum thickness of the first portion 110 a , and the average thickness of the second portion 110 b is greater than the maximum thickness of the first portion 110 a .

[0083] It should be noted that Figures 10 to 12 In the figure, a dotted line is used to indicate the approximate area of ​​the groove 105, another dotted line is used to indicate the approximate area of ​​the channel region 130, and a first portion 110a and a second portion 110b in the source region 110 and a third portion 120a and a fourth portion 120b in the drain region 120 are indicated by a dotted line.

[0084] In the above embodiment, the second direction Y is the thickness extension direction of the gate 111 , that is, the thickness extension direction of the substrate 100 .

[0085] It should be noted that the doping type of the doping ions in the source region 110 and the drain region 120 can be the same, for example, both are first doping ions, and the channel region 130 has second doping ions, which are different from the first doping ions. Among them, one of the first doping ions and the second doping ions is a P-type doping ion, and the other is an N-type doping ion. Specifically, the N-type doping ion is at least one of arsenic ions, phosphorus ions, or antimony ions; the P-type doping ion is at least one of boron ions, indium ions, or gallium ions.

[0086] The first portion 110 a and the third portion 120 a are described in detail below.

[0087] In some embodiments, reference Fig.10 , along the second direction Y, the first portion 110 a has a first side a and a second side b opposite to each other, the first side a is inclined toward the second side b, and the second side b is inclined toward the first side a. In other words, the source region 110 has a tip toward the channel region 130 .

[0088] In other embodiments, reference Fig.11, along the second direction Y, the third portion 120 a has a third side c and a fourth side d opposite to each other, the third side c is inclined toward the fourth side d, and the fourth side d is inclined toward the third side c. In other words, the drain region 120 has a tip toward the channel region 130 .

[0089] In some other embodiments, reference Fig.12 , along the second direction Y, the first portion 110a has a first side a and a second side b relative to each other, the third portion 120a has a third side c and a fourth side d relative to each other, the third side c is inclined toward the fourth side d, wherein the first side a is inclined toward the second side b, the second side b is inclined toward the first side a, and the third side c is inclined toward the fourth side d, and the fourth side d is inclined toward the third side c. It should be noted that the same or corresponding parts as those in the above-mentioned embodiments are not described in detail here.

[0090] It should be noted that Fig.10 and Fig.12 Only one situation in which "along the third direction Z, the thickness of the first portion 110a in the second direction Y gradually decreases" is illustrated. Fig.11 and Fig.12 Only a situation in which "the thickness of the third part 120a in the second direction Y gradually increases along the third direction Z" is illustrated. In actual applications, an embodiment of the present disclosure does not restrict the manner in which the thickness of the first part 110a in the second direction Y gradually decreases along the third direction Z, and the manner in which the thickness of the third part 120a in the second direction Y gradually increases along the third direction Z.

[0091] In some embodiments, reference Figures 10 to 12 , at least part of the gate 111 is located in the groove 105, the first direction X and the second direction Y constitute a reference plane, and in the second direction Y, the length of the overlapping area of ​​the gate 111 and the positive projection of any conductive column 102 on the reference plane is less than the thickness of the gate 111, wherein the second direction Y is the thickness extension direction of the gate 111.

[0092] It can be understood that, in the second direction Y, the length of the overlapping area of ​​the orthographic projection of the gate 111 and any conductive pillar 102 on the reference plane is less than the thickness of the gate 111, which is conducive to reducing the facing area between the gate 111 and any conductive pillar 102 by arranging at least part of the gate 111 in the groove 105, thereby facilitating reducing the coupling effect between the gate 111 and any conductive pillar 102. In addition, on the basis of reducing the coupling effect between the gate 111 and any conductive pillar 102, the spacing between the gate 111 and the conductive pillar 102 can be further reduced to improve the integration density of the semiconductor device structure.

[0093] In other words, taking the flat surface of the substrate 100 away from the gate structure 101 as the reference plane, in the second direction Y, the length of the overlapping area between the gate 111 and the positive projection of any conductive column 102 on the reference plane is less than the thickness of the gate 111, which means that the minimum vertical distance between the gate 111 and the reference plane is less than the minimum vertical distance between any conductive column and the reference plane.

[0094] In some embodiments, reference Figure 2 , Figure 3 , Figure 5 5b, and Figures 10 to 12 , the gate 111 and the gate oxide layer 121 both have a shape that matches the surface of the channel region 130. In other words, along the second direction Y, the gate 111 and the gate oxide layer 121 both have a uniform thickness, that is, the gate structure 101 as a whole has a uniform thickness. In this way, it is beneficial to improve the control capability of the gate 111 over the conduction or shutoff of the channel region 130 in the transistor through the gate structure 101 with uniform thickness, so as to improve the performance of the transistor.

[0095] The positional relationship between the plurality of conductive pillars 102 and the recessed structure 104 is described in detail below.

[0096] It is understandable that the conductive pillar 102 in contact with the source region 110 is the first conductive pillar 112 , and the conductive pillar 102 in contact with the drain region 120 is the second conductive pillar 122 , with the flat surface of the substrate 100 away from the gate structure 101 being the reference plane.

[0097] In some embodiments, reference Figure 2 Among the multiple first conductive pillars 112 spaced apart from each other and in contact with the source region 110, the minimum vertical distance between one of two adjacent first conductive pillars 112 and the reference plane is a first distance, and the minimum vertical distance between the other first conductive pillar 112 and the reference plane is a second distance, and the first distance is different from the second distance to ensure that the positions where the two adjacent first conductive pillars 112 contact with the source region 110 are at different heights in the second direction Y.

[0098] In other embodiments, reference Figure 3 Among the multiple second conductive pillars 122 spaced apart from each other and in contact with the drain region 120, the minimum vertical distance between one of two adjacent second conductive pillars 122 and the reference plane is a third distance, and the minimum vertical distance between the other second conductive pillar 122 and the reference plane is a fourth distance, and the third distance is different from the fourth distance to ensure that the positions where the two adjacent second conductive pillars 122 contact the drain region 120 are at different heights in the second direction Y.

[0099] In the above various embodiments, whether it is the recessed structure 104 or the groove 105, in a cross section parallel to the second direction Y, the cross-sectional shape of the recessed structure 104 or the groove 105 can be as follows: Figure 2 , Figure 3 , Figure 5 5b, and Figures 10 to 12 The shape shown is an arc. In practical applications, the cross-sectional shape of the recessed structure 104 or the groove 105 may also be a trapezoid, a rectangle, or a sawtooth shape.

[0100] It should be noted that the semiconductor device structure provided in an embodiment of the present disclosure can be applied to the sensing amplifier circuit in DRAM. By improving the performance of transistors in the semiconductor device structure and reducing the coupling between different conductive columns, the size of the semiconductor device structure can be further reduced without affecting the performance of the semiconductor device structure. This means that the semiconductor device structure can be scaled, and the sensing amplifier circuit can be further scaled without affecting its performance.

[0101] In summary, the surface of the source region 110 and / or the drain region 120 presents an uneven morphology. On this basis, the plurality of conductive pillars 102 in contact with one of the source region 110 or the drain region 120 are arranged on the uneven morphology, that is, at least one conductive pillar 102 is arranged in the recessed structure 104, which is conducive to making the positions of the two adjacent conductive pillars 102 in contact with the substrate 100 in the thickness direction of the substrate 100 different in height, that is, the conductive pillars 102 located in different areas of the surface of the substrate 100 are staggered in the thickness direction of the substrate 100, which is conducive to reducing the facing area between adjacent conductive pillars 102, thereby reducing the coupling effect between different conductive pillars 102. In addition, on the basis of reducing the coupling effect between adjacent conductive pillars 102, the spacing between adjacent conductive pillars 102 can be further reduced to improve the integration density of the semiconductor device structure.

[0102] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device structure. The method for manufacturing a semiconductor device structure provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Fig.13 A flow chart of a method for manufacturing a semiconductor device structure provided by another embodiment of the present disclosure; Figures 14 to 25 A schematic structural diagram corresponding to each step in a method for manufacturing a semiconductor device structure provided in another embodiment of the present disclosure.

[0103] It should be noted that, in order to facilitate description and clearly illustrate the steps of the semiconductor device structure manufacturing method, Figures 14 to 25All of them are partial structural diagrams of semiconductor device structures. In addition, the same or corresponding parts as the above embodiments are not described in detail here.

[0104] refer to Figures 1 to 25 , a method for manufacturing a semiconductor device structure comprises the following steps:

[0105] S101: Reference Fig.13 and Fig.14 , providing a substrate 140 , the substrate 140 includes an initial substrate 150 and a first doping region 160 and a second doping region 170 disposed in the initial substrate 150 .

[0106] In some embodiments, different doping ions are implanted into different regions of the substrate 140, so that the doping type of the doping ions in the first doping region 160 and the second doping region 170 is the same, for example, the first doping ions, and the doping ions in at least a portion of the initial substrate 150 other than the first doping region 160 and the second doping region 170 are the second doping ions. One of the first doping ions and the second doping ions is a P-type doping ion, and the other is an N-type doping ion.

[0107] It can be understood that the first doping region 160 is used to form the source region 110 later, the second doping region 170 is used to form the drain region 120 later, and the initial substrate 150 is used to form the channel region 130 later.

[0108] S102: Reference Fig.13 and Fig.15 , a mask layer 106 is formed on the substrate 140 , and the mask layer 106 has at least one first opening 116 facing the first doping region 160 and / or the second doping region 170 to expose a portion of the surface of the first doping region 160 and / or the second doping region 170 .

[0109] The mask layer 106 will be described in detail below.

[0110] In some embodiments, reference Fig.15 The mask layer 106 directly facing the first doping region 160 has a plurality of first openings 116 arranged at intervals along the first direction X. The first doping region 160 exposed by the plurality of first openings 116 is subsequently processed to form Figure 1 The source region 110 is shown. It is understandable that, in practical applications, the mask layer 106 directly facing the first doped region 160 may also have only one first opening 116 .

[0111] It should be noted that Fig.15The plurality of first openings 116 in the mask layer 106 facing the first doping region 160 are not only arranged at intervals along the first direction X, but also arranged at intervals along the third direction Z. In practical applications, the plurality of first openings 116 in the mask layer 106 facing the first doping region 160 may be arranged at intervals only along the first direction X.

[0112] In other embodiments, reference Fig.16 The mask layer 106 directly facing the second doping region 170 has a plurality of first openings 116 arranged at intervals along the first direction X. Subsequently, the second doping region 170 exposed by the plurality of first openings 116 is processed to form Figure 3 The drain region 120 is shown. It is understandable that, in practical applications, the mask layer 106 directly facing the second doping region 170 may also have only one first opening 116 .

[0113] It should be noted that Fig.16 The plurality of first openings 116 in the mask layer 106 facing the second doping region 170 are not only arranged at intervals along the first direction X, but also arranged at intervals along the third direction Z. In practical applications, the plurality of first openings 116 in the mask layer 106 facing the second doping region 170 may only be arranged at intervals along the first direction X.

[0114] In some other embodiments, reference Fig.17 The mask layer 106 directly facing the first doping region 160 and the second doping region 170 has a plurality of first openings 116 arranged at intervals along the first direction X. Subsequently, the first doping regions 160 and the second doping regions 170 exposed by the plurality of first openings 116 are processed to form Figure 4 The source region 110 and the drain region 120 are shown. It is understandable that in practical applications, the mask layer 106 facing the first doping region 160 may also have only one first opening 116 , and the mask layer 106 facing the second doping region 170 may also have only one first opening 116 .

[0115] It should be noted that Fig.17 The plurality of first openings 116 in the mask layer 106 directly facing the first doping region 160 and the second doping region 170 are not only arranged at intervals along the first direction X, but also arranged at intervals along the third direction Z. In practical applications, the plurality of first openings 116 in the mask layer 106 directly facing the first doping region 160 and the second doping region 170 may be arranged at intervals only along the first direction X.

[0116] In some embodiments, reference Fig.18The mask layer 106 has a middle portion 126 directly opposite to the first doping region 160 and the second doping region 170, and the middle portion 126 also has a plurality of first openings 116 arranged at intervals along the first direction X to expose a portion of the surface of the initial substrate 150 located between the first doping region 160 and the second doping region 170. It can be understood that the middle portion 126 in the mask layer 106 and the channel region 130 (see FIG. Figure 5 ), that is, the orthographic projection of the middle portion 126 on the reference plane covers the orthographic projection of the channel region 130 on the reference plane. In this way, after the exposed substrate 140 is subsequently processed based on the first opening 116, the following Figure 1 The source region 110 shown and Figure 3 Based on the drain region 120 shown in FIG. Figure 5 A channel region 130 is shown.

[0117] It should be noted that Fig.18 The plurality of first openings 116 in the middle portion 126 are not only arranged at intervals along the first direction X, but also arranged at intervals along the third direction Z. In practical applications, the plurality of first openings 116 in the middle portion 126 may be arranged at intervals along the first direction X only.

[0118] In some embodiments, the plurality of first openings 116 of the mask layer 106 are arranged in an array.

[0119] In some embodiments, reference Fig.19 The plurality of first openings 116 of the mask layer 106 are arranged in a quadrilateral arrangement, that is, the plurality of first openings 116 are arranged at intervals along the first direction X and also arranged at intervals along the third direction Z. Subsequently, the substrate 140 exposed by the plurality of first openings 116 is processed to form Figure 6 A substrate 100 is shown.

[0120] In other embodiments, reference Fig. 20 , a plurality of first openings 116 arranged at intervals along the first direction X constitute a column of first opening groups 146, and the first openings 116 in two adjacent columns of first opening groups 146 are arranged in a staggered manner. Fig. 20 , the first openings 116 in two adjacent columns of first opening groups 146 are not arranged at intervals along the third direction Z, and the first openings 116 in the two groups of first opening groups 146 located on both sides of the first opening group 146 in the middle column of the first opening groups 146 in the three adjacent columns are arranged at intervals along the third direction Z. It should be noted that Fig. 20 This is only a case where the first openings 116 in two adjacent columns of the first opening groups 146 are staggered. An embodiment of the present disclosure does not limit the specific case of the staggered arrangement of the first openings 116 in two adjacent columns of the first opening groups 146. It only needs to ensure the staggered arrangement, and the specific degree of the staggered arrangement is not limited.

[0121] It should be noted that Fig. 20 The plurality of first openings 116 framed by a dotted frame constitute a row of first opening groups 146 , and only two dotted frames are used to illustrate two adjacent first opening groups 146 .

[0122] In the above two embodiments, the multiple first openings 116 arranged in an array and provided on the substrate 140 may refer to the multiple first openings 116 provided only in the mask layer 106 and the middle part 126 directly opposite to the first doping region 160; or, may refer to the multiple first openings 116 provided only in the mask layer 106 and the middle part 126 directly opposite to the second doping region 170; or, may refer to the multiple first openings 116 provided in the mask layer 106 and the middle part 126 directly opposite to the first doping region 160 and the second doping region 170.

[0123] It should be noted that the mask layer 106 directly opposite to the first doping region 160 refers to the mask layer 106 whose orthographic projection on the reference plane coincides with the orthographic projection of the first doping region 160 on the reference plane; the mask layer 106 directly opposite to the second doping region 170 refers to the mask layer 106 whose orthographic projection on the reference plane coincides with the orthographic projection of the second doping region 170 on the reference plane.

[0124] In some embodiments, reference Fig.21 The mask layer 106 has a middle portion 126 (refer to Fig.18 ), and the middle portion 126 has a second opening 136 extending along the first direction X. It can be understood that the second opening 136 exposes at least a portion of the substrate 140 directly opposite to the middle portion 126. The substrate 140 exposed by the second opening 136 is subsequently processed to form Figure 8 A channel region 130 is shown.

[0125] In some embodiments, continue to refer to Fig.21 On the basis that the middle portion 126 has a second opening 136 extending along the first direction X, the second opening 136 can also expose a portion of the surface of the first doping region 160 and a portion of the surface of the second doping region 170. The substrate 140 exposed by the second opening 136 is subsequently processed to form Figure 8 or Fig.12 A channel region 130 is shown.

[0126] It is understandable that in the step of processing the substrate 140 exposed by the second opening 136 , the first doping region 160 , the second doping region 170 , and a portion of the initial substrate 150 between the first doping region 160 and the second doping region 170 will all be processed.

[0127] It should be noted that, on the basis of the second opening 136 exposing the substrate 140 for forming the channel region 130 later, the second opening 136 may also expose a portion of the surface of the first doping region 160 or a portion of the surface of the second doping region 170 to form Fig.10 or Fig.11 A substrate 100 is shown.

[0128] In other embodiments, reference Fig. 22 The middle portion 126 may have a plurality of second openings 136 extending along the first direction X, the plurality of second openings 136 are arranged at intervals along the third direction Z, and each second opening 136 exposes a portion of the substrate 140 directly opposite to the middle portion 126. The substrate 140 exposed by the plurality of second openings 136 is subsequently processed to form Fig. 9 A channel region 130 is shown.

[0129] It should be noted that, in one embodiment of the present disclosure, there is no limitation on the number of the second openings 136 in the middle portion 126 of the mask layer 106 .

[0130] In some embodiments, in conjunction with reference Fig.21 and Fig.23 After forming the mask layer 106 and before subsequently forming the oxide layer 107 , the method for manufacturing the semiconductor device structure may further include: performing patterning on the substrate 140 using the mask layer 106 as a mask, so that the surface of the remaining substrate 140 exposed by the first opening 116 is recessed toward a direction close to the interior of the substrate 140 .

[0131] In some embodiments, the mask layer 106 has a first opening 116, and patterning the substrate 140 using the mask layer 106 as a mask means: through the first opening 116, the substrate 140 exposed by the first opening 116 is patterned, so that the recessed degree of the recessed structure 104 formed based on the remaining substrate 140 exposed by the first opening 116 is greater, which is beneficial to further increase the width of the subsequently formed channel region 130 along the first direction X. Therefore, without increasing the channel length of the channel region 130, it is beneficial to further increase the width-to-length ratio of the channel region 130. In addition, it is also beneficial to further reduce the facing area between adjacent conductive pillars 102 formed subsequently, so as to further reduce the coupling effect between adjacent conductive pillars 102.

[0132] In other embodiments, on the basis of the first opening 116 in the mask layer 106, the mask layer 106 further has a second opening 136. The patterning of the substrate 140 using the mask layer 106 as a mask further includes: patterning the substrate 140 exposed by the second opening 136 through the second opening 136, so that the recess 105 subsequently formed based on the remaining substrate 140 exposed by the second opening 136 is more depressed, thereby facilitating further increasing the length of the subsequently formed channel region 130 along the third direction Z, and therefore facilitating further reducing the channel length modulation effect of the transistor, and in addition, facilitating further reducing the directly facing area between the subsequently formed gate 111 and any conductive pillar 102, so as to further reduce the coupling effect between the gate 111 and any conductive pillar 102.

[0133] S103: Combined with reference Fig.21 and Fig.24 or Fig.23 and Fig.24 , the substrate 140 is oxidized based on the mask layer 106 to form an oxide layer 107 .

[0134] In some embodiments, the mask layer 106 has a first opening 116 , and oxidation treatment of the substrate 140 based on the mask layer 106 refers to oxidation treatment of the substrate 140 exposed by the first opening 116 through the first opening 116 . It is understandable that an oxide layer 107 is formed in each first opening 116 .

[0135] In some other embodiments, on the basis of the first opening 116 in the mask layer 106, the mask layer 106 further has a second opening 136. The oxidation treatment of the substrate 140 based on the mask layer 106 further includes: performing an oxidation treatment on the substrate 140 exposed by the second opening 136 through the second opening 136. It can be understood that an oxide layer 107 is formed in each second opening 136.

[0136] It should be noted that Fig.24 This is only an example of “oxidizing the substrate 140 based on the mask layer 106 to form the oxide layer 107”. The various mask layers 106 described in the above embodiments are applicable to this step to form multiple oxide layers 107 of various styles. Fig.24 The shape of the oxide layer 107 shown in the figure is just an example. In actual applications, depending on the mold oxidation process parameters, the shape of the oxide layer 107 can be adjusted according to actual needs.

[0137] S104: Binding residues Fig.24 and Fig.12, the mask layer 106 and the oxide layer 107 are removed, so that the source region 110 and / or the drain region 120 has at least one recessed structure 104 , the remaining initial substrate 150 is the substrate 100 , the remaining first doping region 160 is the source region 110 , and the remaining second doping region 170 is the drain region 120 .

[0138] In some embodiments, in the step of forming the oxide layer 107, a portion of the first doped region 160 will be oxidized as part of the oxide layer 107. Then, in the step of removing the oxide layer 107, the oxidized first doped region 160 will also be removed, so that when the remaining first doped region 160 that has not been oxidized and removed serves as the source region 110, the source region 110 has a first portion 110a close to the channel region 130 and a second portion 110b away from the channel region 130, and along the third direction Z, the thickness of the first portion 110a in the second direction Y gradually decreases.

[0139] In other embodiments, in the step of forming the oxide layer 107, part of the second doped region 170 will be oxidized as part of the oxide layer 107. Then, in the step of removing the oxide layer 107, the oxidized second doped region 170 will also be removed, so that when the remaining second doped region 170 that has not been oxidized and removed serves as the drain region 120, the drain region 120 has a third portion 120a close to the channel region 130 and a fourth portion 120b away from the channel region 130, and along the third direction Z, the thickness of the third portion 120a in the second direction Y gradually increases.

[0140] It should be noted that, in another embodiment of the present disclosure, Fig.12 The substrate 100 shown is used as an example to explain step S104 in detail. In practical applications, various substrates 100 described in the above embodiments can be formed by step S104. Fig.12 The semiconductor device structure shown is described in detail as an example.

[0141] S105: Reference Fig.25 , based on the substrate 100, a length is formed along the first direction X (see Figure 1 The gate structure 101 includes a gate 111 extending along a first direction X and a gate oxide layer 121 disposed between the gate 111 and the substrate 100.

[0142] S106: Reference Fig.25 , forming a dielectric layer 108 that at least covers the source region 110 and the drain region 120, and having a plurality of vias 118 in the dielectric layer 108. It can be understood that the vias 118 are used to expose a portion of the surface of the source region 110 or the drain region 120, and the conductive pillars 102 are subsequently formed in the vias 118.

[0143] S107: Combined with reference Fig.25 and Fig.12 , a conductive column 102 is formed in the plurality of via holes 118, and at least one conductive column 102 is disposed in the recessed structure 104; wherein, among the plurality of conductive columns 102 contacting one of the source region 110 or the drain region 120, the positions where two adjacent conductive columns 102 contact the substrate 100 have different heights in the thickness direction of the substrate 100. It can be understood that the via holes 118 correspond to the conductive columns 102 one by one.

[0144] In summary, in the semiconductor device structure formed by the manufacturing method provided by another embodiment of the present disclosure, the surface of the source region 110 and / or the drain region 120 presents an uneven morphology. On this basis, the multiple conductive pillars 102 in contact with one of the source region 110 or the drain region 120 are arranged on the uneven morphology, that is, at least one conductive pillar 102 is arranged in the recessed structure 104, which is conducive to making the positions of the two adjacent conductive pillars 102 in contact with the substrate 100 in the thickness direction of the substrate 100 different in height, that is, in the thickness direction of the substrate 100, the conductive pillars 102 located in different areas of the surface of the substrate 100 are staggered, which is conducive to reducing the facing area between adjacent conductive pillars 102, thereby reducing the coupling effect between different conductive pillars 102. In addition, on the basis of reducing the coupling effect between adjacent conductive pillars 102, the spacing between adjacent conductive pillars 102 can be further reduced to improve the integration density of the semiconductor device structure.

[0145] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor device structure, characterized in that: include: A substrate having a source region and a drain region spaced apart from each other; A gate structure disposed on the upper surface of the substrate; and a plurality of conductive pillars respectively contacting the source region and / or the drain region; Wherein, the gate structure includes a gate whose length extends along a first direction and a gate oxide layer arranged between the gate and the substrate; the source region and / or the drain region has at least one recessed structure, and at least one conductive column is arranged in the recessed structure; among the multiple conductive columns contacting one of the source region or the drain region, the positions at which two adjacent conductive columns contact the substrate have different heights in the thickness direction of the substrate.

2. The semiconductor device structure according to claim 1, characterized in that: The source region and / or the drain region has a plurality of the recess structures arranged at intervals along the first direction.

3. The semiconductor device structure according to claim 2, characterized in that: The substrate further includes a channel region disposed between the source region and the drain region, and the channel region also has a plurality of the recess structures arranged at intervals along the first direction.

4. The semiconductor device structure according to claim 3, characterized in that: The plurality of recessed structures disposed on the substrate are arranged in an array.

5. The semiconductor device structure according to claim 4, characterized in that: A plurality of the recessed structures arranged at intervals along the first direction form a column of recessed groups, and the recessed structures in two adjacent columns of the recessed groups are arranged in a staggered manner.

6. The semiconductor device structure according to claim 1, characterized in that: The substrate further includes a channel region disposed between the source region and the drain region. A groove having a length extending along the first direction is disposed in the substrate, and the groove is at least partially located in the channel region.

7. The semiconductor device structure according to claim 6, characterized in that: The source region has a first portion close to the channel region and a second portion away from the channel region, and a thickness of the first portion in the second direction gradually decreases along a direction from the source region to the drain region; and / or, The drain region comprises a third portion close to the channel region and a fourth portion away from the channel region, and the thickness of the third portion gradually increases in the second direction along the direction from the source region to the drain region; The second direction is a thickness extension direction of the gate.

8. The semiconductor device structure according to claim 7, characterized in that: In the second direction, the first portion has a first side and a second side opposite to each other, the first side is inclined toward the second side, and the second side is inclined toward the first side; and / or, The third portion has a third side and a fourth side opposite to each other along the second direction, the third side is inclined toward the fourth side, and the fourth side is inclined toward the third side.

9. The semiconductor device structure according to claim 6, characterized in that: At least part of the gate is located in the groove, the first direction and the second direction constitute a reference plane, and in the second direction, the length of the overlapping area of ​​the gate and the positive projection of any of the conductive columns on the reference plane is less than the thickness of the gate, wherein the second direction is the thickness extension direction of the gate.

10. The semiconductor device structure according to any one of claims 3 to 9, characterized in that: The gate and the gate oxide layer both have shapes matching the surface of the channel region.

11. A method for manufacturing a semiconductor device structure, characterized in that: include: Providing a substrate, the substrate comprising an initial substrate and a first doping region and a second doping region disposed in the initial substrate; forming a mask layer on the substrate, wherein the mask layer has at least one first opening directly opposite to the first doping region and / or the second doping region to expose a portion of a surface of the first doping region and / or the second doping region; performing oxidation treatment on the substrate based on the mask layer to form an oxide layer; Removing the mask layer and the oxide layer, so that the remaining initial substrate is used as a substrate, the remaining first doping region is used as a source region, and the remaining second doping region is used as a drain region, so that the source region and / or the drain region has at least one recessed structure; forming a gate structure having a length extending along a first direction based on the substrate; forming a dielectric layer at least covering the source region and the drain region, wherein the dielectric layer has a plurality of vias; Conductive pillars are formed in the plurality of vias, and at least one of the conductive pillars is disposed in the recessed structure; wherein, among the plurality of conductive pillars contacting one of the source region or the drain region, positions where two adjacent conductive pillars contact the substrate have different heights in the thickness direction of the substrate.

12. The manufacturing method according to claim 11, characterized in that: The mask layer directly facing the first doping region and / or the second doping region has a plurality of first openings arranged at intervals along the first direction.

13. The manufacturing method according to claim 12, characterized in that: The mask layer has a middle portion directly opposite to the first doping region and the second doping region, and the middle portion also has a plurality of first openings arranged at intervals along the first direction to expose a portion of the surface of the initial substrate between the first doping region and the second doping region.

14. The manufacturing method according to claim 13, characterized in that: The plurality of first openings of the mask layer are arranged in an array.

15. The manufacturing method according to claim 11, characterized in that: The mask layer has a middle portion directly opposite to the first doping region and the second doping region, and the middle portion has a second opening extending along the first direction.

16. The manufacturing method according to claim 14, characterized in that: The second opening also exposes a portion of the surface of the first doping region and a portion of the surface of the second doping region.

17. The manufacturing method according to any one of claims 11 to 16, characterized in that: After forming the mask layer and before forming the oxide layer, the method further includes: The substrate is patterned using the mask layer as a mask, so that the surface of the substrate remaining exposed by the first opening is recessed toward the interior of the substrate.

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