Three-dimensional memory, memory system and manufacturing method of three-dimensional memory

Abstract

The embodiment of the invention provides a semiconductor layer. The stacked structure is located on one side of the semiconductor layer; the plurality of channel structures penetrate through the stacked structure and are connected with the semiconductor layer; the metal layer is located on one side of the semiconductor layer away from the stacked structure; the source line is located on the side, away from the stacked structure, of the metal layer; and a source contact connected between the metal layer and the source line.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a three-dimensional memory, a memory system, and a method for manufacturing the three-dimensional memory. Background Art

[0002] As the feature size of memory cells approaches the process lower limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of planar memories to approach an upper limit.

[0003] To overcome the limitations of planar memory, the industry has developed a memory with a three-dimensional structure (e.g., 3D NAND memory) to increase storage density by arranging storage cells three-dimensionally. Currently, how to optimize the process and performance of three-dimensional memory is one of the problems that need to be solved. Summary of the invention

[0004] The present application provides a three-dimensional memory, a memory system, and a method for manufacturing a three-dimensional memory that can at least partially solve the above-mentioned problems existing in the related art or other problems in the art.

[0005] Some embodiments of the present application provide a three-dimensional memory. The three-dimensional memory includes: a stacked structure located on one side of a semiconductor layer; a plurality of channel structures penetrating the stacked structure and connected to the semiconductor layer; a metal layer located on a side of the semiconductor layer away from the stacked structure; a source line located on a side of the metal layer away from the stacked structure; and a source contact connected between the metal layer and the source line.

[0006] In some embodiments, the metal layer is in contact with the semiconductor layer.

[0007] In some embodiments, the three-dimensional memory further includes a metal silicide layer located between the metal layer and the semiconductor layer and in contact with the metal layer and the semiconductor layer, respectively.

[0008] In some embodiments, the three-dimensional memory includes an array region, a connection region, and a peripheral region, and the semiconductor layer and the metal layer are located in the array region; the three-dimensional memory also includes an insulating layer, and the insulating layer and the semiconductor layer are located on the same side of the stacked structure, contacting the stacked structure in the connection region and extending to the peripheral region.

[0009] In some embodiments, the three-dimensional memory also includes: a peripheral circuit structure connected to a side of the multiple channel structures away from the semiconductor layer; and a first through contact penetrating the insulating layer in the peripheral region and extending along the stacking direction of the stacking structure, the first end of the first through contact being connected to the source line, and the second end of the first through contact being connected to the peripheral circuit structure.

[0010] In some embodiments, the three-dimensional memory further includes a power line, and the power line is in the same layer as the source line.

[0011] In some embodiments, the three-dimensional memory further includes: a solder pad, which is in the same layer as the power line and is connected to the power line; and a second through-contact, which penetrates the insulating layer in the peripheral area and extends along the stacking direction, wherein the first end of the second through-contact is connected to the power line, and the second end of the second through-contact is connected to the peripheral circuit structure.

[0012] In some embodiments, the channel structure includes a functional layer and a channel layer from the outside to the inside, and the channel layer is in contact with the semiconductor layer.

[0013] Some other embodiments of the present application provide a memory system, which includes: at least one three-dimensional memory as mentioned in any of the above embodiments; and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0014] Some embodiments of the present application provide a method for manufacturing a three-dimensional memory. The method for manufacturing the three-dimensional memory includes: providing a semiconductor structure, wherein the semiconductor structure includes a substrate, a stacking structure, and a plurality of initial channel structures, the stacking structure is located on one side of the substrate, and the plurality of initial channel structures penetrate the stacking structure and extend into the substrate; removing a portion of the substrate and the initial channel structure to convert the initial channel structure into a channel structure; forming a semiconductor layer connected to the plurality of channel structures; forming a metal layer on a side of the semiconductor layer away from the stacking structure; and forming a source contact and a source line connected to the source contact on a side of the metal layer away from the stacking structure.

[0015] In some embodiments, forming the metal layer on a side of the semiconductor layer away from the stacked structure includes: forming the metal layer on a surface of the semiconductor layer.

[0016] In some embodiments, before forming a metal layer on a side of the semiconductor layer away from the stacking structure, the method further includes: forming a metal silicide layer on a surface of the semiconductor layer; wherein forming a metal layer on a side of the semiconductor layer away from the stacking structure includes: forming a metal layer on a surface of the metal silicide layer.

[0017] In some embodiments, the semiconductor structure includes an array region, a connection region, and a peripheral region, and a semiconductor layer and a metal layer are formed in the array region, the connection region, and the peripheral region, wherein after the metal layer is formed on a side of the semiconductor layer away from the stacked structure, the method further includes: removing portions of the semiconductor layer and the metal layer located in the connection region and the peripheral region to form a cavity; and forming an insulating layer in the cavity.

[0018] In some embodiments, the semiconductor structure also includes a peripheral circuit structure and a first through-portion, the peripheral circuit structure is connected to a side of the multiple channel structures away from the substrate, the first through-portion extends in the peripheral region along the stacking direction of the stacking structure and is connected to the peripheral circuit structure, wherein the method also includes: forming a first contact portion that penetrates the insulating layer and is connected to the first through-portion; wherein forming a source contact and a source line connected to the source contact on a side of the metal layer away from the stacking structure includes: forming a source line connected to the first contact portion and the source contact.

[0019] In some embodiments, the semiconductor structure also includes a second through-portion, which extends in the stacking direction in the peripheral region and is connected to the peripheral circuit structure, wherein the method also includes: forming a second contact portion that penetrates the insulating layer and is connected to the second through-portion; and forming a solder pad and a power line connected to the second contact portion, wherein the power line and the solder pad are connected.

[0020] In some embodiments, the initial channel structure includes a functional layer and a channel layer from the outside to the inside, and the functional layer and the channel layer extend into the substrate, wherein removing a portion of the substrate and the channel structure to convert the initial channel structure into the channel structure includes: removing the portion of the functional layer extending into the substrate, and using the remaining portion of the initial channel structure as the channel structure.

[0021] In some embodiments, forming a semiconductor layer connected to the plurality of channel structures includes: forming a semiconductor layer in contact with the channel layers in the plurality of channel structures.

[0022] According to at least one embodiment of the present application, the three-dimensional memory, memory system and method for manufacturing the three-dimensional memory provided by the present application can reduce the number of source contacts by forming a metal layer on the side of the semiconductor layer away from the stacked structure and connecting the source contact between the metal layer and the source line, thereby freeing up the area occupied by the source line, which is beneficial to optimizing the layout of the metal interconnect lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0024] Figure 1 is a cross-sectional schematic diagram of a three-dimensional memory according to an exemplary embodiment of the present application;

[0025] Figure 2 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an exemplary embodiment of the present application;

[0026] Figures 3A to 3G is a cross-sectional schematic diagram of a three-dimensional memory device according to an exemplary embodiment of the present application during a manufacturing process;

[0027] Figure 4 is a block diagram of a system having a memory system according to an exemplary embodiment of the present application; and

[0028] Figure 5A and Figure 5B is a schematic diagram of a memory system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first through-contact discussed in this application may also be referred to as the second through-contact, and vice versa.

[0031] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0032] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0033] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0034] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0035] In addition, in the present application, when "connect" or "couple" is used, it can indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0036] It should be noted that, in the following, the x-direction, y-direction, and z-direction in each figure illustrate the spatial relationship of the components in the three-dimensional memory. For example, the z-direction is the stacking direction of the stacking structure, and the x-direction and the y-direction are two directions perpendicular to each other on a plane perpendicular to the stacking direction. The same concept will be used throughout this application to describe the spatial relationship of the components in the three-dimensional memory.

[0037] In the manufacturing process of three-dimensional memory (e.g., 3D NAND memory), the common source of the memory cell array is led out from the back side to reduce the process challenges caused by the increase in the number of layers of the stacked structure. However, this common source lead-out method increases the difficulty of layout of metal interconnects.

[0038] Figure 1 is a cross-sectional schematic diagram of a three-dimensional memory according to an embodiment of the present application. For example, the three-dimensional memory may be a 3D NAND memory. Figure 1As shown, in some embodiments, the three-dimensional memory 100 may include an array area 101, a connection area 102, and peripheral areas 103-1 and 103-2. The stacked structure 121 is located on one side of the semiconductor layer 111. The stacked structure 121 is located in the array area 101 and the connection area 102. The stacked structure 121 may include dielectric layers 122 and gate layers 123 alternately stacked in the z direction. The more stacked layers of the dielectric layer 122 and the gate layer 123, the higher the integration of the memory cell, that is, the greater the unit storage density. The material of the dielectric layer 122 may include silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. The material of the gate layer 123 may include tungsten, cobalt, copper, aluminum, polysilicon, silicide, or any other suitable conductive material. For example, the gate layer 123 may include a conductive layer 125 and an adhesive layer 124 and a gate barrier layer (not shown) that sequentially surround the conductive layer. For example, the gate layer 123 may extend laterally in a plane perpendicular to the z-direction as a word line of the three-dimensional memory 100 , and terminate at a stepped structure where the stacked structure 121 is located in the connection region 102 .

[0039] In some embodiments, the stacked structure 121 may also extend to a portion of the peripheral region (eg, the peripheral region 103 - 1 ). In some embodiments, the insulating cover layer 145 may be located in another portion of the peripheral region (eg, the peripheral region 103 - 2 ) and extend to cover the stepped structure of the stacked structure 121 located in the connection region 102 .

[0040] A plurality of channel structures 131 penetrate the stacked structure 121 in the array region 101. In some embodiments, the channel structure 131 may include a functional layer 132 and a channel layer 133 arranged sequentially from the outside to the inside. For example, the functional layer 132 may be a substantially tubular structure with both ends open, which penetrates the stacked structure 121 and extends into the semiconductor layer 111. For example, the channel layer 133 may be a substantially tubular structure with both ends closed, which penetrates the stacked structure 121 and extends into the semiconductor layer 111. The extension distance of the channel layer 133 in the semiconductor layer 111 is greater than the extension distance of the functional layer 132 in the semiconductor layer 111. In other words, the channel layer 133 protrudes from the end face of the functional layer 132 away from the stacked structure 121. Optionally, the interior of the channel layer 133 may be at least partially filled with an insulating material. In some embodiments, the functional layer 132 may include a blocking layer, a charge capture layer, and a tunneling layer arranged sequentially from the outside to the inside. For example, the materials of the blocking layer, the charge trapping layer and the tunneling layer may include silicon oxide, silicon nitride and silicon oxide in sequence. The material of the channel layer 133 may include silicon (eg, amorphous silicon, polysilicon or single crystal silicon) or any other appropriate semiconductor material.

[0041] In some embodiments, a portion of the channel structure 131 surrounded by a gate layer 123 and a portion of the gate layer 123 constitute a memory cell. Multiple memory cells are arranged in series along the extension direction (e.g., z direction) of the channel structure 131 to form a memory string, and share the channel layer 133. The remaining portion of the gate layer 123 can be used as a word line connecting multiple memory cells at the same height in different memory strings. For example, by applying a voltage to the gate layer 123, the memory cell can cause the charge in the channel layer 133 to enter the charge trapping layer, or cause the charge in the charge trapping layer to return to the channel layer 133, so that the memory cell is in a programmed state or an erased state (unprogrammed state).

[0042] In some embodiments, some dummy channel structures 134 may penetrate the stacked structure 121 in the array region 101 and extend into the semiconductor layer 111. The internal structure of the dummy channel structure 134 is similar to that of the channel structure 131, and the present application will not repeat them here. Optionally, some dummy structures (not shown) may also penetrate the stacked structure 121 in the connection region 102 and extend from a side of the stacked structure 121 close to the semiconductor layer 111. For example, the dummy channel structure 134 may be used to provide mechanical support and / or load balancing.

[0043] In some embodiments, the gate isolation structure 181 may penetrate the stacked structure 121 and extend into the semiconductor layer 111. For example, the gate isolation structure 181 may extend along the x-direction. For example, the gate isolation structure 181 may be used as an insulating boundary of a memory block. In some examples, the gate isolation structure 181 may include a dielectric material layer 182 and a polysilicon layer 183 sequentially arranged from the outside to the inside. In other examples, the gate isolation structure 181 may be composed of at least one dielectric material (not shown).

[0044] In some embodiments, the semiconductor layer 111 contacts the channel layer 133 of the channel structure 131, so that the semiconductor layer 111 is connected to the plurality of channel structures 131. In some embodiments, the surface 112 of the semiconductor layer 111 close to the stacked structure 121 is substantially flush, and the surface of the semiconductor layer 111 away from the stacked structure 113 is in a concave-convex shape. For example, the surface of the semiconductor layer 111 away from the stacked structure 113 is in a convex shape corresponding to the channel structure 131 and / or the dummy channel structure 134, and corresponds to a concave shape between adjacent channel structures 131 or between the channel structure 131 and the dummy channel structure 134. In other embodiments, the surface of the semiconductor layer 111 away from the stacked structure 121 is substantially flush (not shown), and the specific shape of the surface of the semiconductor layer 111 away from the stacked structure 121 is not specifically limited in the present application. The material of the semiconductor layer 111 may include silicon (e.g., amorphous silicon, polycrystalline silicon or polysilicon) or any other appropriate semiconductor material. For example, the semiconductor layer 111 may be doped with a P-type or N-type dopant.

[0045] In some embodiments, the semiconductor layer 111 contacts the channel layer 133 of each of the plurality of channel structures 131 (eg, the plurality of channel structures 131 in the same memory block). For example, the semiconductor layer 111 can serve as a common source of memory cell arrays in the same memory block.

[0046] In some embodiments, the metal silicide layer 156 and the metal layer 141 are sequentially located on the surface of the semiconductor layer 111 away from the stacked structure 121. In other words, the metal silicide layer 156 is located between the metal layer 141 and the semiconductor layer 111, and contacts the metal layer 141 and the semiconductor layer 111 respectively. On a plane perpendicular to the z direction, the projection of the metal silicide layer 156, the projection of the metal layer 141, and the projection of the semiconductor layer 111 overlap. Thus, the metal layer 141 and the semiconductor layer 111 can be indirectly contacted at various locations in the overlapping projection area through the metal silicide layer 156. The material of the metal silicide layer 156 may include tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, or any combination thereof. The metal silicide layer 156 can be used to improve the electrical connection performance between the semiconductor layer 111 and the metal layer 141, for example, to reduce the contact resistance between the semiconductor layer 111 and the metal layer 141. The material of the metal layer 141 may include tungsten, cobalt, copper, aluminum, or any other appropriate metal material. In other embodiments, the metal silicide layer 156 may be omitted (not shown), and the metal layer 141 and the semiconductor layer 111 are in direct contact at all locations in the projected overlapping region.

[0047] In some embodiments, the semiconductor layer 111 and the metal layer 141 are located in the array region 101. Optionally, in the case where the three-dimensional memory 100 includes a metal silicide layer 156, the metal silicide layer 156 located between the semiconductor layer 111 and the metal layer 141 is also located in the array region 101. The insulating layer 144 is located on the same side of the stacked structure 121 as the semiconductor layer 111 and the metal layer 141, and the insulating layer 144 is arranged in parallel with the semiconductor layer 111 and the metal layer 141. For example, in the case where the three-dimensional memory 100 does not include the metal silicide layer 156, the surface of the insulating layer 144 close to the stacked structure 121 is substantially flush with the surface of the semiconductor layer 111 close to the stacked structure 121, and the thickness of the insulating layer 144 is greater than or equal to the total thickness of the metal layer 141 and the semiconductor layer 111. For another example, in the case where the three-dimensional memory 100 includes the metal silicide layer 156, the surface of the insulating layer 144 close to the stacked structure 121 is substantially flush with the surface of the semiconductor layer 111 close to the stacked structure 121, and the thickness of the insulating layer 144 is greater than or equal to the total thickness of the metal layer 141, the metal silicide layer 156, and the semiconductor layer 111. Exemplarily, the insulating layer 144 also extends to cover the surface of the metal layer 141 away from the stacked structure 121 to serve as an interlayer dielectric layer of the source contact 143. In this embodiment, the semiconductor layer 111 and the metal layer 141 are arranged in the array region 101 and the insulating layer 144 is arranged in the connection region 102, which can ensure that the semiconductor layer 111 is electrically connected to the channel structure 131 located in the array region 101, and can also avoid leakage between the dummy channel structure (not shown) located in the connection region 102 and the semiconductor layer 111, thereby affecting the electrical performance of the three-dimensional memory 100. For example, a portion of the dummy channel structure located in the connection region 102 extending from a side of the stack structure 121 close to the semiconductor layer 111 is surrounded by the insulating layer 144 , thereby preventing electrical leakage between the dummy channel structure and the semiconductor layer 111 .

[0048] In some embodiments, the source contact 143 is located on a side of the metal layer 141 away from the stack structure 121. For example, the source contact 143 penetrates the portion of the insulating layer 144 covering the metal layer 141 and is connected to the metal layer 141. The source line 142 is located on a side of the source contact 143 away from the stack structure 121 and is connected to the source contact 143. In other words, the source contact 143 is connected between the source line 142 and the metal layer 141. The material of the source line 142 and the source contact 143 may include tungsten, cobalt, copper, aluminum, polysilicon, silicide, or any other appropriate conductive material.

[0049] In some exemplary embodiments, when a three-dimensional memory does not include a metal layer, a larger number of source contacts need to be provided above the semiconductor layer to ensure electrical connectivity between the semiconductor layer and the source line, which increases the area occupied by the source line and affects the rational layout of metal interconnects (e.g., source lines).

[0050] According to the three-dimensional memory of the implementation mode of the present application, a metal layer is arranged on the side of the semiconductor layer away from the stacking structure, and the source contact is connected between the metal layer and the source line. This can reduce the number of source contacts, thereby freeing up the area occupied by the source line, which is conducive to optimizing the layout of the metal interconnection lines.

[0051] In some embodiments, the three-dimensional memory 100 may further include a peripheral circuit structure 151. For example, the stacked structure 121 and the plurality of channel structures 131 may be used to provide a plurality of memory cells to implement data storage. The peripheral circuit structure 151 may be used to provide a peripheral circuit for controlling the memory cells to implement various operations such as writing, reading, erasing, etc. The peripheral circuit structure 151 is connected to the side of the plurality of channel structures 131 away from the semiconductor layer 111. For example, the peripheral circuit structure 151 is bonded to the channel structure 131, the first through contact 161, and the second through contact 164 in the z direction through the bonding layer 152. For example, the bonding layer 152 may include a plurality of bonding contacts 153. The portion of the bonding layer 152 other than the bonding contacts 153 may be made of an insulating material. The material of the bonding contacts 153 may include, but is not limited to, tungsten, cobalt, copper, aluminum, titanium nitride, polysilicon, or any other suitable conductive material. It should be noted that the bonding referred to in the present application may be any appropriate bonding technology, such as hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, etc.

[0052] In some embodiments, the peripheral circuit structure 151 may include a first substrate 154 and a plurality of peripheral devices 155. The plurality of peripheral devices 155 may be located on one side of the first substrate 154. The material of the first substrate 154 may include, but is not limited to, silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. The types of peripheral devices 155 may include metal-oxide-semiconductor field-effect transistors (MOSFET), fin field-effect transistors (FINFET), bipolar junction transistors (BJT), diodes, resistors, inductors, capacitors, or any other suitable semiconductor devices. Several peripheral devices 155 may constitute digital, analog, and / or mixed digital-analog functional circuits for implementing various functions. These functional circuits may, for example, control the memory cell array through word lines and / or bit lines to implement various operations such as writing, reading, and erasing. Functional circuits may include, but are not limited to, page buffers / sense amplifiers, decoders (e.g., row decoders or column decoders), word line drivers, input / output (I / O) circuits, charge pumps, voltage sources or generators, current or voltage references, etc.

[0053] In some embodiments, the first through contact 161 penetrates the insulating layer 144 in the peripheral area 103-1 and extends along the z direction. The first end of the first through contact 161 is connected to the source line 142, and the second end of the first through contact 161 is connected to the peripheral circuit structure 151. Exemplarily, the first through contact 161 may include a first contact portion 162 and a first through portion 163. The first contact portion 162 penetrates the insulating layer 144, and its first end is connected to the source line 142. The first through portion 163 penetrates the stacked structure 121, and its first end is connected to the second end of the first contact portion 162, and its second end is connected to the peripheral circuit structure 151, for example, through the bonding contact 153 of the bonding layer 152. As a result, the semiconductor layer 111 as a common source can be electrically connected to the peripheral circuit structure 151 through the source line 142 and the first through contact 161, thereby realizing signal transmission.

[0054] In some embodiments, the power line 146 is disposed in the same layer as the source line 142. For example, the source line 142 and the power line 146 are approximately at the same height in the z direction, and the thickness of the two is approximately the same. Optionally, the pad 147 is disposed in the same layer as the power line 146 and is connected to the power line 146. For example, the power line 146 and the pad 147 are approximately at the same height in the z direction, and the thickness of the two is approximately the same. For another example, in a plane perpendicular to the z direction, the pad 147 and the power line 146 are connected to each other (not shown).

[0055] In some embodiments, the second through-contact 164 penetrates the insulating layer 144 in the peripheral region 103-2 and extends along the z-direction. Figure 1 As shown, the first end of the second through contact 164 is connected to the pad 147, and the second end of the second through contact 164 is connected to the peripheral circuit structure 151. Exemplarily, the second through contact 164 may include a second contact portion 165 and a second through portion 166. The second contact portion 165 penetrates the insulating layer 144, and its first end is connected to the pad 147. The second through portion 166 penetrates the insulating cover layer 145, and its first end is connected to the second end of the second contact portion 165, and its second end is connected to the peripheral circuit structure 151, for example, through the bonding contact 153 of the bonding layer 152. In this example, the pad 147 can be used to receive an external signal (for example, a power signal), so that the external signal can be electrically connected to the peripheral circuit structure 151 through the pad 147 and the second through contact 164, thereby realizing signal transmission. In other examples, the first end of the second through contact is connected to the power line 146, and the second end of the second through contact is connected to the peripheral circuit structure 151 (not shown). In this example, since the pad 147 and the power line 146 are connected to each other, the external signal can be electrically connected to the peripheral circuit structure 151 through the pad 147, the power line 146 and the second through contact in this example, thereby achieving signal transmission.

[0056] In some exemplary embodiments, reference Figure 1 , the pad 147 and the power line 146 can be arranged on the side of the peripheral circuit structure 151 away from the stacked structure 121. Compared with the above exemplary embodiment, the three-dimensional memory according to the embodiment of the present application releases the occupied area of ​​the source line 142, and the power line 146, the pad 147 and the source line 142 can be arranged on the same layer, so that the manufacturing process of separately forming the pad 147 and the power line 146 on the side of the peripheral circuit structure 151 away from the stacked structure 121 can be omitted, which is conducive to reducing manufacturing costs and reducing process steps.

[0057] Some embodiments of the present application provide a method for manufacturing a three-dimensional memory. Figure 2FIG. 1 is a flow chart of a method for manufacturing a three-dimensional memory according to an exemplary embodiment of the present application. Figure 2 As shown, a method 200 for manufacturing a semiconductor device (hereinafter referred to as the manufacturing method 200 ) includes steps S210 to S250 .

[0058] S210, providing a semiconductor structure, wherein the semiconductor structure includes a substrate, a stacking structure, and a plurality of initial channel structures, the stacking structure is located on one side of the substrate, and the plurality of initial channel structures penetrate the stacking structure and extend into the substrate.

[0059] S220, removing the substrate and a portion of the initial channel structure to transform the initial channel structure into a channel structure.

[0060] S230 , forming a semiconductor layer connected to the plurality of channel structures.

[0061] S240, forming a metal layer on a side of the semiconductor layer away from the stack structure.

[0062] S250 , forming a source contact and a source line connected to the source contact on a side of the metal layer away from the stack structure.

[0063] According to the manufacturing method of the three-dimensional memory provided in the embodiment of the present application, by forming a metal layer on the side of the semiconductor layer away from the stacking structure, and forming a source contact and a source line connected to the source contact on the side of the metal layer away from the stacking structure, the number of source contacts can be reduced, thereby releasing the area occupied by the source line, which is conducive to optimizing the layout of the metal interconnection lines.

[0064] Figures 3A to 3G Schematic diagram of the cross section of the three-dimensional memory in the manufacturing process of the exemplary embodiment of the present application. Figures 3A to 3G as well as Figure 1 The above steps S210 to S250 are explained by way of example.

[0065] S210, A semiconductor structure is provided.

[0066] In step S210, Figure 3A As shown, in the semiconductor structure 100a, the stacked structure 121 may be formed on one side of a substrate 148 (hereinafter referred to as the second substrate 148). For example, a stop layer 149 may be provided between the stacked structure 121 and the second substrate 148. The material of the second substrate 148 may include, but is not limited to, silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other appropriate material. For example, the second substrate 148 may be a composite substrate (not shown) having a multilayer structure.

[0067] In some embodiments, the semiconductor structure 100a may include an array region 101, a connection region 102, and peripheral regions 103-1 and 103-2. In some embodiments, the stacked structure 121 may include dielectric layers 122 and gate layers 123 alternately stacked in the z direction. For example, the gate layer 123 may be formed by a "gate replacement" process. The portion of the stacked structure 121 located in the connection region 102 may have a stepped structure. For example, the stepped structure may be formed by a "trim-etch" process. In some embodiments, the stacked structure 121 also extends to a portion of the peripheral region (e.g., the peripheral region 103-1). In some embodiments, the insulating cap layer 145 may be located in another portion of the peripheral region (e.g., the peripheral region 103-2) and extend to cover the stepped structure located in the connection region 102.

[0068] In some embodiments, the first penetration portion 163 may extend along the z direction in the peripheral region 103-1. For example, the first penetration portion 163 penetrates the stacked structure 121, and one end thereof extends to the stop layer 149. The second penetration portion 166 may extend along the z direction in the peripheral region 103-2. For example, the second penetration portion 166 penetrates the insulating cover layer 145, and one end thereof extends to the stop layer 149.

[0069] In some embodiments, the semiconductor structure 100a may further include a peripheral circuit structure 151. As described in detail above, the peripheral circuit structure 151 may include a first substrate 154 and a plurality of peripheral devices 155. The plurality of peripheral devices 155 may be located on one side of the first substrate 154. The peripheral circuit structure 151 may be connected to the initial channel structure 131', the first through portion 163, and the second through portion 166 in the z direction through the bonding layer 152.

[0070] The initial channel structure 131' penetrates the stacked structure 121 and extends into the second substrate 148. The initial channel structure 131' may include a functional layer 132 and a channel layer 133 from the outside to the inside, and both the functional layer 132 and the channel layer 133 extend into the second substrate 148. For example, the functional layer 132 in the initial channel structure 131' may be a tubular structure with one end closed, and the closed end extends into the second substrate 148. The channel layer 133 in the initial channel structure 131' may be a tubular structure with both ends closed, and is located inside the functional layer 132.

[0071] In some embodiments, when there is a stop layer 149 between the stacked structure 121 and the second substrate 148, the material of the stop layer 149 may be different from the material of the functional layer 132. For example, the material of the stop layer 149 may include polysilicon. The stop layer 149 may serve as an etching stop layer for removing a portion of the functional layer 132 of the initial channel structure 131' in the subsequent step S220.

[0072] S220, Removing a portion of the substrate and the initial channel structure to convert the initial channel structure into a channel structure .

[0073] In step S220, Figure 3A and Figure 3B As shown, in some embodiments, an etching process (e.g., dry etching or wet etching) may be used to remove the second substrate 148 to expose the initial channel structure 131'. Optionally, before the etching process is used to remove the second substrate 148, a chemical mechanical polishing (CMP) process may be used to remove a portion of the second substrate 148 to improve the removal efficiency. Next, as shown in FIG. Figure 3B and Figure 3C As shown, an etching (eg, dry etching or wet etching) process may be used to remove the portion of the functional layer 132 in the initial channel structure 131 ′ extending into the second substrate 148 to expose the channel layer 133 in the initial channel structure 131 ′.

[0074] After the above process, the initial channel structure 131 ′ can be transformed into the channel structure 131 . In other words, the remaining portion of the initial channel structure 131 ′ after removing a portion of the functional layer 132 can be used as the channel structure 131 .

[0075] S230, Forming a semiconductor layer connected to a plurality of channel structures .

[0076] In step S230, if Figure 3D As shown, in some embodiments, when the stop layer 149 is provided on the surface of the stacked structure 121, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof may be used to form an initial semiconductor layer 111' covering the stop layer 149 and the channel layer 133 of the channel structure 131. For example, the material of the initial semiconductor layer 111' may be the same as that of the stop layer 149. Optionally, the initial semiconductor layer 111' may be doped with a P-type or N-type dopant. When the materials of the stop layer 149 and the initial semiconductor layer 111' are the same, the two do not have a clear interface. The stop layer 149 may constitute the semiconductor layer 111 together with the initial semiconductor layer 111'. Thus, the semiconductor layer 111 may be in contact with the plurality of channel structures 131 (eg, the channel layers 133 of the respective channel structures 131 ), thereby connecting the semiconductor layer 111 to the plurality of channel structures 131 .

[0077] In some embodiments, the initial semiconductor layer 111' may be conformally deposited on the surfaces of the stop layer 149 and the channel layer 133. When the initial semiconductor layer 111' is thin, the surface of the initial semiconductor layer 111' (or the semiconductor layer 111) away from the stacked structure 121 is concave-convex. When the initial semiconductor layer 111' is thick, the surface of the initial semiconductor layer 111' (or the semiconductor layer 111) away from the stacked structure 121 is substantially flat.

[0078] In some embodiments, when the surface of the stacked structure 121 does not have the stop layer 149, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to form a semiconductor layer (not shown) directly covering the stacked structure 121 and the channel layer 133 of the channel structure 131. Similarly, depending on the thickness of the semiconductor layer, the surface of the semiconductor layer away from the stacked structure 121 may be flat or have a concave-convex shape.

[0079] S240, A metal layer is formed on the side of the semiconductor layer away from the stack structure. .

[0080] In step S240, if Figure 3E As shown, in some embodiments, a metal silicide layer 156 may be formed on the surface of the semiconductor layer 111 away from the stacked structure 121 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof or any other known process. The material of the metal silicide layer 156 may include tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide or any combination thereof. Next, a metal layer 141 may be formed on the surface of the metal silicide layer 156 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The material of the metal layer 141 may include tungsten, cobalt, copper, aluminum or any other appropriate metal material. It should be noted that, depending on the thickness of the metal silicide layer 156 and the metal layer 141, the surface of the metal silicide layer 156 and the metal layer 141 away from the stacked structure 121 may be flat or concave-convex, and the present application does not limit this. The metal silicide layer 156 may reduce the contact resistance between the metal layer 141 and the semiconductor layer 111, and further improve the conductive properties of the two.

[0081] In some embodiments, the step of forming the metal silicide layer 156 may be omitted. In other words, the metal layer 141 may be formed on a surface of the semiconductor layer 111 away from the stacked structure 121 , so that the semiconductor layer 111 is in direct contact with the metal layer 141 .

[0082] In some embodiments, Figure 3EAs shown, the semiconductor layer 111, the metal silicide layer 156, and the metal layer 141 formed by the above process can be formed in the array area 101, the connection area 102, and the peripheral areas 103-1 and 103-2. After the semiconductor layer 111, the metal silicide layer 156, and the metal layer 141 are formed, the semiconductor layer 111, the metal silicide layer 156, and the metal layer 141 located in the connection area 102 and the peripheral areas 103-1 and 103-2 can be removed by photolithography and etching (for example, dry etching and / or wet etching) processes to form a cavity (not shown). Next, as shown in FIG. Figure 3F As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form an insulating layer 144 in the cavity. Optionally, in the process of forming the insulating layer 144 in the cavity, the insulating layer 144 may be formed on the surface of the metal layer 141 away from the stacked structure 121. In this embodiment, it is possible to ensure that the semiconductor layer 111 is electrically connected to the channel structure 131 located in the array region 101, and to avoid leakage between the dummy channel structure (not shown) located in the connection region 102 and the semiconductor layer 111.

[0083] S250, A source contact and a source electrode connected to the source contact are formed on the side of the metal layer away from the stack structure. Wire .

[0084] In step S250, if Figure 3G As shown, in some embodiments, a photolithography and etching (e.g., dry etching and / or wet etching) process may be used to form a source contact hole (corresponding to the outer contour of the source contact 143) penetrating the insulating layer 144 and located at the surface portion of the metal layer 141. The source contact hole exposes the metal layer 141. Optionally, in the process of forming the source contact hole, a first contact hole (corresponding to the outer contour of the first contact portion 162) and a second contact hole (corresponding to the outer contour of the second contact portion 165) penetrating the insulating layer 144 may be formed in the peripheral regions 103-1 and 103-2, respectively. The first contact hole is at least partially aligned with the first penetration portion 163, for example, the first contact hole at least partially exposes the first penetration portion 163. Similarly, the second contact hole is at least partially aligned with the second penetration portion 166, for example, the second contact hole at least partially exposes the second penetration portion 166.

[0085] Next, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to fill the source contact hole with a conductive material to form a source contact 143. Thus, the source contact 143 is electrically connected to the metal layer 141. Optionally, the conductive material may also be filled in the first contact hole and the second contact hole to form a first contact portion 162 and a second contact portion 165. Thus, the first contact portion 162 and the first penetration portion 163 are electrically connected to form a first penetration contact 161. The second contact portion 165 and the second penetration portion 166 are electrically connected to form a second penetration contact 164.

[0086] In step S250, if Figure 1 As shown, in some embodiments, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be first used to deposit an insulating material layer on the surfaces of the insulating layer 144, the source contact 143, the first contact portion 162 and the second contact portion 165. Then, the insulating material layer may be patterned using a photolithography and etching process (e.g., dry etching and / or wet etching), and a conductive material may be filled into the patterned insulating material layer to form, for example, the source line 142, the power line 146 and the pad 147.

[0087] In some embodiments, on a plane perpendicular to the z-direction, the source line 142, the power line 146, and the pad 147 may have a preset pattern. For example, the source line 142 and the power line 146 may be referred to as metal interconnects. In some embodiments, the source line 142 may be connected to the source contact 143 and the first through-contact 161 (e.g., the first contact portion 162), respectively, by patterning the source line 142. For example, on a projection plane perpendicular to the z-direction, the projection of the source contact 143 and the projection of the first through-contact 161 are located within the projection of the source line 142. As described above, one end of the first through-contact 161 (e.g., the first through-portion 163) is connected to the peripheral circuit structure 151, and signal transmission between the semiconductor layer 111 and the peripheral circuit structure 151 is achieved through the first through-contact 161, the source line 142, and the metal layer 141.

[0088] In some embodiments, the power line 146 and the pad 147 can be connected to each other by designing the pattern forming the power line 146 and the pad 147, and the power line 146 and some second through contacts (not shown) can be connected by patterning the power line 146. For example, on a projection plane perpendicular to the z direction, the projection of these second through contacts is located within the projection of the power line 146. Signal transmission between an external signal and a peripheral circuit structure 151 is achieved through the pad 147, the power line 146, and the second through contacts. Optionally, the pad 147 and some second through contacts 164 (for example, the second contact portion 165) can also be directly connected by patterning the pad 147. For example, on a projection plane perpendicular to the z direction, the projection of these second through contacts 164 is located within the projection of the pad 147. Signal transmission between an external signal and a peripheral circuit structure 151 is achieved through the pad 147 and these second through contacts 164.

[0089] In some embodiments, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form a passivation layer 171 covering source line 142 and power line 146 and exposing pad 147. Passivation layer 171 may include silicon nitride or any other suitable material.

[0090] According to the manufacturing method of the three-dimensional memory provided in the embodiment of the present application, by forming a metal layer on the side of the semiconductor layer away from the stacking structure, and forming a source contact and a source line connected to the source contact on the side of the metal layer away from the stacking structure, the number of source contacts can be reduced, thereby releasing the area occupied by the source line, which is conducive to optimizing the layout of the metal interconnection lines.

[0091] Some embodiments of the present application also provide a memory system. Figure 4 is a block diagram of a system having a memory system according to an exemplary embodiment of the present application.

[0092] like Figure 4 As shown, the system 11 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has the memory system 12 located therein). Figure 4 As shown, the system 11 may include a host 18 and a memory system 12, the memory system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0093] The three-dimensional memory 14 may be implemented as a three-dimensional memory described in any embodiment of the present application, for example, Figure 13D memory 100 is shown. According to some embodiments, controller 16 is coupled to 3D memory 14 and host 18, and is configured to control 3D memory 14. Controller 16 can manage data stored in 3D memory 14 and communicate with host 18. In some embodiments, controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, controller 16 is designed to operate in a high duty cycle environment, such as a solid state disk (SSD) or an embedded multi-media card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, such as a smart phone, a tablet computer, a laptop computer, etc. Controller 16 can be configured to control operations of 3D memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate functions may also be performed by the controller 16, such as formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., a host 18) according to a specific communication protocol.For example, the controller 16 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, high-speed PCI (PCI-express, PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Internet Small Computer System Interface (SCSI) protocol, Enhanced Small Device Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0094] The controller 16 and the one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash storage (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of final electronic products. Figure 5A In one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Figure 4 The host 18 in the memory card connector 24 is coupled. Figure 5B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Figure 4 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0095] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A three-dimensional memory, characterized in that: include: Semiconductor layer; A stacked structure located on one side of the semiconductor layer; A plurality of channel structures, penetrating the stacked structure and connected to the semiconductor layer; A metal layer, located on a side of the semiconductor layer away from the stacked structure; A source line, located at a side of the metal layer away from the stack structure; as well as The source contact is connected between the metal layer and the source line.

2. The three-dimensional memory according to claim 1, wherein: The metal layer contacts the semiconductor layer.

3. The three-dimensional memory according to claim 1, wherein: It also includes a metal silicide layer, which is located between the metal layer and the semiconductor layer and contacts the metal layer and the semiconductor layer respectively.

4. The three-dimensional memory according to any one of claims 1 to 3, wherein: The three-dimensional memory comprises an array region, a connection region and a peripheral region, and the semiconductor layer and the metal layer are located in the array region; The three-dimensional memory further includes an insulating layer, which is located on the same side of the stacked structure as the semiconductor layer, contacts the stacked structure in the connection region and extends to the peripheral region.

5. The three-dimensional memory according to claim 4, wherein: Also includes: A peripheral circuit structure connected to a side of the plurality of channel structures away from the semiconductor layer; as well as A first through contact penetrates the insulating layer in the peripheral region and extends along the stacking direction of the stacking structure, wherein a first end of the first through contact is connected to the source line, and a second end of the first through contact is connected to the peripheral circuit structure.

6. The three-dimensional memory according to claim 5, wherein: It also includes a power line, which is in the same layer as the source line.

7. The three-dimensional memory according to claim 6, wherein: Also includes: A soldering pad, which is in the same layer as the power line and connected to the power line; as well as A second through contact penetrates the insulating layer in the peripheral region and extends along the stacking direction, wherein a first end of the second through contact is connected to the power line, and a second end of the second through contact is connected to the peripheral circuit structure.

8. The three-dimensional memory according to claim 1, wherein: The channel structure comprises a functional layer and a channel layer from the outside to the inside, and the channel layer is in contact with the semiconductor layer.

9. A memory system, characterized in that: include: At least one three-dimensional memory as claimed in any one of claims 1 to 8; as well as The controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

10. A method for manufacturing a three-dimensional memory, characterized in that: include: A semiconductor structure is provided, wherein the semiconductor structure comprises a substrate, a stacked structure and a plurality of initial channel structures, the stacked structure is located on one side of the substrate, and the plurality of initial channel structures penetrate the stacked structure and extend into the substrate; removing the substrate and a portion of the initial channel structure to transform the initial channel structure into a channel structure; forming a semiconductor layer connected to the plurality of channel structures; forming a metal layer on a side of the semiconductor layer away from the stacked structure; and A source contact and a source line connected to the source contact are formed on a side of the metal layer away from the stack structure.

11. The manufacturing method according to claim 10, wherein: Forming a metal layer on a side of the semiconductor layer away from the stacked structure comprises: The metal layer is formed on the surface of the semiconductor layer.

12. The manufacturing method according to claim 10, wherein: Before forming a metal layer on a side of the semiconductor layer away from the stacked structure, the method further comprises: forming a metal silicide layer on the surface of the semiconductor layer; Wherein, forming a metal layer on a side of the semiconductor layer away from the stacked structure comprises: The metal layer is formed on the surface of the metal silicide layer.

13. The manufacturing method according to claim 10, wherein: The semiconductor structure comprises an array region, a connection region and a peripheral region, the semiconductor layer and the metal layer are formed in the array region, the connection region and the peripheral region, wherein after the metal layer is formed on a side of the semiconductor layer away from the stacked structure, the method further comprises: removing portions of the semiconductor layer and the metal layer located in the connection region and the peripheral region to form a cavity; and An insulating layer is formed in the cavity.

14. The manufacturing method according to claim 13, wherein: The semiconductor structure further includes a peripheral circuit structure and a first penetration portion, wherein the peripheral circuit structure is connected to a side of the plurality of channel structures away from the substrate, and the first penetration portion extends in the peripheral region along a stacking direction of the stacked structure and is connected to the peripheral circuit structure, wherein the method further includes: forming a first contact portion penetrating through the insulating layer and connected to the first penetrating portion; Wherein, forming a source contact on a side of the metal layer away from the stack structure and a source line connected to the source contact comprises: The source line connected to the first contact portion and the source contact is formed.

15. The manufacturing method according to claim 14, wherein: The semiconductor structure further includes a second penetration portion, the second penetration portion extending in the peripheral region along the stacking direction and connected to the peripheral circuit structure, wherein the method further includes: forming a second contact portion penetrating through the insulating layer and connected to the second penetrating portion; and A pad and a power line connected to the second contact portion are formed, wherein the power line is connected to the pad.

16. The manufacturing method according to claim 10, wherein: The initial channel structure includes a functional layer and a channel layer from outside to inside, and the functional layer and the channel layer extend into the substrate, wherein removing a portion of the substrate and the channel structure to transform the initial channel structure into a channel structure includes: The portion of the functional layer extending into the substrate is removed, and the remaining portion of the initial channel structure is used as the channel structure.

17. The manufacturing method according to claim 16, wherein: Forming a semiconductor layer connected to the plurality of channel structures comprises: The semiconductor layer is formed in contact with the channel layers in the plurality of channel structures.

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