Novel memory and preparation method thereof

Abstract

The invention provides a novel memory and a preparation method thereof. The memory unit is directly formed on the substrate corresponding to the active region, so that the influence of thermal budget of a related process of the memory unit on a device in a previous process is reduced, and the influence of a front layer on the outline of the memory unit is reduced; the lower electrode of the storage unit is directly connected with the active region, and the upper electrode of the storage unit and the active region / gate structure without the storage unit are led out through the corresponding contact structure / connection structure, so that the dielectric layer and the photomask process are reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a novel memory and a preparation method thereof. Background Art

[0002] New memory devices such as phase change memory (PRAM) or ferroelectric memory (FeRAM) are devices that integrate memory cells in the back-end of the line (BEOL). The memory cells are inserted between metal layers, and their storage performance is proportional to the effective area of ​​the storage layer and the electrode layer.

[0003] The memory cell of the conventional two-dimensional (2D) memory structure is composed of an upper and lower electrode layer and a middle memory layer. The upper and lower electrode layers and the memory layer are deposited and grown layer by layer by atomic layer deposition (ALD), and the memory layer is formed by phase change material or ferroelectric material. However, after the conventional memory cell process is integrated into the device and contact structure of the front-end-of-line (FEOL) process, the thermal budget of the memory cell process (the heat energy required for silicon exposure in the process) may affect the front-end process device, and the profile of the memory cell is greatly affected by the front layer; and the preparation of the contact structure connecting the upper and lower electrode layers of the memory cell requires multiple mask processes, resulting in increased production costs. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a new type of memory and a preparation method thereof, which can reduce the impact of the thermal budget of the memory cell related process on the front-end process devices and reduce the impact of the front layer on the memory cell profile while ensuring the connection performance of the contact structure remains unchanged, and can save the mask process and reduce production costs.

[0005] In order to solve the above problems, the present invention provides a new type of memory, including: a substrate, an active area is defined in the substrate; a memory cell, the memory cell is formed on the surface of the substrate corresponding to the active area, and the width of the memory cell is smaller than the width of the active area, the memory cell includes a first electrode layer, a memory layer and a second electrode layer stacked in sequence, the first electrode layer is in contact with the active area; a dielectric layer, covering the substrate surface and all the memory cells; a contact structure, penetrating the dielectric layer in a direction perpendicular to the substrate surface and in contact with the second electrode layer; and a metal structure, located on the surface of the dielectric layer and in contact with the contact structure.

[0006] In order to solve the above problems, the present invention also provides a method for preparing a new type of memory, the method comprising the following steps: forming a semiconductor substrate, the semiconductor substrate comprising a substrate, an active area defined in the substrate; forming a memory cell, the memory cell is formed on the surface of the substrate corresponding to the active area, and the width of the memory cell is smaller than the width of the active area, the memory cell comprises a first electrode layer, a memory layer and a second electrode layer stacked in sequence, the first electrode layer is in contact with the active area; forming a dielectric layer, the dielectric layer covers the substrate and all the memory cells; forming a contact structure, the contact structure penetrates the dielectric layer in a direction perpendicular to the substrate surface and is in contact with the second electrode layer; and forming a metal structure, the metal structure is located on the surface of the dielectric layer and is in contact with the contact structure.

[0007] The above technical solution reduces the impact of the thermal budget of the process related to the memory cell on the front-end process device and reduces the impact of the front layer on the memory cell profile by directly forming the memory cell on the substrate corresponding to the active area; the lower electrode (first electrode layer) of the memory cell is directly connected to the active area, and the upper electrode (second electrode layer) of the memory cell and the active area / gate structure without the memory cell are led out through the corresponding contact structure / connection structure, thereby reducing the dielectric layer and photomask process. The present invention can reduce the impact of the thermal budget of the process related to the memory cell on the front-end process device, reduce the impact of the front layer on the memory cell profile, reduce the dielectric layer and photomask process on the basis of keeping the connection performance of the contact structure unchanged, thereby improving the storage performance, optimizing and improving the operation efficiency and reliability of the device, and reducing the production cost.

[0008] It should be understood that the above general description and the detailed description below are exemplary and explanatory only and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0010] Figure 1A It is a schematic diagram of the device structure of a memory in the prior art;

[0011] Figure 1B A schematic diagram of a profile defect of a memory in the prior art;

[0012] Figure 2 A schematic diagram of the device structure of a novel memory according to an embodiment of the present invention;

[0013] Figure 3 A schematic diagram of the steps of a method for preparing a novel memory according to an embodiment of the present invention;

[0014] Figure 4 A schematic diagram of a device structure of a semiconductor substrate provided by an embodiment of the present invention;

[0015] Figure 5A to Figure 5C A schematic diagram of a device structure for forming a storage unit according to an embodiment of the present invention;

[0016] Figure 6 A schematic diagram of a device structure for forming a dielectric layer according to an embodiment of the present invention;

[0017] Figure 7A to Figure 7B A schematic diagram of a device structure for forming a contact structure according to an embodiment of the present invention;

[0018] Figure 8 FIG. 1 is a schematic diagram of a device structure for forming a metal structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] See also Figure 1A , which is a schematic diagram of the device structure of a memory in the prior art. Figure 1A As shown, the existing memory includes: a substrate 10, a first dielectric layer 111 formed on the substrate 10, a first connection structure 121 formed in the first dielectric layer 111, a storage unit 14 formed on the first dielectric layer 111 and in contact with the first connection structure 121, a second dielectric layer 112 covering the first dielectric layer 111 and the storage unit 14, a second connection structure 122 formed in the second dielectric layer 112 and in contact with the storage unit 14, and a metal structure 15 formed on the surface of the second dielectric layer 112 and in contact with the second connection structure 122. The storage unit 14 is composed of a lower electrode layer 141, a middle storage layer 142, and an upper electrode layer 143.

[0021] The memory cell manufacturing process is integrated into the devices and contact structures of the front-end process (FEOL), and the thermal budget of the process affects the front-end process devices. The profile of the memory cell is greatly affected by the previous layer, such as Figure 1B As shown in the dotted box. Figure 1B In the figure, a single-layer color block is used to indicate a storage unit, and the outline of the storage unit in the dotted frame is affected by the protruding contact structure and deformed. At the same time, when preparing the memory, multiple dielectric layers need to be deposited, and the preparation of the first connection structure 121 and the second connection structure 122 requires at least two photomask processes, resulting in increased production costs.

[0022] In order to solve the problem in the prior art that the thermal budget of the storage unit preparation process affects the front-end process devices, the profile of the storage unit is greatly affected by the front layer, and multiple dielectric layer deposition and multiple mask processes are required, resulting in increased production costs, the present invention provides a new type of memory and a preparation method thereof, which can reduce the impact of the thermal budget of the storage unit related process on the front-end process devices, reduce the impact of the front layer on the storage unit profile, reduce the dielectric layer and mask processes, thereby improving storage performance, optimizing and improving device operation efficiency and reliability, and reducing production costs.

[0023] An embodiment of the present invention provides a new type of memory.

[0024] See also Figure 2 The novel memory described in this embodiment includes: a substrate 20 , an active region 201 , a storage unit 22 , a dielectric layer 24 , a contact structure 251 , and a metal structure 26 .

[0025] Specifically, the active area 201 is defined in the substrate 20. The storage unit 22 is formed on the surface of the substrate 20 corresponding to the active area 201, and the width W1 of the storage unit 22 is smaller than the width W2 of the active area 201. The storage unit 22 includes a first electrode layer 221, a storage layer 222 and a second electrode layer 223 which are stacked in sequence, and the first electrode layer 221 is in contact with the active area 201. The dielectric layer 24 covers the substrate 20 and all the storage units 22. The contact structure 251 penetrates the dielectric layer 24 in a direction perpendicular to the surface of the substrate 20 and is in contact with the second electrode layer 223. The metal structure 26 is located on the surface of the dielectric layer 24 and is in contact with the contact structure 251.

[0026] In this embodiment, the materials of the first electrode layer 221 and the second electrode layer 223 are both titanium nitride, the material of the storage layer 222 is a ferroelectric material or a phase change material, the material of the dielectric layer 24 is an oxide (for example, silicon oxide), the material of the contact structure 251 is metal tungsten, and the material of the metal structure 26 is selected from aluminum, copper, or aluminum-copper alloy.

[0027] In this embodiment, the dielectric layer 24 has a certain thickness, and the top surface of the contact structure 251 is substantially flush with the top surface of the dielectric layer 24 .

[0028] In this embodiment, the novel memory further includes: a connection structure 252, which is formed by the same process as the contact structure 251; the connection structure 252 penetrates the dielectric layer 20 in a direction perpendicular to the surface of the substrate 20, and the connection structure 252 is spaced apart from the contact structure 251. The connection structure 252 is used to contact the substrate 20 (specifically, to contact another active area without a storage unit in the substrate 20). The upper electrode (second electrode layer) of the storage unit and the active area without a storage unit are led out through the contact structure 251 and the connection structure 252. The metal structure 26 is also in one-to-one contact with the connection structure 252. The metal structure 26 serves as a lead-out structure or a pad.

[0029] In this embodiment, an etching stop layer 23 is further formed between the dielectric layer 24 and the substrate to protect the substrate when etching contact holes for preparing the contact structure 251 and the connecting structure 252 .

[0030] In this embodiment, the first electrode layer 221 , the storage layer 222 and the second electrode layer 223 have the same shape, which are all long strips.

[0031] This embodiment reduces the impact of the thermal budget of the memory cell-related process on the front-end process devices and reduces the impact of the front layer on the memory cell profile by directly forming the memory cell on the active area in the substrate; the lower electrode (first electrode layer) of the memory cell is directly connected to the active area, and the upper electrode (second electrode layer) of the memory cell and the active area without the memory cell are led out through the corresponding contact structure / connection structure, thereby reducing the dielectric layer and mask process.

[0032] Based on the same inventive concept, the present invention also provides a method for preparing the above-mentioned novel memory.

[0033] Please also read Figure 3 to Figure 8 ,in, Figure 3 A schematic diagram of the steps of a method for preparing a novel memory according to an embodiment of the present invention; Figure 4 A schematic diagram of a device structure of a semiconductor substrate provided by an embodiment of the present invention; Figure 5A to Figure 5CA schematic diagram of a device structure for forming a storage unit according to an embodiment of the present invention; Figure 6 A schematic diagram of a device structure for forming a dielectric layer according to an embodiment of the present invention; Figure 7A to Figure 7B A schematic diagram of a device structure for forming a contact structure according to an embodiment of the present invention; Figure 8 FIG. 1 is a schematic diagram of a device structure for forming a metal structure according to an embodiment of the present invention.

[0034] like Figure 3 As shown, the preparation method of the new memory described in this embodiment includes the following steps: S1, forming a semiconductor substrate, the semiconductor substrate includes a substrate, and an active area is defined in the substrate; S2, forming a memory cell, the memory cell is formed on the surface of the substrate corresponding to the active area, and the width of the memory cell is smaller than the width of the active area, and the memory cell includes a first electrode layer, a memory layer and a second electrode layer which are stacked in sequence, and the first electrode layer is in contact with the active area; S3, forming a dielectric layer, the dielectric layer covers the substrate and all the memory cells; S4, forming a contact structure, the contact structure penetrates the dielectric layer in a direction perpendicular to the substrate surface and is in contact with the second electrode layer; and S5, forming a metal structure, the metal structure is located on the surface of the dielectric layer and is in contact with the contact structure.

[0035] Please refer to step S1 and Figure 4 , forming a semiconductor substrate, the semiconductor substrate includes a substrate 40, and an active area 401 is defined in the substrate 40.

[0036] The substrate 40 is used to support the device structure above it, and the device structure may also be formed in the substrate 40. In this embodiment, the substrate 40 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; the substrate 40 may also be a stacked structure, such as a silicon / germanium silicon stack, etc.

[0037] In this embodiment, a gate structure 49 is further formed on the surface of the substrate 40, and an active region 401 is defined in the substrate 40 between two adjacent gate structures 49. Before the step (S2) of forming a memory cell, the method further includes: forming a contact layer 41, the contact layer 41 covers the surface of the substrate 40 and exposes the gate structure 49, such as Figure 4As shown. The source / drain on both sides of the gate structure 49 can be led out through the contact layer 41. Specifically, the material of the contact layer 41 is metal silicide. The gate structure 49 includes a polysilicon gate 491, a gate oxide layer 492 located below the polysilicon gate 491, and a spacer 493 located on the sidewall of the polysilicon gate 491.

[0038] Please refer to step S2 and Figure 5C , forming a storage unit 50, the storage unit 50 is formed on the surface of the substrate 40 corresponding to the active area 401, and the width W1 of the storage unit 50 is smaller than the width W2 of the active area 401, the storage unit 50 includes a first electrode layer 51, a storage layer 52 and a second electrode layer 53 which are stacked in sequence, and the first electrode layer 51 is in contact with the active area 401.

[0039] Specifically, when the surface of the substrate 40 is covered with a contact layer 41 , the first electrode layer 51 is in contact with the active region 401 through the contact layer 41 .

[0040] In this embodiment, a gate structure 49 is further formed on the surface of the substrate 40, and an active region 401 is defined in the substrate 40 between two adjacent gate structures 49; the steps of forming the memory cell 50 specifically include: (1) depositing a first electrode material layer 510, a memory material layer 520, and a second electrode material layer 530 on the surface of the substrate 40 and all the surfaces of the gate structures 49 in sequence, such as Figure 5A (2) depositing an anti-reflection material on the surface of the second electrode material layer 530 and planarizing it to form an anti-reflection layer 591, and forming a photoresist structure 593 on the surface of the anti-reflection layer 591, wherein the anti-reflection layer 591 fills the area between two adjacent gate structures 49, and the photoresist structure 593 corresponds to the active area 401, and the width W9 of the photoresist structure 593 is less than the spacing W8 between the two adjacent gate structures 49, as shown in FIG. Figure 5B (3) using the photoresist structure 593 as a mask to perform etching, etching the remaining second electrode material layer 530 to form the second electrode layer 53, etching the remaining storage material layer 520 to form the storage layer 52, and etching the remaining first electrode material layer 510 to form the first electrode layer 51; and (4) removing the remaining photoresist structure 593 and the anti-reflection layer 591 to obtain a storage unit 50, as shown. Figure 5C shown.

[0041] In some embodiments, the first electrode material layer 510, the storage material layer 520 and the second electrode material layer 530 can be deposited and grown by maskless atomic layer deposition (ALD). The materials of the first electrode layer 51 and the second electrode layer 53 are both titanium nitride, and the material of the storage layer 52 is a ferroelectric material or a phase change material.

[0042] In some embodiments, the anti-reflective layer 591 may be a bottom anti-reflective coating (BARC), which is a layer of organic or inorganic anti-reflective material deposited before photolithography coating to achieve the purpose of increasing the photolithography process window and improving the photolithography strip width control. The process of forming the anti-reflective layer 591 may also include a planarization process so that the formed anti-reflective layer has a relatively flat surface. The planarization can be achieved by a chemical mechanical polishing (CMP) process. The positive projection of the photoresist structure 593 on the substrate 40 falls between the two adjacent gate structures 49, and there is a gap between the two adjacent gate structures 49, so that the width of the photoresist structure 593 has a certain margin, thereby facilitating the implementation of the mask and etching process.

[0043] In some embodiments, the step of forming the memory cell 50 specifically includes: depositing a first electrode material layer, a memory material layer, and a second electrode material layer on the surface of the substrate in sequence; patterning the first electrode material layer, the memory material layer, and the second electrode material layer to form the first electrode layer, the memory layer, and the second electrode layer located on the surface of the substrate corresponding to the active area and stacked in sequence. The first electrode material layer, the memory material layer, and the second electrode material layer can be deposited and grown by maskless atomic layer deposition (ALD). The patterning can be achieved by etching the first electrode material layer, the memory material layer, and the second electrode material layer using a predetermined mask.

[0044] In this embodiment, the first electrode layer 221, the storage layer 222 and the second electrode layer 223 have the same shape, which are all long strips. The first electrode layer 51 covers the substrate 40 between two adjacent gate structures 49 (specifically, it contacts the active area 401 through the contact layer 41); the storage layer 52 covers the surface of the first electrode layer 51; and the second electrode layer 53 covers the surface of the storage layer 52.

[0045] This embodiment directly forms a memory cell after forming a gate structure (further forming a contact layer) process, thereby reducing the impact of the thermal budget of the memory cell-related process on the front-end process device and reducing the impact of the front layer on the memory cell profile; the lower electrode (first electrode layer) of the memory cell is directly connected to the active area, and the subsequent upper electrode (second electrode layer) of the memory cell and the active area / gate structure without the memory cell are led out through the corresponding contact structure, thereby reducing the dielectric layer and mask process.

[0046] Please refer to step S3 and Figure 6 , forming a dielectric layer 61 , wherein the dielectric layer 61 covers the substrate 40 and all the storage units 50 .

[0047] In this embodiment, the material of the dielectric layer 61 may be an oxide (OX) material, such as silicon oxide (SiO).

[0048] In this embodiment, a gate structure 49 is also formed on the surface of the substrate 40, and an active area 401 is defined in the substrate 40 between two adjacent gate structures 49; the step of forming the dielectric layer 61 specifically includes: forming an etch stop layer 69 covering the substrate 40, all the gate structures 49 and all the memory cells 50, and forming the dielectric layer 61 covering the etch stop layer 69 and filling the area between two adjacent gate structures 49. The etch stop layer 69 serves as an etch stop layer for subsequent etching of contact holes for forming contact structures. The material of the etch stop layer 69 may be silicon nitride (SiN).

[0049] In some embodiments, the step of forming the dielectric layer 61 specifically includes: forming an etch stop layer 69 covering the substrate 40 and all the memory cells 50, and forming the dielectric layer 61 having a certain thickness and covering the etch stop layer 69. The etch stop layer 69 serves as an etch stop layer for subsequent etching of contact holes for forming contact structures.

[0050] Please refer to step S4 and Figure 7B , forming a contact structure 71 , wherein the contact structure 71 penetrates the dielectric layer 61 along a direction perpendicular to the surface of the substrate 40 and contacts the second electrode layer 53 .

[0051] When the step of forming the dielectric layer 61 also forms the etching stop layer 69, the step of forming the contact structure 71 specifically includes: (1) using the etching stop layer 69 as an etching stop layer, etching in the dielectric layer 61 to form a contact hole exposing the second electrode layer 53;

[0052] A contact hole 701 exposing the second electrode layer 53 is formed by etching in the dielectric layer 61 in the groove 490 area. Fig. 7Aand (2) depositing a metal material and planarizing it to form the contact structure 71 in the contact hole 701, as shown in FIG. Figure 7B The material of the contact structure 71 can be metal tungsten.

[0053] In this embodiment, the dielectric layer 61 has a certain thickness, and the top surface of the contact structure 71 is substantially flush with the top surface of the dielectric layer 61 .

[0054] In this embodiment, a connection structure 72 is formed while forming the contact structure 71. The connection structure 72 penetrates the dielectric layer 40 in a direction perpendicular to the surface of the substrate 40, and the connection structure 72 is spaced apart from the contact structure 71. The connection structure 252 is used to contact the substrate 20 (specifically, to contact another active area without a memory cell in the substrate 20). The upper electrode (second electrode layer) of the memory cell and the active area without a memory cell are led out through the contact structure 251 and the connection structure 252. When a gate structure 49 is also formed on the surface of the substrate 40, and an active area 401 is defined in the substrate 40 between two adjacent gate structures 49, a portion of the connection structure 72 is used to contact the substrate 40 (specifically, to contact another active area without a memory cell in the substrate 40), and a portion of the connection structure 72 is used to contact the gate structure 49. The upper electrode (second electrode layer) of the memory cell and the active area / gate structure without a memory cell are led out through the contact structure 71 and the connection structure 72. Specifically, while etching to form the contact hole 701 exposing the second electrode layer 53 , etching to form the connection hole 702 exposing the substrate 40 , and etching to form the connection hole (not shown) exposing the top of the gate structure 49 .

[0055] Please refer to step S5 and Figure 8 , forming a metal structure 81 , wherein the metal structure 81 is located on the surface of the dielectric layer 61 and contacts the contact structure 71 .

[0056] In this embodiment, the step of forming the metal structure 81 specifically includes: depositing and patterning a metal material on the surface of the dielectric layer 61 to form the metal structure 81. The patterning process can refer to the existing metal patterning process, which will not be described in detail here.

[0057] In this embodiment, the metal structure 81 is in one-to-one contact with the connection structure 72. The metal structure 81 serves as a lead-out structure or a pad. The material of the metal structure 81 is selected from one of aluminum, copper, or aluminum-copper alloy, preferably aluminum-copper alloy.

[0058] Based on the same inventive concept, the present invention also provides a new type of memory prepared by the above preparation method.

[0059] See also Figures 4 to 8 The novel memory described in this embodiment includes: a substrate 40, an active region 401, a gate structure 49, a memory cell 50, a dielectric layer 61, a contact structure 71, and a metal structure 81. The memory cell 50 is formed on the surface of the substrate 40 corresponding to the active region 401 between two adjacent gate structures 49, and the width W1 of the memory cell 40 is smaller than the width W2 of the active region 401.

[0060] Specifically, a gate structure 49 is formed on the surface of the substrate 40, and an active area 401 is defined in the substrate between two adjacent gate structures 49. The storage unit 50 includes a first electrode layer 51, a storage layer 52 and a second electrode layer 53 which are stacked in sequence, and the first electrode layer 51 is in contact with the active area 401. The dielectric layer 61 covers the substrate 40, all the gate structures 49 and all the storage units 50, and fills the area between two adjacent gate structures 49. The contact structure 71 penetrates the dielectric layer 61 in a direction perpendicular to the surface of the substrate 40 and is in contact with the second electrode layer 53. The metal structure 81 is located on the surface of the dielectric layer 61 and is in contact with the contact structure 71.

[0061] In this embodiment, the materials of the first electrode layer 51 and the second electrode layer 53 are both titanium nitride, the material of the storage layer 52 is a ferroelectric material or a phase change material, the material of the dielectric layer 61 is an oxide (for example, silicon oxide), the material of the contact structure 71 is metal tungsten, and the material of the metal structure 81 is selected from aluminum, copper, or aluminum-copper alloy.

[0062] In this embodiment, the gate structure 49 includes a polysilicon gate (Poly Gate) 491 , a gate oxide layer (Oxide) 492 located below the polysilicon gate 491 , and a spacer (Spacer) 493 located on the sidewall of the polysilicon gate 491 .

[0063] In this embodiment, the novel memory further includes: a contact layer 41, the contact layer 41 covers the surface of the substrate 40 and exposes the gate structure 49. Specifically, the material of the contact layer 41 is metal silicide.

[0064] In this embodiment, the top surface of the contact structure 71 is substantially flush with the top surface of the dielectric layer 61 .

[0065] In this embodiment, the novel memory further includes: a connection structure 72, which is formed by the same process as the contact structure 71; the connection structure 72 penetrates the dielectric layer 40 in a direction perpendicular to the surface of the substrate 40, and the connection structure 72 is spaced apart from the contact structure 71. A portion of the connection structure 72 is used to contact the substrate 40 (specifically, another active area without a storage unit in the substrate 40), and a portion of the connection structure 72 is used to contact the gate structure 49. The upper electrode (second electrode layer) of the storage unit and the active area / gate structure without a storage unit are led out through the contact structure 71 and the connection structure 72. The metal structure 81 is also in one-to-one contact with the connection structure 72. The metal structure 81 serves as a lead-out structure or a pad.

[0066] In this embodiment, the first electrode layer 51 , the storage layer 52 and the second electrode layer 53 have the same shape.

[0067] This embodiment forms a memory cell directly on the active area after forming a gate structure (further forming a contact layer) process, thereby reducing the impact of the thermal budget of the memory cell-related process on the front-end process device and reducing the impact of the front layer on the memory cell profile; the lower electrode (first electrode layer) of the memory cell is directly connected to the active area, and the upper electrode (second electrode layer) of the memory cell and the active area / gate structure without the memory cell are led out through the corresponding contact structure / connection structure, thereby reducing the dielectric layer and mask process.

[0068] In the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0069] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only include those elements, but also include other elements not clearly listed, or also include elements inherent to such process, method, article or equipment. In the absence of more restrictions, there is a sentence "also includes a ..." The elements limited do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. It should be noted that a person skilled in the art may make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications shall also be regarded as the protection scope of the present invention.

Claims

1. A new type of memory, characterized in that: include: A substrate having an active region defined therein; A memory cell, wherein the memory cell is formed on the surface of the substrate corresponding to the active region, and the width of the memory cell is smaller than the width of the active region, and the memory cell comprises a first electrode layer, a memory layer and a second electrode layer which are sequentially stacked, and the first electrode layer is in contact with the active region; A dielectric layer covering the substrate surface and all the storage units; a contact structure, penetrating the dielectric layer in a direction perpendicular to the substrate surface and contacting the second electrode layer; as well as The metal structure is located on the surface of the dielectric layer and contacts the contact structure.

2. The novel memory according to claim 1, characterized in that: The materials of the first electrode layer and the second electrode layer are both titanium nitride, the material of the storage layer is ferroelectric material or phase change material, the material of the dielectric layer is oxide, the material of the contact structure is metal tungsten, and the material of the metal structure is selected from aluminum, copper, or aluminum-copper alloy.

3. The novel memory according to claim 1, characterized in that: Also includes: A gate structure is formed on the surface of the substrate, and the active area is defined in the substrate between two adjacent gate structures; The contact layer covers the surface of the substrate and exposes the gate structure.

4. The novel memory according to claim 3, characterized in that: The material of the contact layer is metal silicide.

5. A method for preparing a novel memory, characterized in that: The method comprises the following steps: Forming a semiconductor substrate, the semiconductor substrate comprising a substrate, an active region defined in the substrate; forming a memory cell, wherein the memory cell is formed on the surface of the substrate corresponding to the active region, and the width of the memory cell is smaller than the width of the active region, and the memory cell comprises a first electrode layer, a memory layer and a second electrode layer which are sequentially stacked, and the first electrode layer is in contact with the active region; forming a dielectric layer, wherein the dielectric layer covers the substrate and all the storage units; forming a contact structure, wherein the contact structure penetrates the dielectric layer in a direction perpendicular to the substrate surface and contacts the second electrode layer; as well as A metal structure is formed, wherein the metal structure is located on the surface of the dielectric layer and contacts the contact structure.

6. The method according to claim 5, characterized in that The steps of forming the storage unit specifically include: Depositing a first electrode material layer, a storage material layer and a second electrode material layer in sequence on the surface of the substrate; The first electrode material layer, the storage material layer and the second electrode material layer are patterned to form the first electrode layer, the storage layer and the second electrode layer which are located on the surface of the substrate corresponding to the active area and are stacked in sequence.

7. The method according to claim 5, characterized in that A gate structure is also formed on the surface of the substrate, and the active region is defined in the substrate between two adjacent gate structures; the step of forming the memory cell further includes: A contact layer is formed, wherein the contact layer covers the surface of the substrate and exposes the gate structure.

8. The method according to claim 7, characterized in that The steps of forming the storage unit specifically include: Sequentially depositing a first electrode material layer, a storage material layer and a second electrode material layer on the surface of the substrate and all the surfaces of the gate structures; Depositing an anti-reflection material on the surface of the second electrode material layer and planarizing it to form an anti-reflection layer, and forming a photoresist structure on the surface of the anti-reflection layer, wherein the anti-reflection layer fills the area between two adjacent gate structures, the photoresist structure corresponds to the active area, and the width of the photoresist structure is smaller than the distance between the two adjacent gate structures; Using the photoresist structure as a mask, etching the remaining second electrode material layer to form the second electrode layer, etching the remaining storage material layer to form the storage layer, and etching the remaining first electrode material layer to form the first electrode layer; The remaining photoresist structure and the anti-reflection layer are removed.

9. The method according to claim 5, characterized in that The step of forming the dielectric layer specifically includes: forming an etch stop layer covering the substrate surface and all the storage units, and forming the dielectric layer covering the etch stop layer; The step of forming the contact structure specifically includes: Using the etching barrier layer as an etching stop layer, etching in the dielectric layer to form a contact hole exposing the second electrode layer; A metal material is deposited and planarized to form the contact structure in the contact hole, wherein the top surface of the contact structure is substantially flush with the top surface of the dielectric layer.

10. The method according to claim 5, characterized in that The steps of forming the metal structure specifically include: A metal material is deposited on the surface of the dielectric layer and patterned to form the metal structure.

11. The method according to claim 5, characterized in that The materials of the first electrode layer and the second electrode layer are both titanium nitride, the material of the storage layer is ferroelectric material or phase change material, the material of the dielectric layer is oxide, the material of the contact structure is metal tungsten, and the material of the metal structure is selected from aluminum, copper, or aluminum-copper alloy.

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